Create Simple_Addition.asm

Author: Binary-Bard-sudo

Simple_Addition.asm

@@ -0,0 +1,80 @@
+#include "p18f4520.inc"
+
+; CONFIG1H
+  CONFIG  OSC = INTIO67         ; Oscillator Selection bits (Internal oscillator block, port function on RA6 and RA7)
+  CONFIG  FCMEN = OFF           ; Fail-Safe Clock Monitor Enable bit (Fail-Safe Clock Monitor disabled)
+  CONFIG  IESO = OFF            ; Internal/External Oscillator Switchover bit (Oscillator Switchover mode disabled)
+
+; CONFIG2L
+  CONFIG  PWRT = ON             ; Power-up Timer Enable bit (PWRT enabled)
+  CONFIG  BOREN = OFF           ; Brown-out Reset Enable bits (Brown-out Reset disabled in hardware and software)
+  CONFIG  BORV = 3              ; Brown Out Reset Voltage bits (Minimum setting)
+
+; CONFIG2H
+  CONFIG  WDT = OFF             ; Watchdog Timer Enable bit (WDT disabled (control is placed on the SWDTEN bit))
+  CONFIG  WDTPS = 32768         ; Watchdog Timer Postscale Select bits (1:32768)
+
+; CONFIG3H
+  CONFIG  CCP2MX = PORTBE       ; CCP2 MUX bit (CCP2 input/output is multiplexed with RB3)
+  CONFIG  PBADEN = OFF          ; PORTB A/D Enable bit (PORTB<4:0> pins are configured as digital I/O on Reset)
+  CONFIG  LPT1OSC = OFF         ; Low-Power Timer1 Oscillator Enable bit (Timer1 configured for higher power operation)
+  CONFIG  MCLRE = OFF           ; MCLR Pin Enable bit (RE3 input pin enabled; MCLR disabled)
+
+; CONFIG4L
+  CONFIG  STVREN = ON           ; Stack Full/Underflow Reset Enable bit (Stack full/underflow will cause Reset)
+  CONFIG  LVP = OFF             ; Single-Supply ICSP Enable bit (Single-Supply ICSP disabled)
+  CONFIG  XINST = OFF           ; Extended Instruction Set Enable bit (Instruction set extension and Indexed Addressing mode disabled (Legacy mode))
+
+; CONFIG5L
+  CONFIG  CP0 = ON              ; Code Protection bit (Block 0 (000800-001FFFh) code-protected)
+  CONFIG  CP1 = ON              ; Code Protection bit (Block 1 (002000-003FFFh) code-protected)
+  CONFIG  CP2 = ON              ; Code Protection bit (Block 2 (004000-005FFFh) code-protected)
+  CONFIG  CP3 = ON              ; Code Protection bit (Block 3 (006000-007FFFh) code-protected)
+
+; CONFIG5H
+  CONFIG  CPB = ON              ; Boot Block Code Protection bit (Boot block (000000-0007FFh) code-protected)
+  CONFIG  CPD = OFF             ; Data EEPROM Code Protection bit (Data EEPROM not code-protected)
+
+; CONFIG6L
+  CONFIG  WRT0 = OFF            ; Write Protection bit (Block 0 (000800-001FFFh) not write-protected)
+  CONFIG  WRT1 = OFF            ; Write Protection bit (Block 1 (002000-003FFFh) not write-protected)
+  CONFIG  WRT2 = OFF            ; Write Protection bit (Block 2 (004000-005FFFh) not write-protected)
+  CONFIG  WRT3 = OFF            ; Write Protection bit (Block 3 (006000-007FFFh) not write-protected)
+
+; CONFIG6H
+  CONFIG  WRTC = OFF            ; Configuration Register Write Protection bit (Configuration registers (300000-3000FFh) not write-protected)
+  CONFIG  WRTB = OFF            ; Boot Block Write Protection bit (Boot block (000000-0007FFh) not write-protected)
+  CONFIG  WRTD = OFF            ; Data EEPROM Write Protection bit (Data EEPROM not write-protected)
+
+; CONFIG7L
+  CONFIG  EBTR0 = OFF           ; Table Read Protection bit (Block 0 (000800-001FFFh) not protected from table reads executed in other blocks)
+  CONFIG  EBTR1 = OFF           ; Table Read Protection bit (Block 1 (002000-003FFFh) not protected from table reads executed in other blocks)
+  CONFIG  EBTR2 = OFF           ; Table Read Protection bit (Block 2 (004000-005FFFh) not protected from table reads executed in other blocks)
+  CONFIG  EBTR3 = OFF           ; Table Read Protection bit (Block 3 (006000-007FFFh) not protected from table reads executed in other blocks)
+
+; CONFIG7H
+  CONFIG  EBTRB = OFF           ; Boot Block Table Read Protection bit (Boot block (000000-0007FFh) not protected from table reads executed in other blocks)
+
+     
+; Program Code
+    org 0x00 ; Reset vector
+    goto Main
+
+    org 0x80 ; Interrupt vector
+    
+
+Main
+ MOVLW 0
+ MOVWF 12H
+ MOVLW 22H
+ ADDWF 12H,F
+ ADDWF 12H,F
+ ADDWF 36H,F
+ ADDWF 36H,F
+ 
+HERE GOTO HERE  
+	
+	
+END
+
+