ADC

// VerilogA for HDL_Lab_8, ADC, veriloga

/*
`include "constants.vams"
`include "disciplines.vams"

module ADC (out, in, clk);
output [7:0] out; input in, clk;
electrical [7:0] out; electrical in, clk;
parameter real vh = 1.8;
parameter real vth = vh/2;
parameter real tt = 10p from (0:inf); // important, should adapt according to input signal freq
//integer temp;
integer result;
genvar i;


analog begin
    @(cross(V(clk) - vth, +1)) begin
        result = 256*(V(in))/1.8;
        if (result > 255) result = 255;
        else if (result < 0) result = 0;
    end

    for (i=0; i<8; i=i+1)
        V(out[i]) <+ transition(result & (1<<i) ? vh : 0, 0, tt);
end

endmodule
*/



`include "constants.vams"
`include "disciplines.vams"

module ADC (out, in, clk);
output [7:0] out; 
input in, clk;
voltage in,clk;
voltage [7:0] out;

parameter real fullscale = 1.8; //was 1 
parameter real delay_ = 0, trise = 0.1n, tfall = 0.1n;  // trise needs to change ???
parameter real clk_vth = 0.9; // ??? uncertain, needs to look at clk voltage in cadnece
parameter real out_high = 1.8, out_low = 0 from (-inf:2);
real sample,thresh;
real result[7:0];
genvar i;

analog begin
  @(cross(V(clk)-clk_vth, +1)) begin
    sample = V(in);
    thresh = fullscale/2;
    for(i=7;i>=0;i=i-1) begin
      if (sample > thresh) begin
        result[i] = out_high;
        sample = sample - thresh;
      end
      else 
        result[i] = out_low;
      sample = 2*sample;
    end
  end

// out = result;


for (i=7;i>=0;i=i-1)
    V(out[i]) <+ transition(result[i],delay_,trise,tfall);
	//V(out[i]) <+ result[i];
end

endmodule