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Commit 451fce9
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StdCellLib DRC fixes and via enclosure improvement
* Fix DRC errors:
* min tap licon enclosure
* minimum licon on poly difftap space
* minimum poly to difftap space
* Update via enclosure for routing to make width/height same as the
wire in the routing direction.
* TODO: CRL.RoutingLayerGauge.PowerSupply1 parent 439e3fd commit 451fce9
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122 files changed
+5811
-6043
lines changed- thirdparty/open_pdk/C4M.Sky130
- libs.ref/StdCellLib
- gds
- liberty
- spice
- verilog
- vhdl
- libs.tech
- coriolis/techno/etc/coriolis2/node130/sky130
- klayout
- tech/C4M.Sky130
- drc
- lvs
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122 files changed
+5811
-6043
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