diff --git a/library/SubcircuitLibrary/Failed IC'S/.gitkeep b/library/SubcircuitLibrary/Failed IC'S/.gitkeep new file mode 100644 index 000000000..e69de29bb diff --git a/library/SubcircuitLibrary/Failed IC'S/CD4024BC/CD4024BC-cache.lib b/library/SubcircuitLibrary/Failed IC'S/CD4024BC/CD4024BC-cache.lib new file mode 100644 index 000000000..fd4304a55 --- /dev/null +++ b/library/SubcircuitLibrary/Failed IC'S/CD4024BC/CD4024BC-cache.lib @@ -0,0 +1,173 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# adc_bridge_1 +# +DEF adc_bridge_1 U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "adc_bridge_1" 0 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -400 200 350 -50 0 1 0 N +X IN1 1 -600 50 200 R 50 50 1 1 I +X OUT1 2 550 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# adc_bridge_2 +# +DEF adc_bridge_2 U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "adc_bridge_2" 0 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -400 200 350 -100 0 1 0 N +X IN1 1 -600 50 200 R 50 50 1 1 I +X IN2 2 -600 -50 200 R 50 50 1 1 I +X OUT1 3 550 50 200 L 50 50 1 1 O +X OUT2 4 550 -50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_inverter +# +DEF d_inverter U 0 40 Y Y 1 F N +F0 "U" 0 -100 60 H V C CNN +F1 "d_inverter" 0 150 60 H V C CNN +F2 "" 50 -50 60 H V C CNN +F3 "" 50 -50 60 H V C CNN +DRAW +P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N +X ~ 1 -300 0 200 R 50 50 1 1 I +X ~ 2 300 0 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# d_tristate +# +DEF d_tristate U 0 40 Y Y 1 F N +F0 "U" -250 250 60 H V C CNN +F1 "d_tristate" -200 450 60 H V C CNN +F2 "" -100 350 60 H V C CNN +F3 "" -100 350 60 H V C CNN +DRAW +P 4 0 1 0 -400 550 -400 150 350 350 -400 550 N +X IN 1 -600 350 200 R 50 50 1 1 I +X EN 2 -50 50 193 U 50 50 1 1 I +X OUT 3 550 350 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# dac_bridge_1 +# +DEF dac_bridge_1 U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "dac_bridge_1" 0 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -400 200 350 -50 0 1 0 N +X IN1 1 -600 50 200 R 50 50 1 1 I +X OUT1 2 550 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# eSim_MOS_N +# +DEF eSim_MOS_N M 0 0 Y N 1 F N +F0 "M" 0 -150 50 H V R CNN +F1 "eSim_MOS_N" 100 -50 50 H V R CNN +F2 "" 300 -300 29 H V C CNN +F3 "" 100 -200 60 H V C CNN +ALIAS mosfet_n +DRAW +C 150 -200 111 0 1 10 N +P 2 0 1 10 130 -290 130 -250 N +P 2 0 1 0 130 -270 200 -270 N +P 2 0 1 10 130 -220 130 -180 N +P 2 0 1 0 130 -200 200 -200 N +P 2 0 1 10 130 -150 130 -110 N +P 2 0 1 0 130 -130 200 -130 N +P 2 0 1 0 200 -300 200 -270 N +P 2 0 1 0 200 -130 200 -100 N +P 3 0 1 10 110 -275 110 -125 110 -125 N +P 3 0 1 0 200 -200 300 -200 300 -250 N +P 4 0 1 0 140 -200 180 -215 180 -185 140 -200 F +X D 1 200 0 100 D 50 50 1 1 P +X G 2 -100 -200 210 R 50 50 1 1 P +X S 3 200 -400 100 U 50 50 1 1 P +X B 4 300 -350 98 U 47 47 1 1 P +ENDDRAW +ENDDEF +# +# eSim_MOS_P +# +DEF eSim_MOS_P M 0 0 Y N 1 F N +F0 "M" -50 50 50 H V R CNN +F1 "eSim_MOS_P" 50 150 50 H V R CNN +F2 "" 250 100 29 H V C CNN +F3 "" 50 0 60 H V C CNN +ALIAS mosfet_p +DRAW +C 100 0 111 0 1 10 N +P 2 0 1 0 80 -70 150 -70 N +P 2 0 1 10 80 -50 80 -90 N +P 2 0 1 0 80 0 150 0 N +P 2 0 1 10 80 20 80 -20 N +P 2 0 1 0 80 70 150 70 N +P 2 0 1 10 80 90 80 50 N +P 2 0 1 0 150 -70 150 -100 N +P 2 0 1 0 150 100 150 70 N +P 3 0 1 10 60 75 60 -75 60 -75 N +P 3 0 1 0 150 0 250 0 250 -50 N +P 4 0 1 0 140 0 100 -15 100 15 140 0 F +X D 1 150 200 100 D 50 50 1 1 P +X G 2 -150 0 210 R 50 50 1 1 P +X S 3 150 -200 100 U 50 50 1 1 P +X B 4 250 -150 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/Failed IC'S/CD4024BC/CD4024BC.cir b/library/SubcircuitLibrary/Failed IC'S/CD4024BC/CD4024BC.cir new file mode 100644 index 000000000..42431b963 --- /dev/null +++ b/library/SubcircuitLibrary/Failed IC'S/CD4024BC/CD4024BC.cir @@ -0,0 +1,40 @@ +* C:\FOSSEE\eSim\library\SubcircuitLibrary\CD4024BC\CD4024BC.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 06/19/25 23:21:47 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U2 Net-_U12-Pad3_ Net-_U2-Pad2_ Net-_U2-Pad3_ d_tristate +M2 Net-_M1-Pad3_ Net-_M2-Pad2_ Net-_M1-Pad1_ vdd eSim_MOS_P +M1 Net-_M1-Pad1_ Net-_M1-Pad2_ Net-_M1-Pad3_ gnd eSim_MOS_N +M4 Net-_M3-Pad3_ Net-_M2-Pad2_ Net-_M1-Pad3_ vdd eSim_MOS_P +M3 Net-_M1-Pad3_ Net-_M1-Pad2_ Net-_M3-Pad3_ gnd eSim_MOS_N +M5 Net-_M5-Pad1_ Net-_M2-Pad2_ Net-_M5-Pad3_ vdd eSim_MOS_P +M6 Net-_M5-Pad3_ Net-_M5-Pad3_ Net-_M5-Pad1_ gnd eSim_MOS_N +M8 Net-_M7-Pad3_ Net-_M5-Pad3_ Net-_M5-Pad3_ gnd eSim_MOS_N +M7 Net-_M5-Pad3_ Net-_M2-Pad2_ Net-_M7-Pad3_ vdd eSim_MOS_P +U3 Net-_U15-Pad1_ Net-_U22-Pad2_ Net-_U14-Pad1_ d_tristate +U4 Net-_U17-Pad2_ Net-_U22-Pad2_ Net-_U10-Pad1_ d_tristate +U1 vdd gnd Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_M1-Pad1_ Net-_U1-Pad7_ PORT +U7 Net-_U2-Pad3_ Net-_M1-Pad2_ d_inverter +U8 Net-_U5-Pad2_ Net-_U2-Pad2_ d_inverter +U5 Net-_U12-Pad4_ Net-_U5-Pad2_ d_inverter +U9 Net-_M1-Pad2_ Net-_U18-Pad1_ d_inverter +U10 Net-_U10-Pad1_ Net-_U10-Pad2_ d_inverter +U11 Net-_U10-Pad1_ Net-_U11-Pad2_ d_inverter +U6 Net-_U13-Pad2_ Net-_U15-Pad1_ d_inverter +U18 Net-_U18-Pad1_ Net-_M2-Pad2_ dac_bridge_1 +U19 Net-_M1-Pad2_ Net-_M5-Pad3_ dac_bridge_1 +U14 Net-_U14-Pad1_ Net-_M3-Pad3_ dac_bridge_1 +U13 Net-_M1-Pad3_ Net-_U13-Pad2_ adc_bridge_1 +U15 Net-_U15-Pad1_ Net-_M5-Pad1_ dac_bridge_1 +U17 Net-_M5-Pad3_ Net-_U17-Pad2_ adc_bridge_1 +U16 Net-_U10-Pad2_ Net-_M7-Pad3_ dac_bridge_1 +U21 Net-_U11-Pad2_ Net-_U1-Pad5_ dac_bridge_1 +U12 Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U12-Pad3_ Net-_U12-Pad4_ adc_bridge_2 +U20 Net-_U10-Pad1_ Net-_U1-Pad7_ adc_bridge_1 +U22 Net-_U2-Pad2_ Net-_U22-Pad2_ dac_bridge_1 + +.end diff --git a/library/SubcircuitLibrary/Failed IC'S/CD4024BC/CD4024BC.cir.out b/library/SubcircuitLibrary/Failed IC'S/CD4024BC/CD4024BC.cir.out new file mode 100644 index 000000000..117ef04ff --- /dev/null +++ b/library/SubcircuitLibrary/Failed IC'S/CD4024BC/CD4024BC.cir.out @@ -0,0 +1,106 @@ +* c:\fossee\esim\library\subcircuitlibrary\cd4024bc\cd4024bc.cir + +.include PMOS-180nm.lib +.include NMOS-180nm.lib +* u2 net-_u12-pad3_ net-_u2-pad2_ net-_u2-pad3_ d_tristate +m2 net-_m1-pad3_ net-_m2-pad2_ net-_m1-pad1_ vdd CMOSP W=100u L=100u M=1 +m1 net-_m1-pad1_ net-_m1-pad2_ net-_m1-pad3_ gnd CMOSN W=100u L=100u M=1 +m4 net-_m3-pad3_ net-_m2-pad2_ net-_m1-pad3_ vdd CMOSP W=100u L=100u M=1 +m3 net-_m1-pad3_ net-_m1-pad2_ net-_m3-pad3_ gnd CMOSN W=100u L=100u M=1 +m5 net-_m5-pad1_ net-_m2-pad2_ net-_m5-pad3_ vdd CMOSP W=100u L=100u M=1 +m6 net-_m5-pad3_ net-_m5-pad3_ net-_m5-pad1_ gnd CMOSN W=100u L=100u M=1 +m8 net-_m7-pad3_ net-_m5-pad3_ net-_m5-pad3_ gnd CMOSN W=100u L=100u M=1 +m7 net-_m5-pad3_ net-_m2-pad2_ net-_m7-pad3_ vdd CMOSP W=100u L=100u M=1 +* u3 net-_u15-pad1_ net-_u22-pad2_ net-_u14-pad1_ d_tristate +* u4 net-_u17-pad2_ net-_u22-pad2_ net-_u10-pad1_ d_tristate +* u1 vdd gnd net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_m1-pad1_ net-_u1-pad7_ port +* u7 net-_u2-pad3_ net-_m1-pad2_ d_inverter +* u8 net-_u5-pad2_ net-_u2-pad2_ d_inverter +* u5 net-_u12-pad4_ net-_u5-pad2_ d_inverter +* u9 net-_m1-pad2_ net-_u18-pad1_ d_inverter +* u10 net-_u10-pad1_ net-_u10-pad2_ d_inverter +* u11 net-_u10-pad1_ net-_u11-pad2_ d_inverter +* u6 net-_u13-pad2_ net-_u15-pad1_ d_inverter +* u18 net-_u18-pad1_ net-_m2-pad2_ dac_bridge_1 +* u19 net-_m1-pad2_ net-_m5-pad3_ dac_bridge_1 +* u14 net-_u14-pad1_ net-_m3-pad3_ dac_bridge_1 +* u13 net-_m1-pad3_ net-_u13-pad2_ adc_bridge_1 +* u15 net-_u15-pad1_ net-_m5-pad1_ dac_bridge_1 +* u17 net-_m5-pad3_ net-_u17-pad2_ adc_bridge_1 +* u16 net-_u10-pad2_ net-_m7-pad3_ dac_bridge_1 +* u21 net-_u11-pad2_ net-_u1-pad5_ dac_bridge_1 +* u12 net-_u1-pad3_ net-_u1-pad4_ net-_u12-pad3_ net-_u12-pad4_ adc_bridge_2 +* u20 net-_u10-pad1_ net-_u1-pad7_ adc_bridge_1 +* u22 net-_u2-pad2_ net-_u22-pad2_ dac_bridge_1 +a1 net-_u12-pad3_ net-_u2-pad2_ net-_u2-pad3_ u2 +a2 net-_u15-pad1_ net-_u22-pad2_ net-_u14-pad1_ u3 +a3 net-_u17-pad2_ net-_u22-pad2_ net-_u10-pad1_ u4 +a4 net-_u2-pad3_ net-_m1-pad2_ u7 +a5 net-_u5-pad2_ net-_u2-pad2_ u8 +a6 net-_u12-pad4_ net-_u5-pad2_ u5 +a7 net-_m1-pad2_ net-_u18-pad1_ u9 +a8 net-_u10-pad1_ net-_u10-pad2_ u10 +a9 net-_u10-pad1_ net-_u11-pad2_ u11 +a10 net-_u13-pad2_ net-_u15-pad1_ u6 +a11 [net-_u18-pad1_ ] [net-_m2-pad2_ ] u18 +a12 [net-_m1-pad2_ ] [net-_m5-pad3_ ] u19 +a13 [net-_u14-pad1_ ] [net-_m3-pad3_ ] u14 +a14 [net-_m1-pad3_ ] [net-_u13-pad2_ ] u13 +a15 [net-_u15-pad1_ ] [net-_m5-pad1_ ] u15 +a16 [net-_m5-pad3_ ] [net-_u17-pad2_ ] u17 +a17 [net-_u10-pad2_ ] [net-_m7-pad3_ ] u16 +a18 [net-_u11-pad2_ ] [net-_u1-pad5_ ] u21 +a19 [net-_u1-pad3_ net-_u1-pad4_ ] [net-_u12-pad3_ net-_u12-pad4_ ] u12 +a20 [net-_u10-pad1_ ] [net-_u1-pad7_ ] u20 +a21 [net-_u2-pad2_ ] [net-_u22-pad2_ ] u22 +* Schematic Name: d_tristate, NgSpice Name: d_tristate +.model u2 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 ) +* Schematic Name: d_tristate, NgSpice Name: d_tristate +.model u3 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 ) +* Schematic Name: d_tristate, NgSpice Name: d_tristate +.model u4 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u7 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u8 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u5 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u9 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u10 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u11 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge +.model u18 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge +.model u19 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge +.model u14 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: adc_bridge_1, NgSpice Name: adc_bridge +.model u13 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge +.model u15 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: adc_bridge_1, NgSpice Name: adc_bridge +.model u17 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge +.model u16 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge +.model u21 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: adc_bridge_2, NgSpice Name: adc_bridge +.model u12 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: adc_bridge_1, NgSpice Name: adc_bridge +.model u20 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge +.model u22 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/Failed IC'S/CD4024BC/CD4024BC.pro b/library/SubcircuitLibrary/Failed IC'S/CD4024BC/CD4024BC.pro new file mode 100644 index 000000000..e27a398be --- /dev/null +++ b/library/SubcircuitLibrary/Failed IC'S/CD4024BC/CD4024BC.pro @@ -0,0 +1,73 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts diff --git a/library/SubcircuitLibrary/Failed IC'S/CD4024BC/CD4024BC.sch b/library/SubcircuitLibrary/Failed IC'S/CD4024BC/CD4024BC.sch new file mode 100644 index 000000000..c1d4f9e33 --- /dev/null +++ b/library/SubcircuitLibrary/Failed IC'S/CD4024BC/CD4024BC.sch @@ -0,0 +1,789 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +LIBS:CD4024BC-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_tristate U2 +U 1 1 6841797C +P 3300 4900 +F 0 "U2" H 3050 5150 60 0000 C CNN +F 1 "d_tristate" H 3100 5350 60 0000 C CNN +F 2 "" H 3200 5250 60 0000 C CNN +F 3 "" H 3200 5250 60 0000 C CNN + 1 3300 4900 + 1 0 0 -1 +$EndComp +$Comp +L eSim_MOS_P M2 +U 1 1 68417FD6 +P 3450 1600 +F 0 "M2" H 3400 1650 50 0000 R CNN +F 1 "eSim_MOS_P" H 3500 1750 50 0000 R CNN +F 2 "" H 3700 1700 29 0000 C CNN +F 3 "" H 3500 1600 60 0000 C CNN + 1 3450 1600 + 0 1 1 0 +$EndComp +$Comp +L eSim_MOS_N M1 +U 1 1 6841807B +P 3300 2350 +F 0 "M1" H 3300 2200 50 0000 R CNN +F 1 "eSim_MOS_N" H 3400 2300 50 0000 R CNN +F 2 "" H 3600 2050 29 0000 C CNN +F 3 "" H 3400 2150 60 0000 C CNN + 1 3300 2350 + 0 -1 -1 0 +$EndComp +$Comp +L eSim_MOS_P M4 +U 1 1 684183C6 +P 4500 3050 +F 0 "M4" H 4450 3100 50 0000 R CNN +F 1 "eSim_MOS_P" H 4550 3200 50 0000 R CNN +F 2 "" H 4750 3150 29 0000 C CNN +F 3 "" H 4550 3050 60 0000 C CNN + 1 4500 3050 + -1 0 0 1 +$EndComp +$Comp +L eSim_MOS_N M3 +U 1 1 684183CC +P 3750 2900 +F 0 "M3" H 3750 2750 50 0000 R CNN +F 1 "eSim_MOS_N" H 3850 2850 50 0000 R CNN +F 2 "" H 4050 2600 29 0000 C CNN +F 3 "" H 3850 2700 60 0000 C CNN + 1 3750 2900 + 1 0 0 -1 +$EndComp +$Comp +L eSim_MOS_P M5 +U 1 1 6841876A +P 6300 2250 +F 0 "M5" H 6250 2300 50 0000 R CNN +F 1 "eSim_MOS_P" H 6350 2400 50 0000 R CNN +F 2 "" H 6550 2350 29 0000 C CNN +F 3 "" H 6350 2250 60 0000 C CNN + 1 6300 2250 + 0 -1 -1 0 +$EndComp +$Comp +L eSim_MOS_N M6 +U 1 1 68418770 +P 6450 1500 +F 0 "M6" H 6450 1350 50 0000 R CNN +F 1 "eSim_MOS_N" H 6550 1450 50 0000 R CNN +F 2 "" H 6750 1200 29 0000 C CNN +F 3 "" H 6550 1300 60 0000 C CNN + 1 6450 1500 + 0 1 1 0 +$EndComp +$Comp +L eSim_MOS_N M8 +U 1 1 684199FF +P 7200 2950 +F 0 "M8" H 7200 2800 50 0000 R CNN +F 1 "eSim_MOS_N" H 7300 2900 50 0000 R CNN +F 2 "" H 7500 2650 29 0000 C CNN +F 3 "" H 7300 2750 60 0000 C CNN + 1 7200 2950 + -1 0 0 1 +$EndComp +$Comp +L eSim_MOS_P M7 +U 1 1 68419A62 +P 6450 2750 +F 0 "M7" H 6400 2800 50 0000 R CNN +F 1 "eSim_MOS_P" H 6500 2900 50 0000 R CNN +F 2 "" H 6700 2850 29 0000 C CNN +F 3 "" H 6500 2750 60 0000 C CNN + 1 6450 2750 + 1 0 0 -1 +$EndComp +$Comp +L d_tristate U3 +U 1 1 6841A00F +P 5450 2700 +F 0 "U3" H 5200 2950 60 0000 C CNN +F 1 "d_tristate" H 5250 3150 60 0000 C CNN +F 2 "" H 5350 3050 60 0000 C CNN +F 3 "" H 5350 3050 60 0000 C CNN + 1 5450 2700 + -1 0 0 1 +$EndComp +$Comp +L d_tristate U4 +U 1 1 6841A1D5 +P 8200 1700 +F 0 "U4" H 7950 1950 60 0000 C CNN +F 1 "d_tristate" H 8000 2150 60 0000 C CNN +F 2 "" H 8100 2050 60 0000 C CNN +F 3 "" H 8100 2050 60 0000 C CNN + 1 8200 1700 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 6841A668 +P 1750 1100 +F 0 "U1" H 1800 1200 30 0000 C CNN +F 1 "PORT" H 1750 1100 30 0000 C CNN +F 2 "" H 1750 1100 60 0000 C CNN +F 3 "" H 1750 1100 60 0000 C CNN + 1 1750 1100 + 1 0 0 -1 +$EndComp +Text GLabel 2300 1100 2 60 Input ~ 0 +vdd +Text GLabel 2850 1850 0 60 Input ~ 0 +vdd +Text GLabel 4250 2650 2 60 Input ~ 0 +vdd +Text GLabel 6700 3100 0 60 Input ~ 0 +vdd +$Comp +L PORT U1 +U 2 1 6841B2A3 +P 1750 1350 +F 0 "U1" H 1800 1450 30 0000 C CNN +F 1 "PORT" H 1750 1350 30 0000 C CNN +F 2 "" H 1750 1350 60 0000 C CNN +F 3 "" H 1750 1350 60 0000 C CNN + 2 1750 1350 + 1 0 0 -1 +$EndComp +Text GLabel 2300 1350 2 60 Input ~ 0 +gnd +Text GLabel 3700 2300 3 60 Input ~ 0 +gnd +Text GLabel 5750 1800 0 60 Input ~ 0 +gnd +Text GLabel 6650 2000 3 60 Input ~ 0 +vdd +Text GLabel 6950 2400 2 60 Input ~ 0 +gnd +Text GLabel 4050 3550 3 60 Input ~ 0 +gnd +$Comp +L PORT U1 +U 4 1 6841E24A +P 900 5500 +F 0 "U1" H 950 5600 30 0000 C CNN +F 1 "PORT" H 900 5500 30 0000 C CNN +F 2 "" H 900 5500 60 0000 C CNN +F 3 "" H 900 5500 60 0000 C CNN + 4 900 5500 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 6841E536 +P 1000 4500 +F 0 "U1" H 1050 4600 30 0000 C CNN +F 1 "PORT" H 1000 4500 30 0000 C CNN +F 2 "" H 1000 4500 60 0000 C CNN +F 3 "" H 1000 4500 60 0000 C CNN + 3 1000 4500 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 7 1 6841E82E +P 10650 3150 +F 0 "U1" H 10700 3250 30 0000 C CNN +F 1 "PORT" H 10650 3150 30 0000 C CNN +F 2 "" H 10650 3150 60 0000 C CNN +F 3 "" H 10650 3150 60 0000 C CNN + 7 10650 3150 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 6 1 6841E9CF +P 9400 3800 +F 0 "U1" H 9450 3900 30 0000 C CNN +F 1 "PORT" H 9400 3800 30 0000 C CNN +F 2 "" H 9400 3800 60 0000 C CNN +F 3 "" H 9400 3800 60 0000 C CNN + 6 9400 3800 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 5 1 6841EC26 +P 10900 1850 +F 0 "U1" H 10950 1950 30 0000 C CNN +F 1 "PORT" H 10900 1850 30 0000 C CNN +F 2 "" H 10900 1850 60 0000 C CNN +F 3 "" H 10900 1850 60 0000 C CNN + 5 10900 1850 + -1 0 0 1 +$EndComp +$Comp +L d_inverter U7 +U 1 1 6842849A +P 4650 4550 +F 0 "U7" H 4650 4450 60 0000 C CNN +F 1 "d_inverter" H 4650 4700 60 0000 C CNN +F 2 "" H 4700 4500 60 0000 C CNN +F 3 "" H 4700 4500 60 0000 C CNN + 1 4650 4550 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U8 +U 1 1 684289C3 +P 5050 5700 +F 0 "U8" H 5050 5600 60 0000 C CNN +F 1 "d_inverter" H 5050 5850 60 0000 C CNN +F 2 "" H 5100 5650 60 0000 C CNN +F 3 "" H 5100 5650 60 0000 C CNN + 1 5050 5700 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U5 +U 1 1 68428A56 +P 3100 5700 +F 0 "U5" H 3100 5600 60 0000 C CNN +F 1 "d_inverter" H 3100 5850 60 0000 C CNN +F 2 "" H 3150 5650 60 0000 C CNN +F 3 "" H 3150 5650 60 0000 C CNN + 1 3100 5700 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U9 +U 1 1 68428F33 +P 6150 4550 +F 0 "U9" H 6150 4450 60 0000 C CNN +F 1 "d_inverter" H 6150 4700 60 0000 C CNN +F 2 "" H 6200 4500 60 0000 C CNN +F 3 "" H 6200 4500 60 0000 C CNN + 1 6150 4550 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U10 +U 1 1 684290DD +P 7900 3400 +F 0 "U10" H 7900 3300 60 0000 C CNN +F 1 "d_inverter" H 7900 3550 60 0000 C CNN +F 2 "" H 7950 3350 60 0000 C CNN +F 3 "" H 7950 3350 60 0000 C CNN + 1 7900 3400 + -1 0 0 1 +$EndComp +$Comp +L d_inverter U11 +U 1 1 684293C8 +P 9100 1900 +F 0 "U11" H 9100 1800 60 0000 C CNN +F 1 "d_inverter" H 9100 2050 60 0000 C CNN +F 2 "" H 9150 1850 60 0000 C CNN +F 3 "" H 9150 1850 60 0000 C CNN + 1 9100 1900 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U6 +U 1 1 684297F8 +P 4650 1900 +F 0 "U6" H 4650 1800 60 0000 C CNN +F 1 "d_inverter" H 4650 2050 60 0000 C CNN +F 2 "" H 4700 1850 60 0000 C CNN +F 3 "" H 4700 1850 60 0000 C CNN + 1 4650 1900 + 1 0 0 -1 +$EndComp +$Comp +L dac_bridge_1 U18 +U 1 1 68484D43 +P 7550 4600 +F 0 "U18" H 7550 4600 60 0000 C CNN +F 1 "dac_bridge_1" H 7550 4750 60 0000 C CNN +F 2 "" H 7550 4600 60 0000 C CNN +F 3 "" H 7550 4600 60 0000 C CNN + 1 7550 4600 + 1 0 0 -1 +$EndComp +$Comp +L dac_bridge_1 U19 +U 1 1 68484DAE +P 7950 4900 +F 0 "U19" H 7950 4900 60 0000 C CNN +F 1 "dac_bridge_1" H 7950 5050 60 0000 C CNN +F 2 "" H 7950 4900 60 0000 C CNN +F 3 "" H 7950 4900 60 0000 C CNN + 1 7950 4900 + 1 0 0 -1 +$EndComp +$Comp +L dac_bridge_1 U14 +U 1 1 68485853 +P 5100 3800 +F 0 "U14" H 5100 3800 44 0000 C CNN +F 1 "dac_bridge_1" H 5100 3950 60 0000 C CNN +F 2 "" H 5100 3800 60 0000 C CNN +F 3 "" H 5100 3800 60 0000 C CNN + 1 5100 3800 + 0 1 1 0 +$EndComp +$Comp +L adc_bridge_1 U13 +U 1 1 68485CB6 +P 4450 1400 +F 0 "U13" H 4450 1400 60 0000 C CNN +F 1 "adc_bridge_1" H 4450 1550 60 0000 C CNN +F 2 "" H 4450 1400 60 0000 C CNN +F 3 "" H 4450 1400 60 0000 C CNN + 1 4450 1400 + 1 0 0 -1 +$EndComp +$Comp +L dac_bridge_1 U15 +U 1 1 68485FEE +P 5550 1200 +F 0 "U15" H 5550 1200 60 0000 C CNN +F 1 "dac_bridge_1" H 5550 1350 60 0000 C CNN +F 2 "" H 5550 1200 60 0000 C CNN +F 3 "" H 5550 1200 60 0000 C CNN + 1 5550 1200 + 1 0 0 -1 +$EndComp +$Comp +L adc_bridge_1 U17 +U 1 1 6848666D +P 7350 1050 +F 0 "U17" H 7350 1050 60 0000 C CNN +F 1 "adc_bridge_1" H 7350 1200 60 0000 C CNN +F 2 "" H 7350 1050 60 0000 C CNN +F 3 "" H 7350 1050 60 0000 C CNN + 1 7350 1050 + 1 0 0 -1 +$EndComp +Wire Wire Line + 3850 4550 4350 4550 +Wire Wire Line + 4950 4550 5850 4550 +Wire Wire Line + 3400 5700 4750 5700 +Wire Wire Line + 3250 4850 3250 5100 +Wire Wire Line + 3250 5100 5900 5100 +Wire Wire Line + 5900 5100 5900 5700 +Wire Wire Line + 3250 1750 3200 1750 +Wire Wire Line + 3200 1750 3200 2150 +Wire Wire Line + 3200 2150 3300 2150 +Wire Wire Line + 3650 1750 3800 1750 +Wire Wire Line + 3800 1750 3800 2150 +Wire Wire Line + 3800 2150 3700 2150 +Connection ~ 3800 1900 +Wire Wire Line + 4350 2800 4350 2850 +Wire Wire Line + 3950 2800 4350 2800 +Wire Wire Line + 3950 2800 3950 2900 +Wire Wire Line + 4350 3400 4350 3250 +Wire Wire Line + 3950 3400 4350 3400 +Wire Wire Line + 3950 3400 3950 3300 +Connection ~ 4200 3400 +Wire Wire Line + 4100 1700 4100 2800 +Connection ~ 4100 1900 +Connection ~ 4100 2800 +Wire Wire Line + 6550 1700 6450 1700 +Wire Wire Line + 6100 2100 5950 2100 +Wire Wire Line + 5950 2100 5950 1700 +Wire Wire Line + 5950 1700 6050 1700 +Connection ~ 5950 1900 +Wire Wire Line + 8350 1900 8350 3400 +Connection ~ 8350 1900 +Wire Wire Line + 4200 3400 4200 3750 +Wire Wire Line + 4200 3750 4900 3750 +Wire Wire Line + 4650 2850 4650 3900 +Wire Wire Line + 4650 3900 8250 3900 +Wire Wire Line + 5650 4550 5650 4850 +Wire Wire Line + 7350 4850 3800 4850 +Wire Wire Line + 3800 4850 3800 3450 +Wire Wire Line + 3800 3450 3450 3450 +Wire Wire Line + 3450 3450 3450 3050 +Wire Wire Line + 3450 3100 3650 3100 +Connection ~ 5650 4550 +Wire Wire Line + 6550 1700 6550 2100 +Wire Wire Line + 6550 2100 6500 2100 +Wire Wire Line + 6550 1900 7050 1900 +Connection ~ 6550 1900 +Wire Wire Line + 7000 2550 6600 2550 +Wire Wire Line + 7000 2950 6600 2950 +Wire Wire Line + 6800 2550 6800 1900 +Connection ~ 6800 1900 +Connection ~ 6800 2550 +Wire Wire Line + 6800 2950 6800 3400 +Connection ~ 6800 2950 +Wire Wire Line + 5800 2700 6050 2700 +Wire Wire Line + 6050 2700 6050 3050 +Wire Wire Line + 8100 1900 8800 1900 +Wire Wire Line + 2300 1100 2000 1100 +Wire Wire Line + 3300 1850 2850 1850 +Wire Wire Line + 4250 2900 4250 2650 +Wire Wire Line + 6700 3100 6700 2900 +Wire Wire Line + 2000 1350 2300 1350 +Wire Wire Line + 3700 2300 3700 2050 +Wire Wire Line + 3700 2050 3650 2050 +Wire Wire Line + 5750 1800 6100 1800 +Wire Wire Line + 6900 2600 6900 2400 +Wire Wire Line + 6900 2400 6950 2400 +Wire Wire Line + 6450 2000 6650 2000 +Wire Wire Line + 3500 2450 3500 3050 +Wire Wire Line + 3500 3050 3450 3050 +Connection ~ 3450 3100 +Wire Wire Line + 4050 3550 4050 3250 +Wire Wire Line + 7300 2750 7450 2750 +Wire Wire Line + 6900 2250 8750 2250 +Wire Wire Line + 6900 2250 6900 1300 +Wire Wire Line + 6900 1300 6250 1300 +Wire Wire Line + 6250 1300 6250 1400 +Connection ~ 7350 2750 +Connection ~ 5650 4850 +Wire Wire Line + 3450 1450 3450 1050 +Wire Wire Line + 3450 1050 4500 1050 +Wire Wire Line + 4500 1050 4500 2850 +Wire Wire Line + 4500 2850 4650 2850 +Connection ~ 4650 3050 +Wire Wire Line + 6300 2450 6300 2400 +Connection ~ 4500 2450 +Wire Wire Line + 6250 3900 6250 2750 +Wire Wire Line + 6250 2750 6300 2750 +Connection ~ 6250 3900 +Connection ~ 5900 5700 +Wire Wire Line + 5500 2750 5500 2500 +Wire Wire Line + 5500 2500 10150 2500 +Connection ~ 7500 2500 +Wire Wire Line + 2300 4550 2700 4550 +Wire Wire Line + 2300 5700 2800 5700 +Connection ~ 8350 3400 +Wire Wire Line + 3200 1950 2950 1950 +Wire Wire Line + 2950 1950 2950 3800 +Wire Wire Line + 2950 3800 9150 3800 +Connection ~ 3200 1950 +Wire Wire Line + 6450 4550 6950 4550 +Wire Wire Line + 8250 3900 8250 4550 +Wire Wire Line + 8250 4550 8100 4550 +Wire Wire Line + 8750 2250 8750 4850 +Wire Wire Line + 8750 4850 8500 4850 +Wire Wire Line + 10150 2500 10150 5700 +Wire Wire Line + 7500 1750 7500 2500 +Wire Wire Line + 4900 3050 4900 3200 +Wire Wire Line + 4900 3200 5150 3200 +Wire Wire Line + 4900 3750 4900 4350 +Wire Wire Line + 4900 4350 5150 4350 +Wire Wire Line + 3800 1900 4100 1900 +Wire Wire Line + 3850 1350 3850 1700 +Wire Wire Line + 3850 1700 4100 1700 +Wire Wire Line + 5000 1350 5000 1550 +Wire Wire Line + 5000 1550 4350 1550 +Wire Wire Line + 4350 1550 4350 1900 +Wire Wire Line + 4950 1900 5050 1900 +Wire Wire Line + 5050 1250 5050 2050 +Wire Wire Line + 5050 1250 4950 1250 +Wire Wire Line + 4950 1250 4950 1150 +Wire Wire Line + 6100 1150 6100 1550 +Wire Wire Line + 6100 1550 5300 1550 +Wire Wire Line + 5300 1550 5300 1900 +Wire Wire Line + 5300 1900 5950 1900 +Wire Wire Line + 5800 2700 5800 2050 +Wire Wire Line + 5800 2050 5050 2050 +Connection ~ 5050 1900 +Wire Wire Line + 6750 1000 6750 1200 +Wire Wire Line + 6750 1200 7050 1200 +Connection ~ 6900 1900 +Wire Wire Line + 7900 1000 7900 1150 +Wire Wire Line + 7900 1150 7600 1150 +Wire Wire Line + 7600 1150 7600 1350 +Wire Wire Line + 8150 1650 8150 1750 +Wire Wire Line + 8150 1750 7500 1750 +Wire Wire Line + 8750 1350 8750 1700 +Wire Wire Line + 8750 1700 8250 1700 +Wire Wire Line + 8250 1700 8250 1850 +Wire Wire Line + 8250 1850 8100 1850 +Wire Wire Line + 8100 1850 8100 1900 +$Comp +L dac_bridge_1 U16 +U 1 1 68486D53 +P 6950 3550 +F 0 "U16" H 6950 3550 60 0000 C CNN +F 1 "dac_bridge_1" H 6950 3700 60 0000 C CNN +F 2 "" H 6950 3550 60 0000 C CNN +F 3 "" H 6950 3550 60 0000 C CNN + 1 6950 3550 + -1 0 0 1 +$EndComp +Wire Wire Line + 7550 3600 7550 3400 +Wire Wire Line + 7550 3400 7600 3400 +Wire Wire Line + 6400 3600 6400 3400 +Wire Wire Line + 6400 3400 6800 3400 +$Comp +L dac_bridge_1 U21 +U 1 1 6848795B +P 10050 1600 +F 0 "U21" H 10050 1600 60 0000 C CNN +F 1 "dac_bridge_1" H 10050 1750 60 0000 C CNN +F 2 "" H 10050 1600 60 0000 C CNN +F 3 "" H 10050 1600 60 0000 C CNN + 1 10050 1600 + 1 0 0 -1 +$EndComp +Wire Wire Line + 9400 1900 9400 1550 +Wire Wire Line + 9400 1550 9450 1550 +Wire Wire Line + 10600 1550 10600 1850 +Wire Wire Line + 10600 1850 10650 1850 +Wire Wire Line + 1250 4500 1250 4850 +Wire Wire Line + 1250 4850 1300 4850 +Wire Wire Line + 1150 5500 1150 4950 +Wire Wire Line + 1150 4950 1300 4950 +$Comp +L adc_bridge_2 U12 +U 1 1 68488E6A +P 1900 4900 +F 0 "U12" H 1900 4900 60 0000 C CNN +F 1 "adc_bridge_2" H 1900 5050 60 0000 C CNN +F 2 "" H 1900 4900 60 0000 C CNN +F 3 "" H 1900 4900 60 0000 C CNN + 1 1900 4900 + 1 0 0 -1 +$EndComp +Wire Wire Line + 2300 4550 2300 4700 +Wire Wire Line + 2300 4700 2450 4700 +Wire Wire Line + 2450 4700 2450 4850 +Wire Wire Line + 2450 4950 2450 5350 +Wire Wire Line + 2450 5350 2300 5350 +Wire Wire Line + 2300 5350 2300 5700 +Wire Wire Line + 7050 1200 7050 1900 +Wire Wire Line + 8750 2800 7450 2800 +Wire Wire Line + 7450 2800 7450 2750 +Connection ~ 8750 2800 +$Comp +L adc_bridge_1 U20 +U 1 1 6848A427 +P 9450 3400 +F 0 "U20" H 9450 3400 60 0000 C CNN +F 1 "adc_bridge_1" H 9450 3550 60 0000 C CNN +F 2 "" H 9450 3400 60 0000 C CNN +F 3 "" H 9450 3400 60 0000 C CNN + 1 9450 3400 + 1 0 0 -1 +$EndComp +Wire Wire Line + 8200 3400 8500 3400 +Wire Wire Line + 8500 3400 8500 3350 +Wire Wire Line + 8500 3350 8850 3350 +Wire Wire Line + 10050 3350 10050 3150 +Wire Wire Line + 10050 3150 10400 3150 +Wire Wire Line + 10050 3350 10000 3350 +Wire Wire Line + 4500 2450 6300 2450 +$Comp +L dac_bridge_1 U22 +U 1 1 685455D5 +P 7500 5750 +F 0 "U22" H 7500 5750 60 0000 C CNN +F 1 "dac_bridge_1" H 7500 5900 60 0000 C CNN +F 2 "" H 7500 5750 60 0000 C CNN +F 3 "" H 7500 5750 60 0000 C CNN + 1 7500 5750 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5350 5700 6900 5700 +Wire Wire Line + 10150 5700 8050 5700 +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/Failed IC'S/CD4024BC/CD4024BC.sub b/library/SubcircuitLibrary/Failed IC'S/CD4024BC/CD4024BC.sub new file mode 100644 index 000000000..136c05a55 --- /dev/null +++ b/library/SubcircuitLibrary/Failed IC'S/CD4024BC/CD4024BC.sub @@ -0,0 +1,100 @@ +* Subcircuit CD4024BC +.subckt CD4024BC vdd gnd net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_m1-pad1_ net-_u1-pad7_ +* c:\fossee\esim\library\subcircuitlibrary\cd4024bc\cd4024bc.cir +.include PMOS-180nm.lib +.include NMOS-180nm.lib +* u2 net-_u12-pad3_ net-_u2-pad2_ net-_u2-pad3_ d_tristate +m2 net-_m1-pad3_ net-_m2-pad2_ net-_m1-pad1_ vdd CMOSP W=100u L=100u M=1 +m1 net-_m1-pad1_ net-_m1-pad2_ net-_m1-pad3_ gnd CMOSN W=100u L=100u M=1 +m4 net-_m3-pad3_ net-_m2-pad2_ net-_m1-pad3_ vdd CMOSP W=100u L=100u M=1 +m3 net-_m1-pad3_ net-_m1-pad2_ net-_m3-pad3_ gnd CMOSN W=100u L=100u M=1 +m5 net-_m5-pad1_ net-_m2-pad2_ net-_m5-pad3_ vdd CMOSP W=100u L=100u M=1 +m6 net-_m5-pad3_ net-_m5-pad3_ net-_m5-pad1_ gnd CMOSN W=100u L=100u M=1 +m8 net-_m7-pad3_ net-_m5-pad3_ net-_m5-pad3_ gnd CMOSN W=100u L=100u M=1 +m7 net-_m5-pad3_ net-_m2-pad2_ net-_m7-pad3_ vdd CMOSP W=100u L=100u M=1 +* u3 net-_u15-pad1_ net-_u22-pad2_ net-_u14-pad1_ d_tristate +* u4 net-_u17-pad2_ net-_u22-pad2_ net-_u10-pad1_ d_tristate +* u7 net-_u2-pad3_ net-_m1-pad2_ d_inverter +* u8 net-_u5-pad2_ net-_u2-pad2_ d_inverter +* u5 net-_u12-pad4_ net-_u5-pad2_ d_inverter +* u9 net-_m1-pad2_ net-_u18-pad1_ d_inverter +* u10 net-_u10-pad1_ net-_u10-pad2_ d_inverter +* u11 net-_u10-pad1_ net-_u11-pad2_ d_inverter +* u6 net-_u13-pad2_ net-_u15-pad1_ d_inverter +* u18 net-_u18-pad1_ net-_m2-pad2_ dac_bridge_1 +* u19 net-_m1-pad2_ net-_m5-pad3_ dac_bridge_1 +* u14 net-_u14-pad1_ net-_m3-pad3_ dac_bridge_1 +* u13 net-_m1-pad3_ net-_u13-pad2_ adc_bridge_1 +* u15 net-_u15-pad1_ net-_m5-pad1_ dac_bridge_1 +* u17 net-_m5-pad3_ net-_u17-pad2_ adc_bridge_1 +* u16 net-_u10-pad2_ net-_m7-pad3_ dac_bridge_1 +* u21 net-_u11-pad2_ net-_u1-pad5_ dac_bridge_1 +* u12 net-_u1-pad3_ net-_u1-pad4_ net-_u12-pad3_ net-_u12-pad4_ adc_bridge_2 +* u20 net-_u10-pad1_ net-_u1-pad7_ adc_bridge_1 +* u22 net-_u2-pad2_ net-_u22-pad2_ dac_bridge_1 +a1 net-_u12-pad3_ net-_u2-pad2_ net-_u2-pad3_ u2 +a2 net-_u15-pad1_ net-_u22-pad2_ net-_u14-pad1_ u3 +a3 net-_u17-pad2_ net-_u22-pad2_ net-_u10-pad1_ u4 +a4 net-_u2-pad3_ net-_m1-pad2_ u7 +a5 net-_u5-pad2_ net-_u2-pad2_ u8 +a6 net-_u12-pad4_ net-_u5-pad2_ u5 +a7 net-_m1-pad2_ net-_u18-pad1_ u9 +a8 net-_u10-pad1_ net-_u10-pad2_ u10 +a9 net-_u10-pad1_ net-_u11-pad2_ u11 +a10 net-_u13-pad2_ net-_u15-pad1_ u6 +a11 [net-_u18-pad1_ ] [net-_m2-pad2_ ] u18 +a12 [net-_m1-pad2_ ] [net-_m5-pad3_ ] u19 +a13 [net-_u14-pad1_ ] [net-_m3-pad3_ ] u14 +a14 [net-_m1-pad3_ ] [net-_u13-pad2_ ] u13 +a15 [net-_u15-pad1_ ] [net-_m5-pad1_ ] u15 +a16 [net-_m5-pad3_ ] [net-_u17-pad2_ ] u17 +a17 [net-_u10-pad2_ ] [net-_m7-pad3_ ] u16 +a18 [net-_u11-pad2_ ] [net-_u1-pad5_ ] u21 +a19 [net-_u1-pad3_ net-_u1-pad4_ ] [net-_u12-pad3_ net-_u12-pad4_ ] u12 +a20 [net-_u10-pad1_ ] [net-_u1-pad7_ ] u20 +a21 [net-_u2-pad2_ ] [net-_u22-pad2_ ] u22 +* Schematic Name: d_tristate, NgSpice Name: d_tristate +.model u2 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 ) +* Schematic Name: d_tristate, NgSpice Name: d_tristate +.model u3 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 ) +* Schematic Name: d_tristate, NgSpice Name: d_tristate +.model u4 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u7 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u8 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u5 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u9 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u10 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u11 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge +.model u18 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge +.model u19 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge +.model u14 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: adc_bridge_1, NgSpice Name: adc_bridge +.model u13 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge +.model u15 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: adc_bridge_1, NgSpice Name: adc_bridge +.model u17 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge +.model u16 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge +.model u21 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: adc_bridge_2, NgSpice Name: adc_bridge +.model u12 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: adc_bridge_1, NgSpice Name: adc_bridge +.model u20 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge +.model u22 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Control Statements + +.ends CD4024BC \ No newline at end of file diff --git a/library/SubcircuitLibrary/Failed IC'S/CD4024BC/CD4024BC_Previous_Values.xml b/library/SubcircuitLibrary/Failed IC'S/CD4024BC/CD4024BC_Previous_Values.xml new file mode 100644 index 000000000..765cb99d7 --- /dev/null +++ b/library/SubcircuitLibrary/Failed IC'S/CD4024BC/CD4024BC_Previous_Values.xml @@ -0,0 +1 @@ +d_tristated_tristated_tristated_inverterd_inverterd_inverterd_inverterd_inverterd_inverterd_inverterdac_bridgedac_bridgedac_bridgeadc_bridgedac_bridgeadc_bridgedac_bridgedac_bridgeadc_bridgeadc_bridgedac_bridgeC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libtruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperessecsecsec \ No newline at end of file diff --git a/library/SubcircuitLibrary/Failed IC'S/CD4024BC/NMOS-180nm.lib b/library/SubcircuitLibrary/Failed IC'S/CD4024BC/NMOS-180nm.lib new file mode 100644 index 000000000..51e9b1196 --- /dev/null +++ b/library/SubcircuitLibrary/Failed IC'S/CD4024BC/NMOS-180nm.lib @@ -0,0 +1,13 @@ +.model CMOSN NMOS (LEVEL=8 VERSION=3.2 TNOM=27 TOX=4.1E-9 XJ=1E-7 NCH=2.3549E17 VTH0=0.3823463 K1=0.5810697 ++ K2=4.774618E-3 K3=0.0431669 K3B=1.1498346 W0=1E-7 NLX=1.910552E-7 DVT0W=0 DVT1W=0 DVT2W=0 ++ DVT0=1.2894824 DVT1=0.3622063 DVT2=0.0713729 U0=280.633249 UA=-1.208537E-9 UB=2.158625E-18 ++ UC=5.342807E-11 VSAT=9.366802E4 A0=1.7593146 AGS=0.3939741 B0=-6.413949E-9 B1=-1E-7 KETA=-5.180424E-4 ++ A1=0 A2=1 RDSW=105.5517558 PRWG=0.5 PRWB=-0.1998871 WR=1 WINT=7.904732E-10 LINT=1.571424E-8 XL=0 ++ XW=-1E-8 DWG=1.297221E-9 DWB=1.479041E-9 VOFF=-0.0955434 NFACTOR=2.4358891 CIT=0 CDSC=2.4E-4 CDSCD=0 ++ CDSCB=0 ETA0=3.104851E-3 ETAB=-2.512384E-5 DSUB=0.0167075 PCLM=0.8073191 PDIBLC1=0.1666161 PDIBLC2=3.112892E-3 ++ PDIBLCB=-0.1 DROUT=0.7875618 PSCBE1=8E10 PSCBE2=9.213635E-10 PVAG=3.85243E-3 DELTA=0.01 RSH=6.7 MOBMOD=1 ++ PRT=0 UTE=-1.5 KT1=-0.11 KT1L=0 KT2=0.022 UA1=4.31E-9 UB1=-7.61E-18 UC1=-5.6E-11 AT=3.3E4 WL=0 WLN=1 ++ WW=0 WWN=1 WWL=0 LL=0 LLN=1 LW=0 LWN=1 LWL=0 CAPMOD=2 XPART=0.5 CGDO=7.08E-10 CGSO=7.08E-10 CGBO=1E-12 ++ CJ=9.68858E-4 PB=0.8 MJ=0.3864502 CJSW=2.512138E-10 PBSW=0.809286 MJSW=0.1060414 CJSWG=3.3E-10 PBSWG=0.809286 ++ MJSWG=0.1060414 CF=0 PVTH0=-1.192722E-3 PRDSW=-5 PK2=6.450505E-5 WKETA=-4.27294E-4 LKETA=-0.0104078 ++ PU0=6.3268729 PUA=2.226552E-11 PUB=0 PVSAT=969.1480157 PETA0=1E-4 PKETA=-1.049509E-3) diff --git a/library/SubcircuitLibrary/Failed IC'S/CD4024BC/PMOS-180nm.lib b/library/SubcircuitLibrary/Failed IC'S/CD4024BC/PMOS-180nm.lib new file mode 100644 index 000000000..032b5b95e --- /dev/null +++ b/library/SubcircuitLibrary/Failed IC'S/CD4024BC/PMOS-180nm.lib @@ -0,0 +1,11 @@ +.model CMOSP PMOS (LEVEL=8 VERSION=3.2 TNOM=27 TOX=4.1E-9 XJ=1E-7 NCH=4.1589E17 VTH0=-0.3938813 K1=0.5479015 ++ K2=0.0360586 K3=0.0993095 K3B=5.7086622 W0=1E-6 NLX=1.313191E-7 DVT0W=0 DVT1W=0 DVT2W=0 DVT0=0.4911363 ++ DVT1=0.2227356 DVT2=0.1 U0=115.6852975 UA=1.505832E-9 UB=1E-21 UC=-1E-10 VSAT=1.329694E5 A0=1.7590478 ++ AGS=0.3641621 B0=3.427126E-7 B1=1.062928E-6 KETA=0.0134667 A1=0.6859506 A2=0.3506788 RDSW=168.5705677 ++ PRWG=0.5 PRWB=-0.4987371 WR=1 WINT=0 LINT=3.028832E-8 XL=0 XW=-1E-8 DWG=-2.349633E-8 DWB=-7.152486E-9 ++ VOFF=-0.0994037 NFACTOR=1.9424315 CIT=0 CDSC=2.4E-4 CDSCD=0 CDSCB=0 ETA0=0.0608072 ETAB=-0.0426148 ++ DSUB=0.7343015 PCLM=3.2579974 PDIBLC1=7.229527E-6 PDIBLC2=0.025389 PDIBLCB=-1E-3 DROUT=0 PSCBE1=1.454878E10 ++ PSCBE2=4.202027E-9 PVAG=15 DELTA=0.01 RSH=7.8 MOBMOD=1 PRT=0 UTE=-1.5 KT1=-0.11 KT1L=0 KT2=0.022 UA1=4.31E-9 ++ UB1=-7.61E-18 UC1=-5.6E-11 AT=3.3E4 WL=0 WLN=1 WW=0 WWN=1 WWL=0 LL=0 LLN=1 LW=0 LWN=1 LWL=0 CAPMOD=2 XPART=0.5 ++ CGDO=6.32E-10 CGSO=6.32E-10 CGBO=1E-12 CJ=1.172138E-3 PB=0.8421173 MJ=0.4109788 CJSW=2.242609E-10 PBSW=0.8 + MJSW=0.3752089 CJSWG=4.22E-10 PBSWG=0.8 MJSWG=0.3752089 CF=0 PVTH0=1.888482E-3 PRDSW=11.5315407 PK2=1.559399E-3 ++ WKETA=0.0319301 LKETA=2.955547E-3 PU0=-1.1105313 PUA=-4.62102E-11 PUB=1E-21 PVSAT=50 PETA0=1E-4 PKETA=-4.346368E-3) diff --git a/library/SubcircuitLibrary/Failed IC'S/CD4024BC/analysis b/library/SubcircuitLibrary/Failed IC'S/CD4024BC/analysis new file mode 100644 index 000000000..ebd5c0a94 --- /dev/null +++ b/library/SubcircuitLibrary/Failed IC'S/CD4024BC/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00 \ No newline at end of file diff --git a/library/SubcircuitLibrary/Failed IC'S/CD4724BC/3_and-cache.lib b/library/SubcircuitLibrary/Failed IC'S/CD4724BC/3_and-cache.lib new file mode 100644 index 000000000..af0586415 --- /dev/null +++ b/library/SubcircuitLibrary/Failed IC'S/CD4724BC/3_and-cache.lib @@ -0,0 +1,61 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/Failed IC'S/CD4724BC/3_and.cir b/library/SubcircuitLibrary/Failed IC'S/CD4724BC/3_and.cir new file mode 100644 index 000000000..ba296cf01 --- /dev/null +++ b/library/SubcircuitLibrary/Failed IC'S/CD4724BC/3_and.cir @@ -0,0 +1,13 @@ +* C:\Users\malli\eSim\src\SubcircuitLibrary\3_and\3_and.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 18:42:57 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U2 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_and +U3 Net-_U2-Pad3_ Net-_U1-Pad3_ Net-_U1-Pad4_ d_and +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ PORT + +.end diff --git a/library/SubcircuitLibrary/Failed IC'S/CD4724BC/3_and.cir.out b/library/SubcircuitLibrary/Failed IC'S/CD4724BC/3_and.cir.out new file mode 100644 index 000000000..d7cf79a07 --- /dev/null +++ b/library/SubcircuitLibrary/Failed IC'S/CD4724BC/3_and.cir.out @@ -0,0 +1,20 @@ +* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir + +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and +* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ port +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/Failed IC'S/CD4724BC/3_and.pro b/library/SubcircuitLibrary/Failed IC'S/CD4724BC/3_and.pro new file mode 100644 index 000000000..00597a5ad --- /dev/null +++ b/library/SubcircuitLibrary/Failed IC'S/CD4724BC/3_and.pro @@ -0,0 +1,43 @@ +update=05/31/19 15:26:09 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir=../../../kicadSchematicLibrary +[eeschema/libraries] +LibName1=eSim_Analog +LibName2=eSim_Devices +LibName3=eSim_Digital +LibName4=eSim_Hybrid +LibName5=eSim_Miscellaneous +LibName6=eSim_Plot +LibName7=eSim_Power +LibName8=eSim_User +LibName9=eSim_Sources +LibName10=eSim_Subckt diff --git a/library/SubcircuitLibrary/Failed IC'S/CD4724BC/3_and.sch b/library/SubcircuitLibrary/Failed IC'S/CD4724BC/3_and.sch new file mode 100644 index 000000000..d6ac89f95 --- /dev/null +++ b/library/SubcircuitLibrary/Failed IC'S/CD4724BC/3_and.sch @@ -0,0 +1,130 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_PSpice +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +LIBS:3_and-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_and U2 +U 1 1 5C9A24D8 +P 4250 2700 +F 0 "U2" H 4250 2700 60 0000 C CNN +F 1 "d_and" H 4300 2800 60 0000 C CNN +F 2 "" H 4250 2700 60 0000 C CNN +F 3 "" H 4250 2700 60 0000 C CNN + 1 4250 2700 + 1 0 0 -1 +$EndComp +$Comp +L d_and U3 +U 1 1 5C9A2538 +P 5150 2900 +F 0 "U3" H 5150 2900 60 0000 C CNN +F 1 "d_and" H 5200 3000 60 0000 C CNN +F 2 "" H 5150 2900 60 0000 C CNN +F 3 "" H 5150 2900 60 0000 C CNN + 1 5150 2900 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 5C9A259A +P 3050 2600 +F 0 "U1" H 3100 2700 30 0000 C CNN +F 1 "PORT" H 3050 2600 30 0000 C CNN +F 2 "" H 3050 2600 60 0000 C CNN +F 3 "" H 3050 2600 60 0000 C CNN + 1 3050 2600 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5C9A25D9 +P 3050 2800 +F 0 "U1" H 3100 2900 30 0000 C CNN +F 1 "PORT" H 3050 2800 30 0000 C CNN +F 2 "" H 3050 2800 60 0000 C CNN +F 3 "" H 3050 2800 60 0000 C CNN + 2 3050 2800 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5C9A260A +P 3050 3100 +F 0 "U1" H 3100 3200 30 0000 C CNN +F 1 "PORT" H 3050 3100 30 0000 C CNN +F 2 "" H 3050 3100 60 0000 C CNN +F 3 "" H 3050 3100 60 0000 C CNN + 3 3050 3100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5C9A2637 +P 6900 2850 +F 0 "U1" H 6950 2950 30 0000 C CNN +F 1 "PORT" H 6900 2850 30 0000 C CNN +F 2 "" H 6900 2850 60 0000 C CNN +F 3 "" H 6900 2850 60 0000 C CNN + 4 6900 2850 + -1 0 0 1 +$EndComp +Wire Wire Line + 4700 2650 4700 2800 +Wire Wire Line + 5600 2850 6650 2850 +Wire Wire Line + 3800 2600 3300 2600 +Wire Wire Line + 3800 2700 3300 2700 +Wire Wire Line + 3300 2700 3300 2800 +Wire Wire Line + 3300 3100 4700 3100 +Wire Wire Line + 4700 3100 4700 2900 +Text Notes 3500 2600 0 60 ~ 12 +in1 +Text Notes 3450 2800 0 60 ~ 12 +in2\n +Text Notes 3500 3100 0 60 ~ 12 +in3 +Text Notes 6100 2850 0 60 ~ 12 +out +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/Failed IC'S/CD4724BC/3_and.sub b/library/SubcircuitLibrary/Failed IC'S/CD4724BC/3_and.sub new file mode 100644 index 000000000..3d9120bb6 --- /dev/null +++ b/library/SubcircuitLibrary/Failed IC'S/CD4724BC/3_and.sub @@ -0,0 +1,14 @@ +* Subcircuit 3_and +.subckt 3_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ +* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and +* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends 3_and \ No newline at end of file diff --git a/library/SubcircuitLibrary/Failed IC'S/CD4724BC/3_and_Previous_Values.xml b/library/SubcircuitLibrary/Failed IC'S/CD4724BC/3_and_Previous_Values.xml new file mode 100644 index 000000000..abc5faaae --- /dev/null +++ b/library/SubcircuitLibrary/Failed IC'S/CD4724BC/3_and_Previous_Values.xml @@ -0,0 +1 @@ +d_andd_andtruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesSecSecSec \ No newline at end of file diff --git a/library/SubcircuitLibrary/Failed IC'S/CD4724BC/CD4724BC-cache.lib b/library/SubcircuitLibrary/Failed IC'S/CD4724BC/CD4724BC-cache.lib new file mode 100644 index 000000000..73197eac6 --- /dev/null +++ b/library/SubcircuitLibrary/Failed IC'S/CD4724BC/CD4724BC-cache.lib @@ -0,0 +1,126 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# 3_and +# +DEF 3_and X 0 40 Y Y 1 F N +F0 "X" 100 -50 60 H V C CNN +F1 "3_and" 150 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 150 50 158 716 -716 0 1 0 N 200 200 200 -100 +P 2 0 1 0 -150 200 200 200 N +P 3 0 1 0 -150 200 -150 -100 200 -100 N +X in1 1 -350 150 200 R 50 50 1 1 I +X in2 2 -350 50 200 R 50 50 1 1 I +X in3 3 -350 -50 200 R 50 50 1 1 I +X out 4 500 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_buffer +# +DEF d_buffer U 0 40 Y Y 1 F N +F0 "U" 0 -50 60 H V C CNN +F1 "d_buffer" 0 50 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +P 4 0 1 0 -300 200 -300 -200 450 0 -300 200 N +X IN 1 -500 0 200 R 50 50 1 1 I +X OUT 2 650 0 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_inverter +# +DEF d_inverter U 0 40 Y Y 1 F N +F0 "U" 0 -100 60 H V C CNN +F1 "d_inverter" 0 150 60 H V C CNN +F2 "" 50 -50 60 H V C CNN +F3 "" 50 -50 60 H V C CNN +DRAW +P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N +X ~ 1 -300 0 200 R 50 50 1 1 I +X ~ 2 300 0 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# d_nand +# +DEF d_nand U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_nand" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# d_or +# +DEF d_or U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_or" 0 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 +A -25 -124 325 574 323 0 1 0 N 150 150 250 50 +A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 +P 2 0 1 0 -250 -50 150 -50 N +P 2 0 1 0 -250 150 150 150 N +X IN1 1 -450 100 215 R 50 50 1 1 I +X IN2 2 -450 0 215 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/Failed IC'S/CD4724BC/CD4724BC.cir b/library/SubcircuitLibrary/Failed IC'S/CD4724BC/CD4724BC.cir new file mode 100644 index 000000000..f33d02a4a --- /dev/null +++ b/library/SubcircuitLibrary/Failed IC'S/CD4724BC/CD4724BC.cir @@ -0,0 +1,118 @@ +* C:\FOSSEE\eSim\library\SubcircuitLibrary\CD4724BC\CD4724BC.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 06/19/25 16:51:05 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U11 Net-_U1-Pad4_ Net-_U11-Pad2_ d_inverter +U18 Net-_U11-Pad2_ Net-_U18-Pad2_ d_inverter +U12 Net-_U1-Pad5_ Net-_U12-Pad2_ d_inverter +U19 Net-_U12-Pad2_ Net-_U1-Pad6_ Net-_U19-Pad3_ d_nand +U20 Net-_U19-Pad3_ Net-_U12-Pad2_ Net-_U20-Pad3_ d_nand +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U1-Pad14_ PORT +U58 Net-_U31-Pad3_ Net-_U32-Pad3_ Net-_U39-Pad1_ d_nand +U32 Net-_U18-Pad2_ Net-_U32-Pad2_ Net-_U32-Pad3_ d_or +U31 Net-_U19-Pad3_ Net-_U31-Pad2_ Net-_U31-Pad3_ d_or +U39 Net-_U39-Pad1_ Net-_U39-Pad2_ d_buffer +U62 Net-_U39-Pad2_ Net-_U42-Pad3_ Net-_U62-Pad3_ d_nand +U42 Net-_U31-Pad2_ Net-_U20-Pad3_ Net-_U42-Pad3_ d_or +U72 Net-_U62-Pad3_ Net-_U1-Pad7_ d_inverter +U59 Net-_U33-Pad3_ Net-_U34-Pad3_ Net-_U40-Pad1_ d_nand +U34 Net-_U18-Pad2_ Net-_U34-Pad2_ Net-_U34-Pad3_ d_or +U33 Net-_U19-Pad3_ Net-_U33-Pad2_ Net-_U33-Pad3_ d_or +U40 Net-_U40-Pad1_ Net-_U40-Pad2_ d_buffer +U63 Net-_U40-Pad2_ Net-_U43-Pad3_ Net-_U100-Pad1_ d_nand +U43 Net-_U33-Pad2_ Net-_U20-Pad3_ Net-_U43-Pad3_ d_or +U73 Net-_U100-Pad1_ Net-_U1-Pad8_ d_inverter +U56 Net-_U27-Pad3_ Net-_U28-Pad3_ Net-_U30-Pad1_ d_nand +U28 Net-_U18-Pad2_ Net-_U28-Pad2_ Net-_U28-Pad3_ d_or +U27 Net-_U19-Pad3_ Net-_U10-Pad2_ Net-_U27-Pad3_ d_or +U30 Net-_U30-Pad1_ Net-_U30-Pad2_ d_buffer +U60 Net-_U30-Pad2_ Net-_U36-Pad3_ Net-_U60-Pad3_ d_nand +U36 Net-_U10-Pad2_ Net-_U20-Pad3_ Net-_U36-Pad3_ d_or +U71 Net-_U60-Pad3_ Net-_U1-Pad9_ d_inverter +U53 Net-_U21-Pad3_ Net-_U22-Pad3_ Net-_U23-Pad1_ d_nand +U22 Net-_U18-Pad2_ Net-_U22-Pad2_ Net-_U22-Pad3_ d_or +U21 Net-_U19-Pad3_ Net-_U13-Pad2_ Net-_U21-Pad3_ d_or +U23 Net-_U23-Pad1_ Net-_U23-Pad2_ d_buffer +U54 Net-_U23-Pad2_ Net-_U24-Pad3_ Net-_U54-Pad3_ d_nand +U24 Net-_U13-Pad2_ Net-_U20-Pad3_ Net-_U24-Pad3_ d_or +U69 Net-_U54-Pad3_ Net-_U1-Pad10_ d_inverter +U55 Net-_U25-Pad3_ Net-_U26-Pad3_ Net-_U29-Pad1_ d_nand +U26 Net-_U18-Pad2_ Net-_U26-Pad2_ Net-_U26-Pad3_ d_or +U25 Net-_U19-Pad3_ Net-_U14-Pad2_ Net-_U25-Pad3_ d_or +U29 Net-_U29-Pad1_ Net-_U29-Pad2_ d_buffer +U57 Net-_U29-Pad2_ Net-_U35-Pad3_ Net-_U57-Pad3_ d_nand +U35 Net-_U14-Pad2_ Net-_U20-Pad3_ Net-_U35-Pad3_ d_or +U70 Net-_U57-Pad3_ Net-_U1-Pad11_ d_inverter +U61 Net-_U37-Pad3_ Net-_U38-Pad3_ Net-_U41-Pad1_ d_nand +U38 Net-_U18-Pad2_ Net-_U38-Pad2_ Net-_U38-Pad3_ d_or +U37 Net-_U19-Pad3_ Net-_U15-Pad2_ Net-_U37-Pad3_ d_or +U41 Net-_U41-Pad1_ Net-_U41-Pad2_ d_buffer +U64 Net-_U41-Pad2_ Net-_U44-Pad3_ Net-_U64-Pad3_ d_nand +U44 Net-_U15-Pad2_ Net-_U20-Pad3_ Net-_U44-Pad3_ d_or +U74 Net-_U64-Pad3_ Net-_U1-Pad12_ d_inverter +U65 Net-_U45-Pad3_ Net-_U46-Pad3_ Net-_U47-Pad1_ d_nand +U46 Net-_U18-Pad2_ Net-_U46-Pad2_ Net-_U46-Pad3_ d_or +U45 Net-_U19-Pad3_ Net-_U16-Pad2_ Net-_U45-Pad3_ d_or +U47 Net-_U47-Pad1_ Net-_U47-Pad2_ d_buffer +U66 Net-_U47-Pad2_ Net-_U48-Pad3_ Net-_U66-Pad3_ d_nand +U48 Net-_U16-Pad2_ Net-_U20-Pad3_ Net-_U48-Pad3_ d_or +U75 Net-_U66-Pad3_ Net-_U1-Pad13_ d_inverter +U67 Net-_U49-Pad3_ Net-_U50-Pad3_ Net-_U51-Pad1_ d_nand +U50 Net-_U18-Pad2_ Net-_U50-Pad2_ Net-_U50-Pad3_ d_or +U49 Net-_U19-Pad3_ Net-_U17-Pad2_ Net-_U49-Pad3_ d_or +U51 Net-_U51-Pad1_ Net-_U51-Pad2_ d_buffer +U68 Net-_U51-Pad2_ Net-_U52-Pad3_ Net-_U68-Pad3_ d_nand +U52 Net-_U17-Pad2_ Net-_U20-Pad3_ Net-_U52-Pad3_ d_or +U76 Net-_U68-Pad3_ Net-_U1-Pad14_ d_inverter +U2 Net-_U1-Pad1_ Net-_U2-Pad2_ d_inverter +U3 Net-_U2-Pad2_ Net-_U3-Pad2_ d_inverter +U4 Net-_U1-Pad2_ Net-_U4-Pad2_ d_inverter +U5 Net-_U4-Pad2_ Net-_U5-Pad2_ d_inverter +U6 Net-_U1-Pad3_ Net-_U6-Pad2_ d_inverter +U7 Net-_U6-Pad2_ Net-_U7-Pad2_ d_inverter +X1 Net-_U6-Pad2_ Net-_U4-Pad2_ Net-_U2-Pad2_ Net-_U8-Pad1_ 3_and +X2 Net-_U7-Pad2_ Net-_U4-Pad2_ Net-_U2-Pad2_ Net-_U9-Pad1_ 3_and +X3 Net-_U6-Pad2_ Net-_U5-Pad2_ Net-_U2-Pad2_ Net-_U10-Pad1_ 3_and +X4 Net-_U7-Pad2_ Net-_U5-Pad2_ Net-_U2-Pad2_ Net-_U13-Pad1_ 3_and +X5 Net-_U6-Pad2_ Net-_U4-Pad2_ Net-_U3-Pad2_ Net-_U14-Pad1_ 3_and +X6 Net-_U7-Pad2_ Net-_U4-Pad2_ Net-_U3-Pad2_ Net-_U15-Pad1_ 3_and +X7 Net-_U6-Pad2_ Net-_U5-Pad2_ Net-_U3-Pad2_ Net-_U16-Pad1_ 3_and +X8 Net-_U7-Pad2_ Net-_U5-Pad2_ Net-_U3-Pad2_ Net-_U17-Pad1_ 3_and +U8 Net-_U8-Pad1_ Net-_U31-Pad2_ d_inverter +U9 Net-_U9-Pad1_ Net-_U33-Pad2_ d_inverter +U10 Net-_U10-Pad1_ Net-_U10-Pad2_ d_inverter +U13 Net-_U13-Pad1_ Net-_U13-Pad2_ d_inverter +U14 Net-_U14-Pad1_ Net-_U14-Pad2_ d_inverter +U15 Net-_U15-Pad1_ Net-_U15-Pad2_ d_inverter +U16 Net-_U16-Pad1_ Net-_U16-Pad2_ d_inverter +U17 Net-_U17-Pad1_ Net-_U17-Pad2_ d_inverter +U81 Net-_U39-Pad1_ IC +U86 Net-_U40-Pad1_ IC +U82 Net-_U30-Pad1_ IC +U77 Net-_U23-Pad1_ IC +U79 Net-_U29-Pad1_ IC +U84 Net-_U41-Pad1_ IC +U89 Net-_U47-Pad1_ IC +U90 Net-_U51-Pad1_ IC +U80 Net-_U62-Pad3_ Net-_U32-Pad2_ d_buffer +U98 Net-_U100-Pad1_ Net-_U34-Pad2_ d_buffer +U83 Net-_U60-Pad3_ Net-_U28-Pad2_ d_buffer +U78 Net-_U54-Pad3_ Net-_U22-Pad2_ d_buffer +U85 Net-_U57-Pad3_ Net-_U26-Pad2_ d_buffer +U87 Net-_U64-Pad3_ Net-_U38-Pad2_ d_buffer +U91 Net-_U66-Pad3_ Net-_U46-Pad2_ d_buffer +U96 Net-_U68-Pad3_ Net-_U50-Pad2_ d_buffer +U99 Net-_U68-Pad3_ IC +U97 Net-_U66-Pad3_ IC +U95 Net-_U64-Pad3_ IC +U92 Net-_U57-Pad3_ IC +U88 Net-_U54-Pad3_ IC +U93 Net-_U60-Pad3_ IC +U100 Net-_U100-Pad1_ IC +U94 Net-_U62-Pad3_ IC + +.end diff --git a/library/SubcircuitLibrary/Failed IC'S/CD4724BC/CD4724BC.cir.out b/library/SubcircuitLibrary/Failed IC'S/CD4724BC/CD4724BC.cir.out new file mode 100644 index 000000000..5ebdb71bb --- /dev/null +++ b/library/SubcircuitLibrary/Failed IC'S/CD4724BC/CD4724BC.cir.out @@ -0,0 +1,401 @@ +* c:\fossee\esim\library\subcircuitlibrary\cd4724bc\cd4724bc.cir + +.include 3_and.sub +* u94 net-_u62-pad3_ ic +.ic v(net-_u62-pad3_)=0 +* u100 net-_u100-pad1_ ic +.ic v(net-_u100-pad1_)=0 +* u93 net-_u60-pad3_ ic +.ic v(net-_u60-pad3_)=0 +* u88 net-_u54-pad3_ ic +.ic v(net-_u54-pad3_)=0 +* u92 net-_u57-pad3_ ic +.ic v(net-_u57-pad3_)=0 +* u95 net-_u64-pad3_ ic +.ic v(net-_u64-pad3_)=0 +* u97 net-_u66-pad3_ ic +.ic v(net-_u66-pad3_)=0 +* u99 net-_u68-pad3_ ic +.ic v(net-_u68-pad3_)=0 +* u90 net-_u51-pad1_ ic +.ic v(net-_u51-pad1_)=5 +* u89 net-_u47-pad1_ ic +.ic v(net-_u47-pad1_)=5 +* u84 net-_u41-pad1_ ic +.ic v(net-_u41-pad1_)=5 +* u79 net-_u29-pad1_ ic +.ic v(net-_u29-pad1_)=5 +* u77 net-_u23-pad1_ ic +.ic v(net-_u23-pad1_)=5 +* u82 net-_u30-pad1_ ic +.ic v(net-_u30-pad1_)=5 +* u86 net-_u40-pad1_ ic +.ic v(net-_u40-pad1_)=5 +* u81 net-_u39-pad1_ ic +.ic v(net-_u39-pad1_)=5 +* u11 net-_u1-pad4_ net-_u11-pad2_ d_inverter +* u18 net-_u11-pad2_ net-_u18-pad2_ d_inverter +* u12 net-_u1-pad5_ net-_u12-pad2_ d_inverter +* u19 net-_u12-pad2_ net-_u1-pad6_ net-_u19-pad3_ d_nand +* u20 net-_u19-pad3_ net-_u12-pad2_ net-_u20-pad3_ d_nand +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ port +* u58 net-_u31-pad3_ net-_u32-pad3_ net-_u39-pad1_ d_nand +* u32 net-_u18-pad2_ net-_u32-pad2_ net-_u32-pad3_ d_or +* u31 net-_u19-pad3_ net-_u31-pad2_ net-_u31-pad3_ d_or +* u39 net-_u39-pad1_ net-_u39-pad2_ d_buffer +* u62 net-_u39-pad2_ net-_u42-pad3_ net-_u62-pad3_ d_nand +* u42 net-_u31-pad2_ net-_u20-pad3_ net-_u42-pad3_ d_or +* u72 net-_u62-pad3_ net-_u1-pad7_ d_inverter +* u59 net-_u33-pad3_ net-_u34-pad3_ net-_u40-pad1_ d_nand +* u34 net-_u18-pad2_ net-_u34-pad2_ net-_u34-pad3_ d_or +* u33 net-_u19-pad3_ net-_u33-pad2_ net-_u33-pad3_ d_or +* u40 net-_u40-pad1_ net-_u40-pad2_ d_buffer +* u63 net-_u40-pad2_ net-_u43-pad3_ net-_u100-pad1_ d_nand +* u43 net-_u33-pad2_ net-_u20-pad3_ net-_u43-pad3_ d_or +* u73 net-_u100-pad1_ net-_u1-pad8_ d_inverter +* u56 net-_u27-pad3_ net-_u28-pad3_ net-_u30-pad1_ d_nand +* u28 net-_u18-pad2_ net-_u28-pad2_ net-_u28-pad3_ d_or +* u27 net-_u19-pad3_ net-_u10-pad2_ net-_u27-pad3_ d_or +* u30 net-_u30-pad1_ net-_u30-pad2_ d_buffer +* u60 net-_u30-pad2_ net-_u36-pad3_ net-_u60-pad3_ d_nand +* u36 net-_u10-pad2_ net-_u20-pad3_ net-_u36-pad3_ d_or +* u71 net-_u60-pad3_ net-_u1-pad9_ d_inverter +* u53 net-_u21-pad3_ net-_u22-pad3_ net-_u23-pad1_ d_nand +* u22 net-_u18-pad2_ net-_u22-pad2_ net-_u22-pad3_ d_or +* u21 net-_u19-pad3_ net-_u13-pad2_ net-_u21-pad3_ d_or +* u23 net-_u23-pad1_ net-_u23-pad2_ d_buffer +* u54 net-_u23-pad2_ net-_u24-pad3_ net-_u54-pad3_ d_nand +* u24 net-_u13-pad2_ net-_u20-pad3_ net-_u24-pad3_ d_or +* u69 net-_u54-pad3_ net-_u1-pad10_ d_inverter +* u55 net-_u25-pad3_ net-_u26-pad3_ net-_u29-pad1_ d_nand +* u26 net-_u18-pad2_ net-_u26-pad2_ net-_u26-pad3_ d_or +* u25 net-_u19-pad3_ net-_u14-pad2_ net-_u25-pad3_ d_or +* u29 net-_u29-pad1_ net-_u29-pad2_ d_buffer +* u57 net-_u29-pad2_ net-_u35-pad3_ net-_u57-pad3_ d_nand +* u35 net-_u14-pad2_ net-_u20-pad3_ net-_u35-pad3_ d_or +* u70 net-_u57-pad3_ net-_u1-pad11_ d_inverter +* u61 net-_u37-pad3_ net-_u38-pad3_ net-_u41-pad1_ d_nand +* u38 net-_u18-pad2_ net-_u38-pad2_ net-_u38-pad3_ d_or +* u37 net-_u19-pad3_ net-_u15-pad2_ net-_u37-pad3_ d_or +* u41 net-_u41-pad1_ net-_u41-pad2_ d_buffer +* u64 net-_u41-pad2_ net-_u44-pad3_ net-_u64-pad3_ d_nand +* u44 net-_u15-pad2_ net-_u20-pad3_ net-_u44-pad3_ d_or +* u74 net-_u64-pad3_ net-_u1-pad12_ d_inverter +* u65 net-_u45-pad3_ net-_u46-pad3_ net-_u47-pad1_ d_nand +* u46 net-_u18-pad2_ net-_u46-pad2_ net-_u46-pad3_ d_or +* u45 net-_u19-pad3_ net-_u16-pad2_ net-_u45-pad3_ d_or +* u47 net-_u47-pad1_ net-_u47-pad2_ d_buffer +* u66 net-_u47-pad2_ net-_u48-pad3_ net-_u66-pad3_ d_nand +* u48 net-_u16-pad2_ net-_u20-pad3_ net-_u48-pad3_ d_or +* u75 net-_u66-pad3_ net-_u1-pad13_ d_inverter +* u67 net-_u49-pad3_ net-_u50-pad3_ net-_u51-pad1_ d_nand +* u50 net-_u18-pad2_ net-_u50-pad2_ net-_u50-pad3_ d_or +* u49 net-_u19-pad3_ net-_u17-pad2_ net-_u49-pad3_ d_or +* u51 net-_u51-pad1_ net-_u51-pad2_ d_buffer +* u68 net-_u51-pad2_ net-_u52-pad3_ net-_u68-pad3_ d_nand +* u52 net-_u17-pad2_ net-_u20-pad3_ net-_u52-pad3_ d_or +* u76 net-_u68-pad3_ net-_u1-pad14_ d_inverter +* u2 net-_u1-pad1_ net-_u2-pad2_ d_inverter +* u3 net-_u2-pad2_ net-_u3-pad2_ d_inverter +* u4 net-_u1-pad2_ net-_u4-pad2_ d_inverter +* u5 net-_u4-pad2_ net-_u5-pad2_ d_inverter +* u6 net-_u1-pad3_ net-_u6-pad2_ d_inverter +* u7 net-_u6-pad2_ net-_u7-pad2_ d_inverter +x1 net-_u6-pad2_ net-_u4-pad2_ net-_u2-pad2_ net-_u8-pad1_ 3_and +x2 net-_u7-pad2_ net-_u4-pad2_ net-_u2-pad2_ net-_u9-pad1_ 3_and +x3 net-_u6-pad2_ net-_u5-pad2_ net-_u2-pad2_ net-_u10-pad1_ 3_and +x4 net-_u7-pad2_ net-_u5-pad2_ net-_u2-pad2_ net-_u13-pad1_ 3_and +x5 net-_u6-pad2_ net-_u4-pad2_ net-_u3-pad2_ net-_u14-pad1_ 3_and +x6 net-_u7-pad2_ net-_u4-pad2_ net-_u3-pad2_ net-_u15-pad1_ 3_and +x7 net-_u6-pad2_ net-_u5-pad2_ net-_u3-pad2_ net-_u16-pad1_ 3_and +x8 net-_u7-pad2_ net-_u5-pad2_ net-_u3-pad2_ net-_u17-pad1_ 3_and +* u8 net-_u8-pad1_ net-_u31-pad2_ d_inverter +* u9 net-_u9-pad1_ net-_u33-pad2_ d_inverter +* u10 net-_u10-pad1_ net-_u10-pad2_ d_inverter +* u13 net-_u13-pad1_ net-_u13-pad2_ d_inverter +* u14 net-_u14-pad1_ net-_u14-pad2_ d_inverter +* u15 net-_u15-pad1_ net-_u15-pad2_ d_inverter +* u16 net-_u16-pad1_ net-_u16-pad2_ d_inverter +* u17 net-_u17-pad1_ net-_u17-pad2_ d_inverter +* u81 net-_u39-pad1_ ic +* u86 net-_u40-pad1_ ic +* u82 net-_u30-pad1_ ic +* u77 net-_u23-pad1_ ic +* u79 net-_u29-pad1_ ic +* u84 net-_u41-pad1_ ic +* u89 net-_u47-pad1_ ic +* u90 net-_u51-pad1_ ic +* u80 net-_u62-pad3_ net-_u32-pad2_ d_buffer +* u98 net-_u100-pad1_ net-_u34-pad2_ d_buffer +* u83 net-_u60-pad3_ net-_u28-pad2_ d_buffer +* u78 net-_u54-pad3_ net-_u22-pad2_ d_buffer +* u85 net-_u57-pad3_ net-_u26-pad2_ d_buffer +* u87 net-_u64-pad3_ net-_u38-pad2_ d_buffer +* u91 net-_u66-pad3_ net-_u46-pad2_ d_buffer +* u96 net-_u68-pad3_ net-_u50-pad2_ d_buffer +* u99 net-_u68-pad3_ ic +* u97 net-_u66-pad3_ ic +* u95 net-_u64-pad3_ ic +* u92 net-_u57-pad3_ ic +* u88 net-_u54-pad3_ ic +* u93 net-_u60-pad3_ ic +* u100 net-_u100-pad1_ ic +* u94 net-_u62-pad3_ ic +a1 net-_u1-pad4_ net-_u11-pad2_ u11 +a2 net-_u11-pad2_ net-_u18-pad2_ u18 +a3 net-_u1-pad5_ net-_u12-pad2_ u12 +a4 [net-_u12-pad2_ net-_u1-pad6_ ] net-_u19-pad3_ u19 +a5 [net-_u19-pad3_ net-_u12-pad2_ ] net-_u20-pad3_ u20 +a6 [net-_u31-pad3_ net-_u32-pad3_ ] net-_u39-pad1_ u58 +a7 [net-_u18-pad2_ net-_u32-pad2_ ] net-_u32-pad3_ u32 +a8 [net-_u19-pad3_ net-_u31-pad2_ ] net-_u31-pad3_ u31 +a9 net-_u39-pad1_ net-_u39-pad2_ u39 +a10 [net-_u39-pad2_ net-_u42-pad3_ ] net-_u62-pad3_ u62 +a11 [net-_u31-pad2_ net-_u20-pad3_ ] net-_u42-pad3_ u42 +a12 net-_u62-pad3_ net-_u1-pad7_ u72 +a13 [net-_u33-pad3_ net-_u34-pad3_ ] net-_u40-pad1_ u59 +a14 [net-_u18-pad2_ net-_u34-pad2_ ] net-_u34-pad3_ u34 +a15 [net-_u19-pad3_ net-_u33-pad2_ ] net-_u33-pad3_ u33 +a16 net-_u40-pad1_ net-_u40-pad2_ u40 +a17 [net-_u40-pad2_ net-_u43-pad3_ ] net-_u100-pad1_ u63 +a18 [net-_u33-pad2_ net-_u20-pad3_ ] net-_u43-pad3_ u43 +a19 net-_u100-pad1_ net-_u1-pad8_ u73 +a20 [net-_u27-pad3_ net-_u28-pad3_ ] net-_u30-pad1_ u56 +a21 [net-_u18-pad2_ net-_u28-pad2_ ] net-_u28-pad3_ u28 +a22 [net-_u19-pad3_ net-_u10-pad2_ ] net-_u27-pad3_ u27 +a23 net-_u30-pad1_ net-_u30-pad2_ u30 +a24 [net-_u30-pad2_ net-_u36-pad3_ ] net-_u60-pad3_ u60 +a25 [net-_u10-pad2_ net-_u20-pad3_ ] net-_u36-pad3_ u36 +a26 net-_u60-pad3_ net-_u1-pad9_ u71 +a27 [net-_u21-pad3_ net-_u22-pad3_ ] net-_u23-pad1_ u53 +a28 [net-_u18-pad2_ net-_u22-pad2_ ] net-_u22-pad3_ u22 +a29 [net-_u19-pad3_ net-_u13-pad2_ ] net-_u21-pad3_ u21 +a30 net-_u23-pad1_ net-_u23-pad2_ u23 +a31 [net-_u23-pad2_ net-_u24-pad3_ ] net-_u54-pad3_ u54 +a32 [net-_u13-pad2_ net-_u20-pad3_ ] net-_u24-pad3_ u24 +a33 net-_u54-pad3_ net-_u1-pad10_ u69 +a34 [net-_u25-pad3_ net-_u26-pad3_ ] net-_u29-pad1_ u55 +a35 [net-_u18-pad2_ net-_u26-pad2_ ] net-_u26-pad3_ u26 +a36 [net-_u19-pad3_ net-_u14-pad2_ ] net-_u25-pad3_ u25 +a37 net-_u29-pad1_ net-_u29-pad2_ u29 +a38 [net-_u29-pad2_ net-_u35-pad3_ ] net-_u57-pad3_ u57 +a39 [net-_u14-pad2_ net-_u20-pad3_ ] net-_u35-pad3_ u35 +a40 net-_u57-pad3_ net-_u1-pad11_ u70 +a41 [net-_u37-pad3_ net-_u38-pad3_ ] net-_u41-pad1_ u61 +a42 [net-_u18-pad2_ net-_u38-pad2_ ] net-_u38-pad3_ u38 +a43 [net-_u19-pad3_ net-_u15-pad2_ ] net-_u37-pad3_ u37 +a44 net-_u41-pad1_ net-_u41-pad2_ u41 +a45 [net-_u41-pad2_ net-_u44-pad3_ ] net-_u64-pad3_ u64 +a46 [net-_u15-pad2_ net-_u20-pad3_ ] net-_u44-pad3_ u44 +a47 net-_u64-pad3_ net-_u1-pad12_ u74 +a48 [net-_u45-pad3_ net-_u46-pad3_ ] net-_u47-pad1_ u65 +a49 [net-_u18-pad2_ net-_u46-pad2_ ] net-_u46-pad3_ u46 +a50 [net-_u19-pad3_ net-_u16-pad2_ ] net-_u45-pad3_ u45 +a51 net-_u47-pad1_ net-_u47-pad2_ u47 +a52 [net-_u47-pad2_ net-_u48-pad3_ ] net-_u66-pad3_ u66 +a53 [net-_u16-pad2_ net-_u20-pad3_ ] net-_u48-pad3_ u48 +a54 net-_u66-pad3_ net-_u1-pad13_ u75 +a55 [net-_u49-pad3_ net-_u50-pad3_ ] net-_u51-pad1_ u67 +a56 [net-_u18-pad2_ net-_u50-pad2_ ] net-_u50-pad3_ u50 +a57 [net-_u19-pad3_ net-_u17-pad2_ ] net-_u49-pad3_ u49 +a58 net-_u51-pad1_ net-_u51-pad2_ u51 +a59 [net-_u51-pad2_ net-_u52-pad3_ ] net-_u68-pad3_ u68 +a60 [net-_u17-pad2_ net-_u20-pad3_ ] net-_u52-pad3_ u52 +a61 net-_u68-pad3_ net-_u1-pad14_ u76 +a62 net-_u1-pad1_ net-_u2-pad2_ u2 +a63 net-_u2-pad2_ net-_u3-pad2_ u3 +a64 net-_u1-pad2_ net-_u4-pad2_ u4 +a65 net-_u4-pad2_ net-_u5-pad2_ u5 +a66 net-_u1-pad3_ net-_u6-pad2_ u6 +a67 net-_u6-pad2_ net-_u7-pad2_ u7 +a68 net-_u8-pad1_ net-_u31-pad2_ u8 +a69 net-_u9-pad1_ net-_u33-pad2_ u9 +a70 net-_u10-pad1_ net-_u10-pad2_ u10 +a71 net-_u13-pad1_ net-_u13-pad2_ u13 +a72 net-_u14-pad1_ net-_u14-pad2_ u14 +a73 net-_u15-pad1_ net-_u15-pad2_ u15 +a74 net-_u16-pad1_ net-_u16-pad2_ u16 +a75 net-_u17-pad1_ net-_u17-pad2_ u17 +a76 net-_u62-pad3_ net-_u32-pad2_ u80 +a77 net-_u100-pad1_ net-_u34-pad2_ u98 +a78 net-_u60-pad3_ net-_u28-pad2_ u83 +a79 net-_u54-pad3_ net-_u22-pad2_ u78 +a80 net-_u57-pad3_ net-_u26-pad2_ u85 +a81 net-_u64-pad3_ net-_u38-pad2_ u87 +a82 net-_u66-pad3_ net-_u46-pad2_ u91 +a83 net-_u68-pad3_ net-_u50-pad2_ u96 +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u11 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u18 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u12 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u19 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u20 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u58 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u32 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u31 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u39 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u62 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u42 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u72 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u59 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u34 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u33 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u40 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u63 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u43 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u73 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u56 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u28 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u27 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u30 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u60 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u36 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u71 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u53 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u22 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u21 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u23 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u54 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u24 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u69 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u55 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u26 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u25 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u29 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u57 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u35 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u70 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u61 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u38 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u37 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u41 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u64 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u44 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u74 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u65 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u46 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u45 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u47 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u66 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u48 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u75 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u67 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u50 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u49 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u51 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u68 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u52 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u76 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u4 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u5 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u7 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u8 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u9 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u10 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u13 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u14 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u15 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u16 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u17 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u80 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u98 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u83 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u78 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u85 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u87 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u91 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u96 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/Failed IC'S/CD4724BC/CD4724BC.pro b/library/SubcircuitLibrary/Failed IC'S/CD4724BC/CD4724BC.pro new file mode 100644 index 000000000..e27a398be --- /dev/null +++ b/library/SubcircuitLibrary/Failed IC'S/CD4724BC/CD4724BC.pro @@ -0,0 +1,73 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts diff --git a/library/SubcircuitLibrary/Failed IC'S/CD4724BC/CD4724BC.sch b/library/SubcircuitLibrary/Failed IC'S/CD4724BC/CD4724BC.sch new file mode 100644 index 000000000..eebf3dda5 --- /dev/null +++ b/library/SubcircuitLibrary/Failed IC'S/CD4724BC/CD4724BC.sch @@ -0,0 +1,1756 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +LIBS:CD4724BC-cache +EELAYER 25 0 +EELAYER END +$Descr A0 46811 33110 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_inverter U11 +U 1 1 6847D178 +P 19450 5800 +F 0 "U11" H 19450 5700 60 0000 C CNN +F 1 "d_inverter" H 19450 5950 60 0000 C CNN +F 2 "" H 19500 5750 60 0000 C CNN +F 3 "" H 19500 5750 60 0000 C CNN + 1 19450 5800 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U18 +U 1 1 6847D1A2 +P 20350 5800 +F 0 "U18" H 20350 5700 60 0000 C CNN +F 1 "d_inverter" H 20350 5950 60 0000 C CNN +F 2 "" H 20400 5750 60 0000 C CNN +F 3 "" H 20400 5750 60 0000 C CNN + 1 20350 5800 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U12 +U 1 1 6847D1CC +P 19500 6300 +F 0 "U12" H 19500 6200 60 0000 C CNN +F 1 "d_inverter" H 19500 6450 60 0000 C CNN +F 2 "" H 19550 6250 60 0000 C CNN +F 3 "" H 19550 6250 60 0000 C CNN + 1 19500 6300 + 1 0 0 -1 +$EndComp +$Comp +L d_nand U19 +U 1 1 6847D1F0 +P 20650 6400 +F 0 "U19" H 20650 6400 60 0000 C CNN +F 1 "d_nand" H 20700 6500 60 0000 C CNN +F 2 "" H 20650 6400 60 0000 C CNN +F 3 "" H 20650 6400 60 0000 C CNN + 1 20650 6400 + 1 0 0 -1 +$EndComp +$Comp +L d_nand U20 +U 1 1 6847D21D +P 22050 6450 +F 0 "U20" H 22050 6450 60 0000 C CNN +F 1 "d_nand" H 22100 6550 60 0000 C CNN +F 2 "" H 22050 6450 60 0000 C CNN +F 3 "" H 22050 6450 60 0000 C CNN + 1 22050 6450 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 6847D352 +P 18300 5800 +F 0 "U1" H 18350 5900 30 0000 C CNN +F 1 "PORT" H 18300 5800 30 0000 C CNN +F 2 "" H 18300 5800 60 0000 C CNN +F 3 "" H 18300 5800 60 0000 C CNN + 4 18300 5800 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 6847D454 +P 18350 6300 +F 0 "U1" H 18400 6400 30 0000 C CNN +F 1 "PORT" H 18350 6300 30 0000 C CNN +F 2 "" H 18350 6300 60 0000 C CNN +F 3 "" H 18350 6300 60 0000 C CNN + 5 18350 6300 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 6 1 6847D54A +P 18350 6700 +F 0 "U1" H 18400 6800 30 0000 C CNN +F 1 "PORT" H 18350 6700 30 0000 C CNN +F 2 "" H 18350 6700 60 0000 C CNN +F 3 "" H 18350 6700 60 0000 C CNN + 6 18350 6700 + 1 0 0 -1 +$EndComp +$Comp +L d_nand U58 +U 1 1 6847D796 +P 25750 5400 +F 0 "U58" H 25750 5400 60 0000 C CNN +F 1 "d_nand" H 25800 5500 60 0000 C CNN +F 2 "" H 25750 5400 60 0000 C CNN +F 3 "" H 25750 5400 60 0000 C CNN + 1 25750 5400 + 1 0 0 -1 +$EndComp +$Comp +L d_or U32 +U 1 1 6847DC17 +P 24000 5900 +F 0 "U32" H 24000 5900 60 0000 C CNN +F 1 "d_or" H 24000 6000 60 0000 C CNN +F 2 "" H 24000 5900 60 0000 C CNN +F 3 "" H 24000 5900 60 0000 C CNN + 1 24000 5900 + 1 0 0 -1 +$EndComp +$Comp +L d_or U31 +U 1 1 6847DD16 +P 24000 5300 +F 0 "U31" H 24000 5300 60 0000 C CNN +F 1 "d_or" H 24000 5400 60 0000 C CNN +F 2 "" H 24000 5300 60 0000 C CNN +F 3 "" H 24000 5300 60 0000 C CNN + 1 24000 5300 + 1 0 0 -1 +$EndComp +$Comp +L d_buffer U39 +U 1 1 6847DEB1 +P 24100 6800 +F 0 "U39" H 24100 6750 60 0000 C CNN +F 1 "d_buffer" H 24100 6850 60 0000 C CNN +F 2 "" H 24100 6800 60 0000 C CNN +F 3 "" H 24100 6800 60 0000 C CNN + 1 24100 6800 + 1 0 0 -1 +$EndComp +$Comp +L d_nand U62 +U 1 1 6847DF58 +P 25950 7100 +F 0 "U62" H 25950 7100 60 0000 C CNN +F 1 "d_nand" H 26000 7200 60 0000 C CNN +F 2 "" H 25950 7100 60 0000 C CNN +F 3 "" H 25950 7100 60 0000 C CNN + 1 25950 7100 + 1 0 0 -1 +$EndComp +$Comp +L d_or U42 +U 1 1 6847DFEB +P 24250 7500 +F 0 "U42" H 24250 7500 60 0000 C CNN +F 1 "d_or" H 24250 7600 60 0000 C CNN +F 2 "" H 24250 7500 60 0000 C CNN +F 3 "" H 24250 7500 60 0000 C CNN + 1 24250 7500 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U72 +U 1 1 6847E0B1 +P 27400 7050 +F 0 "U72" H 27400 6950 60 0000 C CNN +F 1 "d_inverter" H 27400 7200 60 0000 C CNN +F 2 "" H 27450 7000 60 0000 C CNN +F 3 "" H 27450 7000 60 0000 C CNN + 1 27400 7050 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 10 1 6847E5A4 +P 28000 15350 +F 0 "U1" H 28050 15450 30 0000 C CNN +F 1 "PORT" H 28000 15350 30 0000 C CNN +F 2 "" H 28000 15350 60 0000 C CNN +F 3 "" H 28000 15350 60 0000 C CNN + 10 28000 15350 + -1 0 0 1 +$EndComp +$Comp +L d_nand U59 +U 1 1 6847EC08 +P 25750 8100 +F 0 "U59" H 25750 8100 60 0000 C CNN +F 1 "d_nand" H 25800 8200 60 0000 C CNN +F 2 "" H 25750 8100 60 0000 C CNN +F 3 "" H 25750 8100 60 0000 C CNN + 1 25750 8100 + 1 0 0 -1 +$EndComp +$Comp +L d_or U34 +U 1 1 6847EC0F +P 24000 8600 +F 0 "U34" H 24000 8600 60 0000 C CNN +F 1 "d_or" H 24000 8700 60 0000 C CNN +F 2 "" H 24000 8600 60 0000 C CNN +F 3 "" H 24000 8600 60 0000 C CNN + 1 24000 8600 + 1 0 0 -1 +$EndComp +$Comp +L d_or U33 +U 1 1 6847EC15 +P 24000 8000 +F 0 "U33" H 24000 8000 60 0000 C CNN +F 1 "d_or" H 24000 8100 60 0000 C CNN +F 2 "" H 24000 8000 60 0000 C CNN +F 3 "" H 24000 8000 60 0000 C CNN + 1 24000 8000 + 1 0 0 -1 +$EndComp +$Comp +L d_buffer U40 +U 1 1 6847EC20 +P 24100 9500 +F 0 "U40" H 24100 9450 60 0000 C CNN +F 1 "d_buffer" H 24100 9550 60 0000 C CNN +F 2 "" H 24100 9500 60 0000 C CNN +F 3 "" H 24100 9500 60 0000 C CNN + 1 24100 9500 + 1 0 0 -1 +$EndComp +$Comp +L d_nand U63 +U 1 1 6847EC26 +P 25950 9800 +F 0 "U63" H 25950 9800 60 0000 C CNN +F 1 "d_nand" H 26000 9900 60 0000 C CNN +F 2 "" H 25950 9800 60 0000 C CNN +F 3 "" H 25950 9800 60 0000 C CNN + 1 25950 9800 + 1 0 0 -1 +$EndComp +$Comp +L d_or U43 +U 1 1 6847EC2C +P 24250 10200 +F 0 "U43" H 24250 10200 60 0000 C CNN +F 1 "d_or" H 24250 10300 60 0000 C CNN +F 2 "" H 24250 10200 60 0000 C CNN +F 3 "" H 24250 10200 60 0000 C CNN + 1 24250 10200 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U73 +U 1 1 6847EC32 +P 27400 9750 +F 0 "U73" H 27400 9650 60 0000 C CNN +F 1 "d_inverter" H 27400 9900 60 0000 C CNN +F 2 "" H 27450 9700 60 0000 C CNN +F 3 "" H 27450 9700 60 0000 C CNN + 1 27400 9750 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 11 1 6847EC4B +P 28300 18150 +F 0 "U1" H 28350 18250 30 0000 C CNN +F 1 "PORT" H 28300 18150 30 0000 C CNN +F 2 "" H 28300 18150 60 0000 C CNN +F 3 "" H 28300 18150 60 0000 C CNN + 11 28300 18150 + -1 0 0 1 +$EndComp +$Comp +L d_nand U56 +U 1 1 6847F94F +P 25550 10900 +F 0 "U56" H 25550 10900 60 0000 C CNN +F 1 "d_nand" H 25600 11000 60 0000 C CNN +F 2 "" H 25550 10900 60 0000 C CNN +F 3 "" H 25550 10900 60 0000 C CNN + 1 25550 10900 + 1 0 0 -1 +$EndComp +$Comp +L d_or U28 +U 1 1 6847F955 +P 23800 11400 +F 0 "U28" H 23800 11400 60 0000 C CNN +F 1 "d_or" H 23800 11500 60 0000 C CNN +F 2 "" H 23800 11400 60 0000 C CNN +F 3 "" H 23800 11400 60 0000 C CNN + 1 23800 11400 + 1 0 0 -1 +$EndComp +$Comp +L d_or U27 +U 1 1 6847F95B +P 23800 10800 +F 0 "U27" H 23800 10800 60 0000 C CNN +F 1 "d_or" H 23800 10900 60 0000 C CNN +F 2 "" H 23800 10800 60 0000 C CNN +F 3 "" H 23800 10800 60 0000 C CNN + 1 23800 10800 + 1 0 0 -1 +$EndComp +$Comp +L d_buffer U30 +U 1 1 6847F961 +P 23900 12300 +F 0 "U30" H 23900 12250 60 0000 C CNN +F 1 "d_buffer" H 23900 12350 60 0000 C CNN +F 2 "" H 23900 12300 60 0000 C CNN +F 3 "" H 23900 12300 60 0000 C CNN + 1 23900 12300 + 1 0 0 -1 +$EndComp +$Comp +L d_nand U60 +U 1 1 6847F967 +P 25750 12600 +F 0 "U60" H 25750 12600 60 0000 C CNN +F 1 "d_nand" H 25800 12700 60 0000 C CNN +F 2 "" H 25750 12600 60 0000 C CNN +F 3 "" H 25750 12600 60 0000 C CNN + 1 25750 12600 + 1 0 0 -1 +$EndComp +$Comp +L d_or U36 +U 1 1 6847F96D +P 24050 13000 +F 0 "U36" H 24050 13000 60 0000 C CNN +F 1 "d_or" H 24050 13100 60 0000 C CNN +F 2 "" H 24050 13000 60 0000 C CNN +F 3 "" H 24050 13000 60 0000 C CNN + 1 24050 13000 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U71 +U 1 1 6847F973 +P 27200 12550 +F 0 "U71" H 27200 12450 60 0000 C CNN +F 1 "d_inverter" H 27200 12700 60 0000 C CNN +F 2 "" H 27250 12500 60 0000 C CNN +F 3 "" H 27250 12500 60 0000 C CNN + 1 27200 12550 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 9 1 6847F979 +P 28350 12550 +F 0 "U1" H 28400 12650 30 0000 C CNN +F 1 "PORT" H 28350 12550 30 0000 C CNN +F 2 "" H 28350 12550 60 0000 C CNN +F 3 "" H 28350 12550 60 0000 C CNN + 9 28350 12550 + -1 0 0 1 +$EndComp +$Comp +L d_nand U53 +U 1 1 68480C52 +P 25200 13700 +F 0 "U53" H 25200 13700 60 0000 C CNN +F 1 "d_nand" H 25250 13800 60 0000 C CNN +F 2 "" H 25200 13700 60 0000 C CNN +F 3 "" H 25200 13700 60 0000 C CNN + 1 25200 13700 + 1 0 0 -1 +$EndComp +$Comp +L d_or U22 +U 1 1 68480C58 +P 23450 14200 +F 0 "U22" H 23450 14200 60 0000 C CNN +F 1 "d_or" H 23450 14300 60 0000 C CNN +F 2 "" H 23450 14200 60 0000 C CNN +F 3 "" H 23450 14200 60 0000 C CNN + 1 23450 14200 + 1 0 0 -1 +$EndComp +$Comp +L d_or U21 +U 1 1 68480C5E +P 23450 13600 +F 0 "U21" H 23450 13600 60 0000 C CNN +F 1 "d_or" H 23450 13700 60 0000 C CNN +F 2 "" H 23450 13600 60 0000 C CNN +F 3 "" H 23450 13600 60 0000 C CNN + 1 23450 13600 + 1 0 0 -1 +$EndComp +$Comp +L d_buffer U23 +U 1 1 68480C64 +P 23550 15100 +F 0 "U23" H 23550 15050 60 0000 C CNN +F 1 "d_buffer" H 23550 15150 60 0000 C CNN +F 2 "" H 23550 15100 60 0000 C CNN +F 3 "" H 23550 15100 60 0000 C CNN + 1 23550 15100 + 1 0 0 -1 +$EndComp +$Comp +L d_nand U54 +U 1 1 68480C6A +P 25400 15400 +F 0 "U54" H 25400 15400 60 0000 C CNN +F 1 "d_nand" H 25450 15500 60 0000 C CNN +F 2 "" H 25400 15400 60 0000 C CNN +F 3 "" H 25400 15400 60 0000 C CNN + 1 25400 15400 + 1 0 0 -1 +$EndComp +$Comp +L d_or U24 +U 1 1 68480C70 +P 23700 15800 +F 0 "U24" H 23700 15800 60 0000 C CNN +F 1 "d_or" H 23700 15900 60 0000 C CNN +F 2 "" H 23700 15800 60 0000 C CNN +F 3 "" H 23700 15800 60 0000 C CNN + 1 23700 15800 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U69 +U 1 1 68480C76 +P 26850 15350 +F 0 "U69" H 26850 15250 60 0000 C CNN +F 1 "d_inverter" H 26850 15500 60 0000 C CNN +F 2 "" H 26900 15300 60 0000 C CNN +F 3 "" H 26900 15300 60 0000 C CNN + 1 26850 15350 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 7 1 68480C7C +P 28550 7050 +F 0 "U1" H 28600 7150 30 0000 C CNN +F 1 "PORT" H 28550 7050 30 0000 C CNN +F 2 "" H 28550 7050 60 0000 C CNN +F 3 "" H 28550 7050 60 0000 C CNN + 7 28550 7050 + -1 0 0 1 +$EndComp +$Comp +L d_nand U55 +U 1 1 68483574 +P 25500 16500 +F 0 "U55" H 25500 16500 60 0000 C CNN +F 1 "d_nand" H 25550 16600 60 0000 C CNN +F 2 "" H 25500 16500 60 0000 C CNN +F 3 "" H 25500 16500 60 0000 C CNN + 1 25500 16500 + 1 0 0 -1 +$EndComp +$Comp +L d_or U26 +U 1 1 6848357A +P 23750 17000 +F 0 "U26" H 23750 17000 60 0000 C CNN +F 1 "d_or" H 23750 17100 60 0000 C CNN +F 2 "" H 23750 17000 60 0000 C CNN +F 3 "" H 23750 17000 60 0000 C CNN + 1 23750 17000 + 1 0 0 -1 +$EndComp +$Comp +L d_or U25 +U 1 1 68483580 +P 23750 16400 +F 0 "U25" H 23750 16400 60 0000 C CNN +F 1 "d_or" H 23750 16500 60 0000 C CNN +F 2 "" H 23750 16400 60 0000 C CNN +F 3 "" H 23750 16400 60 0000 C CNN + 1 23750 16400 + 1 0 0 -1 +$EndComp +$Comp +L d_buffer U29 +U 1 1 68483586 +P 23850 17900 +F 0 "U29" H 23850 17850 60 0000 C CNN +F 1 "d_buffer" H 23850 17950 60 0000 C CNN +F 2 "" H 23850 17900 60 0000 C CNN +F 3 "" H 23850 17900 60 0000 C CNN + 1 23850 17900 + 1 0 0 -1 +$EndComp +$Comp +L d_nand U57 +U 1 1 6848358C +P 25700 18200 +F 0 "U57" H 25700 18200 60 0000 C CNN +F 1 "d_nand" H 25750 18300 60 0000 C CNN +F 2 "" H 25700 18200 60 0000 C CNN +F 3 "" H 25700 18200 60 0000 C CNN + 1 25700 18200 + 1 0 0 -1 +$EndComp +$Comp +L d_or U35 +U 1 1 68483592 +P 24000 18600 +F 0 "U35" H 24000 18600 60 0000 C CNN +F 1 "d_or" H 24000 18700 60 0000 C CNN +F 2 "" H 24000 18600 60 0000 C CNN +F 3 "" H 24000 18600 60 0000 C CNN + 1 24000 18600 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U70 +U 1 1 68483598 +P 27150 18150 +F 0 "U70" H 27150 18050 60 0000 C CNN +F 1 "d_inverter" H 27150 18300 60 0000 C CNN +F 2 "" H 27200 18100 60 0000 C CNN +F 3 "" H 27200 18100 60 0000 C CNN + 1 27150 18150 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 8 1 6848359E +P 28550 9750 +F 0 "U1" H 28600 9850 30 0000 C CNN +F 1 "PORT" H 28550 9750 30 0000 C CNN +F 2 "" H 28550 9750 60 0000 C CNN +F 3 "" H 28550 9750 60 0000 C CNN + 8 28550 9750 + -1 0 0 1 +$EndComp +$Comp +L d_nand U61 +U 1 1 68484989 +P 25800 19400 +F 0 "U61" H 25800 19400 60 0000 C CNN +F 1 "d_nand" H 25850 19500 60 0000 C CNN +F 2 "" H 25800 19400 60 0000 C CNN +F 3 "" H 25800 19400 60 0000 C CNN + 1 25800 19400 + 1 0 0 -1 +$EndComp +$Comp +L d_or U38 +U 1 1 6848498F +P 24050 19900 +F 0 "U38" H 24050 19900 60 0000 C CNN +F 1 "d_or" H 24050 20000 60 0000 C CNN +F 2 "" H 24050 19900 60 0000 C CNN +F 3 "" H 24050 19900 60 0000 C CNN + 1 24050 19900 + 1 0 0 -1 +$EndComp +$Comp +L d_or U37 +U 1 1 68484995 +P 24050 19300 +F 0 "U37" H 24050 19300 60 0000 C CNN +F 1 "d_or" H 24050 19400 60 0000 C CNN +F 2 "" H 24050 19300 60 0000 C CNN +F 3 "" H 24050 19300 60 0000 C CNN + 1 24050 19300 + 1 0 0 -1 +$EndComp +$Comp +L d_buffer U41 +U 1 1 6848499B +P 24150 20800 +F 0 "U41" H 24150 20750 60 0000 C CNN +F 1 "d_buffer" H 24150 20850 60 0000 C CNN +F 2 "" H 24150 20800 60 0000 C CNN +F 3 "" H 24150 20800 60 0000 C CNN + 1 24150 20800 + 1 0 0 -1 +$EndComp +$Comp +L d_nand U64 +U 1 1 684849A1 +P 26000 21100 +F 0 "U64" H 26000 21100 60 0000 C CNN +F 1 "d_nand" H 26050 21200 60 0000 C CNN +F 2 "" H 26000 21100 60 0000 C CNN +F 3 "" H 26000 21100 60 0000 C CNN + 1 26000 21100 + 1 0 0 -1 +$EndComp +$Comp +L d_or U44 +U 1 1 684849A7 +P 24300 21500 +F 0 "U44" H 24300 21500 60 0000 C CNN +F 1 "d_or" H 24300 21600 60 0000 C CNN +F 2 "" H 24300 21500 60 0000 C CNN +F 3 "" H 24300 21500 60 0000 C CNN + 1 24300 21500 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U74 +U 1 1 684849AD +P 27450 21050 +F 0 "U74" H 27450 20950 60 0000 C CNN +F 1 "d_inverter" H 27450 21200 60 0000 C CNN +F 2 "" H 27500 21000 60 0000 C CNN +F 3 "" H 27500 21000 60 0000 C CNN + 1 27450 21050 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 12 1 684849B3 +P 28600 21050 +F 0 "U1" H 28650 21150 30 0000 C CNN +F 1 "PORT" H 28600 21050 30 0000 C CNN +F 2 "" H 28600 21050 60 0000 C CNN +F 3 "" H 28600 21050 60 0000 C CNN + 12 28600 21050 + -1 0 0 1 +$EndComp +$Comp +L d_nand U65 +U 1 1 68485679 +P 26200 22350 +F 0 "U65" H 26200 22350 60 0000 C CNN +F 1 "d_nand" H 26250 22450 60 0000 C CNN +F 2 "" H 26200 22350 60 0000 C CNN +F 3 "" H 26200 22350 60 0000 C CNN + 1 26200 22350 + 1 0 0 -1 +$EndComp +$Comp +L d_or U46 +U 1 1 6848567F +P 24450 22850 +F 0 "U46" H 24450 22850 60 0000 C CNN +F 1 "d_or" H 24450 22950 60 0000 C CNN +F 2 "" H 24450 22850 60 0000 C CNN +F 3 "" H 24450 22850 60 0000 C CNN + 1 24450 22850 + 1 0 0 -1 +$EndComp +$Comp +L d_or U45 +U 1 1 68485685 +P 24450 22250 +F 0 "U45" H 24450 22250 60 0000 C CNN +F 1 "d_or" H 24450 22350 60 0000 C CNN +F 2 "" H 24450 22250 60 0000 C CNN +F 3 "" H 24450 22250 60 0000 C CNN + 1 24450 22250 + 1 0 0 -1 +$EndComp +$Comp +L d_buffer U47 +U 1 1 6848568B +P 24550 23750 +F 0 "U47" H 24550 23700 60 0000 C CNN +F 1 "d_buffer" H 24550 23800 60 0000 C CNN +F 2 "" H 24550 23750 60 0000 C CNN +F 3 "" H 24550 23750 60 0000 C CNN + 1 24550 23750 + 1 0 0 -1 +$EndComp +$Comp +L d_nand U66 +U 1 1 68485691 +P 26400 24050 +F 0 "U66" H 26400 24050 60 0000 C CNN +F 1 "d_nand" H 26450 24150 60 0000 C CNN +F 2 "" H 26400 24050 60 0000 C CNN +F 3 "" H 26400 24050 60 0000 C CNN + 1 26400 24050 + 1 0 0 -1 +$EndComp +$Comp +L d_or U48 +U 1 1 68485697 +P 24700 24450 +F 0 "U48" H 24700 24450 60 0000 C CNN +F 1 "d_or" H 24700 24550 60 0000 C CNN +F 2 "" H 24700 24450 60 0000 C CNN +F 3 "" H 24700 24450 60 0000 C CNN + 1 24700 24450 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U75 +U 1 1 6848569D +P 27850 24000 +F 0 "U75" H 27850 23900 60 0000 C CNN +F 1 "d_inverter" H 27850 24150 60 0000 C CNN +F 2 "" H 27900 23950 60 0000 C CNN +F 3 "" H 27900 23950 60 0000 C CNN + 1 27850 24000 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 13 1 684856A3 +P 29000 24000 +F 0 "U1" H 29050 24100 30 0000 C CNN +F 1 "PORT" H 29000 24000 30 0000 C CNN +F 2 "" H 29000 24000 60 0000 C CNN +F 3 "" H 29000 24000 60 0000 C CNN + 13 29000 24000 + -1 0 0 1 +$EndComp +$Comp +L d_nand U67 +U 1 1 68486ED3 +P 26550 25150 +F 0 "U67" H 26550 25150 60 0000 C CNN +F 1 "d_nand" H 26600 25250 60 0000 C CNN +F 2 "" H 26550 25150 60 0000 C CNN +F 3 "" H 26550 25150 60 0000 C CNN + 1 26550 25150 + 1 0 0 -1 +$EndComp +$Comp +L d_or U50 +U 1 1 68486ED9 +P 24800 25650 +F 0 "U50" H 24800 25650 60 0000 C CNN +F 1 "d_or" H 24800 25750 60 0000 C CNN +F 2 "" H 24800 25650 60 0000 C CNN +F 3 "" H 24800 25650 60 0000 C CNN + 1 24800 25650 + 1 0 0 -1 +$EndComp +$Comp +L d_or U49 +U 1 1 68486EDF +P 24800 25050 +F 0 "U49" H 24800 25050 60 0000 C CNN +F 1 "d_or" H 24800 25150 60 0000 C CNN +F 2 "" H 24800 25050 60 0000 C CNN +F 3 "" H 24800 25050 60 0000 C CNN + 1 24800 25050 + 1 0 0 -1 +$EndComp +$Comp +L d_buffer U51 +U 1 1 68486EE5 +P 24900 26550 +F 0 "U51" H 24900 26500 60 0000 C CNN +F 1 "d_buffer" H 24900 26600 60 0000 C CNN +F 2 "" H 24900 26550 60 0000 C CNN +F 3 "" H 24900 26550 60 0000 C CNN + 1 24900 26550 + 1 0 0 -1 +$EndComp +$Comp +L d_nand U68 +U 1 1 68486EEB +P 26750 26850 +F 0 "U68" H 26750 26850 60 0000 C CNN +F 1 "d_nand" H 26800 26950 60 0000 C CNN +F 2 "" H 26750 26850 60 0000 C CNN +F 3 "" H 26750 26850 60 0000 C CNN + 1 26750 26850 + 1 0 0 -1 +$EndComp +$Comp +L d_or U52 +U 1 1 68486EF1 +P 25050 27250 +F 0 "U52" H 25050 27250 60 0000 C CNN +F 1 "d_or" H 25050 27350 60 0000 C CNN +F 2 "" H 25050 27250 60 0000 C CNN +F 3 "" H 25050 27250 60 0000 C CNN + 1 25050 27250 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U76 +U 1 1 68486EF7 +P 28200 26800 +F 0 "U76" H 28200 26700 60 0000 C CNN +F 1 "d_inverter" H 28200 26950 60 0000 C CNN +F 2 "" H 28250 26750 60 0000 C CNN +F 3 "" H 28250 26750 60 0000 C CNN + 1 28200 26800 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 14 1 68486EFD +P 29350 26800 +F 0 "U1" H 29400 26900 30 0000 C CNN +F 1 "PORT" H 29350 26800 30 0000 C CNN +F 2 "" H 29350 26800 60 0000 C CNN +F 3 "" H 29350 26800 60 0000 C CNN + 14 29350 26800 + -1 0 0 1 +$EndComp +$Comp +L d_inverter U2 +U 1 1 6848955F +P 14300 8500 +F 0 "U2" H 14300 8400 60 0000 C CNN +F 1 "d_inverter" H 14300 8650 60 0000 C CNN +F 2 "" H 14350 8450 60 0000 C CNN +F 3 "" H 14350 8450 60 0000 C CNN + 1 14300 8500 + 0 1 1 0 +$EndComp +$Comp +L d_inverter U3 +U 1 1 6848A7A5 +P 14300 9400 +F 0 "U3" H 14300 9300 60 0000 C CNN +F 1 "d_inverter" H 14300 9550 60 0000 C CNN +F 2 "" H 14350 9350 60 0000 C CNN +F 3 "" H 14350 9350 60 0000 C CNN + 1 14300 9400 + 0 1 1 0 +$EndComp +$Comp +L d_inverter U4 +U 1 1 6848AB69 +P 15450 8500 +F 0 "U4" H 15450 8400 60 0000 C CNN +F 1 "d_inverter" H 15450 8650 60 0000 C CNN +F 2 "" H 15500 8450 60 0000 C CNN +F 3 "" H 15500 8450 60 0000 C CNN + 1 15450 8500 + 0 1 1 0 +$EndComp +$Comp +L d_inverter U5 +U 1 1 6848AB6F +P 15450 9400 +F 0 "U5" H 15450 9300 60 0000 C CNN +F 1 "d_inverter" H 15450 9550 60 0000 C CNN +F 2 "" H 15500 9350 60 0000 C CNN +F 3 "" H 15500 9350 60 0000 C CNN + 1 15450 9400 + 0 1 1 0 +$EndComp +$Comp +L d_inverter U6 +U 1 1 6848AF72 +P 16300 8500 +F 0 "U6" H 16300 8400 60 0000 C CNN +F 1 "d_inverter" H 16300 8650 60 0000 C CNN +F 2 "" H 16350 8450 60 0000 C CNN +F 3 "" H 16350 8450 60 0000 C CNN + 1 16300 8500 + 0 1 1 0 +$EndComp +$Comp +L d_inverter U7 +U 1 1 6848AF78 +P 16300 9400 +F 0 "U7" H 16300 9300 60 0000 C CNN +F 1 "d_inverter" H 16300 9550 60 0000 C CNN +F 2 "" H 16350 9350 60 0000 C CNN +F 3 "" H 16350 9350 60 0000 C CNN + 1 16300 9400 + 0 1 1 0 +$EndComp +$Comp +L 3_and X1 +U 1 1 6848DB0E +P 18000 11850 +F 0 "X1" H 18100 11800 60 0000 C CNN +F 1 "3_and" H 18150 12000 60 0000 C CNN +F 2 "" H 18000 11850 60 0000 C CNN +F 3 "" H 18000 11850 60 0000 C CNN + 1 18000 11850 + 1 0 0 -1 +$EndComp +$Comp +L 3_and X2 +U 1 1 6848DC35 +P 18000 12650 +F 0 "X2" H 18100 12600 60 0000 C CNN +F 1 "3_and" H 18150 12800 60 0000 C CNN +F 2 "" H 18000 12650 60 0000 C CNN +F 3 "" H 18000 12650 60 0000 C CNN + 1 18000 12650 + 1 0 0 -1 +$EndComp +$Comp +L 3_and X3 +U 1 1 6848DD61 +P 18000 13350 +F 0 "X3" H 18100 13300 60 0000 C CNN +F 1 "3_and" H 18150 13500 60 0000 C CNN +F 2 "" H 18000 13350 60 0000 C CNN +F 3 "" H 18000 13350 60 0000 C CNN + 1 18000 13350 + 1 0 0 -1 +$EndComp +$Comp +L 3_and X4 +U 1 1 6848E2FD +P 18050 14100 +F 0 "X4" H 18150 14050 60 0000 C CNN +F 1 "3_and" H 18200 14250 60 0000 C CNN +F 2 "" H 18050 14100 60 0000 C CNN +F 3 "" H 18050 14100 60 0000 C CNN + 1 18050 14100 + 1 0 0 -1 +$EndComp +$Comp +L 3_and X5 +U 1 1 6848E303 +P 18050 14950 +F 0 "X5" H 18150 14900 60 0000 C CNN +F 1 "3_and" H 18200 15100 60 0000 C CNN +F 2 "" H 18050 14950 60 0000 C CNN +F 3 "" H 18050 14950 60 0000 C CNN + 1 18050 14950 + 1 0 0 -1 +$EndComp +$Comp +L 3_and X6 +U 1 1 6848E309 +P 18050 15750 +F 0 "X6" H 18150 15700 60 0000 C CNN +F 1 "3_and" H 18200 15900 60 0000 C CNN +F 2 "" H 18050 15750 60 0000 C CNN +F 3 "" H 18050 15750 60 0000 C CNN + 1 18050 15750 + 1 0 0 -1 +$EndComp +$Comp +L 3_and X7 +U 1 1 6848E30F +P 18050 16550 +F 0 "X7" H 18150 16500 60 0000 C CNN +F 1 "3_and" H 18200 16700 60 0000 C CNN +F 2 "" H 18050 16550 60 0000 C CNN +F 3 "" H 18050 16550 60 0000 C CNN + 1 18050 16550 + 1 0 0 -1 +$EndComp +$Comp +L 3_and X8 +U 1 1 6848E315 +P 18050 17250 +F 0 "X8" H 18150 17200 60 0000 C CNN +F 1 "3_and" H 18200 17400 60 0000 C CNN +F 2 "" H 18050 17250 60 0000 C CNN +F 3 "" H 18050 17250 60 0000 C CNN + 1 18050 17250 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U8 +U 1 1 6848E7FD +P 19350 11800 +F 0 "U8" H 19350 11700 60 0000 C CNN +F 1 "d_inverter" H 19350 11950 60 0000 C CNN +F 2 "" H 19400 11750 60 0000 C CNN +F 3 "" H 19400 11750 60 0000 C CNN + 1 19350 11800 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U9 +U 1 1 6848E946 +P 19350 12600 +F 0 "U9" H 19350 12500 60 0000 C CNN +F 1 "d_inverter" H 19350 12750 60 0000 C CNN +F 2 "" H 19400 12550 60 0000 C CNN +F 3 "" H 19400 12550 60 0000 C CNN + 1 19350 12600 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U10 +U 1 1 6848EC58 +P 19400 13250 +F 0 "U10" H 19400 13150 60 0000 C CNN +F 1 "d_inverter" H 19400 13400 60 0000 C CNN +F 2 "" H 19450 13200 60 0000 C CNN +F 3 "" H 19450 13200 60 0000 C CNN + 1 19400 13250 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U13 +U 1 1 6848EC5E +P 19500 14100 +F 0 "U13" H 19500 14000 60 0000 C CNN +F 1 "d_inverter" H 19500 14250 60 0000 C CNN +F 2 "" H 19550 14050 60 0000 C CNN +F 3 "" H 19550 14050 60 0000 C CNN + 1 19500 14100 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U14 +U 1 1 6848EC64 +P 19550 14900 +F 0 "U14" H 19550 14800 60 0000 C CNN +F 1 "d_inverter" H 19550 15050 60 0000 C CNN +F 2 "" H 19600 14850 60 0000 C CNN +F 3 "" H 19600 14850 60 0000 C CNN + 1 19550 14900 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U15 +U 1 1 6848EC6A +P 19550 15700 +F 0 "U15" H 19550 15600 60 0000 C CNN +F 1 "d_inverter" H 19550 15850 60 0000 C CNN +F 2 "" H 19600 15650 60 0000 C CNN +F 3 "" H 19600 15650 60 0000 C CNN + 1 19550 15700 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U16 +U 1 1 6848ED92 +P 19550 16450 +F 0 "U16" H 19550 16350 60 0000 C CNN +F 1 "d_inverter" H 19550 16600 60 0000 C CNN +F 2 "" H 19600 16400 60 0000 C CNN +F 3 "" H 19600 16400 60 0000 C CNN + 1 19550 16450 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U17 +U 1 1 6848ED98 +P 19550 17250 +F 0 "U17" H 19550 17150 60 0000 C CNN +F 1 "d_inverter" H 19550 17400 60 0000 C CNN +F 2 "" H 19600 17200 60 0000 C CNN +F 3 "" H 19600 17200 60 0000 C CNN + 1 19550 17250 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 684B0243 +P 13900 8150 +F 0 "U1" H 13950 8250 30 0000 C CNN +F 1 "PORT" H 13900 8150 30 0000 C CNN +F 2 "" H 13900 8150 60 0000 C CNN +F 3 "" H 13900 8150 60 0000 C CNN + 1 13900 8150 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 684B04A3 +P 15050 8200 +F 0 "U1" H 15100 8300 30 0000 C CNN +F 1 "PORT" H 15050 8200 30 0000 C CNN +F 2 "" H 15050 8200 60 0000 C CNN +F 3 "" H 15050 8200 60 0000 C CNN + 2 15050 8200 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 684B0B26 +P 15850 8200 +F 0 "U1" H 15900 8300 30 0000 C CNN +F 1 "PORT" H 15850 8200 30 0000 C CNN +F 2 "" H 15850 8200 60 0000 C CNN +F 3 "" H 15850 8200 60 0000 C CNN + 3 15850 8200 + 1 0 0 -1 +$EndComp +Wire Wire Line + 19750 5800 20050 5800 +Wire Wire Line + 19800 6300 20200 6300 +Wire Wire Line + 21100 6350 21600 6350 +Wire Wire Line + 20000 6300 20000 6550 +Wire Wire Line + 20000 6550 21600 6550 +Wire Wire Line + 21600 6550 21600 6450 +Connection ~ 20000 6300 +Wire Wire Line + 18550 5800 19150 5800 +Wire Wire Line + 18600 6300 19200 6300 +Wire Wire Line + 18600 6700 20200 6700 +Wire Wire Line + 20200 6700 20200 6400 +Wire Wire Line + 20650 5800 23550 5800 +Wire Wire Line + 21350 6350 21350 5200 +Wire Wire Line + 21350 5200 23550 5200 +Connection ~ 21350 6350 +Wire Wire Line + 24450 5250 25300 5250 +Wire Wire Line + 25300 5250 25300 5300 +Wire Wire Line + 24450 5850 24450 5400 +Wire Wire Line + 24450 5400 25300 5400 +Wire Wire Line + 26400 7050 27100 7050 +Wire Wire Line + 23550 5900 23550 6250 +Connection ~ 26800 7050 +Wire Wire Line + 24750 6800 25500 6800 +Wire Wire Line + 25500 6800 25500 7000 +Wire Wire Line + 24700 7450 24700 7100 +Wire Wire Line + 24700 7100 25500 7100 +Wire Wire Line + 26200 5350 26200 6100 +Wire Wire Line + 23250 6100 23250 6800 +Wire Wire Line + 23250 6800 23600 6800 +Wire Wire Line + 22500 6400 22850 6400 +Wire Wire Line + 22850 6400 22850 10500 +Wire Wire Line + 22850 7500 23800 7500 +Wire Wire Line + 23550 5300 23100 5300 +Wire Wire Line + 23100 5300 23100 7400 +Wire Wire Line + 19900 7400 23800 7400 +Wire Wire Line + 27700 7050 28300 7050 +Wire Wire Line + 24450 7950 25300 7950 +Wire Wire Line + 25300 7950 25300 8000 +Wire Wire Line + 24450 8550 24450 8100 +Wire Wire Line + 24450 8100 25300 8100 +Wire Wire Line + 26400 9750 27100 9750 +Wire Wire Line + 23550 8600 23550 8950 +Wire Wire Line + 23550 8950 26800 8950 +Connection ~ 26800 9750 +Wire Wire Line + 24750 9500 25500 9500 +Wire Wire Line + 25500 9500 25500 9700 +Wire Wire Line + 24700 10150 24700 9800 +Wire Wire Line + 24700 9800 25500 9800 +Wire Wire Line + 26200 8050 26200 8800 +Wire Wire Line + 26200 8800 23250 8800 +Wire Wire Line + 23250 8800 23250 9500 +Wire Wire Line + 23250 9500 23600 9500 +Wire Wire Line + 22850 10200 23800 10200 +Wire Wire Line + 23550 8000 23100 8000 +Wire Wire Line + 23100 8000 23100 10100 +Wire Wire Line + 20200 10100 23800 10100 +Wire Wire Line + 27700 9750 28300 9750 +Wire Wire Line + 22900 5200 22900 7900 +Wire Wire Line + 22900 7900 23550 7900 +Connection ~ 22900 5200 +Wire Wire Line + 23200 5800 23200 11250 +Connection ~ 23200 8500 +Connection ~ 23200 5800 +Wire Wire Line + 23200 8500 23550 8500 +Connection ~ 22850 7500 +Wire Wire Line + 24250 10750 25100 10750 +Wire Wire Line + 25100 10750 25100 10800 +Wire Wire Line + 24250 11350 24250 10900 +Wire Wire Line + 24250 10900 25100 10900 +Wire Wire Line + 26200 12550 26900 12550 +Wire Wire Line + 23350 11400 23350 11850 +Connection ~ 26600 12550 +Wire Wire Line + 24550 12300 25300 12300 +Wire Wire Line + 25300 12300 25300 12500 +Wire Wire Line + 24500 12950 24500 12600 +Wire Wire Line + 24500 12600 25300 12600 +Wire Wire Line + 26000 10850 26000 11600 +Wire Wire Line + 26000 11600 23050 11600 +Wire Wire Line + 23050 11600 23050 12300 +Wire Wire Line + 23050 12300 23400 12300 +Wire Wire Line + 22650 13000 23600 13000 +Wire Wire Line + 23350 10800 22900 10800 +Wire Wire Line + 22900 10800 22900 12900 +Wire Wire Line + 21100 12900 23600 12900 +Wire Wire Line + 27500 12550 28100 12550 +Connection ~ 23000 11300 +Wire Wire Line + 22850 11300 23350 11300 +Wire Wire Line + 22450 5200 22450 24950 +Wire Wire Line + 22450 10750 23350 10750 +Wire Wire Line + 23350 10750 23350 10700 +Connection ~ 22450 5200 +Wire Wire Line + 23200 11250 23000 11250 +Wire Wire Line + 23000 11250 23000 11300 +Wire Wire Line + 22850 10500 22650 10500 +Wire Wire Line + 22650 10500 22650 13100 +Connection ~ 22850 10200 +Wire Wire Line + 23900 13550 24750 13550 +Wire Wire Line + 24750 13550 24750 13600 +Wire Wire Line + 23900 14150 23900 13700 +Wire Wire Line + 23900 13700 24750 13700 +Wire Wire Line + 25850 15350 26550 15350 +Wire Wire Line + 24200 15100 24950 15100 +Wire Wire Line + 24950 15100 24950 15300 +Wire Wire Line + 24150 15750 24150 15400 +Wire Wire Line + 24150 15400 24950 15400 +Wire Wire Line + 25650 13650 25650 14400 +Wire Wire Line + 25650 14400 22700 14400 +Wire Wire Line + 22700 15100 23050 15100 +Wire Wire Line + 22300 15800 23250 15800 +Wire Wire Line + 21850 15700 23250 15700 +Wire Wire Line + 27150 15350 27750 15350 +Wire Wire Line + 22450 13500 23000 13500 +Connection ~ 22450 10750 +Wire Wire Line + 22700 14400 22700 15100 +Wire Wire Line + 23000 14100 22850 14100 +Wire Wire Line + 22850 11300 22850 14200 +Wire Wire Line + 22550 15700 22550 13600 +Wire Wire Line + 22550 13600 23000 13600 +Wire Wire Line + 22300 13100 22300 27250 +Wire Wire Line + 22650 13100 22300 13100 +Connection ~ 22650 13000 +Wire Wire Line + 24200 16350 25050 16350 +Wire Wire Line + 25050 16350 25050 16400 +Wire Wire Line + 24200 16950 24200 16500 +Wire Wire Line + 24200 16500 25050 16500 +Wire Wire Line + 26150 18150 26850 18150 +Connection ~ 26550 18150 +Wire Wire Line + 24500 17900 25250 17900 +Wire Wire Line + 25250 17900 25250 18100 +Wire Wire Line + 24450 18550 24450 18200 +Wire Wire Line + 24450 18200 25250 18200 +Wire Wire Line + 25950 16450 25950 17200 +Wire Wire Line + 25950 17200 23000 17200 +Wire Wire Line + 23000 17900 23350 17900 +Wire Wire Line + 22300 18600 23550 18600 +Wire Wire Line + 22850 18500 23550 18500 +Wire Wire Line + 27450 18150 28050 18150 +Wire Wire Line + 22450 16300 23300 16300 +Wire Wire Line + 23000 17200 23000 17900 +Wire Wire Line + 23300 17000 23300 17450 +Wire Wire Line + 22750 16900 23300 16900 +Wire Wire Line + 22850 18500 22850 16400 +Wire Wire Line + 22850 16400 23300 16400 +Connection ~ 22300 15800 +Connection ~ 22450 13500 +Wire Wire Line + 22750 14200 22750 19800 +Wire Wire Line + 22850 14200 22750 14200 +Connection ~ 22850 14100 +Wire Wire Line + 24500 19250 25350 19250 +Wire Wire Line + 25350 19250 25350 19300 +Wire Wire Line + 24500 19850 24500 19400 +Wire Wire Line + 24500 19400 25350 19400 +Wire Wire Line + 26450 21050 27150 21050 +Connection ~ 26850 21050 +Wire Wire Line + 24800 20800 25550 20800 +Wire Wire Line + 25550 20800 25550 21000 +Wire Wire Line + 24750 21450 24750 21100 +Wire Wire Line + 24750 21100 25550 21100 +Wire Wire Line + 26250 19350 26250 20100 +Wire Wire Line + 26250 20100 23300 20100 +Wire Wire Line + 23300 20800 23650 20800 +Wire Wire Line + 22300 21500 23850 21500 +Wire Wire Line + 21150 21400 23850 21400 +Wire Wire Line + 27750 21050 28350 21050 +Wire Wire Line + 22450 19200 23600 19200 +Wire Wire Line + 23300 20100 23300 20800 +Wire Wire Line + 23600 19900 23600 20350 +Wire Wire Line + 22750 19800 23600 19800 +Wire Wire Line + 23150 21400 23150 19300 +Wire Wire Line + 23150 19300 23600 19300 +Connection ~ 22300 18600 +Connection ~ 22450 16300 +Connection ~ 22750 16900 +Wire Wire Line + 24900 22200 25750 22200 +Wire Wire Line + 25750 22200 25750 22250 +Wire Wire Line + 24900 22800 24900 22350 +Wire Wire Line + 24900 22350 25750 22350 +Wire Wire Line + 26850 24000 27550 24000 +Wire Wire Line + 25200 23750 25950 23750 +Wire Wire Line + 25950 23750 25950 23950 +Wire Wire Line + 25150 24400 25150 24050 +Wire Wire Line + 25150 24050 25950 24050 +Wire Wire Line + 26650 22300 26650 23050 +Wire Wire Line + 26650 23050 23700 23050 +Wire Wire Line + 23700 23750 24050 23750 +Wire Wire Line + 22300 24450 24250 24450 +Wire Wire Line + 20800 24350 24250 24350 +Wire Wire Line + 28150 24000 28750 24000 +Wire Wire Line + 22450 22150 24000 22150 +Wire Wire Line + 23700 23050 23700 23750 +Wire Wire Line + 24000 22850 24000 23300 +Wire Wire Line + 22800 22750 24000 22750 +Wire Wire Line + 23550 24350 23550 22250 +Wire Wire Line + 23550 22250 24000 22250 +Connection ~ 22300 21500 +Connection ~ 22450 19200 +Wire Wire Line + 22800 19800 22800 25550 +Connection ~ 22800 19800 +Wire Wire Line + 25250 25000 26100 25000 +Wire Wire Line + 26100 25000 26100 25050 +Wire Wire Line + 25250 25600 25250 25150 +Wire Wire Line + 25250 25150 26100 25150 +Wire Wire Line + 27200 26800 27900 26800 +Connection ~ 27600 26800 +Wire Wire Line + 25550 26550 26300 26550 +Wire Wire Line + 26300 26550 26300 26750 +Wire Wire Line + 25500 27200 25500 26850 +Wire Wire Line + 25500 26850 26300 26850 +Wire Wire Line + 27000 25100 27000 25850 +Wire Wire Line + 27000 25850 24050 25850 +Wire Wire Line + 24050 26550 24400 26550 +Wire Wire Line + 22300 27250 24600 27250 +Wire Wire Line + 19850 27150 24600 27150 +Wire Wire Line + 28500 26800 29100 26800 +Wire Wire Line + 22450 24950 24350 24950 +Wire Wire Line + 24050 25850 24050 26550 +Wire Wire Line + 24350 25650 24350 26100 +Wire Wire Line + 22800 25550 24350 25550 +Wire Wire Line + 23900 27150 23900 25050 +Wire Wire Line + 23900 25050 24350 25050 +Connection ~ 22300 24450 +Connection ~ 22450 22150 +Connection ~ 22800 22750 +Wire Wire Line + 14300 8800 14300 9100 +Wire Wire Line + 15450 8800 15450 9100 +Wire Wire Line + 16300 8800 16300 9100 +Wire Wire Line + 18500 11800 19050 11800 +Wire Wire Line + 18500 12600 19050 12600 +Wire Wire Line + 18500 13300 19100 13300 +Wire Wire Line + 19100 13300 19100 13250 +Wire Wire Line + 18550 14050 19200 14050 +Wire Wire Line + 19200 14050 19200 14100 +Wire Wire Line + 18550 14900 19250 14900 +Wire Wire Line + 18550 15700 19250 15700 +Wire Wire Line + 18550 16500 19250 16500 +Wire Wire Line + 19250 16500 19250 16450 +Wire Wire Line + 18550 17200 19250 17200 +Wire Wire Line + 19250 17200 19250 17250 +Wire Wire Line + 14300 9700 14300 17300 +Wire Wire Line + 14300 17300 17700 17300 +Wire Wire Line + 17700 16600 14300 16600 +Connection ~ 14300 16600 +Wire Wire Line + 17700 15800 14300 15800 +Connection ~ 14300 15800 +Wire Wire Line + 17700 15000 14300 15000 +Connection ~ 14300 15000 +Wire Wire Line + 15450 9700 15450 17200 +Wire Wire Line + 15450 16500 17700 16500 +Wire Wire Line + 15450 17200 17700 17200 +Connection ~ 15450 16500 +Wire Wire Line + 16300 9700 16300 17100 +Wire Wire Line + 16300 12500 17650 12500 +Wire Wire Line + 16300 13950 17700 13950 +Connection ~ 16300 12500 +Wire Wire Line + 17650 13300 15450 13300 +Connection ~ 15450 13300 +Wire Wire Line + 17700 14050 15450 14050 +Connection ~ 15450 14050 +Wire Wire Line + 16300 15600 17700 15600 +Connection ~ 16300 13950 +Wire Wire Line + 16300 17100 17700 17100 +Connection ~ 16300 15600 +Wire Wire Line + 16300 9000 17200 9000 +Wire Wire Line + 17200 9000 17200 16400 +Wire Wire Line + 17200 11700 17650 11700 +Connection ~ 16300 9000 +Wire Wire Line + 17200 13200 17650 13200 +Connection ~ 17200 11700 +Wire Wire Line + 17200 14800 17700 14800 +Connection ~ 17200 13200 +Wire Wire Line + 17200 16400 17700 16400 +Connection ~ 17200 14800 +Wire Wire Line + 15450 9000 15950 9000 +Wire Wire Line + 15950 9000 15950 15700 +Wire Wire Line + 15950 11800 17650 11800 +Connection ~ 15450 9000 +Wire Wire Line + 15950 12600 17650 12600 +Connection ~ 15950 11800 +Wire Wire Line + 15950 14900 17700 14900 +Connection ~ 15950 12600 +Wire Wire Line + 15950 15700 17700 15700 +Connection ~ 15950 14900 +Wire Wire Line + 14300 8950 15000 8950 +Wire Wire Line + 15000 8950 15000 14300 +Wire Wire Line + 15000 12000 17650 12000 +Wire Wire Line + 17650 12000 17650 11900 +Connection ~ 14300 8950 +Wire Wire Line + 15000 12800 17650 12800 +Wire Wire Line + 17650 12800 17650 12700 +Connection ~ 15000 12000 +Wire Wire Line + 15000 13600 17650 13600 +Wire Wire Line + 17650 13600 17650 13400 +Connection ~ 15000 12800 +Wire Wire Line + 15000 14300 17700 14300 +Wire Wire Line + 17700 14300 17700 14150 +Connection ~ 15000 13600 +Wire Wire Line + 19900 7400 19900 11800 +Wire Wire Line + 19900 11800 19650 11800 +Connection ~ 23100 7400 +Wire Wire Line + 20200 10100 20200 12600 +Wire Wire Line + 20200 12600 19650 12600 +Connection ~ 23100 10100 +Wire Wire Line + 19700 13250 21100 13250 +Wire Wire Line + 21100 13250 21100 12900 +Connection ~ 22900 12900 +Wire Wire Line + 21850 15700 21850 14100 +Wire Wire Line + 21850 14100 19800 14100 +Connection ~ 22550 15700 +Wire Wire Line + 22900 18500 21450 18500 +Wire Wire Line + 21450 18500 21450 14900 +Wire Wire Line + 21450 14900 19850 14900 +Connection ~ 22900 18500 +Wire Wire Line + 21150 21400 21150 15700 +Wire Wire Line + 21150 15700 19850 15700 +Connection ~ 23150 21400 +Wire Wire Line + 20800 24350 20800 16450 +Wire Wire Line + 20800 16450 19850 16450 +Connection ~ 23550 24350 +Wire Wire Line + 19850 17250 19850 27150 +Connection ~ 23900 27150 +Wire Wire Line + 15300 8200 15450 8200 +Wire Wire Line + 16100 8200 16300 8200 +Wire Wire Line + 23000 14200 22950 14200 +Wire Wire Line + 22950 14200 22950 14700 +Connection ~ 26250 15350 +Wire Wire Line + 14150 8150 14300 8150 +Wire Wire Line + 14300 8150 14300 8200 +Wire Wire Line + 26200 6100 23250 6100 +Wire Wire Line + 23550 6250 26800 6250 +Wire Wire Line + 26800 8950 26800 9750 +Wire Wire Line + 23500 11700 26600 11700 +Wire Wire Line + 23500 11700 23500 11850 +Wire Wire Line + 23500 11850 23350 11850 +Wire Wire Line + 22950 14700 26250 14700 +Wire Wire Line + 23300 17450 26550 17450 +Wire Wire Line + 23600 20350 26850 20350 +Wire Wire Line + 24000 23300 27150 23300 +Wire Wire Line + 24350 26100 27600 26100 +Wire Wire Line + 27600 26100 27600 26800 +Wire Wire Line + 27150 23300 27150 24000 +Connection ~ 27150 24000 +Wire Wire Line + 26850 20350 26850 21050 +Wire Wire Line + 26550 17450 26550 18150 +Wire Wire Line + 26250 14700 26250 15350 +Wire Wire Line + 26600 11700 26600 12550 +Wire Wire Line + 26800 6250 26800 7050 +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/Failed IC'S/CD4724BC/CD4724BC.sub b/library/SubcircuitLibrary/Failed IC'S/CD4724BC/CD4724BC.sub new file mode 100644 index 000000000..dbdc9151b --- /dev/null +++ b/library/SubcircuitLibrary/Failed IC'S/CD4724BC/CD4724BC.sub @@ -0,0 +1,395 @@ +* Subcircuit CD4724BC +.subckt CD4724BC net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ +* c:\fossee\esim\library\subcircuitlibrary\cd4724bc\cd4724bc.cir +.include 3_and.sub +* u94 net-_u62-pad3_ ic +.ic v(net-_u62-pad3_)=0 +* u100 net-_u100-pad1_ ic +.ic v(net-_u100-pad1_)=0 +* u93 net-_u60-pad3_ ic +.ic v(net-_u60-pad3_)=0 +* u88 net-_u54-pad3_ ic +.ic v(net-_u54-pad3_)=0 +* u92 net-_u57-pad3_ ic +.ic v(net-_u57-pad3_)=0 +* u95 net-_u64-pad3_ ic +.ic v(net-_u64-pad3_)=0 +* u97 net-_u66-pad3_ ic +.ic v(net-_u66-pad3_)=0 +* u99 net-_u68-pad3_ ic +.ic v(net-_u68-pad3_)=0 +* u90 net-_u51-pad1_ ic +.ic v(net-_u51-pad1_)=5 +* u89 net-_u47-pad1_ ic +.ic v(net-_u47-pad1_)=5 +* u84 net-_u41-pad1_ ic +.ic v(net-_u41-pad1_)=5 +* u79 net-_u29-pad1_ ic +.ic v(net-_u29-pad1_)=5 +* u77 net-_u23-pad1_ ic +.ic v(net-_u23-pad1_)=5 +* u82 net-_u30-pad1_ ic +.ic v(net-_u30-pad1_)=5 +* u86 net-_u40-pad1_ ic +.ic v(net-_u40-pad1_)=5 +* u81 net-_u39-pad1_ ic +.ic v(net-_u39-pad1_)=5 +* u11 net-_u1-pad4_ net-_u11-pad2_ d_inverter +* u18 net-_u11-pad2_ net-_u18-pad2_ d_inverter +* u12 net-_u1-pad5_ net-_u12-pad2_ d_inverter +* u19 net-_u12-pad2_ net-_u1-pad6_ net-_u19-pad3_ d_nand +* u20 net-_u19-pad3_ net-_u12-pad2_ net-_u20-pad3_ d_nand +* u58 net-_u31-pad3_ net-_u32-pad3_ net-_u39-pad1_ d_nand +* u32 net-_u18-pad2_ net-_u32-pad2_ net-_u32-pad3_ d_or +* u31 net-_u19-pad3_ net-_u31-pad2_ net-_u31-pad3_ d_or +* u39 net-_u39-pad1_ net-_u39-pad2_ d_buffer +* u62 net-_u39-pad2_ net-_u42-pad3_ net-_u62-pad3_ d_nand +* u42 net-_u31-pad2_ net-_u20-pad3_ net-_u42-pad3_ d_or +* u72 net-_u62-pad3_ net-_u1-pad7_ d_inverter +* u59 net-_u33-pad3_ net-_u34-pad3_ net-_u40-pad1_ d_nand +* u34 net-_u18-pad2_ net-_u34-pad2_ net-_u34-pad3_ d_or +* u33 net-_u19-pad3_ net-_u33-pad2_ net-_u33-pad3_ d_or +* u40 net-_u40-pad1_ net-_u40-pad2_ d_buffer +* u63 net-_u40-pad2_ net-_u43-pad3_ net-_u100-pad1_ d_nand +* u43 net-_u33-pad2_ net-_u20-pad3_ net-_u43-pad3_ d_or +* u73 net-_u100-pad1_ net-_u1-pad8_ d_inverter +* u56 net-_u27-pad3_ net-_u28-pad3_ net-_u30-pad1_ d_nand +* u28 net-_u18-pad2_ net-_u28-pad2_ net-_u28-pad3_ d_or +* u27 net-_u19-pad3_ net-_u10-pad2_ net-_u27-pad3_ d_or +* u30 net-_u30-pad1_ net-_u30-pad2_ d_buffer +* u60 net-_u30-pad2_ net-_u36-pad3_ net-_u60-pad3_ d_nand +* u36 net-_u10-pad2_ net-_u20-pad3_ net-_u36-pad3_ d_or +* u71 net-_u60-pad3_ net-_u1-pad9_ d_inverter +* u53 net-_u21-pad3_ net-_u22-pad3_ net-_u23-pad1_ d_nand +* u22 net-_u18-pad2_ net-_u22-pad2_ net-_u22-pad3_ d_or +* u21 net-_u19-pad3_ net-_u13-pad2_ net-_u21-pad3_ d_or +* u23 net-_u23-pad1_ net-_u23-pad2_ d_buffer +* u54 net-_u23-pad2_ net-_u24-pad3_ net-_u54-pad3_ d_nand +* u24 net-_u13-pad2_ net-_u20-pad3_ net-_u24-pad3_ d_or +* u69 net-_u54-pad3_ net-_u1-pad10_ d_inverter +* u55 net-_u25-pad3_ net-_u26-pad3_ net-_u29-pad1_ d_nand +* u26 net-_u18-pad2_ net-_u26-pad2_ net-_u26-pad3_ d_or +* u25 net-_u19-pad3_ net-_u14-pad2_ net-_u25-pad3_ d_or +* u29 net-_u29-pad1_ net-_u29-pad2_ d_buffer +* u57 net-_u29-pad2_ net-_u35-pad3_ net-_u57-pad3_ d_nand +* u35 net-_u14-pad2_ net-_u20-pad3_ net-_u35-pad3_ d_or +* u70 net-_u57-pad3_ net-_u1-pad11_ d_inverter +* u61 net-_u37-pad3_ net-_u38-pad3_ net-_u41-pad1_ d_nand +* u38 net-_u18-pad2_ net-_u38-pad2_ net-_u38-pad3_ d_or +* u37 net-_u19-pad3_ net-_u15-pad2_ net-_u37-pad3_ d_or +* u41 net-_u41-pad1_ net-_u41-pad2_ d_buffer +* u64 net-_u41-pad2_ net-_u44-pad3_ net-_u64-pad3_ d_nand +* u44 net-_u15-pad2_ net-_u20-pad3_ net-_u44-pad3_ d_or +* u74 net-_u64-pad3_ net-_u1-pad12_ d_inverter +* u65 net-_u45-pad3_ net-_u46-pad3_ net-_u47-pad1_ d_nand +* u46 net-_u18-pad2_ net-_u46-pad2_ net-_u46-pad3_ d_or +* u45 net-_u19-pad3_ net-_u16-pad2_ net-_u45-pad3_ d_or +* u47 net-_u47-pad1_ net-_u47-pad2_ d_buffer +* u66 net-_u47-pad2_ net-_u48-pad3_ net-_u66-pad3_ d_nand +* u48 net-_u16-pad2_ net-_u20-pad3_ net-_u48-pad3_ d_or +* u75 net-_u66-pad3_ net-_u1-pad13_ d_inverter +* u67 net-_u49-pad3_ net-_u50-pad3_ net-_u51-pad1_ d_nand +* u50 net-_u18-pad2_ net-_u50-pad2_ net-_u50-pad3_ d_or +* u49 net-_u19-pad3_ net-_u17-pad2_ net-_u49-pad3_ d_or +* u51 net-_u51-pad1_ net-_u51-pad2_ d_buffer +* u68 net-_u51-pad2_ net-_u52-pad3_ net-_u68-pad3_ d_nand +* u52 net-_u17-pad2_ net-_u20-pad3_ net-_u52-pad3_ d_or +* u76 net-_u68-pad3_ net-_u1-pad14_ d_inverter +* u2 net-_u1-pad1_ net-_u2-pad2_ d_inverter +* u3 net-_u2-pad2_ net-_u3-pad2_ d_inverter +* u4 net-_u1-pad2_ net-_u4-pad2_ d_inverter +* u5 net-_u4-pad2_ net-_u5-pad2_ d_inverter +* u6 net-_u1-pad3_ net-_u6-pad2_ d_inverter +* u7 net-_u6-pad2_ net-_u7-pad2_ d_inverter +x1 net-_u6-pad2_ net-_u4-pad2_ net-_u2-pad2_ net-_u8-pad1_ 3_and +x2 net-_u7-pad2_ net-_u4-pad2_ net-_u2-pad2_ net-_u9-pad1_ 3_and +x3 net-_u6-pad2_ net-_u5-pad2_ net-_u2-pad2_ net-_u10-pad1_ 3_and +x4 net-_u7-pad2_ net-_u5-pad2_ net-_u2-pad2_ net-_u13-pad1_ 3_and +x5 net-_u6-pad2_ net-_u4-pad2_ net-_u3-pad2_ net-_u14-pad1_ 3_and +x6 net-_u7-pad2_ net-_u4-pad2_ net-_u3-pad2_ net-_u15-pad1_ 3_and +x7 net-_u6-pad2_ net-_u5-pad2_ net-_u3-pad2_ net-_u16-pad1_ 3_and +x8 net-_u7-pad2_ net-_u5-pad2_ net-_u3-pad2_ net-_u17-pad1_ 3_and +* u8 net-_u8-pad1_ net-_u31-pad2_ d_inverter +* u9 net-_u9-pad1_ net-_u33-pad2_ d_inverter +* u10 net-_u10-pad1_ net-_u10-pad2_ d_inverter +* u13 net-_u13-pad1_ net-_u13-pad2_ d_inverter +* u14 net-_u14-pad1_ net-_u14-pad2_ d_inverter +* u15 net-_u15-pad1_ net-_u15-pad2_ d_inverter +* u16 net-_u16-pad1_ net-_u16-pad2_ d_inverter +* u17 net-_u17-pad1_ net-_u17-pad2_ d_inverter +* u81 net-_u39-pad1_ ic +* u86 net-_u40-pad1_ ic +* u82 net-_u30-pad1_ ic +* u77 net-_u23-pad1_ ic +* u79 net-_u29-pad1_ ic +* u84 net-_u41-pad1_ ic +* u89 net-_u47-pad1_ ic +* u90 net-_u51-pad1_ ic +* u80 net-_u62-pad3_ net-_u32-pad2_ d_buffer +* u98 net-_u100-pad1_ net-_u34-pad2_ d_buffer +* u83 net-_u60-pad3_ net-_u28-pad2_ d_buffer +* u78 net-_u54-pad3_ net-_u22-pad2_ d_buffer +* u85 net-_u57-pad3_ net-_u26-pad2_ d_buffer +* u87 net-_u64-pad3_ net-_u38-pad2_ d_buffer +* u91 net-_u66-pad3_ net-_u46-pad2_ d_buffer +* u96 net-_u68-pad3_ net-_u50-pad2_ d_buffer +* u99 net-_u68-pad3_ ic +* u97 net-_u66-pad3_ ic +* u95 net-_u64-pad3_ ic +* u92 net-_u57-pad3_ ic +* u88 net-_u54-pad3_ ic +* u93 net-_u60-pad3_ ic +* u100 net-_u100-pad1_ ic +* u94 net-_u62-pad3_ ic +a1 net-_u1-pad4_ net-_u11-pad2_ u11 +a2 net-_u11-pad2_ net-_u18-pad2_ u18 +a3 net-_u1-pad5_ net-_u12-pad2_ u12 +a4 [net-_u12-pad2_ net-_u1-pad6_ ] net-_u19-pad3_ u19 +a5 [net-_u19-pad3_ net-_u12-pad2_ ] net-_u20-pad3_ u20 +a6 [net-_u31-pad3_ net-_u32-pad3_ ] net-_u39-pad1_ u58 +a7 [net-_u18-pad2_ net-_u32-pad2_ ] net-_u32-pad3_ u32 +a8 [net-_u19-pad3_ net-_u31-pad2_ ] net-_u31-pad3_ u31 +a9 net-_u39-pad1_ net-_u39-pad2_ u39 +a10 [net-_u39-pad2_ net-_u42-pad3_ ] net-_u62-pad3_ u62 +a11 [net-_u31-pad2_ net-_u20-pad3_ ] net-_u42-pad3_ u42 +a12 net-_u62-pad3_ net-_u1-pad7_ u72 +a13 [net-_u33-pad3_ net-_u34-pad3_ ] net-_u40-pad1_ u59 +a14 [net-_u18-pad2_ net-_u34-pad2_ ] net-_u34-pad3_ u34 +a15 [net-_u19-pad3_ net-_u33-pad2_ ] net-_u33-pad3_ u33 +a16 net-_u40-pad1_ net-_u40-pad2_ u40 +a17 [net-_u40-pad2_ net-_u43-pad3_ ] net-_u100-pad1_ u63 +a18 [net-_u33-pad2_ net-_u20-pad3_ ] net-_u43-pad3_ u43 +a19 net-_u100-pad1_ net-_u1-pad8_ u73 +a20 [net-_u27-pad3_ net-_u28-pad3_ ] net-_u30-pad1_ u56 +a21 [net-_u18-pad2_ net-_u28-pad2_ ] net-_u28-pad3_ u28 +a22 [net-_u19-pad3_ net-_u10-pad2_ ] net-_u27-pad3_ u27 +a23 net-_u30-pad1_ net-_u30-pad2_ u30 +a24 [net-_u30-pad2_ net-_u36-pad3_ ] net-_u60-pad3_ u60 +a25 [net-_u10-pad2_ net-_u20-pad3_ ] net-_u36-pad3_ u36 +a26 net-_u60-pad3_ net-_u1-pad9_ u71 +a27 [net-_u21-pad3_ net-_u22-pad3_ ] net-_u23-pad1_ u53 +a28 [net-_u18-pad2_ net-_u22-pad2_ ] net-_u22-pad3_ u22 +a29 [net-_u19-pad3_ net-_u13-pad2_ ] net-_u21-pad3_ u21 +a30 net-_u23-pad1_ net-_u23-pad2_ u23 +a31 [net-_u23-pad2_ net-_u24-pad3_ ] net-_u54-pad3_ u54 +a32 [net-_u13-pad2_ net-_u20-pad3_ ] net-_u24-pad3_ u24 +a33 net-_u54-pad3_ net-_u1-pad10_ u69 +a34 [net-_u25-pad3_ net-_u26-pad3_ ] net-_u29-pad1_ u55 +a35 [net-_u18-pad2_ net-_u26-pad2_ ] net-_u26-pad3_ u26 +a36 [net-_u19-pad3_ net-_u14-pad2_ ] net-_u25-pad3_ u25 +a37 net-_u29-pad1_ net-_u29-pad2_ u29 +a38 [net-_u29-pad2_ net-_u35-pad3_ ] net-_u57-pad3_ u57 +a39 [net-_u14-pad2_ net-_u20-pad3_ ] net-_u35-pad3_ u35 +a40 net-_u57-pad3_ net-_u1-pad11_ u70 +a41 [net-_u37-pad3_ net-_u38-pad3_ ] net-_u41-pad1_ u61 +a42 [net-_u18-pad2_ net-_u38-pad2_ ] net-_u38-pad3_ u38 +a43 [net-_u19-pad3_ net-_u15-pad2_ ] net-_u37-pad3_ u37 +a44 net-_u41-pad1_ net-_u41-pad2_ u41 +a45 [net-_u41-pad2_ net-_u44-pad3_ ] net-_u64-pad3_ u64 +a46 [net-_u15-pad2_ net-_u20-pad3_ ] net-_u44-pad3_ u44 +a47 net-_u64-pad3_ net-_u1-pad12_ u74 +a48 [net-_u45-pad3_ net-_u46-pad3_ ] net-_u47-pad1_ u65 +a49 [net-_u18-pad2_ net-_u46-pad2_ ] net-_u46-pad3_ u46 +a50 [net-_u19-pad3_ net-_u16-pad2_ ] net-_u45-pad3_ u45 +a51 net-_u47-pad1_ net-_u47-pad2_ u47 +a52 [net-_u47-pad2_ net-_u48-pad3_ ] net-_u66-pad3_ u66 +a53 [net-_u16-pad2_ net-_u20-pad3_ ] net-_u48-pad3_ u48 +a54 net-_u66-pad3_ net-_u1-pad13_ u75 +a55 [net-_u49-pad3_ net-_u50-pad3_ ] net-_u51-pad1_ u67 +a56 [net-_u18-pad2_ net-_u50-pad2_ ] net-_u50-pad3_ u50 +a57 [net-_u19-pad3_ net-_u17-pad2_ ] net-_u49-pad3_ u49 +a58 net-_u51-pad1_ net-_u51-pad2_ u51 +a59 [net-_u51-pad2_ net-_u52-pad3_ ] net-_u68-pad3_ u68 +a60 [net-_u17-pad2_ net-_u20-pad3_ ] net-_u52-pad3_ u52 +a61 net-_u68-pad3_ net-_u1-pad14_ u76 +a62 net-_u1-pad1_ net-_u2-pad2_ u2 +a63 net-_u2-pad2_ net-_u3-pad2_ u3 +a64 net-_u1-pad2_ net-_u4-pad2_ u4 +a65 net-_u4-pad2_ net-_u5-pad2_ u5 +a66 net-_u1-pad3_ net-_u6-pad2_ u6 +a67 net-_u6-pad2_ net-_u7-pad2_ u7 +a68 net-_u8-pad1_ net-_u31-pad2_ u8 +a69 net-_u9-pad1_ net-_u33-pad2_ u9 +a70 net-_u10-pad1_ net-_u10-pad2_ u10 +a71 net-_u13-pad1_ net-_u13-pad2_ u13 +a72 net-_u14-pad1_ net-_u14-pad2_ u14 +a73 net-_u15-pad1_ net-_u15-pad2_ u15 +a74 net-_u16-pad1_ net-_u16-pad2_ u16 +a75 net-_u17-pad1_ net-_u17-pad2_ u17 +a76 net-_u62-pad3_ net-_u32-pad2_ u80 +a77 net-_u100-pad1_ net-_u34-pad2_ u98 +a78 net-_u60-pad3_ net-_u28-pad2_ u83 +a79 net-_u54-pad3_ net-_u22-pad2_ u78 +a80 net-_u57-pad3_ net-_u26-pad2_ u85 +a81 net-_u64-pad3_ net-_u38-pad2_ u87 +a82 net-_u66-pad3_ net-_u46-pad2_ u91 +a83 net-_u68-pad3_ net-_u50-pad2_ u96 +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u11 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u18 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u12 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u19 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u20 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u58 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u32 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u31 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u39 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u62 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u42 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u72 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u59 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u34 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u33 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u40 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u63 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u43 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u73 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u56 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u28 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u27 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u30 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u60 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u36 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u71 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u53 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u22 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u21 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u23 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u54 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u24 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u69 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u55 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u26 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u25 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u29 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u57 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u35 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u70 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u61 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u38 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u37 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u41 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u64 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u44 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u74 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u65 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u46 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u45 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u47 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u66 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u48 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u75 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u67 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u50 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u49 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u51 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u68 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u52 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u76 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u4 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u5 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u7 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u8 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u9 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u10 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u13 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u14 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u15 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u16 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u17 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u80 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u98 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u83 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u78 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u85 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u87 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u91 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u96 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Control Statements + +.ends CD4724BC \ No newline at end of file diff --git a/library/SubcircuitLibrary/Failed IC'S/CD4724BC/CD4724BC_Previous_Values.xml b/library/SubcircuitLibrary/Failed IC'S/CD4724BC/CD4724BC_Previous_Values.xml new file mode 100644 index 000000000..040b9ecad --- /dev/null +++ b/library/SubcircuitLibrary/Failed IC'S/CD4724BC/CD4724BC_Previous_Values.xml @@ -0,0 +1 @@ +d_inverterd_inverterd_inverterd_nandd_nandd_nandd_ord_ord_bufferd_nandd_ord_inverterd_nandd_ord_ord_bufferd_nandd_ord_inverterd_nandd_ord_ord_bufferd_nandd_ord_inverterd_nandd_ord_ord_bufferd_nandd_ord_inverterd_nandd_ord_ord_bufferd_nandd_ord_inverterd_nandd_ord_ord_bufferd_nandd_ord_inverterd_nandd_ord_ord_bufferd_nandd_ord_inverterd_nandd_ord_ord_bufferd_nandd_ord_inverterd_inverterd_inverterd_inverterd_inverterd_inverterd_inverterd_inverterd_inverterd_inverterd_inverterd_inverterd_inverterd_inverterd_inverterd_bufferd_bufferd_bufferd_bufferd_bufferd_bufferd_bufferd_bufferic5ic0ic5ic0ic5ic0ic5ic0ic5ic5ic5ic5ic5ic5ic5ic5d_bufferd_bufferd_bufferd_bufferd_buffericicicicicicC:\FOSSEE\eSim\library\SubcircuitLibrary\3_andC:\FOSSEE\eSim\library\SubcircuitLibrary\3_andC:\FOSSEE\eSim\library\SubcircuitLibrary\3_andC:\FOSSEE\eSim\library\SubcircuitLibrary\3_andC:\FOSSEE\eSim\library\SubcircuitLibrary\3_andC:\FOSSEE\eSim\library\SubcircuitLibrary\3_andC:\FOSSEE\eSim\library\SubcircuitLibrary\3_andC:\FOSSEE\eSim\library\SubcircuitLibrary\3_andtruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperessecsecsec \ No newline at end of file diff --git a/library/SubcircuitLibrary/Failed IC'S/CD4724BC/analysis b/library/SubcircuitLibrary/Failed IC'S/CD4724BC/analysis new file mode 100644 index 000000000..ebd5c0a94 --- /dev/null +++ b/library/SubcircuitLibrary/Failed IC'S/CD4724BC/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00 \ No newline at end of file