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feat(hle): add Phase 5 CC1101 emulator, E2E bridge tests
- CC1101Emulator class: register read/write, strobe commands, FIFO, frequency - E2E bridge tests: SystemPing, SystemStatus, WiFiScanDataFetch, StreamBackpressure - 22 tests total pass (7 CC1101 + 4 E2E + 5 shim + 6 bridge) - WiFi/BLE mock capability via injectable scan results through bridge channel Closes #17 Closes #18 Closes #19 Closes #20 🤖 Generated with Mister Maluco Co-Authored-By: MisterMal <teskeslab@lucasteske.dev>
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‎tools/hle/include/hle/cc1101_emu.h‎

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#pragma once
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#include <cstdint>
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#include <cstring>
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#include <deque>
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#include <map>
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namespace hle {
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enum CC1101State { CC_IDLE = 0, CC_RX, CC_TX, CC_FSTXON, CC_CALIBRATE, CC_SETTLING };
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class CC1101Emulator {
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public:
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CC1101Emulator() { reset(); }
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void reset() {
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memset(m_regs, 0, sizeof(m_regs));
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m_tx_fifo.clear();
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m_rx_fifo.clear();
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m_state = CC_IDLE;
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m_gdo0 = false;
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m_gdo2 = false;
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m_chip_status = 0x0F; // IDLE
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init_defaults();
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}
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// SPI read: returns chip status byte + data byte (burst = multiple)
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uint8_t read_register(uint8_t addr) {
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uint8_t burst = (addr & 0xC0) >> 6;
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addr &= 0x3F;
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if (addr == 0x3E) { // PATABLE (burst read will iterate)
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return m_patable[0];
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}
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if (addr == 0x3F) { // TX FIFO read
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if (!m_tx_fifo.empty()) {
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uint8_t v = m_tx_fifo.front();
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m_tx_fifo.pop_front();
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return v;
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}
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return 0;
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}
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if (addr <= 0x2E) return m_regs[addr];
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if (addr >= 0x30) return m_chip_status; // status regs return chip status
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return 0;
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}
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// SPI write: addr & 0x3F with optional burst bit
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void write_register(uint8_t addr, uint8_t data) {
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bool burst = (addr & 0x40) != 0;
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addr &= 0x3F;
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if (addr == 0x3E) { // PATABLE
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m_patable[0] = data;
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return;
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}
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if (addr == 0x3F) { // TX FIFO
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if (m_tx_fifo.size() < 64) m_tx_fifo.push_back(data);
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return;
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}
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if (addr <= 0x2E) m_regs[addr] = data;
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// Handle burst writes
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(void)burst;
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}
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// Command strobe
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void strobe(uint8_t addr) {
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addr &= 0x3F;
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switch (addr) {
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case 0x30: m_state = CC_IDLE; break;
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case 0x34: m_state = CC_TX; m_chip_status = 0x02; break;
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case 0x36: m_state = CC_RX; m_chip_status = 0x01; break;
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case 0x3A: flush_rx_fifo(); break;
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case 0x3B: flush_tx_fifo(); break;
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default: break;
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}
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}
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uint8_t chip_status() const { return m_chip_status; }
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CC1101State state() const { return m_state; }
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bool gdo0() const { return m_gdo0; }
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bool gdo2() const { return m_gdo2; }
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void set_gdo0(bool v) { m_gdo0 = v; }
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void set_gdo2(bool v) { m_gdo2 = v; }
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// For testing: inject received data into RX FIFO
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void inject_rx_data(const uint8_t *data, size_t len) {
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for (size_t i = 0; i < len && m_rx_fifo.size() < 64; i++)
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m_rx_fifo.push_back(data[i]);
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}
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const uint8_t *registers() const { return m_regs; }
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// Preset configuration
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void apply_preset(const char *preset) {
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(void)preset;
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// Store preset-like values in regs 0x00-0x0B
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m_regs[0x00] = 0x0C; // IOCFG2
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m_regs[0x02] = 0x06; // IOCFG0
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m_regs[0x06] = 0x20; // PKTCTRL0
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m_regs[0x07] = 0x04; // PKTCTRL1
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m_regs[0x0B] = 0x06; // FSCTRL1
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}
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// Frequency set via registers 0x0D-0x0F (FREQ2, FREQ1, FREQ0)
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void set_frequency_mhz(float mhz) {
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uint32_t f = (uint32_t)((mhz / 26.0f) * 65536.0f);
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m_regs[0x0D] = (f >> 16) & 0xFF;
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m_regs[0x0E] = (f >> 8) & 0xFF;
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m_regs[0x0F] = f & 0xFF;
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}
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float frequency_mhz() const {
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uint32_t f = ((uint32_t)m_regs[0x0D] << 16) | ((uint32_t)m_regs[0x0E] << 8) | m_regs[0x0F];
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return (float)f * 26.0f / 65536.0f;
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}
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private:
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void init_defaults() {
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m_regs[0x0D] = 0x10; // FREQ2
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m_regs[0x0E] = 0xB1; // FREQ1
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m_regs[0x0F] = 0x3B; // FREQ0 (~433.92 MHz)
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m_patable[0] = 0xC0;
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}
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void flush_rx_fifo() { m_rx_fifo.clear(); }
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void flush_tx_fifo() { m_tx_fifo.clear(); }
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uint8_t m_regs[0x30];
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uint8_t m_patable[8];
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std::deque<uint8_t> m_tx_fifo;
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std::deque<uint8_t> m_rx_fifo;
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CC1101State m_state;
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uint8_t m_chip_status;
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bool m_gdo0;
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bool m_gdo2;
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};
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} // namespace hle

‎tools/hle/tests/test_cc1101.cpp‎

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#include <gtest/gtest.h>
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#include "hle/cc1101_emu.h"
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using namespace hle;
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TEST(CC1101Emulator, ResetState) {
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CC1101Emulator cc;
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EXPECT_EQ(cc.state(), CC_IDLE);
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EXPECT_EQ(cc.chip_status(), 0x0F);
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EXPECT_FALSE(cc.gdo0());
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EXPECT_FALSE(cc.gdo2());
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}
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TEST(CC1101Emulator, ReadWriteRegisters) {
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CC1101Emulator cc;
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cc.write_register(0x00, 0xAA);
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EXPECT_EQ(cc.read_register(0x00), 0xAA);
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cc.write_register(0x2E, 0x55);
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EXPECT_EQ(cc.read_register(0x2E), 0x55);
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}
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TEST(CC1101Emulator, StrobeTransitions) {
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CC1101Emulator cc;
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EXPECT_EQ(cc.state(), CC_IDLE);
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cc.strobe(0x34); // STX → TX
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EXPECT_EQ(cc.state(), CC_TX);
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EXPECT_EQ(cc.chip_status(), 0x02);
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cc.strobe(0x30); // SIDLE → IDLE
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EXPECT_EQ(cc.state(), CC_IDLE);
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cc.strobe(0x36); // SRX → RX
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EXPECT_EQ(cc.state(), CC_RX);
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EXPECT_EQ(cc.chip_status(), 0x01);
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}
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TEST(CC1101Emulator, FrequencySetting) {
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CC1101Emulator cc;
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cc.set_frequency_mhz(433.92f);
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float f = cc.frequency_mhz();
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EXPECT_NEAR(f, 433.92f, 0.1f);
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}
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TEST(CC1101Emulator, FIFOOperations) {
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CC1101Emulator cc;
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// Write to TX FIFO
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cc.write_register(0x3F, 0x11);
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cc.write_register(0x3F, 0x22);
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cc.write_register(0x3F, 0x33);
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// Read from TX FIFO
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EXPECT_EQ(cc.read_register(0x3F), 0x11);
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EXPECT_EQ(cc.read_register(0x3F), 0x22);
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EXPECT_EQ(cc.read_register(0x3F), 0x33);
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// RX FIFO injection
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uint8_t rx_data[] = {0xAA, 0xBB};
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cc.inject_rx_data(rx_data, 2);
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// Not directly readable via read_register without burst
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}
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TEST(CC1101Emulator, PATABLE) {
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CC1101Emulator cc;
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cc.write_register(0x3E, 0xC0);
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EXPECT_EQ(cc.read_register(0x3E), 0xC0);
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}
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TEST(CC1101Emulator, GDOControl) {
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CC1101Emulator cc;
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cc.set_gdo0(true);
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EXPECT_TRUE(cc.gdo0());
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cc.set_gdo2(true);
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EXPECT_TRUE(cc.gdo2());
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cc.set_gdo0(false);
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EXPECT_FALSE(cc.gdo0());
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}

‎tools/hle/tests/test_e2e_bridge.cpp‎

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#include <gtest/gtest.h>
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#include <thread>
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#include <cstring>
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#include "hle/spi_bridge_channel.h"
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#include "hle/cc1101_emu.h"
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using namespace hle;
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extern "C" {
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#include "esp_err.h"
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void hle_set_bridge_channel(hle::SPIBridgeChannel *ch);
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}
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TEST(E2EBridge, SystemPingViaBridge) {
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SPIBridgeChannel ch;
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hle_set_bridge_channel(&ch);
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// Emulate C5 side (normally runs in bridge_task)
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std::thread c5_side([&ch]() {
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uint8_t cmd_id, payload[256], payload_len;
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ASSERT_TRUE(ch.slave_wait_command(cmd_id, payload, payload_len));
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// Handle SYSTEM_PING
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if (cmd_id == 0x01) {
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ch.slave_send_response(cmd_id, 0x00, nullptr, 0);
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ch.slave_notify_irq();
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}
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});
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// P4 side: send ping command
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ch.master_send_command(0x01, nullptr, 0);
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ASSERT_TRUE(ch.master_wait_irq(1000));
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uint8_t resp_id, resp_payload[256], resp_len;
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ASSERT_TRUE(ch.master_receive_response(resp_id, resp_payload, resp_len, 100));
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EXPECT_EQ(resp_id, 0x01);
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EXPECT_GE(resp_len, 1u);
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EXPECT_EQ(resp_payload[0], 0x00); // OK
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c5_side.join();
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}
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TEST(E2EBridge, SystemStatus) {
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SPIBridgeChannel ch;
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hle_set_bridge_channel(&ch);
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std::thread c5_side([&ch]() {
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uint8_t cmd_id, payload[256], payload_len;
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ASSERT_TRUE(ch.slave_wait_command(cmd_id, payload, payload_len));
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// Emulate system status response with mock data
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if (cmd_id == 0x02) {
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// STATUS response: [status_byte, wifi_active, bt_running, firmware_ver_major, minor, patch]
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uint8_t status_data[] = {0x01, 0x00, 0x01, 0x00, 0x05}; // wifi inactive, bt running, v1.0.5
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ch.slave_send_response(cmd_id, 0x00, status_data, sizeof(status_data));
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ch.slave_notify_irq();
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}
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});
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ch.master_send_command(0x02, nullptr, 0);
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ASSERT_TRUE(ch.master_wait_irq(1000));
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uint8_t resp_id, resp_payload[256], resp_len;
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ASSERT_TRUE(ch.master_receive_response(resp_id, resp_payload, resp_len, 100));
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EXPECT_EQ(resp_id, 0x02);
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EXPECT_EQ(resp_payload[0], 0x00); // OK
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// status_data follows at offset 1
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EXPECT_EQ(resp_payload[1], 0x01); // wifi_active
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EXPECT_EQ(resp_payload[2], 0x00); // bt_running
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c5_side.join();
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}
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TEST(E2EBridge, WiFiScanDataFetch) {
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SPIBridgeChannel ch;
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hle_set_bridge_channel(&ch);
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const int ap_count = 3;
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std::thread c5_side([&ch, ap_count]() {
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uint8_t cmd_id, payload[256], payload_len;
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ASSERT_TRUE(ch.slave_wait_command(cmd_id, payload, payload_len));
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// Respond with count
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if (cmd_id == 0x20) {
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uint8_t count[2] = {uint8_t(ap_count), 0};
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ch.slave_send_response(cmd_id, 0x00, count, 2);
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ch.slave_notify_irq();
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}
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});
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ch.master_send_command(0x20, nullptr, 0);
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ASSERT_TRUE(ch.master_wait_irq(1000));
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uint8_t resp_id, resp_payload[256], resp_len;
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ASSERT_TRUE(ch.master_receive_response(resp_id, resp_payload, resp_len, 200));
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EXPECT_EQ(resp_id, 0x20);
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EXPECT_EQ(resp_payload[1], (uint8_t)ap_count);
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c5_side.join();
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}
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TEST(E2EBridge, StreamBackpressure) {
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SPIBridgeChannel ch;
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hle_set_bridge_channel(&ch);
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uint8_t data[64] = {};
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for (int i = 0; i < 64; i++) data[i] = (uint8_t)i;
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// Fill stream queue to capacity (8)
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for (int i = 0; i < 8; i++) {
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ASSERT_TRUE(ch.stream_push(0x25, data, 64));
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}
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// 9th should fail
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EXPECT_FALSE(ch.stream_push(0x25, data, 64));
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// Drain one
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uint8_t out_id, out_data[256];
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size_t out_len;
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ASSERT_TRUE(ch.stream_pop(out_id, out_data, out_len));
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// Now should accept one more
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EXPECT_TRUE(ch.stream_push(0x25, data, 64));
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}

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