Files

SIM

change to Verilog2001

Jun 9, 2023

33eb8bb · Jun 9, 2023

This branch is up to date with WangXuan95/FPGA-FOC:main.

Name		Name	Last commit message	Last commit date
parent directory ..
tb_clark_park_tr.v		tb_clark_park_tr.v	change to Verilog2001	Jun 9, 2023
tb_clark_park_tr_run_iverilog.bat		tb_clark_park_tr_run_iverilog.bat	change to Verilog2001	Jun 9, 2023
tb_svpwm.v		tb_svpwm.v	change to Verilog2001	Jun 9, 2023
tb_svpwm_run_iverilog.bat		tb_svpwm_run_iverilog.bat	change to Verilog2001	Jun 9, 2023