@@ -41,6 +41,7 @@ extern "C" {
4141#include " hal/spi_flash_ll.h"
4242#if !CONFIG_IDF_TARGET_ESP32
4343#include " hal/spimem_flash_ll.h"
44+ #include " soc/spi_mem_struct.h"
4445#endif
4546
4647#ifdef ESP_IDF_VERSION_MAJOR // IDF 4+
@@ -543,11 +544,12 @@ uint8_t EspClass::getFlashSourceFrequencyMHz(void) {
543544}
544545
545546/* *
546- * @brief Read the clock divider from hardware
547+ * @brief Read the clock divider from hardware using HAL structures
547548 * @return Clock divider value (1 = no division, 2 = divide by 2, etc.)
548549 */
549550uint8_t EspClass::getFlashClockDivider (void ) {
550- // Read CLOCK register using DR_REG_SPI0_BASE from soc/soc.h
551+ #if CONFIG_IDF_TARGET_ESP32
552+ // ESP32 classic: Read CLOCK register directly (no SPIMEM structure available)
551553 volatile uint32_t * clock_reg = (volatile uint32_t *)(DR_REG_SPI0_BASE + 0x14 );
552554 uint32_t clock_val = *clock_reg;
553555
@@ -559,6 +561,13 @@ uint8_t EspClass::getFlashClockDivider(void) {
559561 // Bits 16-23: clkdiv_pre
560562 uint8_t clkdiv_pre = (clock_val >> 16 ) & 0xFF ;
561563 return clkdiv_pre + 1 ;
564+ #else
565+ // Modern chips (S2, S3, C2, C3, C5, C6, H2, P4): Use SPIMEM0 structure
566+ if (SPIMEM0.clock .clk_equ_sysclk ) {
567+ return 1 ; // 1:1 clock (no divider)
568+ }
569+ return SPIMEM0.clock .clkcnt_n + 1 ;
570+ #endif
562571}
563572
564573/* *
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