Refactor flash frequency functions with HAL support

Refactor flash frequency functions to use ESP-IDF HAL for better maintainability and chip-specific handling.

Author: Jason2866

cores/esp32/Esp.cpp

@@ -36,6 +36,18 @@ extern "C" {
 #include "esp_chip_info.h"
 #include "esp_mac.h"
 #include "esp_flash.h"
+
+// Include for HPM (High Performance Mode) functions
+#if CONFIG_SPI_FLASH_HPM_ON
+#include "esp_private/spi_flash_os.h"
+#endif
+
+// Include HAL layer for flash clock access
+#include "hal/spi_flash_ll.h"
+#if !CONFIG_IDF_TARGET_ESP32
+#include "hal/spimem_flash_ll.h"
+#endif
+
 #ifdef ESP_IDF_VERSION_MAJOR  // IDF 4+
 #if CONFIG_IDF_TARGET_ESP32   // ESP32/PICO-D4
 #include "esp32/rom/spi_flash.h"
@@ -521,71 +533,51 @@ uint64_t EspClass::getEfuseMac(void) {
 // Flash Frequency Runtime Detection
 // ============================================================================
 
-// Note: DR_REG_SPI0_BASE is defined in soc/soc.h or soc/reg_base.h for each chip
-
-// Register offsets
-#define FLASH_CORE_CLK_SEL_OFFSET 0x80
-#define FLASH_CLOCK_OFFSET 0x14
+// Note: Using ESP-IDF HAL layer functions instead of direct register access
+// for better maintainability and chip-specific handling
 
 /**
- * @brief Read the source clock frequency from hardware registers
+ * @brief Read the source clock frequency using ESP-IDF HAL functions
  * @return Source clock frequency in MHz (80, 120, 160, or 240)
  */
 uint8_t EspClass::getFlashSourceFrequencyMHz(void) {
 #if CONFIG_IDF_TARGET_ESP32
-  // ESP32 classic supports 40 MHz and 80 MHz
-  // Note: ESP32 uses the PLL clock (80 MHz) as source and divides it
-  return 80;  // Always 80 MHz source, divider determines 40/80 MHz
+  // ESP32 classic: Use HAL function
+  return spi_flash_ll_get_source_clock_freq_mhz(0);  // host_id = 0 for SPI0
 #else
-  volatile uint32_t* core_clk_reg = (volatile uint32_t*)(DR_REG_SPI0_BASE + FLASH_CORE_CLK_SEL_OFFSET);
-  uint32_t core_clk_sel = (*core_clk_reg) & 0x3;  // Bits 0-1
-  
-  uint8_t source_freq = 80;  // Default
-  
-#if CONFIG_IDF_TARGET_ESP32S3
-  switch (core_clk_sel) {
-    case 0:  source_freq = 80;  break;
-    case 1:  source_freq = 120; break;
-    case 2:  source_freq = 160; break;
-    case 3:  source_freq = 240; break;
-  }
-#elif CONFIG_IDF_TARGET_ESP32S2
-  switch (core_clk_sel) {
-    case 0:  source_freq = 80;  break;
-    case 1:  source_freq = 120; break;
-    case 2:  source_freq = 160; break;
-  }
-#elif CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32C2 || \
-      CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32H2
-  switch (core_clk_sel) {
-    case 0:  source_freq = 80;  break;
-    case 1:  source_freq = 120; break;
-  }
-#else
-  switch (core_clk_sel) {
-    case 0:  source_freq = 80;  break;
-    case 1:  source_freq = 120; break;
-    default: source_freq = 80;  break;
-  }
-#endif
-  
-  return source_freq;
+  // For newer chips (S2, S3, C2, C3, C6, H2): Use spimem HAL function
+  return spimem_flash_ll_get_source_freq_mhz();
 #endif
 }
 
 /**
- * @brief Read the clock divider from hardware registers
+ * @brief Read the clock divider from hardware using HAL abstraction
  * @return Clock divider value (1 = no division, 2 = divide by 2, etc.)
+ * 
+ * @note This function still reads hardware registers but uses chip-specific
+ *       base addresses from ESP-IDF HAL layer
  */
 uint8_t EspClass::getFlashClockDivider(void) {
-  volatile uint32_t* clock_reg = (volatile uint32_t*)(DR_REG_SPI0_BASE + FLASH_CLOCK_OFFSET);
+  // Read CLOCK register using DR_REG_SPI0_BASE from soc/soc.h
+  volatile uint32_t* clock_reg = (volatile uint32_t*)(DR_REG_SPI0_BASE + 0x14);
   uint32_t clock_val = *clock_reg;
 
   // Bit 31: if set, clock is 1:1 (no divider)
   if (clock_val & (1 << 31)) {
     return 1;
   }
 
+  // Bits 16-23: clkdiv_pre
+  // This is consistent across all ESP32 chips
+  uint8_t clkdiv_pre = (clock_val >> 16) & 0xFF;
+  return clkdiv_pre + 1;
+}
+  
+  // Bit 31: if set, clock is 1:1 (no divider)
+  if (clock_val & (1 << 31)) {
+    return 1;
+  }
+  
   // Bits 16-23: clkdiv_pre
   uint8_t clkdiv_pre = (clock_val >> 16) & 0xFF;
   return clkdiv_pre + 1;
@@ -607,7 +599,36 @@ uint32_t EspClass::getFlashFrequencyMHz(void) {
 /**
  * @brief Check if High Performance Mode is enabled
  * @return true if flash runs > 80 MHz, false otherwise
+ * 
+ * @note This function combines hardware register reading with ESP-IDF HPM status
+ *       to provide accurate HPM detection across all scenarios.
  */
 bool EspClass::isFlashHighPerformanceModeEnabled(void) {
-  return getFlashFrequencyMHz() > 80;
+  uint32_t freq = getFlashFrequencyMHz();
+  
+  // Primary check: If frequency is > 80 MHz, HPM should be active
+  if (freq <= 80) {
+    return false;
+  }
+  
+#if CONFIG_SPI_FLASH_HPM_ON
+  // Secondary check: Use ESP-IDF HPM functions if available
+  // spi_flash_hpm_dummy_adjust() returns true if HPM with dummy adjustment is active
+  // Note: Some flash chips use other HPM methods (command, status register), 
+  // so we also trust the frequency reading
+  bool hpm_dummy_active = spi_flash_hpm_dummy_adjust();
+  
+  // If dummy adjust is active, definitely in HPM mode
+  if (hpm_dummy_active) {
+    return true;
+  }
+  
+  // If frequency > 80 MHz but dummy adjust not reported, 
+  // HPM might be enabled via other method (command/status register)
+  // Trust the frequency reading in this case
+  return true;
+#else
+  // If HPM support not compiled in, rely on frequency reading only
+  return true;
+#endif
 }