RISC-V support

[dendibakh]

Are there any plans to support RISC-V?

I tried hotspot on SiFive P550 and see the following:

// dump file collected with simple `perf record -e branches -- <my app>`
feature not properly read PerfHeader::CACHE 8 0
feature not properly read PerfHeader::SAMPLE_TIME 16 0
feature not properly read PerfHeader::BPF_BTF 4 0
1 528384 6 1 0
feature not properly read PerfHeader::BPF_PROG_INFO 4 0
feature not properly read PerfHeader::CPU_TOPOLOGY 380 348
feature not properly read PerfHeader::CPU_PMU_CAPS 4 0
Linux version "6.6.21" detected. Switching to automatic buffering.
No information about CPU architecture found. Cannot unwind.
"The hotspot-perfparser binary exited with code 6 (invalid perf data file)."

An estimate of how hard it would be to add the RISC-V support would also be great.
Thank you for considering.

[milianw]

Can you record some data on a small test binary compiled statically for RISC-V, then attach the static binary and the accompanying perf.data file?

An estimate of how hard it would be to add the RISC-V support would also be great.

Potentially trivial, assuming elfutils already supports that arch. we'd first need to extend perfregisterinfo.h/cpp based on info we can hopefully copy from the linux kernel and then hope for the best. then there might be arch specifics we might need to take into account, but that is only possible with someone who knows the details on that platform, i.e. do we need to adjust the instruction pointer address in a similar fashion as we do for ARM?