root scope declaration is not allowed in verilog 95/2K mode

[buttercutter]

ERROR: [VRFC 10-1342] root scope declaration is not allowed in verilog 95/2K mode [../../../../../../../riffa_hdl/functions.vh:44]
ERROR: [VRFC 10-1342] root scope declaration is not allowed in verilog 95/2K mode [../../../../../../../riffa_hdl/functions.vh:60]
ERROR: [VRFC 10-1342] root scope declaration is not allowed in verilog 95/2K mode [../../../../../../../riffa_hdl/tlp.vh:213]
ERROR: [VRFC 10-1342] root scope declaration is not allowed in verilog 95/2K mode [../../../../../../../riffa_hdl/tlp.vh:230]

I am using Vivado version 2017.2 as well as the default supported 2015.4 version to simulate the design. However, I got into the above errors. These errors only occur during simulation, not during synthesis/P&R stages.

I have tried both solution (introducing module wrapper as well as setting the file type as systemverilog) as in https://stackoverflow.com/questions/44979043/vivado-sim-error-root-scope-declaration-is-not-allowed-in-verilog-95-2k-mode , but they do not solve the above errors.

[Jzone315]

@ProMach
Did you fixed the issue? i am using riffa in vivado 2018.2, synthesized with the same issue, i am stuck here.Thanks a lot for your help.

[buttercutter]

@Jzone315 No, I am now using Quartus with Altera DE4

By the way, please have a look at #31

[YiSyuanChen]

@ProMach I'm facing exactly same problem. However, I'm wondering if the simulation is really workable? It seems that there is no usual testbench file for simulation. Does that means I can only verify the design by generate bitstream then load to FPGA? Any comment would be extremely appreciated.

[buttercutter]

@YiSyuanChen You could probably write your own simulation testbench, but for me, I use waveforms captured using ILA (some people call it as chipscope) which you should be very familiar with

[YiSyuanChen]

@ProMach Thanks for your rapid response, and you give a really useful information!! I'll check it in this way.