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MJoergenMJoergen
committedMar 6, 2023
Add avm_increase
1 parent ac5e371 commit 1b6bdf9

7 files changed

+772
-1
lines changed
 

‎Makefile

+3-1
Original file line numberDiff line numberDiff line change
@@ -6,6 +6,7 @@ SRC += avm_pause.vhd
66
SRC += avm_master_general.vhd
77
SRC += avm_arbit.vhd
88
SRC += avm_decrease.vhd
9+
SRC += avm_increase.vhd
910
SRC += avm_memory.vhd
1011
SRC += avm_memory_pause.vhd
1112
SRC += avm_cache.vhd
@@ -21,13 +22,14 @@ SRC += axi_skid_buffer.vhd
2122

2223
#DUT ?= burst_ctrl
2324
#DUT ?= avm_decrease
25+
DUT ?= avm_increase
2426
#DUT ?= avalon_axi
2527
#DUT ?= avm_arbit
2628
#DUT ?= avm_pause
2729
#DUT ?= avm_cache
2830
#DUT ?= avm_cache2
2931
#DUT ?= avm_master2
30-
DUT ?= avm_pipe
32+
#DUT ?= avm_pipe
3133
#DUT ?= axi_gcr
3234
#DUT ?= axi_shrinker
3335
#DUT ?= axi_expander

‎avm_increase.gtkw

+51
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@@ -0,0 +1,51 @@
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[*]
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[*] GTKWave Analyzer v3.3.104 (w)1999-2020 BSI
3+
[*] Mon Mar 6 19:12:24 2023
4+
[*]
5+
[dumpfile] "/home/mike/git/MJoergen/Avalon/avm_increase_bmc/engine_0/trace.vcd"
6+
[dumpfile_mtime] "Mon Mar 6 19:10:45 2023"
7+
[dumpfile_size] 6176
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[savefile] "/home/mike/git/MJoergen/Avalon/avm_increase.gtkw"
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[timestart] 0
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[size] 1566 856
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[pos] 2018 30
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*-3.624538 24 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
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[treeopen] avm_increase.
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[sst_width] 373
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[signals_width] 365
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[sst_expanded] 1
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[sst_vpaned_height] 232
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@28
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avm_increase.clk_i
20+
avm_increase.rst_i
21+
@22
22+
avm_increase.i_avm_increase.f_m_rd_burstcount[31:0]
23+
avm_increase.i_avm_increase.f_s_rd_burstcount[31:0]
24+
@23
25+
avm_increase.i_avm_increase.f_s_wr_burstcount[31:0]
26+
@28
27+
avm_increase.s_avm_waitrequest_o
28+
avm_increase.s_avm_write_i
29+
avm_increase.s_avm_read_i
30+
@22
31+
avm_increase.s_avm_address_i[9:0]
32+
avm_increase.s_avm_burstcount_i[7:0]
33+
@28
34+
avm_increase.s_avm_readdatavalid_o
35+
avm_increase.m_avm_waitrequest_i
36+
avm_increase.m_avm_write_o
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avm_increase.m_avm_read_o
38+
@22
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avm_increase.m_avm_address_o[8:0]
40+
avm_increase.m_avm_burstcount_o[7:0]
41+
@28
42+
avm_increase.m_avm_readdatavalid_i
43+
avm_increase.m_avm_ready
44+
avm_increase.m_avm_readdatavalid
45+
@22
46+
avm_increase.s_burstcount[7:0]
47+
@28
48+
avm_increase.offset
49+
avm_increase.state[1:0]
50+
[pattern_trace] 1
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[pattern_trace] 0

‎avm_increase.psl

+117
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,117 @@
1+
vunit i_avm_increase(avm_increase(synthesis))
2+
{
3+
-- set all declarations to run on clk_i
4+
default clock is rising_edge(clk_i);
5+
6+
-- Additional signals used during formal verification
7+
signal f_s_wr_burstcount : integer;
8+
signal f_s_rd_burstcount : integer;
9+
signal f_m_rd_burstcount : integer;
10+
11+
p_s_wr_burstcount : process (clk_i)
12+
begin
13+
if rising_edge(clk_i) then
14+
if s_avm_write_i and not s_avm_waitrequest_o then
15+
if f_s_wr_burstcount = 0 then
16+
f_s_wr_burstcount <= to_integer(s_avm_burstcount_i) - 1;
17+
else
18+
f_s_wr_burstcount <= f_s_wr_burstcount - 1;
19+
end if;
20+
end if;
21+
if rst_i then
22+
f_s_wr_burstcount <= 0;
23+
end if;
24+
end if;
25+
end process p_s_wr_burstcount;
26+
27+
p_s_rd_burstcount : process (clk_i)
28+
begin
29+
if rising_edge(clk_i) then
30+
if s_avm_readdatavalid_o then
31+
f_s_rd_burstcount <= f_s_rd_burstcount - 1;
32+
end if;
33+
if s_avm_read_i and not s_avm_waitrequest_o then
34+
f_s_rd_burstcount <= to_integer(s_avm_burstcount_i);
35+
end if;
36+
if rst_i then
37+
f_s_rd_burstcount <= 0;
38+
end if;
39+
end if;
40+
end process p_s_rd_burstcount;
41+
42+
p_m_rd_burstcount : process (clk_i)
43+
begin
44+
if rising_edge(clk_i) then
45+
if m_avm_readdatavalid_i then
46+
f_m_rd_burstcount <= f_m_rd_burstcount - 1;
47+
end if;
48+
if m_avm_read_o and not m_avm_waitrequest_i then
49+
f_m_rd_burstcount <= to_integer(m_avm_burstcount_o);
50+
end if;
51+
if rst_i then
52+
f_m_rd_burstcount <= 0;
53+
end if;
54+
end if;
55+
end process p_m_rd_burstcount;
56+
57+
58+
-----------------------------
59+
-- ASSERTIONS ABOUT OUTPUTS
60+
-----------------------------
61+
62+
-- Master must be empty after reset
63+
f_master_after_reset_empty : assert always {rst_i} |=> not (m_avm_write_o or m_avm_read_o);
64+
65+
-- Master may not assert both write and read.
66+
f_master_not_double: assert always rst_i or not (m_avm_write_o and m_avm_read_o);
67+
68+
-- Master must be stable until accepted
69+
f_master_stable : assert always {(m_avm_write_o or m_avm_read_o) and m_avm_waitrequest_i and not rst_i} |=>
70+
{stable(m_avm_write_o) and stable(m_avm_read_o) and stable(m_avm_address_o) and stable(m_avm_writedata_o) and
71+
stable(m_avm_byteenable_o) and stable(m_avm_burstcount_o)};
72+
73+
-- Slave must keep accepting
74+
f_slave_no_new_wait : assert always {not s_avm_waitrequest_o and not s_avm_read_i and not s_avm_write_i} |=> stable(s_avm_waitrequest_o);
75+
76+
f_master_burst_valid : assert always rst_i or not (m_avm_read_o and not m_avm_waitrequest_i and nor(m_avm_burstcount_o));
77+
f_slave_burst_reset : assert always rst_i |=> {f_s_rd_burstcount = 0};
78+
f_slave_burst_range : assert always rst_i or f_s_rd_burstcount >= 0;
79+
f_slave_burst_block : assert always rst_i or f_s_rd_burstcount = 0 or s_avm_waitrequest_o or (f_s_rd_burstcount = 1 and s_avm_readdatavalid_o = '1');
80+
f_slave_no_data : assert always rst_i or not (f_s_rd_burstcount = 0 and s_avm_readdatavalid_o = '1');
81+
82+
83+
-----------------------------
84+
-- ASSUMPTIONS ABOUT INPUTS
85+
-----------------------------
86+
87+
-- Require reset at startup.
88+
f_reset : assume {rst_i};
89+
90+
-- Slave must be empty after reset
91+
f_slave_after_reset_empty : assume always {rst_i} |=> not (s_avm_write_i or s_avm_read_i);
92+
93+
-- Slave may not assert both write and read.
94+
f_slave_not_double: assume always not (s_avm_write_i and s_avm_read_i);
95+
96+
-- Slaves must be stable until accepted
97+
f_slave_input_stable : assume always {(s_avm_write_i or s_avm_read_i) and s_avm_waitrequest_o and not rst_i} |=>
98+
{stable(s_avm_write_i) and stable(s_avm_read_i) and stable(s_avm_address_i) and stable(s_avm_writedata_i) and
99+
stable(s_avm_byteenable_i) and stable(s_avm_burstcount_i)};
100+
101+
-- Master must keep accepting
102+
f_master_no_new_wait : assume always {not m_avm_waitrequest_i and not m_avm_read_o and not m_avm_write_o} |=> stable(m_avm_waitrequest_i);
103+
104+
f_slave_burst_valid : assume always rst_i or not (s_avm_read_i and not s_avm_waitrequest_o and nor(s_avm_burstcount_i));
105+
f_master_burst_reset : assume always rst_i |=> {f_m_rd_burstcount = 0};
106+
f_master_burst_range : assume always rst_i or f_m_rd_burstcount >= 0;
107+
f_master_burst_block : assume always rst_i or f_m_rd_burstcount = 0 or m_avm_waitrequest_i or (f_m_rd_burstcount = 1 and m_avm_readdatavalid_i = '1');
108+
f_master_no_data : assume always rst_i or not (f_m_rd_burstcount = 0 and m_avm_readdatavalid_i = '1');
109+
f_slave_wr_burst : assume always f_s_wr_burstcount /= 0 -> s_avm_read_i = '0';
110+
111+
112+
--------------------------------------------
113+
-- COVER STATEMENTS TO VERIFY REACHABILITY
114+
--------------------------------------------
115+
116+
} -- vunit i_avm_increase(avm_increase(synthesis))
117+

‎avm_increase.sby

+19
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,19 @@
1+
[tasks]
2+
bmc
3+
4+
[options]
5+
bmc: mode bmc
6+
bmc: depth 6
7+
8+
[engines]
9+
smtbmc
10+
11+
[script]
12+
ghdl --std=08 -gG_SLAVE_DATA_SIZE=8 -gG_MASTER_DATA_SIZE=16 -gG_SLAVE_ADDRESS_SIZE=10 -gG_MASTER_ADDRESS_SIZE=9 avm_increase.vhd avm_increase.psl axi_fifo_small.vhd -e avm_increase
13+
prep -top avm_increase
14+
15+
[files]
16+
avm_increase.psl
17+
avm_increase.vhd
18+
axi_fifo_small.vhd
19+

‎avm_increase.vhd

+201
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,201 @@
1+
library ieee;
2+
use ieee.std_logic_1164.all;
3+
use ieee.numeric_std.all;
4+
use ieee.numeric_std_unsigned.all;
5+
6+
-- This increases the data width of an Avalon Memory Map interface.
7+
8+
entity avm_increase is
9+
generic (
10+
G_SLAVE_ADDRESS_SIZE : integer;
11+
G_SLAVE_DATA_SIZE : integer;
12+
G_MASTER_ADDRESS_SIZE : integer;
13+
G_MASTER_DATA_SIZE : integer -- Must be an integer multiple of G_SLAVE_DATA_SIZE
14+
);
15+
port (
16+
clk_i : in std_logic;
17+
rst_i : in std_logic;
18+
19+
-- Slave interface (input)
20+
s_avm_write_i : in std_logic;
21+
s_avm_read_i : in std_logic;
22+
s_avm_address_i : in std_logic_vector(G_SLAVE_ADDRESS_SIZE - 1 downto 0);
23+
s_avm_writedata_i : in std_logic_vector(G_SLAVE_DATA_SIZE - 1 downto 0);
24+
s_avm_byteenable_i : in std_logic_vector(G_SLAVE_DATA_SIZE / 8 - 1 downto 0);
25+
s_avm_burstcount_i : in std_logic_vector(7 downto 0);
26+
s_avm_readdata_o : out std_logic_vector(G_SLAVE_DATA_SIZE - 1 downto 0);
27+
s_avm_readdatavalid_o : out std_logic;
28+
s_avm_waitrequest_o : out std_logic;
29+
30+
-- Master interface (output)
31+
m_avm_write_o : out std_logic;
32+
m_avm_read_o : out std_logic;
33+
m_avm_address_o : out std_logic_vector(G_MASTER_ADDRESS_SIZE - 1 downto 0);
34+
m_avm_writedata_o : out std_logic_vector(G_MASTER_DATA_SIZE - 1 downto 0);
35+
m_avm_byteenable_o : out std_logic_vector(G_MASTER_DATA_SIZE / 8 - 1 downto 0);
36+
m_avm_burstcount_o : out std_logic_vector(7 downto 0);
37+
m_avm_readdata_i : in std_logic_vector(G_MASTER_DATA_SIZE - 1 downto 0);
38+
m_avm_readdatavalid_i : in std_logic;
39+
m_avm_waitrequest_i : in std_logic
40+
);
41+
end entity avm_increase;
42+
43+
architecture synthesis of avm_increase is
44+
45+
constant C_RATIO : integer := G_MASTER_DATA_SIZE / G_SLAVE_DATA_SIZE;
46+
constant C_ADDRESS_SHIFT : integer := G_SLAVE_ADDRESS_SIZE - G_MASTER_ADDRESS_SIZE;
47+
48+
type t_state is (IDLE_ST, WRITING_ST, READING_ST, RESPONSE_ST);
49+
signal state : t_state := IDLE_ST;
50+
51+
signal offset : std_logic_vector(C_ADDRESS_SHIFT - 1 downto 0);
52+
signal s_burstcount : std_logic_vector(7 downto 0);
53+
signal m_avm_readdata : std_logic_vector(G_MASTER_DATA_SIZE - 1 downto 0);
54+
signal m_avm_readdatavalid : std_logic;
55+
signal m_avm_ready : std_logic;
56+
57+
begin
58+
59+
s_avm_waitrequest_o <= '0' when (state = IDLE_ST or state = WRITING_ST) and
60+
(m_avm_write_o = '0' or m_avm_waitrequest_i = '0') else
61+
'1';
62+
63+
assert C_RATIO > 1
64+
severity failure;
65+
assert C_ADDRESS_SHIFT > 0
66+
severity failure;
67+
assert G_MASTER_DATA_SIZE = C_RATIO * G_SLAVE_DATA_SIZE
68+
severity failure;
69+
assert G_MASTER_DATA_SIZE * (2 ** G_MASTER_ADDRESS_SIZE) =
70+
G_SLAVE_DATA_SIZE * (2 ** G_SLAVE_ADDRESS_SIZE)
71+
severity failure;
72+
73+
fsm_proc : process (clk_i)
74+
pure function calc_m_burstcount (address : std_logic_vector; burstcount : std_logic_vector) return std_logic_vector is
75+
variable res : std_logic_vector(G_SLAVE_ADDRESS_SIZE + 1 downto 0);
76+
begin
77+
res := (("00" & address) + burstcount - 1) / C_RATIO - ("00" & address) / C_RATIO + 1;
78+
return res(7 downto 0);
79+
end function calc_m_burstcount;
80+
81+
begin
82+
if rising_edge(clk_i) then
83+
if m_avm_waitrequest_i = '0' then
84+
m_avm_read_o <= '0';
85+
m_avm_write_o <= '0';
86+
end if;
87+
88+
case state is
89+
90+
when IDLE_ST =>
91+
if s_avm_write_i = '1' and s_avm_waitrequest_o = '0' then
92+
m_avm_write_o <= '1';
93+
m_avm_read_o <= '0';
94+
m_avm_address_o <= s_avm_address_i(G_SLAVE_ADDRESS_SIZE - 1 downto C_ADDRESS_SHIFT);
95+
m_avm_byteenable_o <= (others => '0');
96+
m_avm_burstcount_o <= calc_m_burstcount(s_avm_address_i, s_avm_burstcount_i);
97+
98+
for i in 0 to C_RATIO - 1 loop
99+
if i = to_integer(s_avm_address_i(C_ADDRESS_SHIFT - 1 downto 0)) then
100+
m_avm_writedata_o(G_SLAVE_DATA_SIZE * (i + 1) - 1 downto G_SLAVE_DATA_SIZE * i) <= s_avm_writedata_i;
101+
m_avm_byteenable_o(G_SLAVE_DATA_SIZE / 8 * (i + 1) - 1 downto G_SLAVE_DATA_SIZE / 8 * i) <= s_avm_byteenable_i;
102+
end if;
103+
end loop;
104+
105+
if s_avm_burstcount_i /= X"01" then
106+
m_avm_write_o <= '0';
107+
s_burstcount <= s_avm_burstcount_i - 1;
108+
offset <= s_avm_address_i(C_ADDRESS_SHIFT - 1 downto 0) + 1;
109+
state <= WRITING_ST;
110+
end if;
111+
end if;
112+
113+
if s_avm_read_i = '1' and s_avm_waitrequest_o = '0' then
114+
m_avm_write_o <= '0';
115+
m_avm_read_o <= '1';
116+
m_avm_address_o <= s_avm_address_i(G_SLAVE_ADDRESS_SIZE - 1 downto C_ADDRESS_SHIFT);
117+
m_avm_burstcount_o <= calc_m_burstcount(s_avm_address_i, s_avm_burstcount_i);
118+
s_burstcount <= s_avm_burstcount_i;
119+
offset <= s_avm_address_i(C_ADDRESS_SHIFT - 1 downto 0);
120+
state <= READING_ST;
121+
end if;
122+
123+
when WRITING_ST =>
124+
if s_avm_write_i = '1' and s_avm_waitrequest_o = '0' and s_burstcount > 0 then
125+
s_burstcount <= s_burstcount - 1;
126+
offset <= offset + 1;
127+
128+
if offset = C_RATIO - 1 then
129+
m_avm_write_o <= '1';
130+
end if;
131+
132+
for i in 0 to C_RATIO - 1 loop
133+
if i = to_integer(offset) then
134+
m_avm_writedata_o(G_SLAVE_DATA_SIZE * (i + 1) - 1 downto G_SLAVE_DATA_SIZE * i) <= s_avm_writedata_i;
135+
m_avm_byteenable_o(G_SLAVE_DATA_SIZE / 8 * (i + 1) - 1 downto G_SLAVE_DATA_SIZE / 8 * i) <= s_avm_byteenable_i;
136+
end if;
137+
end loop;
138+
139+
if s_burstcount = 1 then
140+
state <= IDLE_ST;
141+
end if;
142+
end if;
143+
144+
when READING_ST =>
145+
if m_avm_readdatavalid = '1' then
146+
s_burstcount <= s_burstcount - 1;
147+
offset <= offset + 1;
148+
if s_burstcount > 1 then
149+
state <= RESPONSE_ST;
150+
else
151+
state <= IDLE_ST;
152+
end if;
153+
end if;
154+
155+
when RESPONSE_ST =>
156+
if s_burstcount > 1 then
157+
s_burstcount <= s_burstcount - 1;
158+
offset <= offset + 1;
159+
else
160+
state <= IDLE_ST;
161+
end if;
162+
163+
when others =>
164+
null;
165+
166+
end case;
167+
168+
if rst_i = '1' then
169+
m_avm_read_o <= '0';
170+
m_avm_write_o <= '0';
171+
state <= IDLE_ST;
172+
end if;
173+
end if;
174+
end process fsm_proc;
175+
176+
s_avm_readdata_o <= m_avm_readdata(G_SLAVE_DATA_SIZE * (to_integer(offset) + 1) - 1 downto G_SLAVE_DATA_SIZE * to_integer(offset));
177+
s_avm_readdatavalid_o <= m_avm_readdatavalid when state = READING_ST else
178+
'1' when state = RESPONSE_ST else
179+
'0';
180+
181+
m_avm_ready <= '1' when offset = C_RATIO - 1 else
182+
'0';
183+
184+
axi_fifo_small_inst : entity work.axi_fifo_small
185+
generic map (
186+
G_RAM_WIDTH => G_MASTER_DATA_SIZE,
187+
G_RAM_DEPTH => 256
188+
)
189+
port map (
190+
clk_i => clk_i,
191+
rst_i => rst_i,
192+
s_ready_o => open,
193+
s_valid_i => m_avm_readdatavalid_i,
194+
s_data_i => m_avm_readdata_i,
195+
m_ready_i => m_avm_ready,
196+
m_valid_o => m_avm_readdatavalid,
197+
m_data_o => m_avm_readdata
198+
); -- axi_fifo_small_inst
199+
200+
end architecture synthesis;
201+

‎tb_avm_increase.gtkw

+89
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@@ -0,0 +1,89 @@
1+
[*]
2+
[*] GTKWave Analyzer v3.3.104 (w)1999-2020 BSI
3+
[*] Mon Mar 6 18:41:12 2023
4+
[*]
5+
[dumpfile] "/home/mike/git/MJoergen/Avalon/tb_avm_increase.ghw"
6+
[dumpfile_mtime] "Mon Mar 6 18:41:00 2023"
7+
[dumpfile_size] 1477391
8+
[savefile] "/home/mike/git/MJoergen/Avalon/tb_avm_increase.gtkw"
9+
[timestart] 0
10+
[size] 1607 902
11+
[pos] 1996 5
12+
*-32.925472 5295300000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
13+
[treeopen] top.
14+
[treeopen] top.tb_avm_increase.
15+
[treeopen] top.tb_avm_increase.i_avm_increase.
16+
[sst_width] 249
17+
[signals_width] 333
18+
[sst_expanded] 1
19+
[sst_vpaned_height] 248
20+
@c00200
21+
-avm_master
22+
@28
23+
top.tb_avm_increase.i_avm_master.clk_i
24+
top.tb_avm_increase.i_avm_master.rst_i
25+
top.tb_avm_increase.i_avm_master.start_i
26+
top.tb_avm_increase.i_avm_master.wait_o
27+
top.tb_avm_increase.i_avm_master.avm_write_o
28+
top.tb_avm_increase.i_avm_master.avm_read_o
29+
top.tb_avm_increase.i_avm_master.avm_readdatavalid_i
30+
top.tb_avm_increase.i_avm_master.avm_waitrequest_i
31+
top.tb_avm_increase.i_avm_master.error_o
32+
@22
33+
#{top.tb_avm_increase.i_avm_master.write_burstcount_i[7:0]} top.tb_avm_increase.i_avm_master.write_burstcount_i[7] top.tb_avm_increase.i_avm_master.write_burstcount_i[6] top.tb_avm_increase.i_avm_master.write_burstcount_i[5] top.tb_avm_increase.i_avm_master.write_burstcount_i[4] top.tb_avm_increase.i_avm_master.write_burstcount_i[3] top.tb_avm_increase.i_avm_master.write_burstcount_i[2] top.tb_avm_increase.i_avm_master.write_burstcount_i[1] top.tb_avm_increase.i_avm_master.write_burstcount_i[0]
34+
#{top.tb_avm_increase.i_avm_master.read_burstcount_i[7:0]} top.tb_avm_increase.i_avm_master.read_burstcount_i[7] top.tb_avm_increase.i_avm_master.read_burstcount_i[6] top.tb_avm_increase.i_avm_master.read_burstcount_i[5] top.tb_avm_increase.i_avm_master.read_burstcount_i[4] top.tb_avm_increase.i_avm_master.read_burstcount_i[3] top.tb_avm_increase.i_avm_master.read_burstcount_i[2] top.tb_avm_increase.i_avm_master.read_burstcount_i[1] top.tb_avm_increase.i_avm_master.read_burstcount_i[0]
35+
#{top.tb_avm_increase.i_avm_master.avm_address_o[5:0]} top.tb_avm_increase.i_avm_master.avm_address_o[5] top.tb_avm_increase.i_avm_master.avm_address_o[4] top.tb_avm_increase.i_avm_master.avm_address_o[3] top.tb_avm_increase.i_avm_master.avm_address_o[2] top.tb_avm_increase.i_avm_master.avm_address_o[1] top.tb_avm_increase.i_avm_master.avm_address_o[0]
36+
#{top.tb_avm_increase.i_avm_master.avm_writedata_o[15:0]} top.tb_avm_increase.i_avm_master.avm_writedata_o[7] top.tb_avm_increase.i_avm_master.avm_writedata_o[6] top.tb_avm_increase.i_avm_master.avm_writedata_o[5] top.tb_avm_increase.i_avm_master.avm_writedata_o[4] top.tb_avm_increase.i_avm_master.avm_writedata_o[3] top.tb_avm_increase.i_avm_master.avm_writedata_o[2] top.tb_avm_increase.i_avm_master.avm_writedata_o[1] top.tb_avm_increase.i_avm_master.avm_writedata_o[0]
37+
@28
38+
#{top.tb_avm_increase.i_avm_master.avm_byteenable_o[1:0]} top.tb_avm_increase.i_avm_master.avm_byteenable_o[0]
39+
@22
40+
#{top.tb_avm_increase.i_avm_master.avm_burstcount_o[7:0]} top.tb_avm_increase.i_avm_master.avm_burstcount_o[7] top.tb_avm_increase.i_avm_master.avm_burstcount_o[6] top.tb_avm_increase.i_avm_master.avm_burstcount_o[5] top.tb_avm_increase.i_avm_master.avm_burstcount_o[4] top.tb_avm_increase.i_avm_master.avm_burstcount_o[3] top.tb_avm_increase.i_avm_master.avm_burstcount_o[2] top.tb_avm_increase.i_avm_master.avm_burstcount_o[1] top.tb_avm_increase.i_avm_master.avm_burstcount_o[0]
41+
#{top.tb_avm_increase.i_avm_master.avm_readdata_i[15:0]} top.tb_avm_increase.i_avm_master.avm_readdata_i[7] top.tb_avm_increase.i_avm_master.avm_readdata_i[6] top.tb_avm_increase.i_avm_master.avm_readdata_i[5] top.tb_avm_increase.i_avm_master.avm_readdata_i[4] top.tb_avm_increase.i_avm_master.avm_readdata_i[3] top.tb_avm_increase.i_avm_master.avm_readdata_i[2] top.tb_avm_increase.i_avm_master.avm_readdata_i[1] top.tb_avm_increase.i_avm_master.avm_readdata_i[0]
42+
#{top.tb_avm_increase.i_avm_master.address_o[5:0]} top.tb_avm_increase.i_avm_master.address_o[5] top.tb_avm_increase.i_avm_master.address_o[4] top.tb_avm_increase.i_avm_master.address_o[3] top.tb_avm_increase.i_avm_master.address_o[2] top.tb_avm_increase.i_avm_master.address_o[1] top.tb_avm_increase.i_avm_master.address_o[0]
43+
#{top.tb_avm_increase.i_avm_master.data_exp_o[15:0]} top.tb_avm_increase.i_avm_master.data_exp_o[7] top.tb_avm_increase.i_avm_master.data_exp_o[6] top.tb_avm_increase.i_avm_master.data_exp_o[5] top.tb_avm_increase.i_avm_master.data_exp_o[4] top.tb_avm_increase.i_avm_master.data_exp_o[3] top.tb_avm_increase.i_avm_master.data_exp_o[2] top.tb_avm_increase.i_avm_master.data_exp_o[1] top.tb_avm_increase.i_avm_master.data_exp_o[0]
44+
#{top.tb_avm_increase.i_avm_master.data_read_o[15:0]} top.tb_avm_increase.i_avm_master.data_read_o[7] top.tb_avm_increase.i_avm_master.data_read_o[6] top.tb_avm_increase.i_avm_master.data_read_o[5] top.tb_avm_increase.i_avm_master.data_read_o[4] top.tb_avm_increase.i_avm_master.data_read_o[3] top.tb_avm_increase.i_avm_master.data_read_o[2] top.tb_avm_increase.i_avm_master.data_read_o[1] top.tb_avm_increase.i_avm_master.data_read_o[0]
45+
@1401200
46+
-avm_master
47+
@800200
48+
-avm_increase
49+
@28
50+
top.tb_avm_increase.i_avm_increase.clk_i
51+
top.tb_avm_increase.i_avm_increase.rst_i
52+
top.tb_avm_increase.i_avm_increase.s_avm_waitrequest_o
53+
top.tb_avm_increase.i_avm_increase.s_avm_write_i
54+
top.tb_avm_increase.i_avm_increase.s_avm_read_i
55+
@22
56+
#{top.tb_avm_increase.i_avm_increase.s_avm_address_i[5:0]} top.tb_avm_increase.i_avm_increase.s_avm_address_i[5] top.tb_avm_increase.i_avm_increase.s_avm_address_i[4] top.tb_avm_increase.i_avm_increase.s_avm_address_i[3] top.tb_avm_increase.i_avm_increase.s_avm_address_i[2] top.tb_avm_increase.i_avm_increase.s_avm_address_i[1] top.tb_avm_increase.i_avm_increase.s_avm_address_i[0]
57+
#{top.tb_avm_increase.i_avm_increase.s_avm_writedata_i[15:0]} top.tb_avm_increase.i_avm_increase.s_avm_writedata_i[7] top.tb_avm_increase.i_avm_increase.s_avm_writedata_i[6] top.tb_avm_increase.i_avm_increase.s_avm_writedata_i[5] top.tb_avm_increase.i_avm_increase.s_avm_writedata_i[4] top.tb_avm_increase.i_avm_increase.s_avm_writedata_i[3] top.tb_avm_increase.i_avm_increase.s_avm_writedata_i[2] top.tb_avm_increase.i_avm_increase.s_avm_writedata_i[1] top.tb_avm_increase.i_avm_increase.s_avm_writedata_i[0]
58+
@28
59+
#{top.tb_avm_increase.i_avm_increase.s_avm_byteenable_i[1:0]} top.tb_avm_increase.i_avm_increase.s_avm_byteenable_i[0]
60+
@23
61+
#{top.tb_avm_increase.i_avm_increase.s_avm_burstcount_i[7:0]} top.tb_avm_increase.i_avm_increase.s_avm_burstcount_i[7] top.tb_avm_increase.i_avm_increase.s_avm_burstcount_i[6] top.tb_avm_increase.i_avm_increase.s_avm_burstcount_i[5] top.tb_avm_increase.i_avm_increase.s_avm_burstcount_i[4] top.tb_avm_increase.i_avm_increase.s_avm_burstcount_i[3] top.tb_avm_increase.i_avm_increase.s_avm_burstcount_i[2] top.tb_avm_increase.i_avm_increase.s_avm_burstcount_i[1] top.tb_avm_increase.i_avm_increase.s_avm_burstcount_i[0]
62+
@28
63+
top.tb_avm_increase.i_avm_increase.s_avm_readdatavalid_o
64+
@22
65+
#{top.tb_avm_increase.i_avm_increase.s_avm_readdata_o[15:0]} top.tb_avm_increase.i_avm_increase.s_avm_readdata_o[7] top.tb_avm_increase.i_avm_increase.s_avm_readdata_o[6] top.tb_avm_increase.i_avm_increase.s_avm_readdata_o[5] top.tb_avm_increase.i_avm_increase.s_avm_readdata_o[4] top.tb_avm_increase.i_avm_increase.s_avm_readdata_o[3] top.tb_avm_increase.i_avm_increase.s_avm_readdata_o[2] top.tb_avm_increase.i_avm_increase.s_avm_readdata_o[1] top.tb_avm_increase.i_avm_increase.s_avm_readdata_o[0]
66+
@28
67+
top.tb_avm_increase.i_avm_increase.m_avm_waitrequest_i
68+
top.tb_avm_increase.i_avm_increase.m_avm_write_o
69+
top.tb_avm_increase.i_avm_increase.m_avm_read_o
70+
@22
71+
#{top.tb_avm_increase.i_avm_increase.m_avm_address_o[4:0]} top.tb_avm_increase.i_avm_increase.m_avm_address_o[4] top.tb_avm_increase.i_avm_increase.m_avm_address_o[3] top.tb_avm_increase.i_avm_increase.m_avm_address_o[2] top.tb_avm_increase.i_avm_increase.m_avm_address_o[1] top.tb_avm_increase.i_avm_increase.m_avm_address_o[0]
72+
#{top.tb_avm_increase.i_avm_increase.m_avm_writedata_o[31:0]} top.tb_avm_increase.i_avm_increase.m_avm_writedata_o[15] top.tb_avm_increase.i_avm_increase.m_avm_writedata_o[14] top.tb_avm_increase.i_avm_increase.m_avm_writedata_o[13] top.tb_avm_increase.i_avm_increase.m_avm_writedata_o[12] top.tb_avm_increase.i_avm_increase.m_avm_writedata_o[11] top.tb_avm_increase.i_avm_increase.m_avm_writedata_o[10] top.tb_avm_increase.i_avm_increase.m_avm_writedata_o[9] top.tb_avm_increase.i_avm_increase.m_avm_writedata_o[8] top.tb_avm_increase.i_avm_increase.m_avm_writedata_o[7] top.tb_avm_increase.i_avm_increase.m_avm_writedata_o[6] top.tb_avm_increase.i_avm_increase.m_avm_writedata_o[5] top.tb_avm_increase.i_avm_increase.m_avm_writedata_o[4] top.tb_avm_increase.i_avm_increase.m_avm_writedata_o[3] top.tb_avm_increase.i_avm_increase.m_avm_writedata_o[2] top.tb_avm_increase.i_avm_increase.m_avm_writedata_o[1] top.tb_avm_increase.i_avm_increase.m_avm_writedata_o[0]
73+
#{top.tb_avm_increase.i_avm_increase.m_avm_byteenable_o[3:0]} top.tb_avm_increase.i_avm_increase.m_avm_byteenable_o[1] top.tb_avm_increase.i_avm_increase.m_avm_byteenable_o[0]
74+
#{top.tb_avm_increase.i_avm_increase.m_avm_burstcount_o[7:0]} top.tb_avm_increase.i_avm_increase.m_avm_burstcount_o[7] top.tb_avm_increase.i_avm_increase.m_avm_burstcount_o[6] top.tb_avm_increase.i_avm_increase.m_avm_burstcount_o[5] top.tb_avm_increase.i_avm_increase.m_avm_burstcount_o[4] top.tb_avm_increase.i_avm_increase.m_avm_burstcount_o[3] top.tb_avm_increase.i_avm_increase.m_avm_burstcount_o[2] top.tb_avm_increase.i_avm_increase.m_avm_burstcount_o[1] top.tb_avm_increase.i_avm_increase.m_avm_burstcount_o[0]
75+
@28
76+
top.tb_avm_increase.i_avm_increase.m_avm_readdatavalid_i
77+
@22
78+
#{top.tb_avm_increase.i_avm_increase.m_avm_readdata_i[31:0]} top.tb_avm_increase.i_avm_increase.m_avm_readdata_i[15] top.tb_avm_increase.i_avm_increase.m_avm_readdata_i[14] top.tb_avm_increase.i_avm_increase.m_avm_readdata_i[13] top.tb_avm_increase.i_avm_increase.m_avm_readdata_i[12] top.tb_avm_increase.i_avm_increase.m_avm_readdata_i[11] top.tb_avm_increase.i_avm_increase.m_avm_readdata_i[10] top.tb_avm_increase.i_avm_increase.m_avm_readdata_i[9] top.tb_avm_increase.i_avm_increase.m_avm_readdata_i[8] top.tb_avm_increase.i_avm_increase.m_avm_readdata_i[7] top.tb_avm_increase.i_avm_increase.m_avm_readdata_i[6] top.tb_avm_increase.i_avm_increase.m_avm_readdata_i[5] top.tb_avm_increase.i_avm_increase.m_avm_readdata_i[4] top.tb_avm_increase.i_avm_increase.m_avm_readdata_i[3] top.tb_avm_increase.i_avm_increase.m_avm_readdata_i[2] top.tb_avm_increase.i_avm_increase.m_avm_readdata_i[1] top.tb_avm_increase.i_avm_increase.m_avm_readdata_i[0]
79+
@28
80+
top.tb_avm_increase.i_avm_increase.offset[0]
81+
@22
82+
#{top.tb_avm_increase.i_avm_increase.s_burstcount[7:0]} top.tb_avm_increase.i_avm_increase.s_burstcount[7] top.tb_avm_increase.i_avm_increase.s_burstcount[6] top.tb_avm_increase.i_avm_increase.s_burstcount[5] top.tb_avm_increase.i_avm_increase.s_burstcount[4] top.tb_avm_increase.i_avm_increase.s_burstcount[3] top.tb_avm_increase.i_avm_increase.s_burstcount[2] top.tb_avm_increase.i_avm_increase.s_burstcount[1] top.tb_avm_increase.i_avm_increase.s_burstcount[0]
83+
#{top.tb_avm_increase.i_avm_increase.m_avm_readdata[15:0]} top.tb_avm_increase.i_avm_increase.m_avm_readdata[15] top.tb_avm_increase.i_avm_increase.m_avm_readdata[14] top.tb_avm_increase.i_avm_increase.m_avm_readdata[13] top.tb_avm_increase.i_avm_increase.m_avm_readdata[12] top.tb_avm_increase.i_avm_increase.m_avm_readdata[11] top.tb_avm_increase.i_avm_increase.m_avm_readdata[10] top.tb_avm_increase.i_avm_increase.m_avm_readdata[9] top.tb_avm_increase.i_avm_increase.m_avm_readdata[8] top.tb_avm_increase.i_avm_increase.m_avm_readdata[7] top.tb_avm_increase.i_avm_increase.m_avm_readdata[6] top.tb_avm_increase.i_avm_increase.m_avm_readdata[5] top.tb_avm_increase.i_avm_increase.m_avm_readdata[4] top.tb_avm_increase.i_avm_increase.m_avm_readdata[3] top.tb_avm_increase.i_avm_increase.m_avm_readdata[2] top.tb_avm_increase.i_avm_increase.m_avm_readdata[1] top.tb_avm_increase.i_avm_increase.m_avm_readdata[0]
84+
@420
85+
top.tb_avm_increase.i_avm_increase.state
86+
@1000200
87+
-avm_increase
88+
[pattern_trace] 1
89+
[pattern_trace] 0

‎tb_avm_increase.vhd

+292
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,292 @@
1+
library ieee;
2+
use ieee.std_logic_1164.all;
3+
use ieee.numeric_std.all;
4+
5+
entity tb_avm_increase is
6+
end entity tb_avm_increase;
7+
8+
architecture simulation of tb_avm_increase is
9+
10+
constant C_SLAVE_DATA_SIZE : integer := 8;
11+
constant C_MASTER_DATA_SIZE : integer := 16;
12+
constant C_SLAVE_ADDRESS_SIZE : integer := 6;
13+
constant C_MASTER_ADDRESS_SIZE : integer := 5;
14+
15+
signal clk : std_logic;
16+
signal rst : std_logic;
17+
signal tb_start : std_logic;
18+
signal tb_wait : std_logic;
19+
signal stop_test : std_logic := '0';
20+
21+
signal sp_avm_start : std_logic;
22+
signal sp_avm_wait : std_logic;
23+
signal sp_avm_write_burstcount : std_logic_vector(7 downto 0);
24+
signal sp_avm_read_burstcount : std_logic_vector(7 downto 0);
25+
26+
signal sp_avm_write : std_logic;
27+
signal sp_avm_read : std_logic;
28+
signal sp_avm_address : std_logic_vector(C_SLAVE_ADDRESS_SIZE-1 downto 0);
29+
signal sp_avm_writedata : std_logic_vector(C_SLAVE_DATA_SIZE-1 downto 0);
30+
signal sp_avm_byteenable : std_logic_vector(C_SLAVE_DATA_SIZE/8-1 downto 0);
31+
signal sp_avm_burstcount : std_logic_vector(7 downto 0);
32+
signal sp_avm_readdata : std_logic_vector(C_SLAVE_DATA_SIZE-1 downto 0);
33+
signal sp_avm_readdatavalid : std_logic;
34+
signal sp_avm_waitrequest : std_logic;
35+
36+
signal s_avm_write : std_logic;
37+
signal s_avm_read : std_logic;
38+
signal s_avm_address : std_logic_vector(C_SLAVE_ADDRESS_SIZE-1 downto 0);
39+
signal s_avm_writedata : std_logic_vector(C_SLAVE_DATA_SIZE-1 downto 0);
40+
signal s_avm_byteenable : std_logic_vector(C_SLAVE_DATA_SIZE/8-1 downto 0);
41+
signal s_avm_burstcount : std_logic_vector(7 downto 0);
42+
signal s_avm_readdata : std_logic_vector(C_SLAVE_DATA_SIZE-1 downto 0);
43+
signal s_avm_readdatavalid : std_logic;
44+
signal s_avm_waitrequest : std_logic;
45+
46+
signal m_avm_write : std_logic;
47+
signal m_avm_read : std_logic;
48+
signal m_avm_address : std_logic_vector(C_MASTER_ADDRESS_SIZE-1 downto 0);
49+
signal m_avm_writedata : std_logic_vector(C_MASTER_DATA_SIZE-1 downto 0);
50+
signal m_avm_byteenable : std_logic_vector(C_MASTER_DATA_SIZE/8-1 downto 0);
51+
signal m_avm_burstcount : std_logic_vector(7 downto 0);
52+
signal m_avm_readdata : std_logic_vector(C_MASTER_DATA_SIZE-1 downto 0);
53+
signal m_avm_readdatavalid : std_logic;
54+
signal m_avm_waitrequest : std_logic;
55+
56+
signal mp_avm_write : std_logic;
57+
signal mp_avm_read : std_logic;
58+
signal mp_avm_address : std_logic_vector(C_MASTER_ADDRESS_SIZE-1 downto 0);
59+
signal mp_avm_writedata : std_logic_vector(C_MASTER_DATA_SIZE-1 downto 0);
60+
signal mp_avm_byteenable : std_logic_vector(C_MASTER_DATA_SIZE/8-1 downto 0);
61+
signal mp_avm_burstcount : std_logic_vector(7 downto 0);
62+
signal mp_avm_readdata : std_logic_vector(C_MASTER_DATA_SIZE-1 downto 0);
63+
signal mp_avm_readdatavalid : std_logic;
64+
signal mp_avm_waitrequest : std_logic;
65+
66+
constant C_CLK_PERIOD : time := 10 ns;
67+
68+
begin
69+
70+
---------------------------------------------------------
71+
-- Controller clock and reset
72+
---------------------------------------------------------
73+
74+
p_clk : process
75+
begin
76+
clk <= '1';
77+
wait for C_CLK_PERIOD/2;
78+
clk <= '0';
79+
wait for C_CLK_PERIOD/2;
80+
if stop_test = '1' then
81+
wait;
82+
end if;
83+
end process p_clk;
84+
85+
p_rst : process
86+
begin
87+
rst <= '1';
88+
wait for 10*C_CLK_PERIOD;
89+
wait until clk = '1';
90+
rst <= '0';
91+
wait;
92+
end process p_rst;
93+
94+
95+
p_start : process
96+
begin
97+
tb_start <= '0';
98+
wait until rst = '0';
99+
wait until clk = '1';
100+
tb_start <= '1';
101+
wait until clk = '1';
102+
tb_start <= '0';
103+
wait;
104+
end process p_start;
105+
106+
p_stop_test : process
107+
begin
108+
wait until tb_start = '1';
109+
wait until tb_wait = '0';
110+
wait until clk = '1';
111+
stop_test <= '1';
112+
wait;
113+
end process p_stop_test;
114+
115+
116+
117+
---------------------------------------------------------
118+
-- Instantiate burst controller
119+
---------------------------------------------------------
120+
121+
i_burst_ctrl : entity work.burst_ctrl
122+
port map (
123+
clk_i => clk,
124+
rst_i => rst,
125+
start_i => tb_start,
126+
wait_o => tb_wait,
127+
start_o => sp_avm_start,
128+
wait_i => sp_avm_wait,
129+
write_burstcount_o => sp_avm_write_burstcount,
130+
read_burstcount_o => sp_avm_read_burstcount
131+
); -- i_burst_ctrl
132+
133+
134+
---------------------------------------------------------
135+
-- Instantiate Master
136+
---------------------------------------------------------
137+
138+
i_avm_master : entity work.avm_master
139+
generic map (
140+
G_DATA_INIT => X"B00BBABEDEAFCAFE",
141+
G_ADDRESS_SIZE => C_SLAVE_ADDRESS_SIZE,
142+
G_DATA_SIZE => C_SLAVE_DATA_SIZE
143+
)
144+
port map (
145+
clk_i => clk,
146+
rst_i => rst,
147+
start_i => sp_avm_start,
148+
wait_o => sp_avm_wait,
149+
write_burstcount_i => sp_avm_write_burstcount,
150+
read_burstcount_i => sp_avm_read_burstcount,
151+
avm_write_o => sp_avm_write,
152+
avm_read_o => sp_avm_read,
153+
avm_address_o => sp_avm_address,
154+
avm_writedata_o => sp_avm_writedata,
155+
avm_byteenable_o => sp_avm_byteenable,
156+
avm_burstcount_o => sp_avm_burstcount,
157+
avm_readdata_i => sp_avm_readdata,
158+
avm_readdatavalid_i => sp_avm_readdatavalid,
159+
avm_waitrequest_i => sp_avm_waitrequest
160+
); -- i_avm_master
161+
162+
163+
---------------------------------------------------------
164+
-- Generate pauses in master trafic
165+
---------------------------------------------------------
166+
167+
i_avm_pause_master : entity work.avm_pause
168+
generic map (
169+
G_REQ_PAUSE => 0,
170+
G_RESP_PAUSE => 0,
171+
G_ADDRESS_SIZE => C_SLAVE_ADDRESS_SIZE,
172+
G_DATA_SIZE => C_SLAVE_DATA_SIZE
173+
)
174+
port map (
175+
clk_i => clk,
176+
rst_i => rst,
177+
s_avm_write_i => sp_avm_write,
178+
s_avm_read_i => sp_avm_read,
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s_avm_address_i => sp_avm_address,
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s_avm_writedata_i => sp_avm_writedata,
181+
s_avm_byteenable_i => sp_avm_byteenable,
182+
s_avm_burstcount_i => sp_avm_burstcount,
183+
s_avm_readdata_o => sp_avm_readdata,
184+
s_avm_readdatavalid_o => sp_avm_readdatavalid,
185+
s_avm_waitrequest_o => sp_avm_waitrequest,
186+
m_avm_write_o => s_avm_write,
187+
m_avm_read_o => s_avm_read,
188+
m_avm_address_o => s_avm_address,
189+
m_avm_writedata_o => s_avm_writedata,
190+
m_avm_byteenable_o => s_avm_byteenable,
191+
m_avm_burstcount_o => s_avm_burstcount,
192+
m_avm_readdata_i => s_avm_readdata,
193+
m_avm_readdatavalid_i => s_avm_readdatavalid,
194+
m_avm_waitrequest_i => s_avm_waitrequest
195+
); -- i_avm_pause_master
196+
197+
198+
---------------------------------------------------------
199+
-- Instantiate DUT
200+
---------------------------------------------------------
201+
202+
i_avm_increase : entity work.avm_increase
203+
generic map (
204+
G_SLAVE_ADDRESS_SIZE => C_SLAVE_ADDRESS_SIZE,
205+
G_MASTER_ADDRESS_SIZE => C_MASTER_ADDRESS_SIZE,
206+
G_SLAVE_DATA_SIZE => C_SLAVE_DATA_SIZE,
207+
G_MASTER_DATA_SIZE => C_MASTER_DATA_SIZE
208+
)
209+
port map (
210+
clk_i => clk,
211+
rst_i => rst,
212+
s_avm_write_i => s_avm_write,
213+
s_avm_read_i => s_avm_read,
214+
s_avm_address_i => s_avm_address,
215+
s_avm_writedata_i => s_avm_writedata,
216+
s_avm_byteenable_i => s_avm_byteenable,
217+
s_avm_burstcount_i => s_avm_burstcount,
218+
s_avm_readdata_o => s_avm_readdata,
219+
s_avm_readdatavalid_o => s_avm_readdatavalid,
220+
s_avm_waitrequest_o => s_avm_waitrequest,
221+
m_avm_write_o => m_avm_write,
222+
m_avm_read_o => m_avm_read,
223+
m_avm_address_o => m_avm_address,
224+
m_avm_writedata_o => m_avm_writedata,
225+
m_avm_byteenable_o => m_avm_byteenable,
226+
m_avm_burstcount_o => m_avm_burstcount,
227+
m_avm_readdata_i => m_avm_readdata,
228+
m_avm_readdatavalid_i => m_avm_readdatavalid,
229+
m_avm_waitrequest_i => m_avm_waitrequest
230+
); -- i_avm_increase
231+
232+
233+
---------------------------------------------------------
234+
-- Generate pauses in slave reception
235+
---------------------------------------------------------
236+
237+
i_avm_pause_slave : entity work.avm_pause
238+
generic map (
239+
G_REQ_PAUSE => 0,
240+
G_RESP_PAUSE => 0,
241+
G_ADDRESS_SIZE => C_MASTER_ADDRESS_SIZE,
242+
G_DATA_SIZE => C_MASTER_DATA_SIZE
243+
)
244+
port map (
245+
clk_i => clk,
246+
rst_i => rst,
247+
s_avm_write_i => m_avm_write,
248+
s_avm_read_i => m_avm_read,
249+
s_avm_address_i => m_avm_address,
250+
s_avm_writedata_i => m_avm_writedata,
251+
s_avm_byteenable_i => m_avm_byteenable,
252+
s_avm_burstcount_i => m_avm_burstcount,
253+
s_avm_readdata_o => m_avm_readdata,
254+
s_avm_readdatavalid_o => m_avm_readdatavalid,
255+
s_avm_waitrequest_o => m_avm_waitrequest,
256+
m_avm_write_o => mp_avm_write,
257+
m_avm_read_o => mp_avm_read,
258+
m_avm_address_o => mp_avm_address,
259+
m_avm_writedata_o => mp_avm_writedata,
260+
m_avm_byteenable_o => mp_avm_byteenable,
261+
m_avm_burstcount_o => mp_avm_burstcount,
262+
m_avm_readdata_i => mp_avm_readdata,
263+
m_avm_readdatavalid_i => mp_avm_readdatavalid,
264+
m_avm_waitrequest_i => mp_avm_waitrequest
265+
); -- i_avm_pause_slave
266+
267+
268+
---------------------------------------------------------
269+
-- Instantiate Slave
270+
---------------------------------------------------------
271+
272+
i_avm_memory : entity work.avm_memory
273+
generic map (
274+
G_ADDRESS_SIZE => C_MASTER_ADDRESS_SIZE,
275+
G_DATA_SIZE => C_MASTER_DATA_SIZE
276+
)
277+
port map (
278+
clk_i => clk,
279+
rst_i => rst,
280+
avm_write_i => mp_avm_write,
281+
avm_read_i => mp_avm_read,
282+
avm_address_i => mp_avm_address,
283+
avm_writedata_i => mp_avm_writedata,
284+
avm_byteenable_i => mp_avm_byteenable,
285+
avm_burstcount_i => mp_avm_burstcount,
286+
avm_readdata_o => mp_avm_readdata,
287+
avm_readdatavalid_o => mp_avm_readdatavalid,
288+
avm_waitrequest_o => mp_avm_waitrequest
289+
); -- i_avm_memory
290+
291+
end architecture simulation;
292+

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