Skip to content

Commit 07e3d58

Browse files
authored
Update README.md (#101)
correct path for the note on "known issue"
1 parent 69e2b84 commit 07e3d58

File tree

1 file changed

+2
-2
lines changed

1 file changed

+2
-2
lines changed

auto_instrument/README.md

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -315,7 +315,7 @@ Running...
315315
This will wait until `inputFifo`'s `empty` signal becomes low. But to get it to become low, we need to run the `auto_instrument.accel.elf` binary that was compiled earlier on-board.
316316
317317
### Running the Software
318-
**NOTE:** this is a known issue. If Windows is being used as host device, open C:\Microchip\Libero_SoC_2025.1\Libero_SoC\SmartHLS-2025.1\SmartHLS\examples\scripts\utils\instrument and go to line 198. Here, change "$merged_file" to "$vcdFile". This issue will be fixed for the next release of Libero.
318+
**NOTE:** this is a known issue. If Windows is being used as host device, open C:\Microchip\Libero_SoC_2025.1\SmartHLS\SmartHLS\examples\scripts\utils\instrument and go to line 198 of update_vcd.tcl. Here, change "$merged_file" to "$vcdFile". This issue will be fixed for the next release of Libero.
319319
320320
Now, to run the design on the board, open an `ssh` session to the Icicle Kit board:
321321
@@ -345,7 +345,7 @@ Now, open the ModelSim window and press Ctrl + R to refresh.
345345
346346
You should see the signals for FIFOs arranged and grouped in an intuitive manner. You can expand the `User_Defined_FIFOs` group to see the signals for the FIFOs in the design. For example, here's the grouped signals for `fifo1` (after toggling on leaf names):
347347
348-
**NOTE:** it is noticed that at times the modelsim displays error message in regards to "....clken" signals not found. This is a known issue. To solve this issue, go to line 257 of "C:\Microchip\Libero_SoC_2025.1\Libero_SoC\SmartHLS-2025.1\SmartHLS\lib\python\instrumentation\read_vcd.py" and change "clk" to "clk$". This issue will be fixed for the next release of Libero.
348+
**NOTE:** it is noticed that at times the modelsim displays error message in regards to "....clken" signals not found. This is a known issue. To solve this issue, go to line 257 of "C:\Microchip\Libero_SoC\SmartHLS\SmartHLS\lib\python\instrumentation\read_vcd.py" and change "clk" to "clk$". This issue will be fixed for the next release of Libero.
349349
350350
![alt text](assets/wave_template_grouping.png)
351351

0 commit comments

Comments
 (0)