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Yes
Also yes, kind of. If the registers overlap and you have instructions that operate on them as such, create larger pseudo registers that overlap the smaller ones. ghidra/Ghidra/Processors/MIPS/data/languages/mips.sinc Lines 182 to 223 in 58e19e9 |
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If a variable is exceeding the CPU's register size and is therefore handled by using two registers, does the decompiler have support for this?
For example, you have registers A:1,B:1 on an 8b CPU holding a 16b value, would the decompiler be able to translate common
sequences for lo/hi parts like this from multiple register handling use into common C use:
If the decompiler can do that, is any special help needed in the Sleigh spec to help the decompiler see such patterns?
I would like to avoid the numerous "CONCAT11", ".0_1" , and ".1_1" references that I get.
My question is in a way generic though, i.e., if you, e.g., had a 64b value on a 32b CPU in two registers R4/R5, the question would remain the same.
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