Is there an existing issue for this?
Current Behavior
Cache configuration is currently disabled across all ST BSPs which include Layer support.
CMSIS-Driver_STM32 pack includes drivers where cache is supported. It also mentions that for DMA on cache-enabled devices, TX/RX buffers should be placed in non-cacheable memory, or the TX cache should be cleaned before transmit and the RX cache invalidated after reception.
Expected Behavior
Enabling Cache configuration in ST Layers would require:
- updating the linker script with required memory layout
- documenting precisely user step in README.md
- testing all layers on board
Steps To Reproduce
No response
Version
No response
Blocker
Is there an existing issue for this?
Current Behavior
Cache configuration is currently disabled across all ST BSPs which include Layer support.
CMSIS-Driver_STM32 pack includes drivers where cache is supported. It also mentions that for DMA on cache-enabled devices, TX/RX buffers should be placed in non-cacheable memory, or the TX cache should be cleaned before transmit and the RX cache invalidated after reception.
Expected Behavior
Enabling Cache configuration in ST Layers would require:
Steps To Reproduce
No response
Version
No response
Blocker