Road to v2

[ginty]

This is an evolving list of some of the big items required to get us to a v1 release which is roughly at feature parity with O1.

• Documentation
  • Infrastructure
  • Guides
    • Getting started
    • Models
    • Patgen
    • Prog gen
    • Simulation
  • Doc Helpers
    • Registers
• Pin/Timing overhaul as discussed in Tester character mapping #106 - Corey
• New app command ("origen new") - Priyavadan
• Origen examples command
  • File differ, add API to define ignore strings/expressions (Rust differ crate?)
• Program generator
  • Infrastructure - Stephen
  • J750
  • Ultraflex
  • Ultraflex+ - Priyavadan
  • SMT7
  • SMT8
  • O1 test cases replicated
• Pattern generator
  • Infrastructure
  • J750
  • Ultraflex
  • Ultraflex+ - Priyavadan
  • SMT7
  • SMT8
  • O1 test cases replicated
  • Concurrent APIs
• Pattern drivers
  • JTAG
  • SWD
  • ARM Debug
  • SPI
  • I2C
• Pattern conversion
  • Infrastructure - Stephen
  • STIL reader - Stephen
• Simulation
  • Infrastructure
  • sim build command
  • Time base in fs (instead of ns)
  • Improved testbench with pin waves generated by the Verilog pin drivers
  • Multi-port simulation
• Misc
  • Python packaging
    • Work out how to package up the origen.so into a Python 'gem'
    • Incorporate into CI tag/release script
  • Plugin/Extension system
    • Python
    • Rust