Align AGU SrcRType encoding with LinxISA v0.58.5

[zhoubot]

Architecture gap

PTO-SPEC currently decodes register-offset AGU SrcRType as 0=unchanged, 1=.sw, 2=.uw, 3=.neg. LinxISA v0.58.5 Sail and compiler output use the shared arithmetic modifier encoding 0=.sw, 1=.uw, 2=.neg, 3=unchanged.

A real add_i32_lat ELF emits lw [t#1, t#2<<2] with raw SrcRType=3. PTO therefore negates index 1 on the second loop iteration and loads the wrong address.

Proposed architecture decision

Adopt the LinxISA v0.58.5 arithmetic modifier mapping for every register-offset AGU form:

• 00: sign-extend low 32 bits (.sw)
• 01: zero-extend low 32 bits (.uw)
• 10: negate the full XLEN value (.neg)
• 11: unchanged (omitted modifier)

Keep modifier-before-shift ordering and all existing fault/atomicity rules. Update owning ASL/contracts and add exact encoded loop/address regressions.

Evidence

• LinxISA Sail: apply_srcrtype_arith64 in isa/sail/model/lib/common.sail
• LinxISA Sail exec_lw applies that helper before shamt
• Compiler ELF instruction 0x179c2f89 decodes as LW with SrcRType=3, plain disassembly
• PTO focused two-iteration ELF-shaped test passes iteration 0 and loads zero at iteration 1 under the current mapping

Target: 0.58.5. This issue is architecture-only; hosted runner and sidecar behavior remain in PTO-ISA/asl-model docs.

[zhoubot]

Rollback baseline: cb0d65b584ce3ad82dd133176e34a97babcfd8ca. The earlier issue body used a Sail/LLVM mapping that was itself changed without matching the LinxISA zh ISA contract, then treated the resulting ELF as architecture evidence. That is circular and must not define PTO.

Corrected contract: register-offset AGU uses 00=unchanged, 01=.sw, 10=.uw, and 11=reserved; the modifier remains before scaling. Arithmetic/logical selectors are separate contracts. Affected requirements/owners: PTO-REQ-SCALAR-ADDRESS-001, the register-offset AGU mnemonic owners, and PTO-SCALAR-MODEL-DISPATCH-DECODE. Existing fault-before-effect and restart ordering are unchanged.

Compatibility: artifacts produced under the short-lived 00=.sw,01=.uw,10=.neg,11=unchanged mapping are not accepted as architectural evidence and must be regenerated downstream. Verification must cover all four raw values, reserved-code rejection, modifier-before-shift, and representative load/store/prefetch forms. Release impact: required.