vivado: fixed Verilog example after changes into resources

Author: rodrigomelo9

vivado/Makefile

@@ -12,4 +12,4 @@ version:
 
 clean:
 	rm -fr *.bit *.cache *.hw *.runs *.xpr *.jou *.ip_user_files
-	rm -fr *.html *.log *.txt *.xml .Xil
+	rm -fr *.html *.log *.txt *.xml .Xil *.zip

vivado/README.md

@@ -12,3 +12,6 @@ VHDL:
   * As a workaround, I set SKIP_ARCH
 * Values are specified following Verilog notation.
   * In case of character, is needed to specify the ASCII value
+
+Verilog:
+* `$finish` is ignored, but fortunatly `$error("some text")` produces the desired result.

vivado/vlog.tcl

@@ -2,19 +2,21 @@ create_project -force vlog-project
 
 set_property "part" xc7z010-1-clg400 [current_project]
 
-add_files ../resources/verilog/blink.v
+add_files ../resources/vlog/blink.v
 
-add_files ../resources/verilog/top.v
+add_files ../resources/vlog/top.v
 add_files ../resources/constraints/zybo/clk.xdc
 add_files ../resources/constraints/zybo/led.xdc
 
 set_property top Top [current_fileset]
 
-set_property verilog_define {VIVADO=1 FREQ=125000000} [current_fileset]
+set_property verilog_define {ARCH_SEL=1 FREQ=125000000} [current_fileset]
 
-set_property "include_dirs" "../resources/verilog/path1 ../resources/verilog/path2" [current_fileset]
+set_property "include_dirs" "../resources/vlog/path1 ../resources/vlog/path2" [current_fileset]
 
-set_property "generic" "BOO=1 INT=255 LOG=1'b1 VEC=8'b11111111 STR=WXYZ REA=1.1" -objects [get_filesets sources_1]
+set_property "generic" "BOO=1 INT=255 LOG=1'b1 VEC=8'b11111111 CHR=Z STR=WXYZ REA=1.1" -objects [get_filesets sources_1]
+
+set_property STEPS.SYNTH_DESIGN.ARGS.ASSERT true [get_runs synth_1]
 
 reset_run synth_1
 launch_runs synth_1