Skip to content

Commit 8f15a47

Browse files
committed
Moved project history from Changelog.md (removed) to the Misc section in the documentation
1 parent 0ac3ec8 commit 8f15a47

File tree

3 files changed

+28
-90
lines changed

3 files changed

+28
-90
lines changed

CHANGELOG.md

Lines changed: 0 additions & 90 deletions
This file was deleted.

docs/index.rst

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -16,6 +16,7 @@ PyFPGA's documentation
1616
tools
1717
internals
1818
extending
19+
misc
1920

2021
.. |timestamp| date:: %Y-%m-%d %H:%M (%Z)
2122

docs/misc.rst

Lines changed: 27 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,27 @@
1+
Miscellaneous
2+
=============
3+
4+
History
5+
-------
6+
7+
The origins of this project trace back to 2015, when an in-house, never-released script called **fpga_tools**, written in *Perl*, was used to populate templates for the Xilinx ISE tool.
8+
9+
In 2016, the project was renamed **fpga_helpers**, transitioning from *Perl* to *Python*.
10+
It was published as open-source on GitHub, adding support for Xilinx Vivado and Altera Quartus, and later for Microsemi (now Microchip) Libero-SoC.
11+
It evolved into a Makefile-based system with two Tcl scripts - one for synthesis and another for programming - both designed to support multiple vendors, along with a few automation scripts.
12+
13+
By the end of 2019, **PyFPGA** emerged as a complete rewrite, replacing the Makefile and Tcl scripts with a Python-based workflow system.
14+
The project was launched on GitLab, with its first official release (0.1.0) on February 29, 2020 - just before the onset of the COVID-19 pandemic.
15+
16+
Throughout 2020, support for open-source tools was gradually introduced.
17+
Initially, Yosys was integrated as the synthesizer, while ISE/Vivado handled place-and-route and bitstream generation.
18+
Later, support for VHDL via *ghdl-yosys-plugin* was added, followed by the introduction of OpenFlow - a fully solved with FLOSS tools workflow - at the end of the year.
19+
Additionally, command-line utilities were introduced to simplify working with small projects and simple and quick proof-of-concepts.
20+
21+
In 2021, PyFPGA was migrated from GitLab to GitHub, aligning with the broader FPGA-related FLOSS ecosystem.
22+
That year, the codebase was significantly expanded and improved, but it also became more complex to maintain.
23+
This led to the release of version 0.2.0 on May 15, 2022, marking a new starting point.
24+
25+
Between 2023 and 2024, the project underwent a major rewrite, incorporating substantial improvements.
26+
In 2024, support for a new vendor tool, Diamond, was contributed.
27+
As a result, a new release is taking place in March 2025.

0 commit comments

Comments
 (0)