Updating the hardware limitation related to yosys

Author: kkumar23

README.md

@@ -51,7 +51,7 @@ ql_symbiflow -compile -d ql-eos-s3 -P pd64 -v counter_16bit.v -t top -p counter_
 ```
 
 For more details on the symbiflow options refer the tutorial guide:
-[Symbiflow_Tutorial](https://github.com/QuickLogic-Corp/quicklogic-fpga-toolchain/files/4786977/Symbiflow_Installation_Guide_and_Tutorial.pdf)
+[Symbiflow_Tutorial](https://github.com/QuickLogic-Corp/quicklogic-fpga-toolchain/files/4787620/Symbiflow_Installation_Guide_and_Tutorial.pdf)
 
 For details on the usage of RAM, FIFO and Multiplier blocks, refer to the following document:
 [Ram_Fifo_Mult_User_Document](https://github.com/QuickLogic-Corp/quicklogic-fpga-toolchain/files/4751774/S3B_Hardmacro_User_Guide.pdf)
@@ -153,3 +153,4 @@ make bin2seven-ql-chandalar_fasm
 - RAM Initialization: RAM initialization as part of the FPGA configuration, We can initialize the FPGA RAM through wishbone interface using M4 (after FPGA configuration). We need to have the wishbone slave interface in the FPGA IP that we design.
 M4 -> Wishbone master (in ASSP)-> Wishbone slave (in FPGA IP)-> FPGA RAMs
 - gclkbuff support: Usage of gclkbuff (clock buffer) in designs
+- Yosys does not target wider muxes (4-8 input) on Logic cell