From 8689929e3cae93f381d92e00cf3bbb35224009f0 Mon Sep 17 00:00:00 2001 From: tawei-amd Date: Fri, 10 Jul 2026 13:09:59 -0700 Subject: [PATCH] docs: trim site nav and focus messaging on AMD NPU Remove the How It Works, Testimonials, Community, and Roadmap pages along with their nav entries. Drop Qualcomm/Intel platform mentions from the homepage, news, and benchmarks so the site highlights the AMD Ryzen AI NPU solution. Co-Authored-By: Claude --- docs/_config.yml | 8 --- docs/benchmarks.md | 25 --------- docs/community.md | 64 ----------------------- docs/how-it-works.md | 117 ------------------------------------------- docs/index.md | 2 +- docs/news.md | 2 +- docs/roadmap.md | 58 --------------------- docs/testimonials.md | 97 ----------------------------------- 8 files changed, 2 insertions(+), 371 deletions(-) delete mode 100644 docs/community.md delete mode 100644 docs/how-it-works.md delete mode 100644 docs/roadmap.md delete mode 100644 docs/testimonials.md diff --git a/docs/_config.yml b/docs/_config.yml index 3758c74b..3f69ff2f 100644 --- a/docs/_config.yml +++ b/docs/_config.yml @@ -40,26 +40,18 @@ defaults: nav_links: - label: Technology children: - - label: How It Works - url: "/how-it-works/" - label: Models url: "/models/" - label: Benchmarks url: "/benchmarks/" - label: Demos url: "/demos/" - - label: Testimonials - url: "/testimonials/" - label: Company children: - label: Team url: "/team/" - - label: Community - url: "/community/" - label: News url: "/news/" - - label: Roadmap - url: "/roadmap/" - label: Docs url: "/docs/" diff --git a/docs/benchmarks.md b/docs/benchmarks.md index 23858078..174de014 100644 --- a/docs/benchmarks.md +++ b/docs/benchmarks.md @@ -54,30 +54,5 @@ sections: alt: "Gemma3 4B benchmark overview of power efficiency (TPS/W) for both prefill and decoding" title: "Ultra-high power efficiency" - - # - type: media - # variant: alt - # kicker: "Qualcomm reference telemetry" - # # title: "Documenting partner power + thermal sweeps" - # media: - # # title: "Power, temp, and workload overlays" - # body: | - # gallery: - # - src: "/assets/bench/qualcomm15.png" - # alt: "Qualcomm benchmark instrumentation on a reference laptop" - # - src: "/assets/bench/qualcomm14-1.png" - # alt: "Qualcomm bench capture 1" - # - src: "/assets/bench/qualcomm14-2.png" - # alt: "Qualcomm bench capture 2" - # - src: "/assets/bench/qualcomm14-3.png" - # alt: "Qualcomm bench capture 3" - # - src: "/assets/bench/qualcomm14-4.png" - # alt: "Qualcomm bench capture 4" - # items: - # - heading: "On-device telemetry" - # body: "Photos include wattage, temperature, and throughput overlays straight from the Qualcomm reference UI." - # - heading: "Replayable sessions" - # body: "Visual artifacts are stored next to CSV logs so OEM teams can validate every published datapoint." - --- diff --git a/docs/community.md b/docs/community.md deleted file mode 100644 index 923b5119..00000000 --- a/docs/community.md +++ /dev/null @@ -1,64 +0,0 @@ ---- -layout: page -title: "Community" -permalink: /community/ -description: "Join the builders pushing AMD Ryzen AI hardware to its limits." -sections: - - type: hero - kicker: "Community" - title: "A developer-first OSS project" - body: | - FastFlowLM is shaped by laptop modders, enterprise AI teams, and AMD engineers who meet in Discord, - GitHub issues, and weekly office hours. Bring your benchmark, integration idea, or feature request. - ctas: - - label: "Join Discord" - href: "https://discord.gg/z24t23HsHF?utm_source=site" - style: primary - external: true - - label: "Star on GitHub" - href: "https://github.com/FastFlowLM/FastFlowLM" - style: ghost - external: true - right: - title: "Weekly cadence" - items: - - heading: "Patch review hour" - body: "Fridays @ 9am PT · Live stream in Discord" - - heading: "Office hours" - body: "One-on-one help with NPUs, models, or deployment hurdles." - - heading: "Community demos" - body: "Show off what you’re building on Ryzen™ AI and get feedback." - - - type: cards - variant: alt - kicker: "Ways to contribute" - title: "Pick the path that matches your stack" - cards: - - label: "Docs & Recipes" - title: "Improve instructions and guides" - body: | - Submit docs PRs, fix typos, or add your own notebooks under `docs/instructions`. - - label: "Runtime" - title: "Optimize kernels + schedulers" - body: | - Help us squeeze more throughput out of XDNA2 with fused ops and better memory planning. - - label: "Integrations" - title: "Bring FastFlowLM into your stack" - body: | - Contribute connector templates for LangChain, AutoGen, Open WebUI, or your product. - - - type: two_column - left: - kicker: "Code of conduct" - title: "Be kind, stay curious, keep shipping" - body: | - We want a welcoming space where seasoned kernel engineers and new builders collaborate. - Respect fellow contributors, share repro steps, and celebrate wins loudly. - right: - title: "Need help?" - body: | - Ping us in Discord or email [info@fastflowlm.com](mailto:info@fastflowlm.com). - We respond within 24 hours. ---- - - diff --git a/docs/how-it-works.md b/docs/how-it-works.md deleted file mode 100644 index 3a389c9d..00000000 --- a/docs/how-it-works.md +++ /dev/null @@ -1,117 +0,0 @@ ---- -layout: page -title: "How It Works" -permalink: /how-it-works/ -description: "How FastFlowLM squeezes every watt and token out of AMD Ryzen™ AI NPUs." -sections: - - type: hero - kicker: "Technology deep dive" - title: "FastFlowLM is built NPU-first" - body: | - FastFlowLM rebuilds the entire inference stack for AMD’s XDNA-based Ryzen™ AI NPUs. - Instead of porting kernels, we split prefill and decoding into tile-aligned workloads, keep KV state on-chip, and stream attention through the NPU’s 2D-tiled mesh. - - The result: up to **5.2× faster prefill** and **4.8× faster decoding** than the iGPU, **33.5× / 2.2×** - gains versus the CPU, while drawing **67× / 223× less energy per token**. We also lift the context ceiling from **2K to - 256K tokens** and halve Gemma 3 image TTFT from **8 s down to 4 s** on the same laptop-class part. - ctas: - - label: "See benchmarks" - href: "/benchmarks/" - style: primary - right: - metrics: - - label: "Prefill acceleration" - value: "5.2× vs iGPU" - desc: "Ryzen AI NPU prefill throughput." - - label: "Decoding acceleration" - value: "4.8× vs iGPU" - desc: "Tile-aware token streaming." - - label: "Context window" - value: "256K tokens" - desc: "Up from 2K in stock stacks." - - label: "Power draw" - value: "67× / 223× less" - desc: "NPU vs iGPU / CPU." - - label: "Image TTFT" - value: "~3 s" - desc: "Gemma 3 vision, down from 8 s." - - - type: two_column - left: - kicker: "Parallel-by-design" - title: "Fine-grained orchestration on XDNA" - body: | - While the GPU enjoys 125 GB/s of memory bandwidth, the NPU sits at 60 GB/s—so FastFlowLM - had to attack the problem with software-led tiling, compression, and scheduling. - items: - - heading: "AIE tile partitioning" - body: | - We map transformer blocks to configurable tiles, fuse matmuls + activation, and ensure the - compute fabric never waits on host memory. - - heading: "Streaming KV residency" - body: | - Attention state stays inside NPU SRAM, enabling 256K-token prompts without bouncing to LPDDR. - - heading: "Dynamic power envelopes" - body: | - Always-on inference taps the NPU's low-leakage island, yielding the 67×/223× power savings cited above. - right: - panel: true - title: "Execution phases" - body: | - FastFlowLM dissects inference into deterministic phases so the runtime can pipeline work on NPU. - items: - - heading: "Prefill turbo" - body: | - Token embedding, rotary math, and large matmuls are staged across contiguous tiles for the 5.2× prefill gains. - - heading: "Token streaming" - body: | - Lightweight kernels reuse on-chip KV blocks, hold steady at 4.8× faster than the iGPU, and avoid cache thrash. - - heading: "Vision + multimodal" - body: | - Image TTFT drops from 8 s to 4 s by overlapping patch projection with text prefill on separate compute islands. - - - type: cards - kicker: "Edge to rack" - title: "Scaling the FastFlowLM approach" - body: | - Ryzen AI proves the concept locally, but the same architecture is already moving toward rack-scale NPU deployments. - cards: - - label: "Edge laptops" - title: "Always-on, efficient AI" - body: | - NPUs stay cool handling assistants, copilots, and background perception without burning the iGPU/CPU. - Users avoid the thermal throttling that plagues CPU/iGPU-only stacks. - - label: "Rack roadmap" - title: "Qualcomm AI200/AI250 & AMD discrete NPU" - body: | - Qualcomm is redefining rack inference with Hexagon NPUs, while AMD is building a discrete XDNA accelerator. - FastFlowLM's close-to-metal runtime is ready for both paths. - - label: "Projected scaling" - title: "10× GPU-class throughput" - body: | - With equal compute and bandwidth, our rack NPU plan models >10.4× faster prefill, >9.6× faster decoding, - and >114× better TPS/W than GPU baselines. - - - type: media - kicker: "Rack architecture" - title: "From chips to racks, all tiled structure" - body: "" - media: - src: "/assets/architecture.png" - alt: "Diagram of racks feeding an AIE and memory tile layout" - title: "Racks of AIE + memory tile array" - items: - - heading: "Racks of NPU Chips" - body: | - The images on the left are photos of multiple server trays and chassis that host NPUs in a rack. - - heading: "AIE compute tiles" - body: | - In the schematic, the upper blocks labeled "AIE tile" represent an array of programmable compute tiles. - - heading: "Memory tiles" - body: | - The darker blocks at the bottom labeled "Memory tile" show the on-chip memory region that sits alongside the AIE tiles. - - heading: "FastFlowLM Technology" - body: | - Our FastFlowLM software scales up and scales out naturally to rack level inferences. ---- - diff --git a/docs/index.md b/docs/index.md index 156fab56..2d97b378 100644 --- a/docs/index.md +++ b/docs/index.md @@ -9,7 +9,7 @@ sections: kicker: "NPU-first runtime" title: "The fastest, most efficient LLM inference on NPUs" body: | - FastFlowLM (FLM) delivers an Ollama-style developer experience optimized for tile-structured NPU accelerators. Install in seconds, stream tokens instantly, and run context windows up to 256k — all with dramatically better efficiency than GPU-first stacks. Our GA release for AMD Ryzen™ AI NPUs is available today, with betas for Qualcomm Snapdragon and Intel Core Ultra coming soon. + FastFlowLM (FLM) delivers an Ollama-style developer experience built exclusively for AMD Ryzen™ AI NPUs. Install in seconds, stream tokens instantly, and run context windows up to 256k — all with dramatically better efficiency than GPU-first stacks. ctas: - label: "Download FastFlowLM (Windows)" href: "https://github.com/FastFlowLM/FastFlowLM/releases/latest/download/flm-setup.exe" diff --git a/docs/news.md b/docs/news.md index 7896d144..d45af0ad 100644 --- a/docs/news.md +++ b/docs/news.md @@ -93,7 +93,7 @@ sections: This isn't a "someday" promise. It is working **right now.** * **Powering AMD:** FastFlowLM is the chosen AI runtime software engine inside the official **[AMD Lemonade Server](https://lemonade-server.ai/)** 🍋, bringing production-ready NPU AI capability to developers and partners. - * **Expanding Platform Support:** FastFlowLM is also prepared for next-generation Qualcomm devices and additional NPU platforms. + * **Expanding Platform Support:** FastFlowLM continues to deepen support across the AMD Ryzen™ AI NPU lineup (Strix, Strix Halo, Kraken). --- diff --git a/docs/roadmap.md b/docs/roadmap.md deleted file mode 100644 index cf66d5d8..00000000 --- a/docs/roadmap.md +++ /dev/null @@ -1,58 +0,0 @@ ---- -layout: page -title: "Roadmap" -permalink: /roadmap/ -description: "Upcoming features and development priorities for FastFlowLM." -sections: - - type: hero - kicker: "Roadmap" - title: "What's coming next" - body: | - Powered by unparalleled expertise in hardware-accelerated parallel processing and deep knowledge of LLM internals, FastFlowLM is advancing the frontier of on-device AI. - - ctas: - - label: "View on GitHub" - href: "https://github.com/FastFlowLM/FastFlowLM" - style: primary - external: true - - label: "Contribute" - href: "https://github.com/FastFlowLM/FastFlowLM/issues" - style: ghost - external: true - right: - title: "Development priorities" - items: - - heading: "Performance" - body: "Ongoing kernel optimizations and memory management improvements." - - heading: "Model support" - body: "Expanding support for new architectures and quantization formats." - - heading: "Developer tools" - body: "Enhanced CLI, better debugging, and improved documentation." - - - type: two_column - variant: alt - left: - kicker: "Roadmap" - title: "Future directions" - body: "" - items: - - heading: "Comprehensive NPU Support" - body: "FastFlowLM aims to be the go-to runtime for Ryzen™ AI NPUs, offering broad model compatibility, top-tier performance, and a robust developer ecosystem." - - heading: "Expanding to New Architectures" - body: "We are actively extending platform support to additional NPU architectures, including Qualcomm, Intel, Broadcom, and more." - - heading: "Inference at Scale" - body: "Building advanced inference optimization software designed to scale seamlessly across multiple chips, cards, and to enable rack-level parallelism." - right: - title: "Get involved" - body: | - Roadmap priorities are discussed openly in our community, and we are actively seeking strategic partners and hardware collaborators to accelerate this work. Join the conversation to help shape FastFlowLM's future. - ctas: - - label: "Join Discord" - href: "https://discord.gg/z24t23HsHF?utm_source=site" - style: primary - external: true - - label: "Contact us" - href: "mailto:info@fastflowlm.com" - style: ghost ---- - diff --git a/docs/testimonials.md b/docs/testimonials.md deleted file mode 100644 index 3c65b856..00000000 --- a/docs/testimonials.md +++ /dev/null @@ -1,97 +0,0 @@ ---- -layout: page -title: "Testimonials" -permalink: /testimonials/ -description: "What developers and partners are saying about FastFlowLM on NPU-first architectures." ---- - -
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Testimonials

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What developers, partners, and silicon teams are saying

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- FastFlowLM combines deep knowledge of LLM architecture with world-class optimization for hardware-level parallelism. The result is the industry’s first—and only—runtime truly engineered for NPU-accelerated AI inference. Our debut product, deployed on AMD’s Ryzen™ AI platform, is revolutionizing on-device intelligence with unprecedented speed, efficiency, and responsiveness. - These stories highlight how an NPU-first runtime lands in the real world—from beta cohorts and AMD’s own AI engineering - org to third-party benchmarking labs. -

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Overwhelming user trials and responses

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- “Within hours of the beta release, thousands of builders pulled FastFlowLM from GitHub and ran it on their own Ryzen™ AI laptops.” -
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  • Within hours of the beta release: Thousands of users pulled FastFlowLM from GitHub and ran it on their own hardware.
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  • Community content: Early users independently produced videos and walkthroughs showing AMD NPUs are far from useless with the right runtime.
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  • Developer competitions: The winning team in a global AI PC developer contest chose FastFlowLM as their NPU runtime.
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  • Customer feedback: One early customer wrote that our solution “seems to be the most elegant so far for AMD NPUs.”
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Feedback from AMD AI engineering leaders

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- “We’re interested in FLM. I spent considerable effort in getting Copilot up on our AIE/NPU and it is a difficult beast. Your kernels and model implementations appear to be closed source but your perf numbers seem impressive.” -
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  • Kernel fidelity: Tile-optimized operators map directly to AMD’s AIE architecture.
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  • Model coverage: Flagship reasoning, multimodal, and MoE models stay inside Ryzen™ AI silicon limits.
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  • Confidence to ship: AMD’s own field teams reference FastFlowLM in partner enablement sessions.
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Proof from independent benchmarking labs

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- “Real-time NPU inference is not just possible, but practical for everyday users.” -
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- “Gaming? No time for that. How about running Llama3.1 8B on the AMD Ryzen AI Z2 Extreme NPU in the ROG Xbox Ally X Via FastFlowLM instead?" ” -
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  • Llama 3.2:3B: Demonstrated on an AMD Ryzen™ AI device with steady token streaming.
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  • Thermal headroom: Runs stay under 2W, extending battery life versus GPU-bound stacks.
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  • Agent workflows: Deterministic latency keeps step-by-step chains responsive in demos.
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Share your FastFlowLM story

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We’re continuing to collect stories from developers, OEM partners, and researchers running FastFlowLM on real Ryzen™ AI hardware.

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  • Developer workflows: How FastFlowLM fits into your local dev loop, CI, or production agents.
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  • NPU performance wins: Concrete improvements in latency, throughput, or power draw vs. GPU-first stacks.
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  • Use cases: From local assistants and multimodal copilots to privacy-preserving RAG and on-device analytics.
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- If you’d like to be featured here, reach out at info@fastflowlm.com or in the FastFlowLM Discord. -

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