[AArch64] Funnel Shift now uses rev32/rev64 instructions (llvm#136707)

Fixes llvm#130469 

Now uses REV32/REV64 instructions to complete operation.

New Output:
```
G1:
        rev64   v0.4s, v0.4s
        ret
G2:
        rev32   v0.8h, v0.8h
        ret
G3:
        rev16   v0.16b, v0.16b
        ret
G4:
        rev32   v0.4h, v0.4h
        ret
G5:
        rev16   v0.8b, v0.8b
        ret
```

Old Output:

```
G1:
        shl     v1.2d, v0.2d, #32
        usra    v1.2d, v0.2d, #32
        mov     v0.16b, v1.16b
        ret

G2:
        shl     v1.4s, v0.4s, #16
        usra    v1.4s, v0.4s, #16
        mov     v0.16b, v1.16b
        ret

G3:
        rev16   v0.16b, v0.16b
        ret

G4:
        shl     v1.2s, v0.2s, #16
        usra    v1.2s, v0.2s, #16
        fmov    d0, d1
        ret

G5:
        rev16   v0.8b, v0.8b
        ret
```

Author: jyli0116

llvm/lib/Target/AArch64/AArch64InstrInfo.td

@@ -5688,6 +5688,17 @@ def : Pat<(v4i32 (bswap (v4i32 V128:$Rn))),
 def : Pat<(v2i64 (bswap (v2i64 V128:$Rn))),
           (v2i64 (REV64v16i8 (v2i64 V128:$Rn)))>;
 
+// Patterns for funnel shifts to be matched to equivalent REV instructions
+def : Pat<(v2i64 (or (v2i64 (AArch64vshl (v2i64 V128:$Rn), (i32 32))), 
+                     (v2i64 (AArch64vlshr (v2i64 V128:$Rn), (i32 32))))), 
+          (v2i64 (REV64v4i32 (v2i64 V128:$Rn)))>;
+def : Pat<(v4i32 (or (v4i32 (AArch64vshl (v4i32 V128:$Rn), (i32 16))), 
+                     (v4i32 (AArch64vlshr (v4i32 V128:$Rn), (i32 16))))), 
+          (v4i32 (REV32v8i16 (v4i32 V128:$Rn)))>;
+def : Pat<(v2i32 (or (v2i32 (AArch64vshl (v2i32 V64:$Rn), (i32 16))), 
+                     (v2i32 (AArch64vlshr (v2i32 V64:$Rn), (i32 16))))), 
+          (v2i32 (REV32v4i16 (v2i32 V64:$Rn)))>;
+
 //===----------------------------------------------------------------------===//
 // Advanced SIMD three vector instructions.
 //===----------------------------------------------------------------------===//

llvm/test/CodeGen/AArch64/fsh.ll

@@ -4506,3 +4506,53 @@ entry:
   %d = call <2 x i128> @llvm.fshr(<2 x i128> %a, <2 x i128> %b, <2 x i128> <i128 3, i128 3>)
   ret <2 x i128> %d
 }
+
+
+
+define <2 x i64> @fshl_to_rev2i64(<2 x i64> %r) {
+; CHECK-SD-LABEL: fshl_to_rev2i64:
+; CHECK-SD:       // %bb.0:
+; CHECK-SD-NEXT:    rev64 v0.4s, v0.4s
+; CHECK-SD-NEXT:    ret
+;
+; CHECK-GI-LABEL: fshl_to_rev2i64:
+; CHECK-GI:       // %bb.0:
+; CHECK-GI-NEXT:    shl v1.2d, v0.2d, #32
+; CHECK-GI-NEXT:    ushr v0.2d, v0.2d, #32
+; CHECK-GI-NEXT:    orr v0.16b, v1.16b, v0.16b
+; CHECK-GI-NEXT:    ret
+    %or = tail call <2 x i64> @llvm.fshl.v2i64(<2 x i64> %r, <2 x i64> %r, <2 x i64> splat (i64 32))
+    ret <2 x i64> %or
+}
+
+define <4 x i32> @fshl_to_rev4i32(<4 x i32> %r) {
+; CHECK-SD-LABEL: fshl_to_rev4i32:
+; CHECK-SD:       // %bb.0:
+; CHECK-SD-NEXT:    rev32 v0.8h, v0.8h
+; CHECK-SD-NEXT:    ret
+;
+; CHECK-GI-LABEL: fshl_to_rev4i32:
+; CHECK-GI:       // %bb.0:
+; CHECK-GI-NEXT:    shl v1.4s, v0.4s, #16
+; CHECK-GI-NEXT:    ushr v0.4s, v0.4s, #16
+; CHECK-GI-NEXT:    orr v0.16b, v1.16b, v0.16b
+; CHECK-GI-NEXT:    ret
+    %or = tail call <4 x i32> @llvm.fshl.v4i32(<4 x i32> %r, <4 x i32> %r, <4 x i32> splat (i32 16))
+    ret <4 x i32> %or
+}
+
+define <2 x i32> @fshl_to_rev2i32(<2 x i32> %r) {
+; CHECK-SD-LABEL: fshl_to_rev2i32:
+; CHECK-SD:       // %bb.0:
+; CHECK-SD-NEXT:    rev32 v0.4h, v0.4h
+; CHECK-SD-NEXT:    ret
+;
+; CHECK-GI-LABEL: fshl_to_rev2i32:
+; CHECK-GI:       // %bb.0:
+; CHECK-GI-NEXT:    shl v1.2s, v0.2s, #16
+; CHECK-GI-NEXT:    ushr v0.2s, v0.2s, #16
+; CHECK-GI-NEXT:    orr v0.8b, v1.8b, v0.8b
+; CHECK-GI-NEXT:    ret
+    %or = tail call <2 x i32> @llvm.fshl.v2i32(<2 x i32> %r, <2 x i32> %r, <2 x i32> splat (i32 16))
+    ret <2 x i32> %or
+}