Skip to content

Commit a492384

Browse files
committed
[TEMP] AMDGPU: Fix LiveRangeEdit+LiveRegMatrix use-after-delete of LiveInterval
1 parent 5ef646d commit a492384

File tree

3 files changed

+32
-3
lines changed

3 files changed

+32
-3
lines changed

llvm/include/llvm/CodeGen/LiveRegMatrix.h

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -135,6 +135,9 @@ class LiveRegMatrix {
135135
/// the assignment and updates VirtRegMap accordingly.
136136
void unassign(const LiveInterval &VirtReg);
137137

138+
/// Remove any assignments for \p VirtReg.
139+
void purge(const LiveInterval &VirtReg);
140+
138141
/// Returns true if the given \p PhysReg has any live intervals assigned.
139142
bool isPhysRegUsed(MCRegister PhysReg) const;
140143

llvm/lib/CodeGen/InlineSpiller.cpp

Lines changed: 15 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -86,6 +86,7 @@ class HoistSpillHelper : private LiveRangeEdit::Delegate {
8686
const TargetInstrInfo &TII;
8787
const TargetRegisterInfo &TRI;
8888
const MachineBlockFrequencyInfo &MBFI;
89+
LiveRegMatrix *Matrix;
8990

9091
InsertPointAnalysis IPA;
9192

@@ -129,16 +130,18 @@ class HoistSpillHelper : private LiveRangeEdit::Delegate {
129130

130131
public:
131132
HoistSpillHelper(const Spiller::RequiredAnalyses &Analyses,
132-
MachineFunction &mf, VirtRegMap &vrm)
133+
MachineFunction &mf, VirtRegMap &vrm,
134+
LiveRegMatrix *matrix = nullptr)
133135
: MF(mf), LIS(Analyses.LIS), LSS(Analyses.LSS), MDT(Analyses.MDT),
134136
VRM(vrm), MRI(mf.getRegInfo()), TII(*mf.getSubtarget().getInstrInfo()),
135137
TRI(*mf.getSubtarget().getRegisterInfo()), MBFI(Analyses.MBFI),
136-
IPA(LIS, mf.getNumBlockIDs()) {}
138+
Matrix(matrix), IPA(LIS, mf.getNumBlockIDs()) {}
137139

138140
void addToMergeableSpills(MachineInstr &Spill, int StackSlot,
139141
Register Original);
140142
bool rmFromMergeableSpills(MachineInstr &Spill, int StackSlot);
141143
void hoistAllSpills();
144+
bool LRE_CanEraseVirtReg(Register) override;
142145
void LRE_DidCloneVirtReg(Register, Register) override;
143146
};
144147

@@ -191,7 +194,7 @@ class InlineSpiller : public Spiller {
191194
: MF(MF), LIS(Analyses.LIS), LSS(Analyses.LSS), VRM(VRM),
192195
MRI(MF.getRegInfo()), TII(*MF.getSubtarget().getInstrInfo()),
193196
TRI(*MF.getSubtarget().getRegisterInfo()), Matrix(Matrix),
194-
HSpiller(Analyses, MF, VRM), VRAI(VRAI) {}
197+
HSpiller(Analyses, MF, VRM, Matrix), VRAI(VRAI) {}
195198

196199
void spill(LiveRangeEdit &, AllocationOrder *Order = nullptr) override;
197200
ArrayRef<Register> getSpilledRegs() override { return RegsToSpill; }
@@ -1750,6 +1753,15 @@ void HoistSpillHelper::hoistAllSpills() {
17501753
}
17511754
}
17521755

1756+
bool HoistSpillHelper::LRE_CanEraseVirtReg(Register VirtReg) {
1757+
if (!Matrix || !LIS.hasInterval(VirtReg) || !VRM.hasPhys(VirtReg))
1758+
return true;
1759+
1760+
LiveInterval &LI = LIS.getInterval(VirtReg);
1761+
Matrix->purge(LI);
1762+
return true;
1763+
}
1764+
17531765
/// For VirtReg clone, the \p New register should have the same physreg or
17541766
/// stackslot as the \p old register.
17551767
void HoistSpillHelper::LRE_DidCloneVirtReg(Register New, Register Old) {

llvm/lib/CodeGen/LiveRegMatrix.cpp

Lines changed: 14 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -142,6 +142,20 @@ void LiveRegMatrix::unassign(const LiveInterval &VirtReg) {
142142
LLVM_DEBUG(dbgs() << '\n');
143143
}
144144

145+
void LiveRegMatrix::purge(const LiveInterval &VirtReg) {
146+
VRM->clearVirt(VirtReg.reg());
147+
148+
for (unsigned i = 0; i < Matrix.size(); ++i) {
149+
LiveIntervalUnion &LIU = Matrix[static_cast<MCRegUnit>(i)];
150+
for (LiveIntervalUnion::SegmentIter SI = LIU.begin(); SI.valid();) {
151+
if (SI.value() == &VirtReg) {
152+
SI.erase();
153+
} else
154+
++SI;
155+
}
156+
}
157+
}
158+
145159
bool LiveRegMatrix::isPhysRegUsed(MCRegister PhysReg) const {
146160
for (MCRegUnit Unit : TRI->regunits(PhysReg)) {
147161
if (!Matrix[Unit].empty())

0 commit comments

Comments
 (0)