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Description
There is a documented unit discrepancy between SKY130 and GF180 when extracting the Netlist from the Layout for the LVS operation.
- For Sky130:
The tech file included in the open_pdk tech stack extracts the Netlist from the GDS using theumunits by default. This does not cause an error in the LVS as the Schematic Netlist generated in the gLayout is also extracted in microns (μm) units. Thus, the LVS passes.
Extracted from Layout
* NGSPICE file created from FVF.ext - technology: sky130A
.subckt FVF VBULK VIN VOUT Ib
X0 VBULK VBULK VBULK VBULK sky130_fd_pr__nfet_01v8 ad=1.425 pd=6.95 as=12.825 ps=62.55 w=3 l=0.15
X1 VBULK VBULK VBULK VBULK sky130_fd_pr__nfet_01v8 ad=1.425 pd=6.95 as=0 ps=0 w=3 l=0.15
X2 VBULK VBULK VBULK VBULK sky130_fd_pr__nfet_01v8 ad=1.425 pd=6.95 as=0 ps=0 w=3 l=0.15
X3 VOUT Ib VBULK VBULK sky130_fd_pr__nfet_01v8 ad=1.425 pd=6.95 as=1.425 ps=6.95 w=3 l=0.15
X4 Ib VIN VOUT VBULK sky130_fd_pr__nfet_01v8 ad=1.425 pd=6.95 as=1.425 ps=6.95 w=3 l=0.15
X5 VBULK VBULK VBULK VBULK sky130_fd_pr__nfet_01v8 ad=1.425 pd=6.95 as=0 ps=0 w=3 l=0.15
.ends
Extracted from Schematic
.include /foss/designs/Subham_MR/gLayout/src/glayout/pdk/sky130_mapped/sky130_fd_sc_hd.spice
.subckt NMOS D G S B l=0.15 w=3 m=1 dm=1
XMAIN D G S B sky130_fd_pr__nfet_01v8 l={l} w={w} m={m}
XDUMMY1 B B B B sky130_fd_pr__nfet_01v8 l={l} w={w} m={dm}
XDUMMY2 B B B B sky130_fd_pr__nfet_01v8 l={l} w={w} m={dm}
.ends NMOS
.subckt FVF VIN VBULK VOUT Ib
X0 Ib VIN VOUT VBULK NMOS l=0.15 w=3 m=0.5 dm=1
X1 VOUT Ib VBULK VBULK NMOS l=0.15 w=3 m=0.5 dm=1
.ends FVF
This pass.
- For GF180
The tech file extracts the Netlist from the layout in SI units. However, gLayout still extracts the Netlist from the schematic in micros. This causes a discrepancy in the element sizing between the two Netlists, causing the LVS to fail with this error
Netlists match uniquely with property errors.
nfet_03v3:2 vs. NMOS:0/nfet_03v3:MAIN:
l circuit1: 2.8e-07 circuit2: 0.28 (delta=200%, cutoff=1%)
w circuit1: 3e-06 circuit2: 3 (delta=200%, cutoff=1%)
nfet_03v3:0 vs. NMOS:0/nfet_03v3:DUMMY1:
l circuit1: 2.8e-07 circuit2: 0.28 (delta=200%, cutoff=1%)
w circuit1: 3e-06 circuit2: 3 (delta=200%, cutoff=1%)
nfet_03v3:3 vs. NMOS:1/nfet_03v3:MAIN:
l circuit1: 2.8e-07 circuit2: 0.28 (delta=200%, cutoff=1%)
w circuit1: 3e-06 circuit2: 3 (delta=200%, cutoff=1%)The Layout Extracted netlist (note the u as in microns)
* NGSPICE file created from FVF.ext - technology: gf180mcuD
.subckt FVF VBULK VIN VOUT Ib
X0 VBULK VBULK VBULK VBULK nfet_03v3 ad=2.19p pd=7.46u as=19.77p ps=67.18u w=3u l=0.28u
X1 VBULK VBULK VBULK VBULK nfet_03v3 ad=2.19p pd=7.46u as=0 ps=0 w=3u l=0.28u
X2 Ib VIN VOUT VBULK nfet_03v3 ad=2.25p pd=7.5u as=2.25p ps=7.5u w=3u l=0.28u
X3 VOUT Ib VBULK VBULK nfet_03v3 ad=2.25p pd=7.5u as=2.25p ps=7.5u w=3u l=0.28u
X4 VBULK VBULK VBULK VBULK nfet_03v3 ad=2.19p pd=7.46u as=0 ps=0 w=3u l=0.28u
X5 VBULK VBULK VBULK VBULK nfet_03v3 ad=2.19p pd=7.46u as=0 ps=0 w=3u l=0.28u
.ends
and the schematic netlist
.include /foss/designs/Subham_MR/gLayout/src/glayout/pdk/gf180_mapped/gf180mcu_osu_sc_9T.spice
.subckt NMOS D G S B l=0.28 w=3 m=1 dm=1
XMAIN D G S B nfet_03v3 l={l} w={w} m={m}
XDUMMY1 B B B B nfet_03v3 l={l} w={w} m={dm}
XDUMMY2 B B B B nfet_03v3 l={l} w={w} m={dm}
.ends NMOS
.subckt FVF VIN VBULK VOUT Ib
X0 Ib VIN VOUT VBULK NMOS l=0.28 w=3 m=0.5 dm=1
X1 VOUT Ib VBULK VBULK NMOS l=0.28 w=3 m=0.5 dm=1
.ends FVF
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