diff --git a/blocks/composite/regulated_cascoded_cmirror/.jupyter_ystore.db b/blocks/composite/regulated_cascoded_cmirror/.jupyter_ystore.db new file mode 100644 index 00000000..2cb6b4ea Binary files /dev/null and b/blocks/composite/regulated_cascoded_cmirror/.jupyter_ystore.db differ diff --git a/blocks/composite/regulated_cascoded_cmirror/A3_core/A3_top/A3_top.gds b/blocks/composite/regulated_cascoded_cmirror/A3_core/A3_top/A3_top.gds new file mode 100644 index 00000000..42de3c92 Binary files /dev/null and b/blocks/composite/regulated_cascoded_cmirror/A3_core/A3_top/A3_top.gds differ diff --git a/blocks/composite/regulated_cascoded_cmirror/A3_core/A3_top/A3_top.sch b/blocks/composite/regulated_cascoded_cmirror/A3_core/A3_top/A3_top.sch new file mode 100644 index 00000000..66cde740 --- /dev/null +++ b/blocks/composite/regulated_cascoded_cmirror/A3_core/A3_top/A3_top.sch @@ -0,0 +1,79 @@ +v {xschem version=3.4.7 file_version=1.2} +G {} +K {} +V {} +S {} +E {} +N 250 -370 580 -370 {lab=ENA} +N 820 -180 820 -170 {lab=VSS} +N 820 -430 820 -400 {lab=VDD} +N 340 -330 580 -330 {lab=VIN_INT} +N 460 -280 580 -280 {lab=VBIAS_INT} +N 400 -570 400 -530 {lab=VSS} +N 400 -710 400 -690 {lab=VDD} +N 820 -170 820 -150 {lab=VSS} +N 760 -850 920 -850 {lab=VIN} +N 750 -600 910 -600 {lab=VBIAS} +N 1020 -350 1110 -350 {lab=VCM_OUT} +N 1110 -370 1110 -350 {lab=VCM_OUT} +N 1110 -370 1180 -370 {lab=VCM_OUT} +N 1020 -330 1180 -330 {lab=BCM_OUT} +N 1020 -310 1110 -310 {lab=CCM_OUT} +N 1110 -310 1110 -290 {lab=CCM_OUT} +N 1110 -290 1180 -290 {lab=CCM_OUT} +N 630 -730 710 -730 {lab=VDD} +N 620 -680 710 -680 {lab=VSS} +N 490 -840 520 -840 {lab=ENA} +N 1020 -370 1090 -370 {lab=VIN_OUT} +N 1090 -400 1090 -370 {lab=VIN_OUT} +N 1090 -400 1180 -400 {lab=VIN_OUT} +N 920 -850 960 -850 {lab=VIN} +N 910 -600 960 -600 {lab=VBIAS} +N 1160 -850 1200 -850 {lab=VIN_INT} +N 1160 -600 1270 -600 {lab=VBIAS_INT} +N 80 -840 290 -840 {lab=EN} +N 80 -610 320 -610 {lab=PU} +N 80 -650 320 -650 {lab=PD} +C {title.sym} 190 -90 0 0 {name=l1 author="Quentin Halbach and Sapta"} +C {lab_pin.sym} 400 -710 2 1 {name=p111 lab=VDD} +C {lab_pin.sym} 410 -760 2 1 {name=p164 lab=VSS} +C {iopin.sym} 710 -730 0 0 {name=p92 lab=VDD} +C {iopin.sym} 710 -680 0 0 {name=p51 lab=VSS} +C {lab_pin.sym} 520 -840 0 1 {name=p1 lab=ENA} +C {lab_pin.sym} 400 -530 2 1 {name=p2 lab=VSS} +C {lab_pin.sym} 820 -430 2 1 {name=p3 lab=VDD} +C {lab_pin.sym} 820 -150 2 1 {name=p4 lab=VSS} +C {lab_pin.sym} 250 -370 2 1 {name=p5 lab=ENA} +C {ipin.sym} 760 -850 0 0 {name=p6 lab=VIN} +C {ipin.sym} 750 -600 0 0 {name=p7 lab=VBIAS} +C {lab_pin.sym} 1200 -850 0 1 {name=p8 lab=VIN_INT} +C {lab_pin.sym} 1270 -600 0 1 {name=p9 lab=VBIAS_INT} +C {lab_pin.sym} 340 -330 2 1 {name=p10 lab=VIN_INT} +C {lab_pin.sym} 460 -280 2 1 {name=p11 lab=VBIAS_INT} +C {opin.sym} 1180 -370 0 0 {name=p24 lab=VCM_OUT} +C {opin.sym} 1180 -330 0 0 {name=p20 lab=BCM_OUT} +C {opin.sym} 1180 -290 0 0 {name=p28 lab=CCM_OUT} +C {lab_pin.sym} 630 -730 2 1 {name=p41 lab=VDD} +C {lab_pin.sym} 620 -680 2 1 {name=p43 lab=VSS} +C {lab_pin.sym} 410 -920 2 1 {name=p49 lab=VDD} +C {opin.sym} 1180 -400 0 0 {name=p54 lab=VIN_OUT} +C {lab_pin.sym} 1080 -930 2 1 {name=p12 lab=VDD} +C {lab_pin.sym} 1080 -770 2 1 {name=p13 lab=VSS} +C {lab_pin.sym} 1080 -680 2 1 {name=p14 lab=VDD} +C {lab_pin.sym} 1080 -520 2 1 {name=p15 lab=VSS} +C {ipin.sym} 80 -610 0 0 {name=p16 lab=PU} +C {ipin.sym} 80 -650 0 0 {name=p17 lab=PD} +C {ipin.sym} 80 -840 0 0 {name=p120 lab=EN} +C {/foss/designs/AutoMOS-chipathon2025/designs/Chipathon2025_pads/xschem/symbols/io_secondary_5p0/io_secondary_5p0.sym} 490 -760 0 1 {name=IO1 +spiceprefix=X +} +C {/foss/designs/AutoMOS-chipathon2025/designs/Chipathon2025_pads/xschem/symbols/io_secondary_5p0/io_secondary_5p0.sym} 1160 -770 0 1 {name=IO2 +spiceprefix=X +} +C {/foss/designs/AutoMOS-chipathon2025/designs/Chipathon2025_pads/xschem/symbols/io_secondary_5p0/io_secondary_5p0.sym} 1160 -520 0 1 {name=IO3 +spiceprefix=X +} +C {/foss/designs/AutoMOS-chipathon2025/designs/gf180mcu_fd_sc_mcu9t5v0/xschem/symbols/sc_tieh_tiel.sym} 440 -570 0 1 {name=SC1 +spiceprefix=X +} +C {top_level/top_level.sym} 820 -290 0 0 {name=x1} diff --git a/blocks/composite/regulated_cascoded_cmirror/A3_core/A3_top/A3_top.sym b/blocks/composite/regulated_cascoded_cmirror/A3_core/A3_top/A3_top.sym new file mode 100644 index 00000000..70ea45d6 --- /dev/null +++ b/blocks/composite/regulated_cascoded_cmirror/A3_core/A3_top/A3_top.sym @@ -0,0 +1,45 @@ +v {xschem version=3.4.7 file_version=1.2} +G {} +K {type=subcircuit +format="@name @pinlist @symname" +template="name=x1" +} +V {} +S {} +E {} +L 4 50 -70 70 -70 {} +L 4 50 -20 70 -20 {} +L 4 50 0 70 0 {} +L 4 50 20 70 20 {} +L 4 50 -50 70 -50 {} +L 4 50 60 70 60 {} +L 4 50 120 70 120 {} +L 4 50 100 70 100 {} +L 4 50 80 70 80 {} +L 7 50 -120 70 -120 {} +L 7 50 -100 70 -100 {} +B 5 67.5 -72.5 72.5 -67.5 {name=VIN dir=in} +B 5 67.5 -22.5 72.5 -17.5 {name=EN dir=in} +B 5 67.5 -122.5 72.5 -117.5 {name=VDD dir=inout} +B 5 67.5 -102.5 72.5 -97.5 {name=VSS dir=inout} +B 5 67.5 -2.5 72.5 2.5 {name=PD dir=in} +B 5 67.5 17.5 72.5 22.5 {name=PU dir=in} +B 5 67.5 -52.5 72.5 -47.5 {name=VBIAS dir=in} +B 5 67.5 57.5 72.5 62.5 {name=VIN_OUT dir=out} +B 5 67.5 117.5 72.5 122.5 {name=VCM_OUT dir=out} +B 5 67.5 97.5 72.5 102.5 {name=BCM_OUT dir=out} +B 5 67.5 77.5 72.5 82.5 {name=CCM_OUT dir=out} +P 4 5 50 -140 -50 -140 -50 140 50 140 50 -140 {} +T {@symname} -14 -51.5 1 0 0.3 0.3 {} +T {@name} 5 -162 0 0 0.2 0.2 {} +T {VIN} 45 -74 0 1 0.2 0.2 {} +T {EN} 45 -24 0 1 0.2 0.2 {} +T {VDD} 45 -124 0 1 0.2 0.2 {} +T {VSS} 45 -104 0 1 0.2 0.2 {} +T {PD} 45 -4 0 1 0.2 0.2 {} +T {PU} 45 16 0 1 0.2 0.2 {} +T {VBIAS} 45 -54 0 1 0.2 0.2 {} +T {VIN_OUT} 45 56 0 1 0.2 0.2 {} +T {VCM_OUT} 45 116 0 1 0.2 0.2 {} +T {BCM_OUT} 45 96 0 1 0.2 0.2 {} +T {CCM_OUT} 45 76 0 1 0.2 0.2 {} diff --git a/blocks/composite/regulated_cascoded_cmirror/A3_core/A3_top/README.md b/blocks/composite/regulated_cascoded_cmirror/A3_core/A3_top/README.md new file mode 100644 index 00000000..ae493767 --- /dev/null +++ b/blocks/composite/regulated_cascoded_cmirror/A3_core/A3_top/README.md @@ -0,0 +1 @@ +Schematics Placeholder diff --git a/blocks/composite/regulated_cascoded_cmirror/A3_core/A3_top/lvs_test.py b/blocks/composite/regulated_cascoded_cmirror/A3_core/A3_top/lvs_test.py new file mode 100644 index 00000000..4d15f218 --- /dev/null +++ b/blocks/composite/regulated_cascoded_cmirror/A3_core/A3_top/lvs_test.py @@ -0,0 +1,850 @@ +from pathlib import Path +from typing import Optional, Union +import os +import re +import subprocess + +from gdsfactory import cell +from gdsfactory.component import Component +from gdsfactory.components import rectangle, text_freetype + +from glayout import MappedPDK, sky130, gf180, nmos, pmos, tapring, via_stack +from glayout.placement.two_transistor_interdigitized import ( + two_nfet_interdigitized, + two_pfet_interdigitized, +) +from glayout.routing import L_route, c_route, straight_route +from glayout.spice.netlist import Netlist +from glayout.util.comp_utils import ( + align_comp_to_port, + evaluate_bbox, + prec_center, + prec_ref_center, +) +from glayout.util.port_utils import add_ports_perimeter, rename_ports_by_orientation +from glayout.util.snap_to_grid import component_snap_to_grid + +from cm_v import current_mirror_base +from cm_sb import self_biased_cascode_current_mirror +from cm_rc import regulated_cascode_current_mirror +from input import input_stage +from bias import bias_stage + +###### Only Required for IIC-OSIC Docker +# Run a shell, source .bashrc, then printenv +cmd = 'bash -c "source ~/.bashrc && printenv"' +result = subprocess.run(cmd, shell=True, text=True, capture_output=True) +env_vars = {} +for line in result.stdout.splitlines(): + if "=" in line: + key, value = line.split("=", 1) + env_vars[key] = value +os.environ.update(env_vars) + +# ---- helpers ---- +_HEADER_RE = re.compile( + r"^\s*\.subckt\s+(\S+)\s+(.*)\s*$", re.IGNORECASE | re.MULTILINE +) + + +def _parse_subckt_header(source: str): + m = _HEADER_RE.search(source) + if not m: + raise ValueError("Could not find .subckt header in child netlist") + name = m.group(1) + pins = [t for t in m.group(2).split() if t.strip()] + return name, pins + + +def _instance_line( + inst_name: str, + subckt_name: str, + ordered_child_pins: list[str], + pinmap: dict[str, str], +): + try: + nodes_in_order = [pinmap[p] for p in ordered_child_pins] + except KeyError as e: + missing = str(e).strip("'") + raise ValueError( + f"Missing mapping for child pin '{missing}' when instantiating {subckt_name}" + ) + return f"X{inst_name} " + " ".join(nodes_in_order) + f" {subckt_name}\n" + + +def generate_top_netlist( + prefix: str, + in_net: str, + aux_net: str, + en_net: str, + out_vcm_net: str, + out_sbcm_net: str, + out_rccm_net: str, + out_vin_net: str, + nl_input: Netlist, + nl_bias: Netlist, + nl_vcm: Netlist, + nl_sbcm: Netlist, + nl_rccm: Netlist, + show_netlist: bool = False, +) -> Netlist: + """ + Build top-level .subckt that instantiates child subckts and wires them to top nets. + TOP pin order must match layout header: + .subckt TOP VIN VSS VDD VOUT_RCCM VOUT_SBCM VOUT_VCM VAUX EN + """ + top_pins = [ + in_net, + "VSS", + "VDD", + out_vin_net, + out_rccm_net, + out_sbcm_net, + out_vcm_net, + aux_net, + en_net, + ] + + # Render children and parse headers + child_texts = { + "INPUT": nl_input.generate_netlist(), + "BIAS": nl_bias.generate_netlist(), + "VCM": nl_vcm.generate_netlist(), + "SBCM": nl_sbcm.generate_netlist(), + "RCCM": nl_rccm.generate_netlist(), + } + parsed = {} + for key, text in child_texts.items(): + subckt_name, pins = _parse_subckt_header(text) + parsed[key] = {"name": subckt_name, "pins": pins, "text": text} + + # Internal nets + in_vcm_int = "IN_VCM" + in_sbcm_int = "IN_SBCM" + in_rccm_int = "IN_RCCM" + + bias_rccm_int = "BIAS_RCCM" + + # Pin maps matching the child headers + # INPUT: .subckt INPUT VIN EN VOUT_VCM VOUT_BCM VOUT_CCM VDD + pinmap_input = { + "VIN": in_net, + "EN": en_net, + "VOUT_VCM": in_vcm_int, + "VOUT_BCM": in_sbcm_int, + "VOUT_CCM": in_rccm_int, + "VOUT_VIN": out_vin_net, + "VDD": "VDD", + } + # BIAS: .subckt BIAS IN_RCCM VAUX EN VDD + pinmap_bias = { + "VOUT": bias_rccm_int, + "VIN": aux_net, + "EN": en_net, + "VDD": "VDD", + "VSS": "VSS", + } + # VCM: .subckt VCM VIN VOUT VSS + pinmap_vcm = {"VIN": in_vcm_int, "VOUT": out_vcm_net, "VSS": "VSS"} + # SBCM: .subckt SBCM VIN VOUT VSS + pinmap_sbcm = {"VIN": in_sbcm_int, "VOUT": out_sbcm_net, "VSS": "VSS"} + # RCCM: .subckt RCCM VIN VAUX VOUT VSS + pinmap_rccm = { + "VIN": in_rccm_int, + "VAUX": bias_rccm_int, + "VOUT": out_rccm_net, + "VSS": "VSS", + } + + # Build instance lines using parsed child pin order + x_lines = [ + _instance_line( + f"{prefix}IN", + parsed["INPUT"]["name"], + parsed["INPUT"]["pins"], + pinmap_input, + ), + _instance_line( + f"{prefix}BIAS", + parsed["BIAS"]["name"], + parsed["BIAS"]["pins"], + pinmap_bias, + ), + _instance_line( + f"{prefix}VCM", + parsed["VCM"]["name"], + parsed["VCM"]["pins"], + pinmap_vcm, + ), + _instance_line( + f"{prefix}SBCM", + parsed["SBCM"]["name"], + parsed["SBCM"]["pins"], + pinmap_sbcm, + ), + _instance_line( + f"{prefix}RCCM", + parsed["RCCM"]["name"], + parsed["RCCM"]["pins"], + pinmap_rccm, + ), + ] + + # Write children FIRST, then TOP + src = [] + for key in ("INPUT", "BIAS", "VCM", "SBCM", "RCCM"): + src.append(parsed[key]["text"].rstrip()) + src.append("") + + src.append(f".subckt {prefix} " + " ".join(top_pins)) + src.extend(x_lines) + src.append(".ends " + prefix) + src.append("") + + source_netlist = "\n".join(src) + + topnet = Netlist( + circuit_name=prefix, + nodes=top_pins, + source_netlist=source_netlist, + instance_format="X{name} {nodes} {circuit_name}", + parameters={}, + ) + + if show_netlist: + print("Generated top-level netlist:\n") + print(topnet.generate_netlist()) + + return topnet + +# def generate_top_netlist( +# prefix: str, +# in_net: str, +# aux_net: str, +# en_net: str, +# out_vcm_net: str, +# out_sbcm_net: str, +# out_rccm_net: str, +# nl_input: Netlist, +# nl_vcm: Netlist, +# nl_sbcm: Netlist, +# nl_rccm: Netlist, +# show_netlist: bool = False, +# ) -> Netlist: +# """ +# Build top-level .subckt that instantiates child subckts and wires them to top nets. +# TOP pin order must match layout header: +# .subckt TOP VIN VSS VDD VOUT_RCCM VOUT_SBCM VOUT_VCM VAUX EN +# """ +# top_pins = [ +# in_net, +# "VSS", +# "VDD", +# out_rccm_net, +# out_sbcm_net, +# out_vcm_net, +# aux_net, +# en_net, +# ] + +# netlist = Netlist( +# circuit_name=prefix, +# nodes=top_pins, +# ) + + +# in_comp = netlist.connect_netlist(nl_input, [('VIN',in_net),('EN',en_net), ('VDD','VDD')]) +# vcm_comp = netlist.connect_netlist(nl_vcm, [('VOUT',out_vcm_net),('VSS','VSS')]) +# sbcm_comp = netlist.connect_netlist(nl_sbcm, [('VOUT',out_sbcm_net),('VSS','VSS')]) +# rccm_comp = netlist.connect_netlist(nl_rccm, [('VAUX',aux_net),('VOUT',out_rccm_net),('VSS','VSS')]) + +# netlist.connect_subnets(in_comp, vcm_comp, [('VOUT_VCM','VIN')]) +# netlist.connect_subnets(in_comp, sbcm_comp, [('VOUT_BCM','VIN')]) +# netlist.connect_subnets(in_comp, rccm_comp, [('VOUT_CCM','VIN')]) + +# if show_netlist: +# print("Generated top-level netlist:\n") +# print(netlist.generate_netlist()) + +# return netlist + + +# @validate_arguments +def top( + pdk: MappedPDK, + with_tie: Optional[bool] = True, + with_dummy: Optional[bool] = True, + tie_layers: tuple[str, str] = ("met2", "met1"), + show_netlist: Optional[bool] = False, + add_labels: bool = True, + **kwargs, +) -> Component: + """An instantiable self biased cascoded current mirror that returns a Component.""" + pdk.activate() + + # Create the current mirror component + top_level = Component(name="top_design") + top_ref = prec_ref_center(top_level) + + viam1m2 = via_stack(pdk, "met1", "met2", centered=True) + viam2m3 = via_stack(pdk, "met2", "met3", centered=True) + viam1m3 = via_stack(pdk, "met1", "met3", centered=True) + + # ------------------------------------------------------------------------- + # CREATING THE INPUT STAGE + # ------------------------------------------------------------------------- + print("Creating Input Stage ...") + + input_stage_comp = input_stage( + pdk, + num_cols=1, + Length=2, + Width=10, + device="pfet", + with_substrate_tap=False, + with_tie=with_tie, + with_dummy=with_dummy, + tie_layers=tie_layers, + add_labels=False, + ) + input_stage_ref = prec_ref_center(input_stage_comp) + input_stage_ref.move(top_ref.center) + top_level.add(input_stage_ref) + top_level.add_ports(input_stage_ref.get_ports_list(), prefix="input_") + + center = top_level.center + + # ------------------------------------------------------------------------- + # CREATING THE VANILLA CURRENT MIRROR STAGE + # ------------------------------------------------------------------------- + print("Creating Vanilla Current Mirror ...") + + VCM = current_mirror_base( + pdk, + num_cols=1, + Length=1, + Width=4, + device="nfet", + with_substrate_tap=False, + add_labels=False, + ) + vcm_ref = prec_ref_center(VCM) + vcm_ref.move(center).movex( + evaluate_bbox(input_stage_ref)[0] + 4 * pdk.util_max_metal_seperation() + ).movey(-evaluate_bbox(input_stage_ref)[1] / 2) + + top_level.add(vcm_ref) + top_level.add_ports(vcm_ref.get_ports_list(), prefix="vcm_") + + top_level << L_route( + pdk, vcm_ref.ports["IN_top_met_N"], input_stage_ref.ports["OUT_B_top_met_E"] + ) + + # ------------------------------------------------------------------------- + # CREATING THE SELF-BIASED CURRENT MIRROR STAGE + # ------------------------------------------------------------------------- + print("Creating Self-Biased Current Mirror ...") + + SBCM = self_biased_cascode_current_mirror( + pdk, num_cols=1, Length=1, Width=4, device="nfet", add_labels=False + ) + sbcm_ref = prec_ref_center(SBCM) + sbcm_ref.move(center).movex( + evaluate_bbox(input_stage_ref)[0] + 4 * pdk.util_max_metal_seperation() + ) + + top_level.add(sbcm_ref) + top_level.add_ports(sbcm_ref.get_ports_list(), prefix="sbcm_") + + top_level << L_route( + pdk, sbcm_ref.ports["IN_top_met_N"], input_stage_ref.ports["OUT_C_top_met_E"] + ) + + # ------------------------------------------------------------------------- + # CREATING THE REGULATED CASCODE CURRENT MIRROR STAGE + # ------------------------------------------------------------------------- + print("Creating Regulated Cascoded Current Mirror ...") + + RCCM = regulated_cascode_current_mirror( + pdk, num_cols=2, Length=1, Width=4, device="nfet", show_netlist=False, add_labels=False + ) + rccm_ref = prec_ref_center(RCCM) + rccm_ref.move(center).movex( + evaluate_bbox(input_stage_ref)[0] + 4 * pdk.util_max_metal_seperation() + ).movey(+evaluate_bbox(input_stage_ref)[1] / 2) + + top_level.add(rccm_ref) + top_level.add_ports(rccm_ref.get_ports_list(), prefix="rccm_") + + dist_via = abs( + rccm_ref.ports["IN_top_met_W"].center[0] + - rccm_ref.ports["IN_top_met_E"].center[0] + ) / 2 + + in_rccm_via = top_level << viam2m3 + in_rccm_via.move((input_stage_ref.ports["OUT_D_top_met_W"].center)).movex(dist_via) + + rccm_in_via = top_level << viam2m3 + rccm_in_via.move((rccm_ref.ports["IN_top_met_W"].center)).movex(dist_via) + + + top_level << L_route( + pdk, in_rccm_via.ports["top_met_N"], rccm_in_via.ports["top_met_W"], hglayer="met3", vglayer="met3", + ) + + # ------------------------------------------------------------------------- + # CREATING THE BIAS STAGE + # ------------------------------------------------------------------------- + print("Creating Bias Stage ...") + + bias_stage_comp = bias_stage( + pdk, + add_labels=False, + ) + bias_stage_ref = prec_ref_center(bias_stage_comp) + + bias_stage_ref.move(center).movex( + -3 * evaluate_bbox(input_stage_ref)[0] - 6 * pdk.util_max_metal_seperation() + ).movey(+evaluate_bbox(input_stage_ref)[1] / 2 + evaluate_bbox(sbcm_ref)[1] / 2 + 6 * pdk.util_max_metal_seperation()) + bias_stage_ref.move(center) + top_level.add(bias_stage_ref) + top_level.add_ports(bias_stage_ref.get_ports_list(), prefix="bias_") + + + # ------------------------------------------------------------------------- + # CONNECTING AUX + # ------------------------------------------------------------------------- + + + top_level << L_route( + pdk, bias_stage_ref.ports["base_right_OUT_top_met_N"], rccm_ref.ports["AUX_A_top_met_W"], hglayer="met1", vglayer="met1", + ) + + en_via = top_level << viam1m2 + en_via.move(bias_stage_ref.ports["fet_right_multiplier_0_gate_E"].center).movex(evaluate_bbox(bias_stage_ref)[0]) + top_level.add_ports(en_via.get_ports_list(), prefix=f"EN_") + + top_level << straight_route( + pdk, + bias_stage_ref.ports["fet_right_multiplier_0_gate_E"], + en_via.ports["top_met_W"], + glayer1="met2", + glayer2="met2", + ) + + en_input_via = top_level << viam2m3 + en_input_via.move((input_stage_ref.ports["EN_A_top_met_N"].center[0], en_via.center[1])) + + en_input_conn_via = top_level << viam2m3 + en_input_conn_via.move(input_stage_ref.ports["EN_A_top_met_N"].center) + + top_level << straight_route( + pdk, + en_input_via.ports["top_met_S"], + en_input_conn_via.ports["top_met_S"], + glayer1="met3", + glayer2="met3", + ) + + aux_via = top_level << viam2m3 + aux_via.move(en_via.center).movey(evaluate_bbox(rccm_ref)[1]) + top_level.add_ports(aux_via.get_ports_list(), prefix=f"VAUX_") + + ##### This one Met 3 + top_level << L_route( + pdk, + bias_stage_ref.ports["base_left_IN_top_met_N"], + aux_via.ports["top_met_W"], + hglayer="met3", vglayer="met2" + ) + + # Outputs + + vcm_via = top_level << viam1m2 + vcm_via.move((en_via.center[0], vcm_ref.ports["OUT_top_met_W"].center[1])) + top_level.add_ports(vcm_via.get_ports_list(), prefix=f"VOUT_VCM_") + + top_level << straight_route( + pdk, + vcm_via.ports["top_met_W"], + vcm_ref.ports["OUT_top_met_E"], + glayer1="met2", + glayer2="met2", + ) + + sbcm_via = top_level << viam1m2 + sbcm_via.move((en_via.center[0], sbcm_ref.ports["OUT_top_met_W"].center[1])) + top_level.add_ports(sbcm_via.get_ports_list(), prefix=f"VOUT_SBCM_") + + top_level << straight_route( + pdk, + sbcm_via.ports["top_met_W"], + sbcm_ref.ports["OUT_top_met_E"], + glayer1="met2", + glayer2="met2", + ) + + rccm_via = top_level << viam1m2 + rccm_via.move((en_via.center[0], rccm_ref.ports["OUT_top_met_W"].center[1])) + top_level.add_ports(rccm_via.get_ports_list(), prefix=f"VOUT_RCCM_") + + top_level << straight_route( + pdk, + rccm_via.ports["top_met_W"], + rccm_ref.ports["OUT_top_met_E"], + glayer1="met2", + glayer2="met2", + ) + + outvin_via = top_level << viam1m2 + outvin_via.move(en_via.center).movey(-evaluate_bbox(vcm_ref)[1] + 6 * pdk.util_max_metal_seperation()) + top_level.add_ports(outvin_via.get_ports_list(), prefix=f"VOUT_VIN_") + + top_level << L_route( + pdk, input_stage_ref.ports["OUT_E_top_met_N"], outvin_via.ports["top_met_W"], hglayer="met2", vglayer="met2", + ) + + # Input + + vin1_via = top_level << viam1m2 + vin1_via.move(input_stage_ref.ports["IN_A_top_met_N"].center).movey(-evaluate_bbox(sbcm_ref)[1]) + + vin2_via = top_level << viam1m2 + vin2_via.move(vin1_via.center).movex(2*evaluate_bbox(input_stage_ref)[0]) + + vin3_via = top_level << viam1m2 + vin3_via.move(aux_via.center).movey(evaluate_bbox(rccm_ref)[1]) + top_level.add_ports(vin3_via.get_ports_list(), prefix=f"VIN_") + + top_level << straight_route( + pdk, + input_stage_ref.ports["IN_A_top_met_S"], + vin1_via.ports["top_met_N"], + glayer1="met1", + glayer2="met1", + ) + + top_level << straight_route( + pdk, + vin1_via.ports["top_met_E"], + vin2_via.ports["top_met_W"], + glayer1="met1", + glayer2="met1", + ) + + top_level << L_route( + pdk, + vin2_via.ports["top_met_N"], + vin3_via.ports["top_met_W"], + hglayer="met1", vglayer="met1", + ) + + # VSS + + vss_via = top_level << viam1m3 + vss_via.move(vin3_via.center).movey(evaluate_bbox(rccm_ref)[1]) + top_level.add_ports(vss_via.get_ports_list(), prefix=f"VSS_") + + top_level << L_route( + pdk, + vss_via.ports["top_met_W"], + rccm_ref.ports["welltie_N_top_met_N"], + hglayer="met1", vglayer="met1", + vwidth=5, hwidth=5 + ) + + ###### DRC_Error + # handles = place_welltie_via_row( + # top_level, pdk, "bias_base_bottom", + # top_layer="met3", + # use_edges=False, offset=5.0, + # fill_mode="auto", + # ) + + # top_level << L_route( + # pdk, + # bias_stage_ref.ports["base_bottom_welltie_N_top_met_N"], + # vss_via.ports["top_met_W"], + # hglayer="met3", vglayer="met3", + # vwidth=12, hwidth=12, + # ) + ####################################################### + + # VDD + vdd_via = top_level << viam1m2 + vdd_via.move(vss_via.center).movey(evaluate_bbox(rccm_ref)[1]) + top_level.add_ports(vdd_via.get_ports_list(), prefix=f"VDD_") + + top_level << L_route( + pdk, + vdd_via.ports["top_met_W"], + bias_stage_ref.ports["fet_left_tie_N_top_met_N"], + hglayer="met1", vglayer="met1", + vwidth=5, hwidth=5 + ) + + + # ------------------------------------------------------------------------- + # CONNECTING VDD TOGETHER + # ------------------------------------------------------------------------- + + top_level << straight_route( + pdk, + bias_stage_ref.ports["VDD_port"], + top_level.ports["input_welltie_W_top_met_W"], + glayer1="met1", + glayer2="met1", + width=10, + ) + + # ------------------------------------------------------------------------- + # CONNECTING VSS TOGETHER + # ------------------------------------------------------------------------- + top_level << straight_route( + pdk, + top_level.ports["vcm_welltie_N_top_met_N"], + top_level.ports["sbcm_welltie_S_top_met_S"], + glayer1="met1", + glayer2="met1", + width=10, + ) + top_level << straight_route( + pdk, + top_level.ports["sbcm_welltie_N_top_met_N"], + top_level.ports["rccm_welltie_S_top_met_S"], + glayer1="met1", + glayer2="met1", + width=10, + ) + + top_level << L_route( + pdk, + bias_stage_ref.ports["base_bottom_welltie_N_top_met_N"], + vss_via.ports["top_met_W"], + hglayer="met2", vglayer="met2", + vwidth=12, hwidth=12, + ) + + top_level = component_snap_to_grid(rename_ports_by_orientation(top_level)) + + top_level.info["netlist"] = generate_top_netlist( + prefix="TOP", + in_net="VIN", + aux_net="VAUX", + en_net="EN", + out_vcm_net="VOUT_VCM", + out_sbcm_net="VOUT_SBCM", + out_rccm_net="VOUT_RCCM", + out_vin_net="VOUT_VIN", + nl_input=input_stage_comp.info["netlist"], + nl_bias=bias_stage_comp.info["netlist"], + nl_vcm=VCM.info["netlist"], + nl_sbcm=SBCM.info["netlist"], + nl_rccm=RCCM.info["netlist"], + show_netlist=show_netlist, + ) + + if add_labels: + return add_cm_labels(top_level, pdk) + return top_level + +def add_cm_labels(cm_in: Component, pdk: MappedPDK) -> Component: + cm_in.unlock() + + psize = (0.35, 0.35) + move_info = [] + + # VIN + vinlabel = rectangle(layer=pdk.get_glayer("met2_pin"), size=psize, centered=True).copy() + vinlabel.add_label(text="VIN", layer=pdk.get_glayer("met2_label")) + move_info.append((vinlabel, cm_in.ports["VIN_top_met_E"], None)) + + # EN + vEnlabel = rectangle(layer=pdk.get_glayer("met2_pin"), size=psize, centered=True).copy() + vEnlabel.add_label(text="EN", layer=pdk.get_glayer("met2_label")) + move_info.append((vEnlabel, cm_in.ports["EN_top_met_E"], None)) + + # VAUX + vauxlabel = rectangle(layer=pdk.get_glayer("met2_pin"), size=psize, centered=True).copy() + vauxlabel.add_label(text="VAUX", layer=pdk.get_glayer("met2_label")) + move_info.append((vauxlabel, cm_in.ports["VAUX_top_met_E"], None)) + + # VOUT VCM + voutvcmlabel = rectangle(layer=pdk.get_glayer("met2_pin"), size=psize, centered=True).copy() + voutvcmlabel.add_label(text="VOUT_VCM", layer=pdk.get_glayer("met2_label")) + move_info.append((voutvcmlabel, cm_in.ports["VOUT_VCM_top_met_E"], None)) + + # VOUT SBCM + voutsbcmlabel = rectangle(layer=pdk.get_glayer("met2_pin"), size=psize, centered=True).copy() + voutsbcmlabel.add_label(text="VOUT_SBCM", layer=pdk.get_glayer("met2_label")) + move_info.append((voutsbcmlabel, cm_in.ports["VOUT_SBCM_top_met_E"], None)) + + # VOUT RCCM + voutrccmlabel = rectangle(layer=pdk.get_glayer("met2_pin"), size=psize, centered=True).copy() + voutrccmlabel.add_label(text="VOUT_RCCM", layer=pdk.get_glayer("met2_label")) + move_info.append((voutrccmlabel, cm_in.ports["VOUT_RCCM_top_met_E"], None)) + + # VOUT VIN + voutvinlabel = rectangle(layer=pdk.get_glayer("met2_pin"), size=psize, centered=True).copy() + voutvinlabel.add_label(text="VOUT_VIN", layer=pdk.get_glayer("met2_label")) + move_info.append((voutvinlabel, cm_in.ports["VOUT_VIN_top_met_E"], None)) + + # VDD (well tie) + vddlabel = rectangle(layer=pdk.get_glayer("met1_pin"), size=psize, centered=True).copy() + vddlabel.add_label(text="VDD", layer=pdk.get_glayer("met1_label")) + move_info.append((vddlabel, cm_in.ports["VDD_top_met_E"], None)) + + # VSS (well tie) + vsslabel = rectangle(layer=pdk.get_glayer("met1_pin"), size=psize, centered=True).copy() + vsslabel.add_label(text="VSS", layer=pdk.get_glayer("met1_label")) + move_info.append((vsslabel, cm_in.ports["VSS_top_met_E"], None)) + + # + + for comp, prt, alignment in move_info: + alignment = ("c", "b") if alignment is None else alignment + compref = align_comp_to_port(comp, prt, alignment=alignment) + cm_in.add(compref) + + return cm_in.flatten() + + +def place_welltie_via_row( + top_level, + pdk, + block_key: str=None, # expects f"{block_key}_welltie_S_top_met_S" + *, + top_layer: str = "met3", # top layer to reach (string, e.g. "met3") + # Where to put the two edge via stacks: + use_edges: bool = True, # True: at ± welltie.width/2; False: at ±offset + offset: float = 5.0, # used when use_edges=False (distance from center) + jog_dy: float = 0.0, # vertical offset for the whole via row center + + # How to fill middle stacks: mode ∈ {"auto","pitch","count"} + fill_mode: str = "auto", + pitch: float | None = None, # used when fill_mode="pitch" + count: int | None = None, # used when fill_mode="count" + edge_margin: float = 0.0, # keep gap from edges for "pitch" mode +): + """ + Returns dict with keys: + left_ref, right_ref: ComponentReference of edge stacks + left_top, right_top: Port on top_layer for each edge stack + mid_refs: list[ComponentReference] for middle stacks + mid_top_ports: list[Port] top ports for middle stacks + """ + # --- 1) resolve the welltie S-facing top-metal port --- + + wt = top_level.ports[f"{block_key}_welltie_N_top_met_N"] # Port (likely on met1 or met2) + + delta_y = abs(top_level.ports[f"{block_key}_welltie_N_top_met_N"].center[1] - top_level.ports[f"{block_key}_welltie_N_top_met_S"].center[1])/2 + x0, y0 = wt.center + + w_wt = wt.width + + # --- 2) utilities: mapping layer tuple<->name and grid snapping --- + def _name_of(gl_tuple): + for nm in ("met1","met2","met3","met4","met5"): + try: + if pdk.get_glayer(nm) == gl_tuple: + return nm + except Exception: + pass + raise ValueError(f"Unknown layer tuple {gl_tuple}") + + snap = pdk.snap_to_2xgrid + bottom_layer = _name_of(wt.layer) # e.g. "met1" or "met2" + bot_gl = pdk.get_glayer(bottom_layer) + top_gl = pdk.get_glayer(top_layer) + + # --- 3) edge stack X positions --- + if use_edges: + xL = snap(x0 - w_wt/2) + xR = snap(x0 + w_wt/2) + else: + xL = snap(x0 - abs(offset)) + xR = snap(x0 + abs(offset)) + yC = snap(y0 - delta_y+ jog_dy) + + # --- 4) create via stack template and place the two edge stacks (as refs) --- + vs_proto = via_stack(pdk, bottom_layer, top_layer) # Component + left_ref = top_level << vs_proto # ComponentReference + right_ref = top_level << vs_proto + left_ref.move((xL, yC)) + right_ref.move((xR, yC)) + + # helper to pick bottom/top ports of a via ref + def _bottom_port(vref): + return next(p for p in vref.ports.values() if p.layer == bot_gl) + def _top_port(vref): + return next(p for p in vref.ports.values() if p.layer == top_gl) + + left_bot = _bottom_port(left_ref) + right_bot = _bottom_port(right_ref) + left_top = _top_port(left_ref) + right_top = _top_port(right_ref) + + + # --- 6) compute middle positions depending on fill_mode --- + mid_refs = [] + mid_top_ports = [] + + xL_center, _ = left_ref.center + xR_center, _ = right_ref.center + + if fill_mode not in {"auto","pitch","count"}: + raise ValueError("fill_mode must be one of {'auto','pitch','count'}") + + if fill_mode == "count": + n = int(count or 0) + if n > 0: + step = (xR_center - xL_center) / (n + 1) + for k in range(1, n+1): + xk = snap(xL_center + k*step) + r = top_level << vs_proto + r.move((xk, yC)) + mid_refs.append(r) + mid_top_ports.append(_top_port(r)) + + else: + # need a pitch value: either provided, or auto-computed + if fill_mode == "pitch": + if pitch is None or pitch <= 0: + raise ValueError("fill_mode='pitch' requires a positive 'pitch' parameter.") + eff_pitch = float(pitch) + else: + # "auto": via width on top layer + min spacing of that layer + # get via *component* width on x from template bbox + vx, _vy = evaluate_bbox(vs_proto) # (w, h) in layout units + min_sp = pdk.get_grule(top_layer)["min_separation"] + eff_pitch = snap(vx + min_sp) + + x_start = snap(xL_center + edge_margin) + x_stop = snap(xR_center - edge_margin) + + x = x_start + eff_pitch + # leave small epsilon to avoid placing on/over the right ref + while x < x_stop - 1e-6: + r = top_level << vs_proto + r.move((snap(x), yC)) + mid_refs.append(r) + mid_top_ports.append(_top_port(r)) + x += eff_pitch + + return { + "left_ref": left_ref, "right_ref": right_ref, + "left_top": left_top, "right_top": right_top, + "mid_refs": mid_refs, "mid_top_ports": mid_top_ports, + } + + +if __name__ == "__main__": + selected_pdk = gf180 + + # DRC + drc_result = selected_pdk.drc_magic("gds/top.gds", "TOP", output_file=Path("DRC/")) + + # LVS + netgen_lvs_result = selected_pdk.lvs_netgen( + "gds/top.gds", "TOP", netlist="gds/top_new.spice", output_file_path=Path("LVS/"), copy_intermediate_files=True + ) diff --git a/blocks/composite/regulated_cascoded_cmirror/A3_core/README.md b/blocks/composite/regulated_cascoded_cmirror/A3_core/README.md new file mode 100644 index 00000000..593458bc --- /dev/null +++ b/blocks/composite/regulated_cascoded_cmirror/A3_core/README.md @@ -0,0 +1,3 @@ +## gLayout-mahowalders + +> 🚧 **Under Construction** diff --git a/blocks/composite/regulated_cascoded_cmirror/A3_core/bias/bias.sch b/blocks/composite/regulated_cascoded_cmirror/A3_core/bias/bias.sch new file mode 100644 index 00000000..84fc96e3 --- /dev/null +++ b/blocks/composite/regulated_cascoded_cmirror/A3_core/bias/bias.sch @@ -0,0 +1,363 @@ +v {xschem version=3.4.7 file_version=1.2} +G {} +K {} +V {} +S {} +E {} +N -370 -210 -370 -150 {lab=#net1} +N -330 -120 -190 -120 {lab=bias_in} +N -330 -240 -190 -240 {lab=#net1} +N -150 -210 -150 -150 {lab=#net2} +N -370 -180 -280 -180 {lab=#net1} +N -280 -120 -280 -60 {lab=bias_in} +N -260 -260 -260 -240 {lab=#net1} +N -260 -240 -260 -190 {lab=#net1} +N -260 -190 -260 -180 {lab=#net1} +N -280 -180 -260 -180 {lab=#net1} +N -370 -340 -370 -270 {lab=VDD} +N -260 -340 -260 -320 {lab=VDD} +N -150 -340 -150 -270 {lab=VDD} +N -330 -290 -300 -290 {lab=ENA} +N -370 -90 -370 -60 {lab=bias_in} +N -150 -90 -150 -70 {lab=#net3} +N 160 -210 160 -150 {lab=#net4} +N 200 -120 340 -120 {lab=#net5} +N 200 -240 340 -240 {lab=#net4} +N 380 -210 380 -150 {lab=#net6} +N 160 -180 250 -180 {lab=#net4} +N 250 -120 250 -60 {lab=#net5} +N 270 -260 270 -240 {lab=#net4} +N 270 -240 270 -190 {lab=#net4} +N 270 -190 270 -180 {lab=#net4} +N 250 -180 270 -180 {lab=#net4} +N 160 -340 160 -270 {lab=VDD} +N 270 -340 270 -320 {lab=VDD} +N 200 -290 230 -290 {lab=ENA} +N 160 -90 160 -60 {lab=#net5} +N 380 -90 380 -70 {lab=bias_out} +N 80 420 80 440 {lab=vss} +N 80 350 120 350 {lab=vss} +N 120 350 120 400 {lab=vss} +N 80 400 120 400 {lab=vss} +N 0 350 40 350 {lab=#net7} +N -60 300 -60 320 {lab=#net7} +N -60 300 0 300 {lab=#net7} +N 0 300 0 350 {lab=#net7} +N -60 180 -60 300 {lab=#net7} +N -60 390 -60 440 {lab=vss} +N -120 350 -60 350 {lab=vss} +N -120 350 -120 390 {lab=vss} +N -120 390 -60 390 {lab=vss} +N 80 230 80 320 {lab=#net8} +N 80 380 80 400 {lab=vss} +N -20 350 0 350 {lab=#net7} +N -60 380 -60 390 {lab=vss} +N 80 400 80 420 {lab=vss} +N -60 440 80 440 {lab=vss} +N 80 200 80 230 {lab=#net8} +N 80 110 120 110 {lab=vss} +N 120 110 120 160 {lab=vss} +N 0 110 40 110 {lab=#net3} +N -60 60 -60 80 {lab=#net3} +N -60 60 0 60 {lab=#net3} +N 0 60 0 110 {lab=#net3} +N -120 110 -60 110 {lab=vss} +N -120 110 -120 150 {lab=vss} +N 80 140 80 160 {lab=#net8} +N -20 110 0 110 {lab=#net3} +N -60 140 -60 150 {lab=#net7} +N -60 50 -60 60 {lab=#net3} +N -60 150 -60 180 {lab=#net7} +N 80 160 80 200 {lab=#net8} +N 80 50 80 80 {lab=#net5} +N -120 20 -100 20 {lab=#net3} +N 120 160 120 350 {lab=vss} +N -120 150 -120 350 {lab=vss} +N -160 440 -60 440 {lab=vss} +N -60 20 -60 50 {lab=#net3} +N -100 20 -60 20 {lab=#net3} +N 80 10 90 10 {lab=#net5} +N 80 10 80 50 {lab=#net5} +N -460 -390 380 -390 {lab=VDD} +N 380 -390 380 -270 {lab=VDD} +N 270 -390 270 -340 {lab=VDD} +N 160 -390 160 -340 {lab=VDD} +N -150 -390 -150 -340 {lab=VDD} +N -370 -390 -370 -340 {lab=VDD} +N -260 -390 -260 -340 {lab=VDD} +N -600 -390 -580 -390 {lab=VDD} +N -580 -330 200 -330 {lab=ENA} +N 200 -330 200 -290 {lab=ENA} +N -330 -330 -330 -290 {lab=ENA} +N -620 -40 -370 -40 {lab=bias_in} +N -370 -60 -370 -40 {lab=bias_in} +N -370 -40 -280 -40 {lab=bias_in} +N -280 -60 -280 -40 {lab=bias_in} +N -150 -70 -150 20 {lab=#net3} +N -150 20 -120 20 {lab=#net3} +N 160 -60 160 10 {lab=#net5} +N 90 10 160 10 {lab=#net5} +N 160 -60 250 -60 {lab=#net5} +N 380 -30 490 -30 {lab=bias_out} +N 380 -70 380 -30 {lab=bias_out} +N -560 440 -160 440 {lab=vss} +N 490 -390 490 -360 {lab=VDD} +N 380 -390 490 -390 {lab=VDD} +N 450 -390 450 -330 {lab=VDD} +N 490 -300 520 -300 {lab=VDD} +N 520 -390 520 -300 {lab=VDD} +N 490 -390 520 -390 {lab=VDD} +N 490 -330 520 -330 {lab=VDD} +N 230 380 230 440 {lab=vss} +N 80 440 230 440 {lab=vss} +N 190 350 190 440 {lab=vss} +N 230 320 270 320 {lab=vss} +N 270 320 270 440 {lab=vss} +N 230 440 270 440 {lab=vss} +N 230 350 270 350 {lab=vss} +C {symbols/pfet_03v3.sym} -350 -240 0 1 {name=M11 +L=2.0u +W=100.0u +nf=10 +m=1 +ad="'int((nf+1)/2) * W/nf * 0.18u'" +pd="'2*int((nf+1)/2) * (W/nf + 0.18u)'" +as="'int((nf+2)/2) * W/nf * 0.18u'" +ps="'2*int((nf+2)/2) * (W/nf + 0.18u)'" +nrd="'0.18u / W'" nrs="'0.18u / W'" +sa=0 sb=0 sd=0 +model=pfet_03v3 +spiceprefix=X +} +C {symbols/pfet_03v3.sym} -350 -120 0 1 {name=M12 +L=2.0u +W=100.0u +nf=10 +m=1 +ad="'int((nf+1)/2) * W/nf * 0.18u'" +pd="'2*int((nf+1)/2) * (W/nf + 0.18u)'" +as="'int((nf+2)/2) * W/nf * 0.18u'" +ps="'2*int((nf+2)/2) * (W/nf + 0.18u)'" +nrd="'0.18u / W'" nrs="'0.18u / W'" +sa=0 sb=0 sd=0 +model=pfet_03v3 +spiceprefix=X +} +C {symbols/pfet_03v3.sym} -280 -290 0 0 {name=M16 +L=2.0u +W=10.0u +nf=1 +m=1 +ad="'int((nf+1)/2) * W/nf * 0.18u'" +pd="'2*int((nf+1)/2) * (W/nf + 0.18u)'" +as="'int((nf+2)/2) * W/nf * 0.18u'" +ps="'2*int((nf+2)/2) * (W/nf + 0.18u)'" +nrd="'0.18u / W'" nrs="'0.18u / W'" +sa=0 sb=0 sd=0 +model=pfet_03v3 +spiceprefix=X +} +C {symbols/pfet_03v3.sym} -170 -240 0 0 {name=M17 +L=2.0u +W=10.0u +nf=1 +m=1 +ad="'int((nf+1)/2) * W/nf * 0.18u'" +pd="'2*int((nf+1)/2) * (W/nf + 0.18u)'" +as="'int((nf+2)/2) * W/nf * 0.18u'" +ps="'2*int((nf+2)/2) * (W/nf + 0.18u)'" +nrd="'0.18u / W'" nrs="'0.18u / W'" +sa=0 sb=0 sd=0 +model=pfet_03v3 +spiceprefix=X +} +C {symbols/pfet_03v3.sym} -170 -120 0 0 {name=M19 +L=2.0u +W=10.0u +nf=1 +m=1 +ad="'int((nf+1)/2) * W/nf * 0.18u'" +pd="'2*int((nf+1)/2) * (W/nf + 0.18u)'" +as="'int((nf+2)/2) * W/nf * 0.18u'" +ps="'2*int((nf+2)/2) * (W/nf + 0.18u)'" +nrd="'0.18u / W'" nrs="'0.18u / W'" +sa=0 sb=0 sd=0 +model=pfet_03v3 +spiceprefix=X +} +C {lab_pin.sym} -370 -240 0 0 {name=p25 sig_type=std_logic lab=VDD} +C {lab_pin.sym} -370 -120 0 0 {name=p26 sig_type=std_logic lab=VDD} +C {lab_pin.sym} -150 -240 2 0 {name=p27 sig_type=std_logic lab=VDD} +C {lab_pin.sym} -150 -120 2 0 {name=p28 sig_type=std_logic lab=VDD} +C {lab_pin.sym} -260 -290 2 0 {name=p29 sig_type=std_logic lab=VDD} +C {symbols/pfet_03v3.sym} 180 -240 0 1 {name=M9 +L=2.0u +W=100.0u +nf=10 +m=1 +ad="'int((nf+1)/2) * W/nf * 0.18u'" +pd="'2*int((nf+1)/2) * (W/nf + 0.18u)'" +as="'int((nf+2)/2) * W/nf * 0.18u'" +ps="'2*int((nf+2)/2) * (W/nf + 0.18u)'" +nrd="'0.18u / W'" nrs="'0.18u / W'" +sa=0 sb=0 sd=0 +model=pfet_03v3 +spiceprefix=X +} +C {symbols/pfet_03v3.sym} 180 -120 0 1 {name=M10 +L=2.0u +W=100.0u +nf=10 +m=1 +ad="'int((nf+1)/2) * W/nf * 0.18u'" +pd="'2*int((nf+1)/2) * (W/nf + 0.18u)'" +as="'int((nf+2)/2) * W/nf * 0.18u'" +ps="'2*int((nf+2)/2) * (W/nf + 0.18u)'" +nrd="'0.18u / W'" nrs="'0.18u / W'" +sa=0 sb=0 sd=0 +model=pfet_03v3 +spiceprefix=X +} +C {symbols/pfet_03v3.sym} 250 -290 0 0 {name=M13 +L=2.0u +W=10.0u +nf=1 +m=1 +ad="'int((nf+1)/2) * W/nf * 0.18u'" +pd="'2*int((nf+1)/2) * (W/nf + 0.18u)'" +as="'int((nf+2)/2) * W/nf * 0.18u'" +ps="'2*int((nf+2)/2) * (W/nf + 0.18u)'" +nrd="'0.18u / W'" nrs="'0.18u / W'" +sa=0 sb=0 sd=0 +model=pfet_03v3 +spiceprefix=X +} +C {symbols/pfet_03v3.sym} 360 -240 0 0 {name=M20 +L=2.0u +W=10.0u +nf=1 +m=1 +ad="'int((nf+1)/2) * W/nf * 0.18u'" +pd="'2*int((nf+1)/2) * (W/nf + 0.18u)'" +as="'int((nf+2)/2) * W/nf * 0.18u'" +ps="'2*int((nf+2)/2) * (W/nf + 0.18u)'" +nrd="'0.18u / W'" nrs="'0.18u / W'" +sa=0 sb=0 sd=0 +model=pfet_03v3 +spiceprefix=X +} +C {symbols/pfet_03v3.sym} 360 -120 0 0 {name=M21 +L=2.0u +W=10.0u +nf=10 +m=1 +ad="'int((nf+1)/2) * W/nf * 0.18u'" +pd="'2*int((nf+1)/2) * (W/nf + 0.18u)'" +as="'int((nf+2)/2) * W/nf * 0.18u'" +ps="'2*int((nf+2)/2) * (W/nf + 0.18u)'" +nrd="'0.18u / W'" nrs="'0.18u / W'" +sa=0 sb=0 sd=0 +model=pfet_03v3 +spiceprefix=X +} +C {lab_pin.sym} 160 -240 0 0 {name=p30 sig_type=std_logic lab=VDD} +C {lab_pin.sym} 160 -120 0 0 {name=p31 sig_type=std_logic lab=VDD} +C {lab_pin.sym} 380 -240 2 0 {name=p32 sig_type=std_logic lab=VDD} +C {lab_pin.sym} 380 -120 2 0 {name=p33 sig_type=std_logic lab=VDD} +C {lab_pin.sym} 270 -290 2 0 {name=p34 sig_type=std_logic lab=VDD} +C {symbols/nfet_03v3.sym} 60 350 0 0 {name=M22 +L=1u +W=8u +nf=1 +m=1 +ad="'int((nf+1)/2) * W/nf * 0.18u'" +pd="'2*int((nf+1)/2) * (W/nf + 0.18u)'" +as="'int((nf+2)/2) * W/nf * 0.18u'" +ps="'2*int((nf+2)/2) * (W/nf + 0.18u)'" +nrd="'0.18u / W'" nrs="'0.18u / W'" +sa=0 sb=0 sd=0 +model=nfet_03v3 +spiceprefix=X +} +C {symbols/nfet_03v3.sym} -40 350 0 1 {name=M23 +L=1u +W=80u +nf=10 +m=1 +ad="'int((nf+1)/2) * W/nf * 0.18u'" +pd="'2*int((nf+1)/2) * (W/nf + 0.18u)'" +as="'int((nf+2)/2) * W/nf * 0.18u'" +ps="'2*int((nf+2)/2) * (W/nf + 0.18u)'" +nrd="'0.18u / W'" nrs="'0.18u / W'" +sa=0 sb=0 sd=0 +model=nfet_03v3 +spiceprefix=X +} +C {symbols/nfet_03v3.sym} 60 110 0 0 {name=M24 +L=1u +W=8u +nf=1 +m=1 +ad="'int((nf+1)/2) * W/nf * 0.18u'" +pd="'2*int((nf+1)/2) * (W/nf + 0.18u)'" +as="'int((nf+2)/2) * W/nf * 0.18u'" +ps="'2*int((nf+2)/2) * (W/nf + 0.18u)'" +nrd="'0.18u / W'" nrs="'0.18u / W'" +sa=0 sb=0 sd=0 +model=nfet_03v3 +spiceprefix=X +} +C {symbols/nfet_03v3.sym} -40 110 0 1 {name=M25 +L=1u +W=80u +nf=10 +m=1 +ad="'int((nf+1)/2) * W/nf * 0.18u'" +pd="'2*int((nf+1)/2) * (W/nf + 0.18u)'" +as="'int((nf+2)/2) * W/nf * 0.18u'" +ps="'2*int((nf+2)/2) * (W/nf + 0.18u)'" +nrd="'0.18u / W'" nrs="'0.18u / W'" +sa=0 sb=0 sd=0 +model=nfet_03v3 +spiceprefix=X +} +C {iopin.sym} -560 440 2 0 {name=p36 lab=vss +} +C {iopin.sym} -600 -390 2 0 {name=p1 lab=VDD +} +C {ipin.sym} -580 -330 0 0 {name=p2 lab=ENA +} +C {ipin.sym} -620 -40 0 0 {name=p3 lab=bias_in +} +C {opin.sym} 490 -30 0 0 {name=p4 lab=bias_out +} +C {lab_pin.sym} -580 -390 2 0 {name=p5 sig_type=std_logic lab=VDD} +C {lab_pin.sym} -460 -390 0 0 {name=p6 sig_type=std_logic lab=VDD} +C {symbols/pfet_03v3.sym} 470 -330 0 0 {name=M1 +L=2.0u +W=10.0u +nf=1 +m=12 +ad="'int((nf+1)/2) * W/nf * 0.18u'" +pd="'2*int((nf+1)/2) * (W/nf + 0.18u)'" +as="'int((nf+2)/2) * W/nf * 0.18u'" +ps="'2*int((nf+2)/2) * (W/nf + 0.18u)'" +nrd="'0.18u / W'" nrs="'0.18u / W'" +sa=0 sb=0 sd=0 +model=pfet_03v3 +spiceprefix=X +} +C {symbols/nfet_03v3.sym} 210 350 0 0 {name=M2 +L=1u +W=8u +nf=1 +m=4 +ad="'int((nf+1)/2) * W/nf * 0.18u'" +pd="'2*int((nf+1)/2) * (W/nf + 0.18u)'" +as="'int((nf+2)/2) * W/nf * 0.18u'" +ps="'2*int((nf+2)/2) * (W/nf + 0.18u)'" +nrd="'0.18u / W'" nrs="'0.18u / W'" +sa=0 sb=0 sd=0 +model=nfet_03v3 +spiceprefix=X +} diff --git a/blocks/composite/regulated_cascoded_cmirror/A3_core/bias/bias.sym b/blocks/composite/regulated_cascoded_cmirror/A3_core/bias/bias.sym new file mode 100644 index 00000000..ac164a01 --- /dev/null +++ b/blocks/composite/regulated_cascoded_cmirror/A3_core/bias/bias.sym @@ -0,0 +1,48 @@ +v {xschem version=3.4.7 file_version=1.2} +G {} +K {type=subcircuit +format="@name @pinlist @symname" +template="name=x1" +} +V {} +S {} +E {} +L 4 -120 -60 -100 -60 {} +L 4 -120 -40 -100 -40 {} +L 4 100 -40 120 -40 {} +L 4 -100 -40 -50 -40 {} +L 4 -50 -40 -50 -20 {} +L 4 -50 -40 -50 -10 {} +L 4 -50 -10 -30 -10 {} +L 4 -30 -10 -30 10 {} +L 4 -50 10 -30 10 {} +L 4 -50 10 -50 30 {} +L 4 -50 -40 0 -40 {} +L 4 -20 -10 -20 10 {} +L 4 -20 0 0 0 {} +L 4 0 -40 0 0 {} +L 4 50 -40 50 -20 {} +L 4 50 -40 50 -10 {} +L 4 30 -10 50 -10 {} +L 4 30 -10 30 10 {} +L 4 30 10 50 10 {} +L 4 50 10 50 30 {} +L 4 20 -10 20 10 {} +L 4 0 0 20 0 {} +L 4 50 -40 100 -40 {} +L 4 -50 30 50 30 {} +L 7 0 -70 0 -50 {} +L 7 0 30 0 50 {} +B 4 -110 -70 110 50 {fill=False} +B 5 -2.5 -72.5 2.5 -67.5 {name=VDD dir=inout} +B 5 -122.5 -62.5 -117.5 -57.5 {name=ENA dir=in} +B 5 -122.5 -42.5 -117.5 -37.5 {name=bias_in dir=in} +B 5 117.5 -42.5 122.5 -37.5 {name=bias_out dir=out} +B 5 -2.5 47.5 2.5 52.5 {name=vss dir=inout} +T {@symname} 14 -66 0 0 0.3 0.3 {} +T {@name} 65 -92 0 0 0.2 0.2 {} +T {VDD} -5 -64 0 1 0.2 0.2 {} +T {ENA} -95 -64 0 0 0.2 0.2 {} +T {bias_in} -95 -34 0 0 0.2 0.2 {} +T {bias_out} 105 -24 0 1 0.2 0.2 {} +T {vss} 5 44 2 1 0.2 0.2 {} diff --git a/blocks/composite/regulated_cascoded_cmirror/A3_core/biased_cm/biased_cm.sch b/blocks/composite/regulated_cascoded_cmirror/A3_core/biased_cm/biased_cm.sch new file mode 100644 index 00000000..f14c03f1 --- /dev/null +++ b/blocks/composite/regulated_cascoded_cmirror/A3_core/biased_cm/biased_cm.sch @@ -0,0 +1,131 @@ +v {xschem version=3.4.7 file_version=1.2} +G {} +K {} +V {} +S {} +E {} +N 320 -60 320 -40 {lab=vss} +N 320 -130 360 -130 {lab=vss} +N 360 -130 360 -80 {lab=vss} +N 320 -80 360 -80 {lab=vss} +N 240 -130 280 -130 {lab=#net1} +N 180 -180 180 -160 {lab=#net1} +N 180 -180 240 -180 {lab=#net1} +N 240 -180 240 -130 {lab=#net1} +N 180 -300 180 -180 {lab=#net1} +N 180 -90 180 -40 {lab=vss} +N 120 -130 180 -130 {lab=vss} +N 120 -130 120 -90 {lab=vss} +N 120 -90 180 -90 {lab=vss} +N 320 -250 320 -160 {lab=#net2} +N 320 -100 320 -80 {lab=vss} +N 220 -130 240 -130 {lab=#net1} +N 180 -100 180 -90 {lab=vss} +N 320 -80 320 -60 {lab=vss} +N 180 -40 320 -40 {lab=vss} +N 320 -280 320 -250 {lab=#net2} +N 320 -370 360 -370 {lab=vss} +N 360 -370 360 -320 {lab=vss} +N 240 -370 280 -370 {lab=v_in} +N 180 -420 180 -400 {lab=v_in} +N 180 -420 240 -420 {lab=v_in} +N 240 -420 240 -370 {lab=v_in} +N 120 -370 180 -370 {lab=vss} +N 120 -370 120 -330 {lab=vss} +N 320 -340 320 -320 {lab=#net2} +N 220 -370 240 -370 {lab=v_in} +N 180 -340 180 -330 {lab=#net1} +N 180 -430 180 -420 {lab=v_in} +N 180 -330 180 -300 {lab=#net1} +N 320 -320 320 -280 {lab=#net2} +N 320 -430 320 -400 {lab=v_out} +N 120 -460 140 -460 {lab=v_in} +N 360 -320 360 -130 {lab=vss} +N 120 -330 120 -130 {lab=vss} +N 80 -40 180 -40 {lab=vss} +N 180 -460 180 -430 {lab=v_in} +N 140 -460 180 -460 {lab=v_in} +N 320 -470 330 -470 {lab=v_out} +N 320 -470 320 -430 {lab=v_out} +N 450 -100 450 -40 {lab=vss} +N 320 -40 450 -40 {lab=vss} +N 410 -130 410 -40 {lab=vss} +N 450 -160 490 -160 {lab=vss} +N 490 -160 490 -40 {lab=vss} +N 450 -40 490 -40 {lab=vss} +N 450 -130 490 -130 {lab=vss} +C {symbols/nfet_03v3.sym} 300 -130 0 0 {name=M3 +L=1u +W=4u +nf=1 +m=1 +ad="'int((nf+1)/2) * W/nf * 0.18u'" +pd="'2*int((nf+1)/2) * (W/nf + 0.18u)'" +as="'int((nf+2)/2) * W/nf * 0.18u'" +ps="'2*int((nf+2)/2) * (W/nf + 0.18u)'" +nrd="'0.18u / W'" nrs="'0.18u / W'" +sa=0 sb=0 sd=0 +model=nfet_03v3 +spiceprefix=X +} +C {symbols/nfet_03v3.sym} 200 -130 0 1 {name=M4 +L=1u +W=4u +nf=1 +m=1 +ad="'int((nf+1)/2) * W/nf * 0.18u'" +pd="'2*int((nf+1)/2) * (W/nf + 0.18u)'" +as="'int((nf+2)/2) * W/nf * 0.18u'" +ps="'2*int((nf+2)/2) * (W/nf + 0.18u)'" +nrd="'0.18u / W'" nrs="'0.18u / W'" +sa=0 sb=0 sd=0 +model=nfet_03v3 +spiceprefix=X +} +C {symbols/nfet_03v3.sym} 300 -370 0 0 {name=M5 +L=1u +W=4u +nf=1 +m=1 +ad="'int((nf+1)/2) * W/nf * 0.18u'" +pd="'2*int((nf+1)/2) * (W/nf + 0.18u)'" +as="'int((nf+2)/2) * W/nf * 0.18u'" +ps="'2*int((nf+2)/2) * (W/nf + 0.18u)'" +nrd="'0.18u / W'" nrs="'0.18u / W'" +sa=0 sb=0 sd=0 +model=nfet_03v3 +spiceprefix=X +} +C {symbols/nfet_03v3.sym} 200 -370 0 1 {name=M6 +L=1u +W=4u +nf=1 +m=1 +ad="'int((nf+1)/2) * W/nf * 0.18u'" +pd="'2*int((nf+1)/2) * (W/nf + 0.18u)'" +as="'int((nf+2)/2) * W/nf * 0.18u'" +ps="'2*int((nf+2)/2) * (W/nf + 0.18u)'" +nrd="'0.18u / W'" nrs="'0.18u / W'" +sa=0 sb=0 sd=0 +model=nfet_03v3 +spiceprefix=X +} +C {ipin.sym} 120 -460 0 0 {name=p1 lab=v_in +} +C {iopin.sym} 80 -40 2 0 {name=p3 lab=vss +} +C {opin.sym} 330 -470 0 0 {name=p4 lab=v_out} +C {symbols/nfet_03v3.sym} 430 -130 0 0 {name=M1 +L=1u +W=4u +nf=1 +m=4 +ad="'int((nf+1)/2) * W/nf * 0.18u'" +pd="'2*int((nf+1)/2) * (W/nf + 0.18u)'" +as="'int((nf+2)/2) * W/nf * 0.18u'" +ps="'2*int((nf+2)/2) * (W/nf + 0.18u)'" +nrd="'0.18u / W'" nrs="'0.18u / W'" +sa=0 sb=0 sd=0 +model=nfet_03v3 +spiceprefix=X +} diff --git a/blocks/composite/regulated_cascoded_cmirror/A3_core/biased_cm/biased_cm.sym b/blocks/composite/regulated_cascoded_cmirror/A3_core/biased_cm/biased_cm.sym new file mode 100644 index 00000000..df0161b1 --- /dev/null +++ b/blocks/composite/regulated_cascoded_cmirror/A3_core/biased_cm/biased_cm.sym @@ -0,0 +1,42 @@ +v {xschem version=3.4.7 file_version=1.2} +G {} +K {type=subcircuit +format="@name @pinlist @symname" +template="name=x1" +} +V {} +S {} +E {} +L 4 100 -40 120 -40 {} +L 4 -120 -40 -100 -40 {} +L 4 -100 -40 -50 -40 {} +L 4 -50 -40 -50 -20 {} +L 4 -50 -40 -50 -10 {} +L 4 -50 -10 -30 -10 {} +L 4 -30 -10 -30 10 {} +L 4 -50 10 -30 10 {} +L 4 -50 10 -50 30 {} +L 4 -50 -40 0 -40 {} +L 4 -20 -10 -20 10 {} +L 4 -20 0 0 0 {} +L 4 0 -40 0 0 {} +L 4 50 -40 50 -20 {} +L 4 50 -40 50 -10 {} +L 4 30 -10 50 -10 {} +L 4 30 -10 30 10 {} +L 4 30 10 50 10 {} +L 4 50 10 50 30 {} +L 4 20 -10 20 10 {} +L 4 0 0 20 0 {} +L 4 50 -40 100 -40 {} +L 4 -50 30 50 30 {} +L 7 0 30 0 50 {} +B 4 -110 -70 110 50 {fill=False} +B 5 117.5 -42.5 122.5 -37.5 {name=v_out dir=out} +B 5 -122.5 -42.5 -117.5 -37.5 {name=v_in dir=in} +B 5 -2.5 47.5 2.5 52.5 {name=vss dir=inout} +T {@symname} -38.5 -66 0 0 0.3 0.3 {} +T {@name} 65 -92 0 0 0.2 0.2 {} +T {v_out} 95 -34 0 1 0.2 0.2 {} +T {v_in} -95 -34 0 0 0.2 0.2 {} +T {vss} 4 25 1 1 0.2 0.2 {} diff --git a/blocks/composite/regulated_cascoded_cmirror/A3_core/cascode_cm/cascode_cm.sch b/blocks/composite/regulated_cascoded_cmirror/A3_core/cascode_cm/cascode_cm.sch new file mode 100644 index 00000000..b06b1185 --- /dev/null +++ b/blocks/composite/regulated_cascoded_cmirror/A3_core/cascode_cm/cascode_cm.sch @@ -0,0 +1,183 @@ +v {xschem version=3.4.7 file_version=1.2} +G {} +K {} +V {} +S {} +E {} +N 170 -190 170 -70 {lab=vss} +N 230 -260 270 -260 {lab=#net1} +N 170 -610 170 -590 {lab=v_aux} +N 110 -260 170 -260 {lab=vss} +N 110 -260 110 -220 {lab=vss} +N 210 -260 230 -260 {lab=#net1} +N 170 -230 170 -220 {lab=vss} +N 170 -620 170 -610 {lab=v_aux} +N 170 -220 170 -190 {lab=vss} +N 170 -360 340 -360 {lab=v_aux} +N 170 -360 170 -290 {lab=v_aux} +N 380 -330 380 -170 {lab=#net1} +N 270 -260 380 -260 {lab=#net1} +N 170 -510 170 -360 {lab=v_aux} +N 380 -110 380 -70 {lab=vss} +N 170 -70 380 -70 {lab=vss} +N 870 -430 870 -310 {lab=v_aux} +N 770 -240 810 -240 {lab=#net2} +N 870 -240 930 -240 {lab=vss} +N 810 -240 830 -240 {lab=#net2} +N 870 -280 870 -270 {lab=v_aux} +N 870 -310 870 -280 {lab=v_aux} +N 870 -210 870 -140 {lab=vss} +N 660 -330 660 -170 {lab=#net2} +N 660 -240 770 -240 {lab=#net2} +N 660 -430 660 -390 {lab=v_out} +N 660 -110 660 -70 {lab=vss} +N 700 -360 870 -360 {lab=v_aux} +N 420 -140 620 -140 {lab=v_in} +N 380 -600 380 -390 {lab=v_in} +N 380 -440 510 -440 {lab=v_in} +N 510 -440 510 -140 {lab=v_in} +N 870 -610 870 -430 {lab=v_aux} +N 200 -610 870 -610 {lab=v_aux} +N 170 -610 200 -610 {lab=v_aux} +N 170 -590 170 -510 {lab=v_aux} +N 380 -690 380 -600 {lab=v_in} +N 170 -710 170 -620 {lab=v_aux} +N 380 -710 380 -690 {lab=v_in} +N 870 -140 870 -70 {lab=vss} +N 660 -70 870 -70 {lab=vss} +N 370 -70 660 -70 {lab=vss} +N 870 -70 930 -70 {lab=vss} +N 380 -360 400 -360 {lab=vss} +N 350 -140 380 -140 {lab=vss} +N 350 -140 350 -70 {lab=vss} +N 660 -140 690 -140 {lab=vss} +N 690 -140 690 -70 {lab=vss} +N 620 -360 660 -360 {lab=vss} +N 930 -240 930 -70 {lab=vss} +N 110 -220 170 -220 {lab=vss} +N 320 -740 340 -740 {lab=v_in} +N 110 -740 130 -740 {lab=v_aux} +N 400 -360 440 -360 {lab=vss} +N 440 -360 440 -70 {lab=vss} +N 570 -360 620 -360 {lab=vss} +N 570 -360 570 -80 {lab=vss} +N 570 -80 570 -70 {lab=vss} +N 130 -740 170 -740 {lab=v_aux} +N 170 -740 170 -720 {lab=v_aux} +N 170 -720 170 -710 {lab=v_aux} +N 380 -740 380 -710 {lab=v_in} +N 340 -740 380 -740 {lab=v_in} +N 660 -770 880 -770 {lab=v_out} +N 660 -770 660 -430 {lab=v_out} +N 1040 -90 1040 -70 {lab=vss} +N 930 -70 1040 -70 {lab=vss} +N 1000 -120 1000 -70 {lab=vss} +N 1040 -150 1070 -150 {lab=vss} +N 1070 -150 1070 -70 {lab=vss} +N 1040 -70 1070 -70 {lab=vss} +N 1040 -120 1070 -120 {lab=vss} +C {symbols/nfet_03v3.sym} 190 -260 0 1 {name=M10 +L=1u +W=8u +nf=2 +m=1 +ad="'int((nf+1)/2) * W/nf * 0.18u'" +pd="'2*int((nf+1)/2) * (W/nf + 0.18u)'" +as="'int((nf+2)/2) * W/nf * 0.18u'" +ps="'2*int((nf+2)/2) * (W/nf + 0.18u)'" +nrd="'0.18u / W'" nrs="'0.18u / W'" +sa=0 sb=0 sd=0 +model=nfet_03v3 +spiceprefix=X +} +C {symbols/nfet_03v3.sym} 360 -360 0 0 {name=M8 +L=1u +W=8u +nf=2 +m=1 +ad="'int((nf+1)/2) * W/nf * 0.18u'" +pd="'2*int((nf+1)/2) * (W/nf + 0.18u)'" +as="'int((nf+2)/2) * W/nf * 0.18u'" +ps="'2*int((nf+2)/2) * (W/nf + 0.18u)'" +nrd="'0.18u / W'" nrs="'0.18u / W'" +sa=0 sb=0 sd=0 +model=nfet_03v3 +spiceprefix=X +} +C {symbols/nfet_03v3.sym} 400 -140 0 1 {name=M11 +L=1u +W=8u +nf=2 +m=1 +ad="'int((nf+1)/2) * W/nf * 0.18u'" +pd="'2*int((nf+1)/2) * (W/nf + 0.18u)'" +as="'int((nf+2)/2) * W/nf * 0.18u'" +ps="'2*int((nf+2)/2) * (W/nf + 0.18u)'" +nrd="'0.18u / W'" nrs="'0.18u / W'" +sa=0 sb=0 sd=0 +model=nfet_03v3 +spiceprefix=X +} +C {symbols/nfet_03v3.sym} 850 -240 0 0 {name=M12 +L=1u +W=8u +nf=2 +m=1 +ad="'int((nf+1)/2) * W/nf * 0.18u'" +pd="'2*int((nf+1)/2) * (W/nf + 0.18u)'" +as="'int((nf+2)/2) * W/nf * 0.18u'" +ps="'2*int((nf+2)/2) * (W/nf + 0.18u)'" +nrd="'0.18u / W'" nrs="'0.18u / W'" +sa=0 sb=0 sd=0 +model=nfet_03v3 +spiceprefix=X +} +C {symbols/nfet_03v3.sym} 640 -140 0 0 {name=M13 +L=1u +W=8u +nf=2 +m=1 +ad="'int((nf+1)/2) * W/nf * 0.18u'" +pd="'2*int((nf+1)/2) * (W/nf + 0.18u)'" +as="'int((nf+2)/2) * W/nf * 0.18u'" +ps="'2*int((nf+2)/2) * (W/nf + 0.18u)'" +nrd="'0.18u / W'" nrs="'0.18u / W'" +sa=0 sb=0 sd=0 +model=nfet_03v3 +spiceprefix=X +} +C {symbols/nfet_03v3.sym} 680 -360 0 1 {name=M14 +L=1u +W=8u +nf=2 +m=1 +ad="'int((nf+1)/2) * W/nf * 0.18u'" +pd="'2*int((nf+1)/2) * (W/nf + 0.18u)'" +as="'int((nf+2)/2) * W/nf * 0.18u'" +ps="'2*int((nf+2)/2) * (W/nf + 0.18u)'" +nrd="'0.18u / W'" nrs="'0.18u / W'" +sa=0 sb=0 sd=0 +model=nfet_03v3 +spiceprefix=X +} +C {ipin.sym} 320 -740 0 0 {name=p1 lab=v_in +} +C {iopin.sym} 510 -70 1 0 {name=p3 lab=vss +} +C {ipin.sym} 110 -740 0 0 {name=p4 lab=v_aux +} +C {opin.sym} 880 -770 0 0 {name=p5 lab=v_out} +C {symbols/nfet_03v3.sym} 1020 -120 0 0 {name=M1 +L=1u +W=4u +nf=1 +m=6 +ad="'int((nf+1)/2) * W/nf * 0.18u'" +pd="'2*int((nf+1)/2) * (W/nf + 0.18u)'" +as="'int((nf+2)/2) * W/nf * 0.18u'" +ps="'2*int((nf+2)/2) * (W/nf + 0.18u)'" +nrd="'0.18u / W'" nrs="'0.18u / W'" +sa=0 sb=0 sd=0 +model=nfet_03v3 +spiceprefix=X +} diff --git a/blocks/composite/regulated_cascoded_cmirror/A3_core/cascode_cm/cascode_cm.sym b/blocks/composite/regulated_cascoded_cmirror/A3_core/cascode_cm/cascode_cm.sym new file mode 100644 index 00000000..4407c3e8 --- /dev/null +++ b/blocks/composite/regulated_cascoded_cmirror/A3_core/cascode_cm/cascode_cm.sym @@ -0,0 +1,45 @@ +v {xschem version=3.4.7 file_version=1.2} +G {} +K {type=subcircuit +format="@name @pinlist @symname" +template="name=x1" +} +V {} +S {} +E {} +L 4 100 -40 120 -40 {} +L 4 -120 0 -100 0 {} +L 4 -120 -40 -100 -40 {} +L 4 -100 -40 -50 -40 {} +L 4 -50 -40 -50 -20 {} +L 4 -50 -40 -50 -10 {} +L 4 -50 -10 -30 -10 {} +L 4 -30 -10 -30 10 {} +L 4 -50 10 -30 10 {} +L 4 -50 10 -50 30 {} +L 4 -50 -40 0 -40 {} +L 4 -20 -10 -20 10 {} +L 4 -20 0 0 0 {} +L 4 0 -40 0 0 {} +L 4 50 -40 50 -20 {} +L 4 50 -40 50 -10 {} +L 4 30 -10 50 -10 {} +L 4 30 -10 30 10 {} +L 4 30 10 50 10 {} +L 4 50 10 50 30 {} +L 4 20 -10 20 10 {} +L 4 0 0 20 0 {} +L 4 50 -40 100 -40 {} +L 4 -50 30 50 30 {} +L 7 0 30 0 50 {} +B 4 -110 -70 110 50 {fill=False} +B 5 117.5 -42.5 122.5 -37.5 {name=v_out dir=out} +B 5 -122.5 -2.5 -117.5 2.5 {name=v_aux dir=in} +B 5 -122.5 -42.5 -117.5 -37.5 {name=v_in dir=in} +B 5 -2.5 47.5 2.5 52.5 {name=vss dir=inout} +T {@symname} -33 -66 0 0 0.3 0.3 {} +T {@name} 65 -92 0 0 0.2 0.2 {} +T {v_out} 95 -34 0 1 0.2 0.2 {} +T {v_aux} -95 -4 0 0 0.2 0.2 {} +T {v_in} -95 -34 0 0 0.2 0.2 {} +T {vss} 4 25 1 1 0.2 0.2 {} diff --git a/blocks/composite/regulated_cascoded_cmirror/A3_core/top_level/top_level.sch b/blocks/composite/regulated_cascoded_cmirror/A3_core/top_level/top_level.sch new file mode 100644 index 00000000..882f09b0 --- /dev/null +++ b/blocks/composite/regulated_cascoded_cmirror/A3_core/top_level/top_level.sch @@ -0,0 +1,336 @@ +v {xschem version=3.4.7 file_version=1.2} +G {} +K {} +V {} +S {} +E {} +N -20 -910 0 -910 {lab=VDD} +N 510 -910 510 -740 {lab=VDD} +N 740 -910 740 -740 {lab=VDD} +N 630 -910 630 -850 {lab=VDD} +N 550 -710 700 -710 {lab=#net1} +N 630 -790 630 -710 {lab=#net1} +N 550 -590 700 -590 {lab=V_IN} +N 510 -680 510 -620 {lab=#net1} +N 740 -680 740 -620 {lab=#net2} +N 630 -710 630 -650 {lab=#net1} +N 510 -650 630 -650 {lab=#net1} +N 1010 -910 1010 -740 {lab=VDD} +N 870 -910 870 -850 {lab=VDD} +N 1120 -910 1120 -850 {lab=VDD} +N 740 -560 740 -470 {lab=#net3} +N 980 -470 2020 -470 {lab=V_OUT_VCM} +N 1010 -560 1010 -340 {lab=#net4} +N 1250 -340 2030 -340 {lab=V_OUT_BCM} +N 1350 -560 1350 -240 {lab=#net5} +N 1350 -910 1350 -740 {lab=VDD} +N 1350 -680 1350 -620 {lab=#net6} +N 630 -760 1310 -760 {lab=#net1} +N 1310 -760 1310 -710 {lab=#net1} +N 910 -710 970 -710 {lab=#net1} +N 910 -760 910 -710 {lab=#net1} +N 1010 -680 1010 -620 {lab=#net7} +N 870 -790 870 -760 {lab=#net1} +N 1120 -790 1120 -760 {lab=#net1} +N 1080 -880 1080 -820 {lab=EN} +N -20 -880 1080 -880 {lab=EN} +N 550 -820 590 -820 {lab=EN} +N 550 -880 550 -820 {lab=EN} +N 790 -820 830 -820 {lab=EN} +N 790 -880 790 -820 {lab=EN} +N 1310 -650 1310 -590 {lab=V_IN} +N 660 -650 660 -590 {lab=V_IN} +N 660 -650 1310 -650 {lab=V_IN} +N 920 -590 970 -590 {lab=V_IN} +N 920 -650 920 -590 {lab=V_IN} +N 1590 -240 2040 -240 {lab=V_OUT_CCM} +N 620 -200 1350 -200 {lab=#net8} +N 1120 -910 1350 -910 {lab=VDD} +N 1010 -910 1120 -910 {lab=VDD} +N 870 -910 1010 -910 {lab=VDD} +N 740 -910 870 -910 {lab=VDD} +N 630 -910 740 -910 {lab=VDD} +N 510 -910 630 -910 {lab=VDD} +N 160 -910 510 -910 {lab=VDD} +N 1470 -150 1470 -70 {lab=VSS} +N 1130 -250 1130 -70 {lab=VSS} +N 860 -380 860 -70 {lab=VSS} +N -20 -520 510 -520 {lab=V_IN} +N 510 -520 630 -520 {lab=V_IN} +N 630 -590 630 -520 {lab=V_IN} +N 510 -560 510 -520 {lab=V_IN} +N -30 -50 1470 -50 {lab=VSS} +N 1470 -70 1470 -50 {lab=VSS} +N 1130 -70 1130 -50 {lab=VSS} +N 860 -70 860 -50 {lab=VSS} +N 500 -110 500 -50 {lab=VSS} +N 340 -200 380 -200 {lab=V_AUX_CCM} +N 330 -220 380 -220 {lab=EN} +N 330 -880 330 -220 {lab=EN} +N -10 -200 340 -200 {lab=V_AUX_CCM} +N 500 -260 500 -230 {lab=VDD} +N 1610 -910 1610 -740 {lab=VDD} +N 1610 -680 1610 -620 {lab=#net9} +N 1570 -760 1570 -710 {lab=#net1} +N 1570 -650 1570 -590 {lab=V_IN} +N 1300 -760 1570 -760 {lab=#net1} +N 1310 -650 1570 -650 {lab=V_IN} +N 1350 -910 1610 -910 {lab=VDD} +N 1470 -790 1470 -760 {lab=#net1} +N 1470 -910 1470 -850 {lab=VDD} +N 1080 -880 1430 -880 {lab=EN} +N 1430 -880 1430 -820 {lab=EN} +N 1610 -560 2020 -560 {lab=V_OUT_VIN} +N 1610 -910 1710 -910 {lab=VDD} +N 1710 -910 1710 -870 {lab=VDD} +N 1670 -910 1670 -840 {lab=VDD} +N 1710 -810 1730 -810 {lab=VDD} +N 1730 -910 1730 -810 {lab=VDD} +N 1710 -910 1730 -910 {lab=VDD} +N 1710 -840 1730 -840 {lab=VDD} +C {iopin.sym} -30 -50 2 0 {name=p1 lab=VSS +} +C {ipin.sym} -10 -200 0 0 {name=p3 lab=V_AUX_CCM +} +C {iopin.sym} -20 -910 2 0 {name=p4 lab=VDD +} +C {opin.sym} 2020 -470 0 0 {name=p5 lab=V_OUT_VCM} +C {opin.sym} 2030 -340 0 0 {name=p6 lab=V_OUT_BCM} +C {opin.sym} 2040 -240 0 0 {name=p7 lab=V_OUT_CCM} +C {ipin.sym} -20 -520 0 0 {name=p9 lab=V_IN +} +C {symbols/pfet_03v3.sym} 530 -710 0 1 {name=M1 +L=2.0u +W=10.0u +nf=1 +m=1 +ad="'int((nf+1)/2) * W/nf * 0.18u'" +pd="'2*int((nf+1)/2) * (W/nf + 0.18u)'" +as="'int((nf+2)/2) * W/nf * 0.18u'" +ps="'2*int((nf+2)/2) * (W/nf + 0.18u)'" +nrd="'0.18u / W'" nrs="'0.18u / W'" +sa=0 sb=0 sd=0 +model=pfet_03v3 +spiceprefix=X +} +C {symbols/pfet_03v3.sym} 530 -590 0 1 {name=M2 +L=2.0u +W=10.0u +nf=1 +m=1 +ad="'int((nf+1)/2) * W/nf * 0.18u'" +pd="'2*int((nf+1)/2) * (W/nf + 0.18u)'" +as="'int((nf+2)/2) * W/nf * 0.18u'" +ps="'2*int((nf+2)/2) * (W/nf + 0.18u)'" +nrd="'0.18u / W'" nrs="'0.18u / W'" +sa=0 sb=0 sd=0 +model=pfet_03v3 +spiceprefix=X +} +C {symbols/pfet_03v3.sym} 720 -710 0 0 {name=M3 +L=2.0u +W=10.0u +nf=1 +m=1 +ad="'int((nf+1)/2) * W/nf * 0.18u'" +pd="'2*int((nf+1)/2) * (W/nf + 0.18u)'" +as="'int((nf+2)/2) * W/nf * 0.18u'" +ps="'2*int((nf+2)/2) * (W/nf + 0.18u)'" +nrd="'0.18u / W'" nrs="'0.18u / W'" +sa=0 sb=0 sd=0 +model=pfet_03v3 +spiceprefix=X +} +C {symbols/pfet_03v3.sym} 720 -590 0 0 {name=M4 +L=2.0u +W=10.0u +nf=1 +m=1 +ad="'int((nf+1)/2) * W/nf * 0.18u'" +pd="'2*int((nf+1)/2) * (W/nf + 0.18u)'" +as="'int((nf+2)/2) * W/nf * 0.18u'" +ps="'2*int((nf+2)/2) * (W/nf + 0.18u)'" +nrd="'0.18u / W'" nrs="'0.18u / W'" +sa=0 sb=0 sd=0 +model=pfet_03v3 +spiceprefix=X +} +C {symbols/pfet_03v3.sym} 990 -710 0 0 {name=M5 +L=2.0u +W=10.0u +nf=1 +m=1 +ad="'int((nf+1)/2) * W/nf * 0.18u'" +pd="'2*int((nf+1)/2) * (W/nf + 0.18u)'" +as="'int((nf+2)/2) * W/nf * 0.18u'" +ps="'2*int((nf+2)/2) * (W/nf + 0.18u)'" +nrd="'0.18u / W'" nrs="'0.18u / W'" +sa=0 sb=0 sd=0 +model=pfet_03v3 +spiceprefix=X +} +C {symbols/pfet_03v3.sym} 990 -590 0 0 {name=M6 +L=2.0u +W=10.0u +nf=1 +m=1 +ad="'int((nf+1)/2) * W/nf * 0.18u'" +pd="'2*int((nf+1)/2) * (W/nf + 0.18u)'" +as="'int((nf+2)/2) * W/nf * 0.18u'" +ps="'2*int((nf+2)/2) * (W/nf + 0.18u)'" +nrd="'0.18u / W'" nrs="'0.18u / W'" +sa=0 sb=0 sd=0 +model=pfet_03v3 +spiceprefix=X +} +C {symbols/pfet_03v3.sym} 1330 -710 0 0 {name=M7 +L=2.0u +W=10.0u +nf=1 +m=1 +ad="'int((nf+1)/2) * W/nf * 0.18u'" +pd="'2*int((nf+1)/2) * (W/nf + 0.18u)'" +as="'int((nf+2)/2) * W/nf * 0.18u'" +ps="'2*int((nf+2)/2) * (W/nf + 0.18u)'" +nrd="'0.18u / W'" nrs="'0.18u / W'" +sa=0 sb=0 sd=0 +model=pfet_03v3 +spiceprefix=X +} +C {symbols/pfet_03v3.sym} 1330 -590 0 0 {name=M8 +L=2.0u +W=10.0u +nf=1 +m=1 +ad="'int((nf+1)/2) * W/nf * 0.18u'" +pd="'2*int((nf+1)/2) * (W/nf + 0.18u)'" +as="'int((nf+2)/2) * W/nf * 0.18u'" +ps="'2*int((nf+2)/2) * (W/nf + 0.18u)'" +nrd="'0.18u / W'" nrs="'0.18u / W'" +sa=0 sb=0 sd=0 +model=pfet_03v3 +spiceprefix=X +} +C {symbols/pfet_03v3.sym} 850 -820 0 0 {name=M14 +L=2.0u +W=10.0u +nf=1 +m=1 +ad="'int((nf+1)/2) * W/nf * 0.18u'" +pd="'2*int((nf+1)/2) * (W/nf + 0.18u)'" +as="'int((nf+2)/2) * W/nf * 0.18u'" +ps="'2*int((nf+2)/2) * (W/nf + 0.18u)'" +nrd="'0.18u / W'" nrs="'0.18u / W'" +sa=0 sb=0 sd=0 +model=pfet_03v3 +spiceprefix=X +} +C {symbols/pfet_03v3.sym} 610 -820 0 0 {name=M18 +L=2.0u +W=10.0u +nf=1 +m=1 +ad="'int((nf+1)/2) * W/nf * 0.18u'" +pd="'2*int((nf+1)/2) * (W/nf + 0.18u)'" +as="'int((nf+2)/2) * W/nf * 0.18u'" +ps="'2*int((nf+2)/2) * (W/nf + 0.18u)'" +nrd="'0.18u / W'" nrs="'0.18u / W'" +sa=0 sb=0 sd=0 +model=pfet_03v3 +spiceprefix=X +} +C {lab_pin.sym} 0 -910 2 0 {name=p10 sig_type=std_logic lab=VDD} +C {lab_pin.sym} 160 -910 0 0 {name=p11 sig_type=std_logic lab=VDD} +C {ipin.sym} -20 -880 0 0 {name=p12 lab=EN +} +C {symbols/pfet_03v3.sym} 1100 -820 0 0 {name=M15 +L=2.0u +W=10.0u +nf=1 +m=1 +ad="'int((nf+1)/2) * W/nf * 0.18u'" +pd="'2*int((nf+1)/2) * (W/nf + 0.18u)'" +as="'int((nf+2)/2) * W/nf * 0.18u'" +ps="'2*int((nf+2)/2) * (W/nf + 0.18u)'" +nrd="'0.18u / W'" nrs="'0.18u / W'" +sa=0 sb=0 sd=0 +model=pfet_03v3 +spiceprefix=X +} +C {lab_pin.sym} 630 -820 2 0 {name=p2 sig_type=std_logic lab=VDD} +C {lab_pin.sym} 870 -820 2 0 {name=p8 sig_type=std_logic lab=VDD} +C {lab_pin.sym} 1120 -820 2 0 {name=p13 sig_type=std_logic lab=VDD} +C {lab_pin.sym} 1010 -710 2 0 {name=p14 sig_type=std_logic lab=VDD} +C {lab_pin.sym} 740 -710 2 0 {name=p15 sig_type=std_logic lab=VDD} +C {lab_pin.sym} 510 -710 0 0 {name=p16 sig_type=std_logic lab=VDD} +C {lab_pin.sym} 510 -590 0 0 {name=p17 sig_type=std_logic lab=VDD} +C {lab_pin.sym} 740 -590 2 0 {name=p18 sig_type=std_logic lab=VDD} +C {lab_pin.sym} 1010 -590 2 0 {name=p19 sig_type=std_logic lab=VDD} +C {lab_pin.sym} 1350 -710 2 0 {name=p20 sig_type=std_logic lab=VDD} +C {lab_pin.sym} 1350 -590 2 0 {name=p21 sig_type=std_logic lab=VDD} +C {lab_pin.sym} 500 -260 0 0 {name=p22 sig_type=std_logic lab=VDD} +C {symbols/pfet_03v3.sym} 1590 -710 0 0 {name=M9 +L=2.0u +W=10.0u +nf=1 +m=1 +ad="'int((nf+1)/2) * W/nf * 0.18u'" +pd="'2*int((nf+1)/2) * (W/nf + 0.18u)'" +as="'int((nf+2)/2) * W/nf * 0.18u'" +ps="'2*int((nf+2)/2) * (W/nf + 0.18u)'" +nrd="'0.18u / W'" nrs="'0.18u / W'" +sa=0 sb=0 sd=0 +model=pfet_03v3 +spiceprefix=X +} +C {symbols/pfet_03v3.sym} 1590 -590 0 0 {name=M10 +L=2.0u +W=10.0u +nf=1 +m=1 +ad="'int((nf+1)/2) * W/nf * 0.18u'" +pd="'2*int((nf+1)/2) * (W/nf + 0.18u)'" +as="'int((nf+2)/2) * W/nf * 0.18u'" +ps="'2*int((nf+2)/2) * (W/nf + 0.18u)'" +nrd="'0.18u / W'" nrs="'0.18u / W'" +sa=0 sb=0 sd=0 +model=pfet_03v3 +spiceprefix=X +} +C {lab_pin.sym} 1610 -710 2 0 {name=p23 sig_type=std_logic lab=VDD} +C {lab_pin.sym} 1610 -590 2 0 {name=p24 sig_type=std_logic lab=VDD} +C {symbols/pfet_03v3.sym} 1450 -820 0 0 {name=M11 +L=2.0u +W=10.0u +nf=1 +m=1 +ad="'int((nf+1)/2) * W/nf * 0.18u'" +pd="'2*int((nf+1)/2) * (W/nf + 0.18u)'" +as="'int((nf+2)/2) * W/nf * 0.18u'" +ps="'2*int((nf+2)/2) * (W/nf + 0.18u)'" +nrd="'0.18u / W'" nrs="'0.18u / W'" +sa=0 sb=0 sd=0 +model=pfet_03v3 +spiceprefix=X +} +C {opin.sym} 2020 -560 0 0 {name=p25 lab=V_OUT_VIN +} +C {lab_pin.sym} 1470 -820 2 0 {name=p26 sig_type=std_logic lab=VDD} +C {symbols/pfet_03v3.sym} 1690 -840 0 0 {name=M12 +L=2.0u +W=10.0u +nf=1 +m=6 +ad="'int((nf+1)/2) * W/nf * 0.18u'" +pd="'2*int((nf+1)/2) * (W/nf + 0.18u)'" +as="'int((nf+2)/2) * W/nf * 0.18u'" +ps="'2*int((nf+2)/2) * (W/nf + 0.18u)'" +nrd="'0.18u / W'" nrs="'0.18u / W'" +sa=0 sb=0 sd=0 +model=pfet_03v3 +spiceprefix=X +} +C {bias/bias.sym} 500 -160 0 0 {name=x4} +C {vanilla_cm/vanilla_cm.sym} 860 -430 0 0 {name=x1} +C {biased_cm/biased_cm.sym} 1130 -300 0 0 {name=x2} +C {cascode_cm/cascode_cm.sym} 1470 -200 0 0 {name=x3} diff --git a/blocks/composite/regulated_cascoded_cmirror/A3_core/top_level/top_level.sym b/blocks/composite/regulated_cascoded_cmirror/A3_core/top_level/top_level.sym new file mode 100644 index 00000000..ebc794c7 --- /dev/null +++ b/blocks/composite/regulated_cascoded_cmirror/A3_core/top_level/top_level.sym @@ -0,0 +1,88 @@ +v {xschem version=3.4.7 file_version=1.2} +G {} +K {type=subcircuit +format="@name @pinlist @symname" +template="name=x1" +} +V {} +S {} +E {} +L 4 -240 -80 -220 -80 {} +L 4 -240 -40 -220 -40 {} +L 4 180 -60 200 -60 {} +L 4 180 -40 200 -40 {} +L 4 180 -20 200 -20 {} +L 4 -240 10 -220 10 {} +L 4 -100 20 -100 100 {} +L 4 -70 20 -70 100 {} +L 4 -40 20 -40 100 {} +L 4 -40 -40 -40 -10 {} +L 4 -100 100 -40 100 {} +L 4 -70 -20 -70 -10 {} +L 4 -160 -60 -40 -60 {} +L 4 -40 -60 -40 -40 {} +L 4 100 20 100 100 {} +L 4 40 100 100 100 {} +L 4 70 20 70 100 {} +L 4 40 20 40 100 {} +L 4 40 -40 40 -10 {} +L 4 70 -20 70 -10 {} +L 4 40 -60 40 -40 {} +L 4 40 -60 110 -60 {} +L 4 70 -40 110 -40 {} +L 4 70 -40 70 -20 {} +L 4 100 -20 100 -10 {} +L 4 100 -20 110 -20 {} +L 4 -70 -40 -70 -20 {} +L 4 -170 -40 -70 -40 {} +L 4 -100 -20 -100 -10 {} +L 4 -170 -20 -100 -20 {} +L 4 -170 -60 -160 -60 {} +L 4 -170 -60 -170 -20 {} +L 4 -190 -40 -170 -40 {} +L 4 -240 -110 -240 110 {} +L 4 200 -110 200 110 {} +L 4 -240 -110 200 -110 {} +L 4 -240 110 200 110 {} +L 4 180 -80 200 -80 {} +L 7 0 -110 0 -90 {} +L 7 0 90 0 110 {} +B 5 -2.5 -112.5 2.5 -107.5 {name=VDD dir=inout} +B 5 -242.5 -82.5 -237.5 -77.5 {name=EN dir=in} +B 5 -242.5 -42.5 -237.5 -37.5 {name=V_IN dir=in} +B 5 197.5 -62.5 202.5 -57.5 {name=V_OUT_VCM dir=out} +B 5 197.5 -42.5 202.5 -37.5 {name=V_OUT_BCM dir=out} +B 5 197.5 -22.5 202.5 -17.5 {name=V_OUT_CCM dir=out} +B 5 -242.5 7.5 -237.5 12.5 {name=V_AUX_CCM dir=in} +B 5 -2.5 107.5 2.5 112.5 {name=VSS dir=inout} +B 5 197.5 -82.5 202.5 -77.5 {name=V_OUT_VIN dir=out} +A 4 -100 0 10 270 360 {} +A 4 -100 10 10 270 360 {} +A 4 -70 0 10 270 360 {} +A 4 -70 10 10 270 360 {} +A 4 -40 0 10 270 360 {} +A 4 -40 10 10 270 360 {} +A 4 100 0 10 270 360 {} +A 4 100 10 10 270 360 {} +A 4 70 0 10 270 360 {} +A 4 70 10 10 270 360 {} +A 4 40 0 10 270 360 {} +A 4 40 10 10 270 360 {} +T {@symname} -228.5 -136 0 0 0.3 0.3 {} +T {@name} 155 -142 0 0 0.2 0.2 {} +T {VDD} -4 -85 3 1 0.2 0.2 {} +T {EN} -215 -84 0 0 0.2 0.2 {} +T {V_IN} -215 -44 0 0 0.2 0.2 {} +T {V_OUT_VCM} 175 -64 0 1 0.2 0.2 {} +T {V_OUT_BCM} 175 -44 0 1 0.2 0.2 {} +T {V_OUT_CCM} 175 -24 0 1 0.2 0.2 {} +T {V_AUX_CCM} -215 6 0 0 0.2 0.2 {} +T {VSS} 4 85 1 1 0.2 0.2 {} +T {3} -100 20 0 0 0.4 0.4 {} +T {2} -70 20 0 0 0.4 0.4 {} +T {1} -40 20 0 0 0.4 0.4 {} +T {3} 100 20 0 0 0.4 0.4 {} +T {2} 70 20 0 0 0.4 0.4 {} +T {1} 40 20 0 0 0.4 0.4 {} +T {V_OUT_VCM} 175 -64 0 1 0.2 0.2 {} +T {V_OUT_VIN} 175 -84 0 1 0.2 0.2 {} diff --git a/blocks/composite/regulated_cascoded_cmirror/A3_core/vanilla_cm/vanilla_cm.sch b/blocks/composite/regulated_cascoded_cmirror/A3_core/vanilla_cm/vanilla_cm.sch new file mode 100644 index 00000000..1e463242 --- /dev/null +++ b/blocks/composite/regulated_cascoded_cmirror/A3_core/vanilla_cm/vanilla_cm.sch @@ -0,0 +1,85 @@ +v {xschem version=3.4.7 file_version=1.2} +G {} +K {} +V {} +S {} +E {} +N 300 -50 300 -30 {lab=vss} +N 300 -120 340 -120 {lab=vss} +N 340 -120 340 -70 {lab=vss} +N 300 -70 340 -70 {lab=vss} +N 220 -120 260 -120 {lab=v_in} +N 160 -170 160 -150 {lab=v_in} +N 160 -170 220 -170 {lab=v_in} +N 220 -170 220 -120 {lab=v_in} +N 160 -290 160 -170 {lab=v_in} +N 160 -80 160 -30 {lab=vss} +N 100 -120 160 -120 {lab=vss} +N 100 -120 100 -80 {lab=vss} +N 100 -80 160 -80 {lab=vss} +N 300 -240 300 -150 {lab=v_out} +N 300 -90 300 -70 {lab=vss} +N 200 -120 220 -120 {lab=v_in} +N 160 -90 160 -80 {lab=vss} +N 300 -70 300 -50 {lab=vss} +N 160 -30 300 -30 {lab=vss} +N 300 -270 300 -240 {lab=v_out} +N 110 -290 130 -290 {lab=v_in} +N 130 -290 160 -290 {lab=v_in} +N 60 -30 160 -30 {lab=vss} +N 300 -290 320 -290 {lab=v_out} +N 300 -290 300 -270 {lab=v_out} +N 440 -90 440 -30 {lab=vss} +N 300 -30 440 -30 {lab=vss} +N 400 -120 400 -30 {lab=vss} +N 440 -150 470 -150 {lab=vss} +N 470 -150 470 -30 {lab=vss} +N 440 -30 470 -30 {lab=vss} +N 440 -120 470 -120 {lab=vss} +C {symbols/nfet_03v3.sym} 280 -120 0 0 {name=M1 +L=1u +W=4u +nf=1 +m=1 +ad="'int((nf+1)/2) * W/nf * 0.18u'" +pd="'2*int((nf+1)/2) * (W/nf + 0.18u)'" +as="'int((nf+2)/2) * W/nf * 0.18u'" +ps="'2*int((nf+2)/2) * (W/nf + 0.18u)'" +nrd="'0.18u / W'" nrs="'0.18u / W'" +sa=0 sb=0 sd=0 +model=nfet_03v3 +spiceprefix=X +} +C {symbols/nfet_03v3.sym} 180 -120 0 1 {name=M2 +L=1u +W=4u +nf=1 +m=1 +ad="'int((nf+1)/2) * W/nf * 0.18u'" +pd="'2*int((nf+1)/2) * (W/nf + 0.18u)'" +as="'int((nf+2)/2) * W/nf * 0.18u'" +ps="'2*int((nf+2)/2) * (W/nf + 0.18u)'" +nrd="'0.18u / W'" nrs="'0.18u / W'" +sa=0 sb=0 sd=0 +model=nfet_03v3 +spiceprefix=X +} +C {ipin.sym} 110 -290 0 0 {name=p1 lab=v_in +} +C {iopin.sym} 60 -30 2 0 {name=p3 lab=vss +} +C {opin.sym} 320 -290 0 0 {name=p4 lab=v_out} +C {symbols/nfet_03v3.sym} 420 -120 0 0 {name=M3 +L=1u +W=4u +nf=1 +m=2 +ad="'int((nf+1)/2) * W/nf * 0.18u'" +pd="'2*int((nf+1)/2) * (W/nf + 0.18u)'" +as="'int((nf+2)/2) * W/nf * 0.18u'" +ps="'2*int((nf+2)/2) * (W/nf + 0.18u)'" +nrd="'0.18u / W'" nrs="'0.18u / W'" +sa=0 sb=0 sd=0 +model=nfet_03v3 +spiceprefix=X +} diff --git a/blocks/composite/regulated_cascoded_cmirror/A3_core/vanilla_cm/vanilla_cm.sym b/blocks/composite/regulated_cascoded_cmirror/A3_core/vanilla_cm/vanilla_cm.sym new file mode 100644 index 00000000..a54648f2 --- /dev/null +++ b/blocks/composite/regulated_cascoded_cmirror/A3_core/vanilla_cm/vanilla_cm.sym @@ -0,0 +1,42 @@ +v {xschem version=3.4.7 file_version=1.2} +G {} +K {type=subcircuit +format="@name @pinlist @symname" +template="name=x1" +} +V {} +S {} +E {} +L 4 -120 -40 -100 -40 {} +L 4 100 -40 120 -40 {} +L 4 -100 -40 -50 -40 {} +L 4 -50 -40 -50 -20 {} +L 4 -50 -40 -50 -10 {} +L 4 -50 -10 -30 -10 {} +L 4 -30 -10 -30 10 {} +L 4 -50 10 -30 10 {} +L 4 -50 10 -50 30 {} +L 4 -50 -40 0 -40 {} +L 4 -20 -10 -20 10 {} +L 4 -20 0 0 0 {} +L 4 0 -40 0 0 {} +L 4 50 -40 50 -20 {} +L 4 50 -40 50 -10 {} +L 4 30 -10 50 -10 {} +L 4 30 -10 30 10 {} +L 4 30 10 50 10 {} +L 4 50 10 50 30 {} +L 4 20 -10 20 10 {} +L 4 0 0 20 0 {} +L 4 50 -40 100 -40 {} +L 4 -50 30 50 30 {} +L 7 0 30 0 50 {} +B 4 -110 -70 110 50 {fill=False} +B 5 -122.5 -42.5 -117.5 -37.5 {name=v_in dir=in} +B 5 117.5 -42.5 122.5 -37.5 {name=v_out dir=out} +B 5 -2.5 47.5 2.5 52.5 {name=vss dir=inout} +T {@symname} -53 -66 0 0 0.3 0.3 {} +T {@name} 65 -92 0 0 0.2 0.2 {} +T {v_in} -95 -34 0 0 0.2 0.2 {} +T {v_out} 95 -34 0 1 0.2 0.2 {} +T {vss} 4 25 1 1 0.2 0.2 {} diff --git a/blocks/composite/regulated_cascoded_cmirror/A3_core/xschemrc b/blocks/composite/regulated_cascoded_cmirror/A3_core/xschemrc new file mode 100644 index 00000000..9f4b09b7 --- /dev/null +++ b/blocks/composite/regulated_cascoded_cmirror/A3_core/xschemrc @@ -0,0 +1,7 @@ +# Source the PDK xschemrc file +if {![info exists PDK]} { +source $env(PDK_ROOT)/$env(PDK)/libs.tech/xschem/xschemrc +} + +# Add current directory to xschem library path +append XSCHEM_LIBRARY_PATH :[file dirname [info script]] diff --git a/blocks/composite/regulated_cascoded_cmirror/DRC/README.md b/blocks/composite/regulated_cascoded_cmirror/DRC/README.md new file mode 100644 index 00000000..593458bc --- /dev/null +++ b/blocks/composite/regulated_cascoded_cmirror/DRC/README.md @@ -0,0 +1,3 @@ +## gLayout-mahowalders + +> 🚧 **Under Construction** diff --git a/blocks/composite/regulated_cascoded_cmirror/DRC/drc/BB/BB.rpt b/blocks/composite/regulated_cascoded_cmirror/DRC/drc/BB/BB.rpt new file mode 100644 index 00000000..75c346f4 --- /dev/null +++ b/blocks/composite/regulated_cascoded_cmirror/DRC/drc/BB/BB.rpt @@ -0,0 +1,3 @@ +BB count: +---------------------------------------- + diff --git a/blocks/composite/regulated_cascoded_cmirror/DRC/drc/BIAS_STAGE/BIAS_STAGE.rpt b/blocks/composite/regulated_cascoded_cmirror/DRC/drc/BIAS_STAGE/BIAS_STAGE.rpt new file mode 100644 index 00000000..8f75485d --- /dev/null +++ b/blocks/composite/regulated_cascoded_cmirror/DRC/drc/BIAS_STAGE/BIAS_STAGE.rpt @@ -0,0 +1,3 @@ +BIAS_STAGE count: +---------------------------------------- + diff --git a/blocks/composite/regulated_cascoded_cmirror/DRC/drc/CM/CM.rpt b/blocks/composite/regulated_cascoded_cmirror/DRC/drc/CM/CM.rpt new file mode 100644 index 00000000..34f9b5c5 --- /dev/null +++ b/blocks/composite/regulated_cascoded_cmirror/DRC/drc/CM/CM.rpt @@ -0,0 +1,3 @@ +CM count: +---------------------------------------- + diff --git a/blocks/composite/regulated_cascoded_cmirror/DRC/drc/CM_SB/CM_SB.rpt b/blocks/composite/regulated_cascoded_cmirror/DRC/drc/CM_SB/CM_SB.rpt new file mode 100644 index 00000000..1069d243 --- /dev/null +++ b/blocks/composite/regulated_cascoded_cmirror/DRC/drc/CM_SB/CM_SB.rpt @@ -0,0 +1,3 @@ +CM_SB count: +---------------------------------------- + diff --git a/blocks/composite/regulated_cascoded_cmirror/DRC/drc/INPUT_STAGE/INPUT_STAGE.rpt b/blocks/composite/regulated_cascoded_cmirror/DRC/drc/INPUT_STAGE/INPUT_STAGE.rpt new file mode 100644 index 00000000..99d22690 --- /dev/null +++ b/blocks/composite/regulated_cascoded_cmirror/DRC/drc/INPUT_STAGE/INPUT_STAGE.rpt @@ -0,0 +1,3 @@ +INPUT_STAGE count: +---------------------------------------- + diff --git a/blocks/composite/regulated_cascoded_cmirror/DRC/drc/M/M.rpt b/blocks/composite/regulated_cascoded_cmirror/DRC/drc/M/M.rpt new file mode 100644 index 00000000..b2355349 --- /dev/null +++ b/blocks/composite/regulated_cascoded_cmirror/DRC/drc/M/M.rpt @@ -0,0 +1,3 @@ +M count: +---------------------------------------- + diff --git a/blocks/composite/regulated_cascoded_cmirror/DRC/drc/RCM/RCM.rpt b/blocks/composite/regulated_cascoded_cmirror/DRC/drc/RCM/RCM.rpt new file mode 100644 index 00000000..5cefe37d --- /dev/null +++ b/blocks/composite/regulated_cascoded_cmirror/DRC/drc/RCM/RCM.rpt @@ -0,0 +1,3 @@ +RCM count: +---------------------------------------- + diff --git a/blocks/composite/regulated_cascoded_cmirror/DRC/drc/SCM/SCM.rpt b/blocks/composite/regulated_cascoded_cmirror/DRC/drc/SCM/SCM.rpt new file mode 100644 index 00000000..195c6e01 --- /dev/null +++ b/blocks/composite/regulated_cascoded_cmirror/DRC/drc/SCM/SCM.rpt @@ -0,0 +1,3 @@ +SCM count: +---------------------------------------- + diff --git a/blocks/composite/regulated_cascoded_cmirror/DRC/drc/TEST/TEST.rpt b/blocks/composite/regulated_cascoded_cmirror/DRC/drc/TEST/TEST.rpt new file mode 100644 index 00000000..bd781ab6 --- /dev/null +++ b/blocks/composite/regulated_cascoded_cmirror/DRC/drc/TEST/TEST.rpt @@ -0,0 +1,3 @@ +TEST count: +---------------------------------------- + diff --git a/blocks/composite/regulated_cascoded_cmirror/DRC/drc/TEST2/TEST2.rpt b/blocks/composite/regulated_cascoded_cmirror/DRC/drc/TEST2/TEST2.rpt new file mode 100644 index 00000000..f438d249 --- /dev/null +++ b/blocks/composite/regulated_cascoded_cmirror/DRC/drc/TEST2/TEST2.rpt @@ -0,0 +1,3 @@ +TEST2 count: +---------------------------------------- + diff --git a/blocks/composite/regulated_cascoded_cmirror/DRC/drc/TOP/TOP.rpt b/blocks/composite/regulated_cascoded_cmirror/DRC/drc/TOP/TOP.rpt new file mode 100644 index 00000000..290a9d4b --- /dev/null +++ b/blocks/composite/regulated_cascoded_cmirror/DRC/drc/TOP/TOP.rpt @@ -0,0 +1,3 @@ +TOP count: +---------------------------------------- + diff --git a/blocks/composite/regulated_cascoded_cmirror/Designs/design/cs-cascoded-cm.sch b/blocks/composite/regulated_cascoded_cmirror/Designs/design/cs-cascoded-cm.sch new file mode 100644 index 00000000..2e3433bf --- /dev/null +++ b/blocks/composite/regulated_cascoded_cmirror/Designs/design/cs-cascoded-cm.sch @@ -0,0 +1,106 @@ +v {xschem version=3.4.7 file_version=1.2} +G {} +K {} +V {} +S {} +E {} +N 360 -780 360 -760 { +lab=IREF} +N 310 -780 360 -780 {lab=IREF} +N 360 -310 360 -240 {lab=VSS} +N 360 -410 420 -410 {lab=#net1} +N 420 -410 420 -340 {lab=#net1} +N 330 -340 360 -340 {lab=VSS} +N 330 -340 330 -240 {lab=VSS} +N 360 -760 360 -670 {lab=IREF} +N 360 -480 360 -370 {lab=#net1} +N 280 -240 360 -240 {lab=VSS} +N 400 -340 500 -340 {lab=#net1} +N 560 -310 560 -240 {lab=VSS} +N 560 -340 580 -340 {lab=VSS} +N 580 -340 590 -340 {lab=VSS} +N 590 -340 590 -250 {lab=VSS} +N 590 -250 590 -240 {lab=VSS} +N 560 -440 560 -370 {lab=#net2} +N 500 -340 520 -340 {lab=#net1} +N 560 -740 660 -740 {lab=IOUT} +N 560 -740 560 -720 {lab=IOUT} +N 360 -240 590 -240 {lab=VSS} +N 310 -810 660 -810 {lab=VDD} +N 360 -610 360 -540 {lab=#net3} +N 360 -570 430 -570 {lab=#net3} +N 430 -570 430 -510 {lab=#net3} +N 400 -510 430 -510 {lab=#net3} +N 560 -480 560 -440 {lab=#net2} +N 430 -510 510 -510 {lab=#net3} +N 510 -510 520 -510 {lab=#net3} +N 560 -660 560 -540 {lab=#net4} +N 290 -510 360 -510 {lab=VSS} +N 290 -510 290 -240 {lab=VSS} +N 590 -510 590 -340 {lab=VSS} +N 560 -510 590 -510 {lab=VSS} +C {ipin.sym} 310 -810 0 0 {name=p9 lab=VDD +} +C {ipin.sym} 280 -240 0 0 {name=p10 lab=VSS +} +C {ipin.sym} 310 -780 0 0 {name=p12 lab=IREF +} +C {devices/ammeter.sym} 360 -640 0 0 {name=Virefin savecurrent=true} +C {symbols/nfet_05v0.sym} 380 -340 0 1 {name=MREF +L=1u +W=11u +nf=1 +m=1 +ad="'int((nf+1)/2) * W/nf * 0.18u'" +pd="'2*int((nf+1)/2) * (W/nf + 0.18u)'" +as="'int((nf+2)/2) * W/nf * 0.18u'" +ps="'2*int((nf+2)/2) * (W/nf + 0.18u)'" +nrd="'0.18u / W'" nrs="'0.18u / W'" +sa=0 sb=0 sd=0 +model=nfet_05v0 +spiceprefix=X +} +C {symbols/nfet_05v0.sym} 540 -340 0 0 {name=MOUT +L=1u +W=11u +nf=1 +m=1 +ad="'int((nf+1)/2) * W/nf * 0.18u'" +pd="'2*int((nf+1)/2) * (W/nf + 0.18u)'" +as="'int((nf+2)/2) * W/nf * 0.18u'" +ps="'2*int((nf+2)/2) * (W/nf + 0.18u)'" +nrd="'0.18u / W'" nrs="'0.18u / W'" +sa=0 sb=0 sd=0 +model=nfet_05v0 +spiceprefix=X +} +C {devices/ammeter.sym} 560 -690 0 0 {name=Vi2 savecurrent=true} +C {opin.sym} 660 -740 0 0 {name=p6 lab=IOUT} +C {symbols/nfet_05v0.sym} 380 -510 0 1 {name=MB1 +L=1u +W=11u +nf=1 +m=1 +ad="'int((nf+1)/2) * W/nf * 0.18u'" +pd="'2*int((nf+1)/2) * (W/nf + 0.18u)'" +as="'int((nf+2)/2) * W/nf * 0.18u'" +ps="'2*int((nf+2)/2) * (W/nf + 0.18u)'" +nrd="'0.18u / W'" nrs="'0.18u / W'" +sa=0 sb=0 sd=0 +model=nfet_05v0 +spiceprefix=X +} +C {symbols/nfet_05v0.sym} 540 -510 0 0 {name=MB2 +L=1u +W=11u +nf=1 +m=1 +ad="'int((nf+1)/2) * W/nf * 0.18u'" +pd="'2*int((nf+1)/2) * (W/nf + 0.18u)'" +as="'int((nf+2)/2) * W/nf * 0.18u'" +ps="'2*int((nf+2)/2) * (W/nf + 0.18u)'" +nrd="'0.18u / W'" nrs="'0.18u / W'" +sa=0 sb=0 sd=0 +model=nfet_05v0 +spiceprefix=X +} diff --git a/blocks/composite/regulated_cascoded_cmirror/Designs/design/cs-cascoded-cm.sym b/blocks/composite/regulated_cascoded_cmirror/Designs/design/cs-cascoded-cm.sym new file mode 100644 index 00000000..2369f274 --- /dev/null +++ b/blocks/composite/regulated_cascoded_cmirror/Designs/design/cs-cascoded-cm.sym @@ -0,0 +1,51 @@ +v {xschem version=3.4.7 file_version=1.2} +G {} +K {type=subcircuit +format="@name @pinlist @symname" +template="name=x1" +} +V {} +S {} +E {} +L 4 80 -150 100 -150 {} +L 4 80 -130 100 -130 {} +L 4 360 -150 380 -150 {} +L 4 80 -110 100 -110 {} +L 4 100 -200 100 -60 {} +L 4 100 -200 360 -200 {} +L 4 360 -200 360 -60 {} +L 4 100 -60 360 -60 {} +L 4 160 -140 180 -140 {} +L 4 180 -140 180 -120 {} +L 4 160 -120 180 -120 {} +L 4 160 -120 160 -100 {} +L 4 180 -130 240 -130 {} +L 4 240 -140 240 -130 {} +L 4 240 -140 260 -140 {} +L 4 240 -130 240 -120 {} +L 4 240 -120 260 -120 {} +L 4 260 -120 260 -100 {} +L 4 160 -150 190 -150 {} +L 4 190 -150 190 -130 {} +L 4 150 -100 270 -100 {} +L 4 270 -150 290 -150 {} +L 4 140 -150 160 -150 {} +L 4 130 -130 140 -130 {} +L 4 290 -150 320 -150 {} +L 4 260 -150 270 -150 {} +L 4 260 -150 260 -140 {} +L 4 160 -150 160 -140 {} +L 4 140 -150 160 -150 {} +L 4 140 -150 140 -130 {} +L 4 270 -100 320 -100 {} +L 4 130 -100 150 -100 {} +B 5 77.5 -152.5 82.5 -147.5 {name=VDD dir=in} +B 5 77.5 -132.5 82.5 -127.5 {name=IREF dir=in} +B 5 377.5 -152.5 382.5 -147.5 {name=IOUT dir=out} +B 5 77.5 -112.5 82.5 -107.5 {name=VSS dir=in} +T {@symname} 127.5 -196 0 0 0.3 0.3 {} +T {@name} 325 -212 0 0 0.2 0.2 {} +T {VDD} 105 -154 0 0 0.2 0.2 {} +T {IREF} 105 -134 0 0 0.2 0.2 {} +T {IOUT} 355 -154 0 1 0.2 0.2 {} +T {VSS} 105 -114 0 0 0.2 0.2 {} diff --git a/blocks/composite/regulated_cascoded_cmirror/Designs/design/cs-regulated-cascoded_5V.sch b/blocks/composite/regulated_cascoded_cmirror/Designs/design/cs-regulated-cascoded_5V.sch new file mode 100644 index 00000000..bf2553af --- /dev/null +++ b/blocks/composite/regulated_cascoded_cmirror/Designs/design/cs-regulated-cascoded_5V.sch @@ -0,0 +1,315 @@ +v {xschem version=3.4.7 file_version=1.2} +G {} +K {} +V {} +S {} +E {} +N 810 -230 930 -230 { +lab=VSS} +N 770 -280 810 -280 { +lab=vgs_casc} +N 930 -250 930 -230 { +lab=VSS} +N 730 -250 730 -230 { +lab=VSS} +N 720 -280 730 -280 { +lab=VSS} +N 720 -240 730 -240 { +lab=VSS} +N 940 -280 940 -240 { +lab=VSS} +N 930 -240 940 -240 { +lab=VSS} +N 730 -550 730 -530 { +lab=#net1} +N 720 -280 720 -240 {lab=VSS} +N 930 -280 940 -280 {lab=VSS} +N 620 -330 730 -330 {lab=vd_ref} +N 480 -300 480 -230 {lab=VSS} +N 580 -230 730 -230 {lab=VSS} +N 150 -640 150 -620 { +lab=IREF} +N 480 -550 480 -530 { +lab=#net2} +N 480 -470 480 -410 {lab=#net3} +N 480 -410 480 -360 {lab=#net3} +N 730 -350 730 -310 {lab=vd_ref} +N 730 -470 730 -410 {lab=vgs_casc} +N 580 -380 690 -380 {lab=#net3} +N 730 -440 780 -440 {lab=vgs_casc} +N 800 -440 800 -280 {lab=vgs_casc} +N 730 -230 810 -230 {lab=VSS} +N 810 -280 890 -280 {lab=vgs_casc} +N 930 -350 930 -310 {lab=vd_out} +N 1190 -300 1190 -230 {lab=VSS} +N 920 -230 1090 -230 {lab=VSS} +N 930 -420 930 -350 {lab=vd_out} +N 930 -520 930 -480 {lab=vout} +N 1190 -350 1190 -300 {lab=VSS} +N 960 -450 1080 -450 {lab=#net4} +N 1180 -450 1190 -450 {lab=#net4} +N 1190 -450 1190 -410 {lab=#net4} +N 930 -380 1060 -380 {lab=vd_out} +N 1190 -510 1190 -450 {lab=#net4} +N 1190 -380 1210 -380 {lab=VSS} +N 1210 -380 1210 -230 {lab=VSS} +N 1190 -230 1210 -230 {lab=VSS} +N 730 -380 760 -380 {lab=VSS} +N 760 -380 760 -230 {lab=VSS} +N 450 -330 480 -330 {lab=VSS} +N 450 -330 450 -230 {lab=VSS} +N 450 -230 480 -230 {lab=VSS} +N 890 -450 930 -450 {lab=VSS} +N 870 -450 890 -450 {lab=VSS} +N 870 -450 870 -230 {lab=VSS} +N 1190 -580 1190 -570 {lab=#net5} +N 1190 -650 1190 -640 {lab=VDD} +N 480 -230 580 -230 {lab=VSS} +N 480 -380 580 -380 {lab=#net3} +N 1090 -230 1190 -230 {lab=VSS} +N 1080 -450 1180 -450 {lab=#net4} +N 1060 -380 1070 -380 {lab=vd_out} +N 780 -440 800 -440 {lab=vgs_casc} +N 930 -600 1030 -600 {lab=IOUT} +N 1190 -670 1190 -650 {lab=VDD} +N 1140 -670 1190 -670 {lab=VDD} +N 730 -670 730 -650 {lab=VDD} +N 730 -670 1140 -670 {lab=VDD} +N 420 -230 450 -230 {lab=VSS} +N 100 -640 150 -640 {lab=IREF} +N 930 -600 930 -580 {lab=IOUT} +N 190 -330 230 -330 {lab=#net6} +N 70 -230 420 -230 {lab=VSS} +N 150 -300 150 -230 {lab=VSS} +N 270 -300 270 -230 {lab=VSS} +N 270 -570 270 -360 {lab=#net7} +N 150 -400 210 -400 {lab=#net6} +N 210 -400 210 -330 {lab=#net6} +N 100 -670 430 -670 {lab=VDD} +N 270 -670 270 -630 {lab=VDD} +N 270 -600 300 -600 {lab=VDD} +N 300 -670 300 -600 {lab=VDD} +N 210 -600 210 -550 {lab=#net7} +N 230 -550 270 -550 {lab=#net7} +N 210 -600 230 -600 {lab=#net7} +N 210 -550 230 -550 {lab=#net7} +N 480 -570 480 -550 {lab=#net2} +N 480 -670 480 -630 {lab=VDD} +N 430 -670 730 -670 {lab=VDD} +N 390 -600 440 -600 {lab=#net7} +N 390 -600 390 -550 {lab=#net7} +N 390 -550 390 -540 {lab=#net7} +N 270 -540 390 -540 {lab=#net7} +N 480 -600 500 -600 {lab=VDD} +N 500 -670 500 -600 {lab=VDD} +N 520 -330 620 -330 {lab=vd_ref} +N 1070 -380 1150 -380 {lab=vd_out} +N 390 -560 650 -560 {lab=#net7} +N 650 -580 650 -560 {lab=#net7} +N 650 -610 690 -610 {lab=#net7} +N 650 -610 650 -580 {lab=#net7} +N 730 -580 730 -550 {lab=#net1} +N 730 -650 730 -640 {lab=VDD} +N 730 -610 750 -610 {lab=VDD} +N 750 -670 750 -610 {lab=VDD} +N 1190 -610 1210 -610 {lab=VDD} +N 1210 -670 1210 -610 {lab=VDD} +N 1190 -670 1210 -670 {lab=VDD} +N 650 -560 1140 -560 {lab=#net7} +N 1140 -610 1140 -560 {lab=#net7} +N 1140 -610 1150 -610 {lab=#net7} +N 120 -330 150 -330 {lab=VSS} +N 120 -330 120 -230 {lab=VSS} +N 270 -330 290 -330 {lab=VSS} +N 290 -330 300 -330 {lab=VSS} +N 300 -330 300 -240 {lab=VSS} +N 300 -240 300 -230 {lab=VSS} +N 150 -620 150 -530 {lab=IREF} +N 150 -470 150 -360 {lab=#net6} +C {devices/ammeter.sym} 730 -500 0 0 {name=Vi1 savecurrent=true} +C {devices/ammeter.sym} 930 -550 0 0 {name=Vi2 savecurrent=true} +C {devices/lab_pin.sym} 780 -440 1 0 {name=p1 sig_type=std_logic lab=vgs_casc} +C {devices/lab_pin.sym} 930 -360 0 1 {name=p2 sig_type=std_logic lab=vd_out +} +C {devices/ammeter.sym} 480 -500 0 0 {name=Vi3 savecurrent=true} +C {devices/ammeter.sym} 1190 -540 0 0 {name=Vi4 savecurrent=true} +C {devices/lab_pin.sym} 930 -500 0 1 {name=p4 sig_type=std_logic lab=vout +} +C {devices/lab_pin.sym} 730 -340 0 1 {name=p3 sig_type=std_logic lab=vd_ref +} +C {opin.sym} 1030 -600 0 0 {name=p6 lab=IOUT} +C {ipin.sym} 100 -670 0 0 {name=p9 lab=VDD +} +C {ipin.sym} 70 -230 0 0 {name=p10 lab=VSS +} +C {ipin.sym} 100 -640 0 0 {name=p12 lab=IREF +} +C {devices/ammeter.sym} 150 -500 0 0 {name=Virefin savecurrent=true} +C {symbols/nfet_05v0.sym} 170 -330 0 1 {name=MB5 +L=0.60u +W=0.30u +nf=1 +m=1 +ad="'int((nf+1)/2) * W/nf * 0.18u'" +pd="'2*int((nf+1)/2) * (W/nf + 0.18u)'" +as="'int((nf+2)/2) * W/nf * 0.18u'" +ps="'2*int((nf+2)/2) * (W/nf + 0.18u)'" +nrd="'0.18u / W'" nrs="'0.18u / W'" +sa=0 sb=0 sd=0 +model=nfet_05v0 +spiceprefix=X +} +C {symbols/nfet_05v0.sym} 250 -330 0 0 {name=MB4 +L=0.60u +W=0.30u +nf=1 +m=1 +ad="'int((nf+1)/2) * W/nf * 0.18u'" +pd="'2*int((nf+1)/2) * (W/nf + 0.18u)'" +as="'int((nf+2)/2) * W/nf * 0.18u'" +ps="'2*int((nf+2)/2) * (W/nf + 0.18u)'" +nrd="'0.18u / W'" nrs="'0.18u / W'" +sa=0 sb=0 sd=0 +model=nfet_05v0 +spiceprefix=X +} +C {symbols/nfet_05v0.sym} 500 -330 0 1 {name=MB1 +L=0.60u +W=0.30u +nf=1 +m=1 +ad="'int((nf+1)/2) * W/nf * 0.18u'" +pd="'2*int((nf+1)/2) * (W/nf + 0.18u)'" +as="'int((nf+2)/2) * W/nf * 0.18u'" +ps="'2*int((nf+2)/2) * (W/nf + 0.18u)'" +nrd="'0.18u / W'" nrs="'0.18u / W'" +sa=0 sb=0 sd=0 +model=nfet_05v0 +spiceprefix=X +} +C {symbols/nfet_05v0.sym} 750 -280 0 1 {name=MREF +L=0.60u +W=0.30u +nf=1 +m=2 +ad="'int((nf+1)/2) * W/nf * 0.18u'" +pd="'2*int((nf+1)/2) * (W/nf + 0.18u)'" +as="'int((nf+2)/2) * W/nf * 0.18u'" +ps="'2*int((nf+2)/2) * (W/nf + 0.18u)'" +nrd="'0.18u / W'" nrs="'0.18u / W'" +sa=0 sb=0 sd=0 +model=nfet_05v0 +spiceprefix=X +} +C {symbols/nfet_05v0.sym} 710 -380 0 0 {name=MCASC_IN +L=0.60u +W=0.30u +nf=1 +m=20 +ad="'int((nf+1)/2) * W/nf * 0.18u'" +pd="'2*int((nf+1)/2) * (W/nf + 0.18u)'" +as="'int((nf+2)/2) * W/nf * 0.18u'" +ps="'2*int((nf+2)/2) * (W/nf + 0.18u)'" +nrd="'0.18u / W'" nrs="'0.18u / W'" +sa=0 sb=0 sd=0 +model=nfet_05v0 +spiceprefix=X +} +C {symbols/nfet_05v0.sym} 950 -450 0 1 {name=MCASC +L=0.60u +W=0.30u +nf=1 +m=20 +ad="'int((nf+1)/2) * W/nf * 0.18u'" +pd="'2*int((nf+1)/2) * (W/nf + 0.18u)'" +as="'int((nf+2)/2) * W/nf * 0.18u'" +ps="'2*int((nf+2)/2) * (W/nf + 0.18u)'" +nrd="'0.18u / W'" nrs="'0.18u / W'" +sa=0 sb=0 sd=0 +model=nfet_05v0 +spiceprefix=X +} +C {symbols/nfet_05v0.sym} 910 -280 0 0 {name=MREF_A +L=0.60u +W=0.30u +nf=1 +m=1 +ad="'int((nf+1)/2) * W/nf * 0.18u'" +pd="'2*int((nf+1)/2) * (W/nf + 0.18u)'" +as="'int((nf+2)/2) * W/nf * 0.18u'" +ps="'2*int((nf+2)/2) * (W/nf + 0.18u)'" +nrd="'0.18u / W'" nrs="'0.18u / W'" +sa=0 sb=0 sd=0 +model=nfet_05v0 +spiceprefix=X +} +C {symbols/nfet_05v0.sym} 1170 -380 0 0 {name=MB_B +L=0.60u +W=0.30u +nf=1 +m=20 +ad="'int((nf+1)/2) * W/nf * 0.18u'" +pd="'2*int((nf+1)/2) * (W/nf + 0.18u)'" +as="'int((nf+2)/2) * W/nf * 0.18u'" +ps="'2*int((nf+2)/2) * (W/nf + 0.18u)'" +nrd="'0.18u / W'" nrs="'0.18u / W'" +sa=0 sb=0 sd=0 +model=nfet_05v0 +spiceprefix=X +} +C {symbols/pfet_05v0.sym} 250 -600 0 0 {name=M2 +L=0.50u +W=0.30u +nf=1 +m=1 +ad="'int((nf+1)/2) * W/nf * 0.18u'" +pd="'2*int((nf+1)/2) * (W/nf + 0.18u)'" +as="'int((nf+2)/2) * W/nf * 0.18u'" +ps="'2*int((nf+2)/2) * (W/nf + 0.18u)'" +nrd="'0.18u / W'" nrs="'0.18u / W'" +sa=0 sb=0 sd=0 +model=pfet_05v0 +spiceprefix=X +} +C {symbols/pfet_05v0.sym} 460 -600 0 0 {name=M1 +L=0.50u +W=0.30u +nf=1 +m=1 +ad="'int((nf+1)/2) * W/nf * 0.18u'" +pd="'2*int((nf+1)/2) * (W/nf + 0.18u)'" +as="'int((nf+2)/2) * W/nf * 0.18u'" +ps="'2*int((nf+2)/2) * (W/nf + 0.18u)'" +nrd="'0.18u / W'" nrs="'0.18u / W'" +sa=0 sb=0 sd=0 +model=pfet_05v0 +spiceprefix=X +} +C {symbols/pfet_05v0.sym} 710 -610 0 0 {name=M3 +L=0.50u +W=0.30u +nf=1 +m=1 +ad="'int((nf+1)/2) * W/nf * 0.18u'" +pd="'2*int((nf+1)/2) * (W/nf + 0.18u)'" +as="'int((nf+2)/2) * W/nf * 0.18u'" +ps="'2*int((nf+2)/2) * (W/nf + 0.18u)'" +nrd="'0.18u / W'" nrs="'0.18u / W'" +sa=0 sb=0 sd=0 +model=pfet_05v0 +spiceprefix=X +} +C {symbols/pfet_05v0.sym} 1170 -610 0 0 {name=M4 +L=0.50u +W=0.30u +nf=1 +m=1 +ad="'int((nf+1)/2) * W/nf * 0.18u'" +pd="'2*int((nf+1)/2) * (W/nf + 0.18u)'" +as="'int((nf+2)/2) * W/nf * 0.18u'" +ps="'2*int((nf+2)/2) * (W/nf + 0.18u)'" +nrd="'0.18u / W'" nrs="'0.18u / W'" +sa=0 sb=0 sd=0 +model=pfet_05v0 +spiceprefix=X +} diff --git a/blocks/composite/regulated_cascoded_cmirror/Designs/design/cs-regulated-cascoded_5V.sym b/blocks/composite/regulated_cascoded_cmirror/Designs/design/cs-regulated-cascoded_5V.sym new file mode 100644 index 00000000..2369f274 --- /dev/null +++ b/blocks/composite/regulated_cascoded_cmirror/Designs/design/cs-regulated-cascoded_5V.sym @@ -0,0 +1,51 @@ +v {xschem version=3.4.7 file_version=1.2} +G {} +K {type=subcircuit +format="@name @pinlist @symname" +template="name=x1" +} +V {} +S {} +E {} +L 4 80 -150 100 -150 {} +L 4 80 -130 100 -130 {} +L 4 360 -150 380 -150 {} +L 4 80 -110 100 -110 {} +L 4 100 -200 100 -60 {} +L 4 100 -200 360 -200 {} +L 4 360 -200 360 -60 {} +L 4 100 -60 360 -60 {} +L 4 160 -140 180 -140 {} +L 4 180 -140 180 -120 {} +L 4 160 -120 180 -120 {} +L 4 160 -120 160 -100 {} +L 4 180 -130 240 -130 {} +L 4 240 -140 240 -130 {} +L 4 240 -140 260 -140 {} +L 4 240 -130 240 -120 {} +L 4 240 -120 260 -120 {} +L 4 260 -120 260 -100 {} +L 4 160 -150 190 -150 {} +L 4 190 -150 190 -130 {} +L 4 150 -100 270 -100 {} +L 4 270 -150 290 -150 {} +L 4 140 -150 160 -150 {} +L 4 130 -130 140 -130 {} +L 4 290 -150 320 -150 {} +L 4 260 -150 270 -150 {} +L 4 260 -150 260 -140 {} +L 4 160 -150 160 -140 {} +L 4 140 -150 160 -150 {} +L 4 140 -150 140 -130 {} +L 4 270 -100 320 -100 {} +L 4 130 -100 150 -100 {} +B 5 77.5 -152.5 82.5 -147.5 {name=VDD dir=in} +B 5 77.5 -132.5 82.5 -127.5 {name=IREF dir=in} +B 5 377.5 -152.5 382.5 -147.5 {name=IOUT dir=out} +B 5 77.5 -112.5 82.5 -107.5 {name=VSS dir=in} +T {@symname} 127.5 -196 0 0 0.3 0.3 {} +T {@name} 325 -212 0 0 0.2 0.2 {} +T {VDD} 105 -154 0 0 0.2 0.2 {} +T {IREF} 105 -134 0 0 0.2 0.2 {} +T {IOUT} 355 -154 0 1 0.2 0.2 {} +T {VSS} 105 -114 0 0 0.2 0.2 {} diff --git a/blocks/composite/regulated_cascoded_cmirror/Designs/design/cs-top.sch b/blocks/composite/regulated_cascoded_cmirror/Designs/design/cs-top.sch new file mode 100644 index 00000000..8ae78423 --- /dev/null +++ b/blocks/composite/regulated_cascoded_cmirror/Designs/design/cs-top.sch @@ -0,0 +1,35 @@ +v {xschem version=3.4.7 file_version=1.2} +G {} +K {} +V {} +S {} +E {} +N 570 -990 700 -990 {lab=VSS} +N 570 -990 570 -400 {lab=VSS} +N 340 -400 570 -400 {lab=VSS} +N 570 -760 700 -760 {lab=VSS} +N 570 -520 700 -520 {lab=VSS} +N 570 -1030 700 -1030 {lab=VDD} +N 550 -800 700 -800 {lab=VDD} +N 540 -560 700 -560 {lab=VDD} +N 540 -1140 540 -560 {lab=VDD} +N 540 -800 550 -800 {lab=VDD} +N 540 -1030 570 -1030 {lab=VDD} +N 340 -1140 540 -1140 {lab=VDD} +N 340 -1010 700 -1010 {lab=IREF_VM_1} +N 340 -780 700 -780 {lab=IREF_CM_1} +N 340 -540 700 -540 {lab=IREF_RCM_1} +N 1000 -1030 1560 -1030 {lab=IOUT_VM_1} +N 1000 -800 1550 -800 {lab=IOUT_CM_1} +N 1000 -560 1550 -560 {lab=IOUT_RCM_1} +C {ipin.sym} 340 -1140 0 0 {name=p1 lab=VDD} +C {ipin.sym} 340 -400 0 0 {name=p2 lab=VSS} +C {ipin.sym} 340 -1010 0 0 {name=p3 lab=IREF_VM_1} +C {ipin.sym} 340 -780 0 0 {name=p4 lab=IREF_CM_1} +C {ipin.sym} 340 -540 0 0 {name=p5 lab=IREF_RCM_1} +C {iopin.sym} 1560 -1030 0 0 {name=p6 lab=IOUT_VM_1} +C {iopin.sym} 1550 -800 0 0 {name=p7 lab=IOUT_CM_1} +C {iopin.sym} 1550 -560 0 0 {name=p8 lab=IOUT_RCM_1} +C {cs-regulated-cascoded_5V.sym} 620 -410 0 0 {name=x3} +C {cs-vanilla-cm.sym} 620 -880 0 0 {name=x2} +C {cs-cascoded-cm.sym} 620 -650 0 0 {name=x1} diff --git a/blocks/composite/regulated_cascoded_cmirror/Designs/design/cs-top.sym b/blocks/composite/regulated_cascoded_cmirror/Designs/design/cs-top.sym new file mode 100644 index 00000000..1823c6a4 --- /dev/null +++ b/blocks/composite/regulated_cascoded_cmirror/Designs/design/cs-top.sym @@ -0,0 +1,86 @@ +v {xschem version=3.4.7 file_version=1.2} +G {} +K {type=subcircuit +format="@name @pinlist @symname" +template="name=x1" +} +V {} +S {} +E {} +L 4 40 -260 60 -260 {} +L 4 40 -220 60 -220 {} +L 4 40 -200 60 -200 {} +L 4 40 -240 60 -240 {} +L 4 40 -80 60 -80 {} +L 4 190 -160 190 -80 {} +L 4 140 -80 190 -80 {} +L 4 220 -160 220 -80 {} +L 4 250 -160 250 -80 {} +L 4 250 -220 250 -190 {} +L 4 190 -80 250 -80 {} +L 4 220 -200 220 -190 {} +L 4 130 -240 250 -240 {} +L 4 250 -240 250 -220 {} +L 4 60 -280 60 -60 {} +L 4 60 -280 470 -280 {} +L 4 470 -280 470 -60 {} +L 4 60 -60 470 -60 {} +L 4 90 -80 140 -80 {} +L 4 390 -160 390 -80 {} +L 4 330 -80 390 -80 {} +L 4 250 -80 330 -80 {} +L 4 360 -160 360 -80 {} +L 4 300 -80 360 -80 {} +L 4 330 -160 330 -80 {} +L 4 330 -220 330 -190 {} +L 4 270 -80 330 -80 {} +L 4 360 -200 360 -190 {} +L 4 330 -240 330 -220 {} +L 4 330 -240 400 -240 {} +L 4 360 -220 400 -220 {} +L 4 360 -220 360 -200 {} +L 4 390 -200 390 -190 {} +L 4 390 -200 400 -200 {} +L 4 220 -220 220 -200 {} +L 4 120 -220 220 -220 {} +L 4 190 -200 190 -190 {} +L 4 120 -200 190 -200 {} +L 7 470 -220 490 -220 {} +L 7 470 -200 490 -200 {} +L 7 470 -240 490 -240 {} +B 5 37.5 -262.5 42.5 -257.5 {name=VDD dir=in} +B 5 487.5 -222.5 492.5 -217.5 {name=IOUT_VM_1 dir=inout} +B 5 37.5 -222.5 42.5 -217.5 {name=IREF_VM_1 dir=in} +B 5 487.5 -202.5 492.5 -197.5 {name=IOUT_CM_1 dir=inout} +B 5 37.5 -202.5 42.5 -197.5 {name=IREF_CM_1 dir=in} +B 5 487.5 -242.5 492.5 -237.5 {name=IOUT_RCM_1 dir=inout} +B 5 37.5 -242.5 42.5 -237.5 {name=IREF_RCM_1 dir=in} +B 5 37.5 -82.5 42.5 -77.5 {name=VSS dir=in} +A 4 190 -180 10 270 360 {} +A 4 190 -170 10 270 360 {} +A 4 220 -180 10 270 360 {} +A 4 220 -170 10 270 360 {} +A 4 250 -180 10 270 360 {} +A 4 250 -170 10 270 360 {} +A 4 390 -180 10 270 360 {} +A 4 390 -170 10 270 360 {} +A 4 360 -180 10 270 360 {} +A 4 360 -170 10 270 360 {} +A 4 330 -180 10 270 360 {} +A 4 330 -170 10 270 360 {} +T {@symname} 225 -276 0 0 0.3 0.3 {} +T {@name} 425 -292 0 0 0.2 0.2 {} +T {VDD} 65 -264 0 0 0.2 0.2 {} +T {IOUT_VM_1} 465 -224 0 1 0.2 0.2 {} +T {IREF_VM_1} 65 -224 0 0 0.2 0.2 {} +T {IOUT_CM_1} 465 -204 0 1 0.2 0.2 {} +T {IREF_CM_1} 65 -204 0 0 0.2 0.2 {} +T {IOUT_RCM_1} 465 -244 0 1 0.2 0.2 {} +T {IREF_RCM_1} 65 -244 0 0 0.2 0.2 {} +T {VSS} 65 -84 0 0 0.2 0.2 {} +T {1} 190 -160 0 0 0.4 0.4 {} +T {2} 220 -160 0 0 0.4 0.4 {} +T {3} 250 -160 0 0 0.4 0.4 {} +T {1} 390 -160 0 0 0.4 0.4 {} +T {2} 360 -160 0 0 0.4 0.4 {} +T {3} 330 -160 0 0 0.4 0.4 {} diff --git a/blocks/composite/regulated_cascoded_cmirror/Designs/design/cs-vanilla-cm.sch b/blocks/composite/regulated_cascoded_cmirror/Designs/design/cs-vanilla-cm.sch new file mode 100644 index 00000000..ed846760 --- /dev/null +++ b/blocks/composite/regulated_cascoded_cmirror/Designs/design/cs-vanilla-cm.sch @@ -0,0 +1,67 @@ +v {xschem version=3.4.7 file_version=1.2} +G {} +K {} +V {} +S {} +E {} +N 360 -650 360 -630 { +lab=IREF} +N 310 -650 360 -650 {lab=IREF} +N 360 -310 360 -240 {lab=VSS} +N 360 -410 420 -410 {lab=#net1} +N 420 -410 420 -340 {lab=#net1} +N 330 -340 360 -340 {lab=VSS} +N 330 -340 330 -240 {lab=VSS} +N 360 -630 360 -540 {lab=IREF} +N 360 -480 360 -370 {lab=#net1} +N 280 -240 360 -240 {lab=VSS} +N 400 -340 500 -340 {lab=#net1} +N 560 -310 560 -240 {lab=VSS} +N 560 -340 580 -340 {lab=VSS} +N 580 -340 590 -340 {lab=VSS} +N 590 -340 590 -250 {lab=VSS} +N 590 -250 590 -240 {lab=VSS} +N 560 -440 560 -370 {lab=#net2} +N 500 -340 520 -340 {lab=#net1} +N 560 -610 660 -610 {lab=IOUT} +N 560 -610 560 -590 {lab=IOUT} +N 560 -530 560 -440 {lab=#net2} +N 360 -240 590 -240 {lab=VSS} +N 310 -680 660 -680 {lab=VDD} +C {ipin.sym} 310 -680 0 0 {name=p9 lab=VDD +} +C {ipin.sym} 280 -240 0 0 {name=p10 lab=VSS +} +C {ipin.sym} 310 -650 0 0 {name=p12 lab=IREF +} +C {devices/ammeter.sym} 360 -510 0 0 {name=Virefin savecurrent=true} +C {symbols/nfet_05v0.sym} 380 -340 0 1 {name=MREF +L=1u +W=11u +nf=1 +m=1 +ad="'int((nf+1)/2) * W/nf * 0.18u'" +pd="'2*int((nf+1)/2) * (W/nf + 0.18u)'" +as="'int((nf+2)/2) * W/nf * 0.18u'" +ps="'2*int((nf+2)/2) * (W/nf + 0.18u)'" +nrd="'0.18u / W'" nrs="'0.18u / W'" +sa=0 sb=0 sd=0 +model=nfet_05v0 +spiceprefix=X +} +C {symbols/nfet_05v0.sym} 540 -340 0 0 {name=MOUT +L=1u +W=11u +nf=1 +m=1 +ad="'int((nf+1)/2) * W/nf * 0.18u'" +pd="'2*int((nf+1)/2) * (W/nf + 0.18u)'" +as="'int((nf+2)/2) * W/nf * 0.18u'" +ps="'2*int((nf+2)/2) * (W/nf + 0.18u)'" +nrd="'0.18u / W'" nrs="'0.18u / W'" +sa=0 sb=0 sd=0 +model=nfet_05v0 +spiceprefix=X +} +C {devices/ammeter.sym} 560 -560 0 0 {name=Vi2 savecurrent=true} +C {opin.sym} 660 -610 0 0 {name=p6 lab=IOUT} diff --git a/blocks/composite/regulated_cascoded_cmirror/Designs/design/cs-vanilla-cm.sym b/blocks/composite/regulated_cascoded_cmirror/Designs/design/cs-vanilla-cm.sym new file mode 100644 index 00000000..2369f274 --- /dev/null +++ b/blocks/composite/regulated_cascoded_cmirror/Designs/design/cs-vanilla-cm.sym @@ -0,0 +1,51 @@ +v {xschem version=3.4.7 file_version=1.2} +G {} +K {type=subcircuit +format="@name @pinlist @symname" +template="name=x1" +} +V {} +S {} +E {} +L 4 80 -150 100 -150 {} +L 4 80 -130 100 -130 {} +L 4 360 -150 380 -150 {} +L 4 80 -110 100 -110 {} +L 4 100 -200 100 -60 {} +L 4 100 -200 360 -200 {} +L 4 360 -200 360 -60 {} +L 4 100 -60 360 -60 {} +L 4 160 -140 180 -140 {} +L 4 180 -140 180 -120 {} +L 4 160 -120 180 -120 {} +L 4 160 -120 160 -100 {} +L 4 180 -130 240 -130 {} +L 4 240 -140 240 -130 {} +L 4 240 -140 260 -140 {} +L 4 240 -130 240 -120 {} +L 4 240 -120 260 -120 {} +L 4 260 -120 260 -100 {} +L 4 160 -150 190 -150 {} +L 4 190 -150 190 -130 {} +L 4 150 -100 270 -100 {} +L 4 270 -150 290 -150 {} +L 4 140 -150 160 -150 {} +L 4 130 -130 140 -130 {} +L 4 290 -150 320 -150 {} +L 4 260 -150 270 -150 {} +L 4 260 -150 260 -140 {} +L 4 160 -150 160 -140 {} +L 4 140 -150 160 -150 {} +L 4 140 -150 140 -130 {} +L 4 270 -100 320 -100 {} +L 4 130 -100 150 -100 {} +B 5 77.5 -152.5 82.5 -147.5 {name=VDD dir=in} +B 5 77.5 -132.5 82.5 -127.5 {name=IREF dir=in} +B 5 377.5 -152.5 382.5 -147.5 {name=IOUT dir=out} +B 5 77.5 -112.5 82.5 -107.5 {name=VSS dir=in} +T {@symname} 127.5 -196 0 0 0.3 0.3 {} +T {@name} 325 -212 0 0 0.2 0.2 {} +T {VDD} 105 -154 0 0 0.2 0.2 {} +T {IREF} 105 -134 0 0 0.2 0.2 {} +T {IOUT} 355 -154 0 1 0.2 0.2 {} +T {VSS} 105 -114 0 0 0.2 0.2 {} diff --git a/blocks/composite/regulated_cascoded_cmirror/LVS/README.md b/blocks/composite/regulated_cascoded_cmirror/LVS/README.md new file mode 100644 index 00000000..593458bc --- /dev/null +++ b/blocks/composite/regulated_cascoded_cmirror/LVS/README.md @@ -0,0 +1,3 @@ +## gLayout-mahowalders + +> 🚧 **Under Construction** diff --git a/blocks/composite/regulated_cascoded_cmirror/LVS/lvs/BB/BB_lvs.rpt b/blocks/composite/regulated_cascoded_cmirror/LVS/lvs/BB/BB_lvs.rpt new file mode 100644 index 00000000..cbc2e01c --- /dev/null +++ b/blocks/composite/regulated_cascoded_cmirror/LVS/lvs/BB/BB_lvs.rpt @@ -0,0 +1,38 @@ + +Circuit 1 cell pfet_03v3 and Circuit 2 cell pfet_03v3 are black boxes. +Warning: Equate pins: cell pfet_03v3 is a placeholder, treated as a black box. +Warning: Equate pins: cell pfet_03v3 is a placeholder, treated as a black box. + +Subcircuit pins: +Circuit 1: pfet_03v3 |Circuit 2: pfet_03v3 +-------------------------------------------|------------------------------------------- +1 |1 +2 |2 +3 |3 +4 |4 +--------------------------------------------------------------------------------------- +Cell pin lists are equivalent. +Device classes pfet_03v3 and pfet_03v3 are equivalent. + +Class BB (0): Merged 21 parallel devices. +Subcircuit summary: +Circuit 1: BB |Circuit 2: BB +-------------------------------------------|------------------------------------------- +pfet_03v3 (26->5) |pfet_03v3 (26->5) +Number of devices: 5 |Number of devices: 5 +Number of nets: 5 |Number of nets: 5 +--------------------------------------------------------------------------------------- +Netlists match uniquely. + +Subcircuit pins: +Circuit 1: BB |Circuit 2: BB +-------------------------------------------|------------------------------------------- +VOUT |VOUT +VIN |VIN +VDD |VDD +--------------------------------------------------------------------------------------- +Cell pin lists are equivalent. +Device classes BB and BB are equivalent. + +Final result: Circuits match uniquely. +. diff --git a/blocks/composite/regulated_cascoded_cmirror/LVS/lvs/BB/BB_lvsmag.spice b/blocks/composite/regulated_cascoded_cmirror/LVS/lvs/BB/BB_lvsmag.spice new file mode 100644 index 00000000..722718ba --- /dev/null +++ b/blocks/composite/regulated_cascoded_cmirror/LVS/lvs/BB/BB_lvsmag.spice @@ -0,0 +1,31 @@ +* NGSPICE file created from BB.ext - technology: gf180mcuD + +.subckt BB VIN VDD VOUT +X0 a_n2573_n881# a_n2573_n881# VDD VDD pfet_03v3 ad=4.8p pd=17.2u as=4.8p ps=17.2u w=8u l=1u +X1 VIN VIN a_n2573_n881# VDD pfet_03v3 ad=4.8p pd=17.2u as=4.8p ps=17.2u w=8u l=1u +X2 VIN VIN a_n2573_n881# VDD pfet_03v3 ad=4.8p pd=17.2u as=4.8p ps=17.2u w=8u l=1u +X3 a_n2573_n881# a_n2573_n881# VDD VDD pfet_03v3 ad=4.8p pd=17.2u as=4.8p ps=17.2u w=8u l=1u +X4 VIN VIN a_n2573_n881# VDD pfet_03v3 ad=4.8p pd=17.2u as=4.8p ps=17.2u w=8u l=1u +X5 a_n2573_n881# a_n2573_n881# VDD VDD pfet_03v3 ad=4.8p pd=17.2u as=4.8p ps=17.2u w=8u l=1u +X6 a_n2573_n881# a_n2573_n881# VDD VDD pfet_03v3 ad=4.8p pd=17.2u as=4.8p ps=17.2u w=8u l=1u +X7 VIN VIN a_n2573_n881# VDD pfet_03v3 ad=4.8p pd=17.2u as=4.8p ps=17.2u w=8u l=1u +X8 VIN VIN a_n2573_n881# VDD pfet_03v3 ad=4.8p pd=17.2u as=4.8p ps=17.2u w=8u l=1u +X9 a_n2573_n881# a_n2573_n881# VDD VDD pfet_03v3 ad=4.8p pd=17.2u as=4.8p ps=17.2u w=8u l=1u +X10 VIN VIN a_n2573_n881# VDD pfet_03v3 ad=4.8p pd=17.2u as=4.8p ps=17.2u w=8u l=1u +X11 a_n2573_n881# a_n2573_n881# VDD VDD pfet_03v3 ad=4.8p pd=17.2u as=4.8p ps=17.2u w=8u l=1u +X12 a_n2573_n881# a_n2573_n881# VDD VDD pfet_03v3 ad=4.8p pd=17.2u as=4.8p ps=17.2u w=8u l=1u +X13 VIN VIN a_n2573_n881# VDD pfet_03v3 ad=4.8p pd=17.2u as=4.8p ps=17.2u w=8u l=1u +X14 a_n2573_n881# a_n2573_n881# VDD VDD pfet_03v3 ad=4.8p pd=17.2u as=4.8p ps=17.2u w=8u l=1u +X15 VIN VIN a_n2573_n881# VDD pfet_03v3 ad=4.8p pd=17.2u as=4.8p ps=17.2u w=8u l=1u +X16 VDD VDD VDD VDD pfet_03v3 ad=4.64p pd=17.16u as=89.92p ps=0.32648m w=8u l=1u +X17 a_n2573_n881# a_n2573_n881# VDD VDD pfet_03v3 ad=4.8p pd=17.2u as=4.8p ps=17.2u w=8u l=1u +X18 a_n2573_n881# a_n2573_n881# VDD VDD pfet_03v3 ad=4.8p pd=17.2u as=4.8p ps=17.2u w=8u l=1u +X19 VDD VDD VDD VDD pfet_03v3 ad=4.64p pd=17.16u as=0 ps=0 w=8u l=1u +X20 VIN VIN a_n2573_n881# VDD pfet_03v3 ad=4.8p pd=17.2u as=4.8p ps=17.2u w=8u l=1u +X21 VIN VIN a_n2573_n881# VDD pfet_03v3 ad=4.8p pd=17.2u as=4.8p ps=17.2u w=8u l=1u +X22 VOUT VIN a_3597_n881# VDD pfet_03v3 ad=4.8p pd=17.2u as=4.8p ps=17.2u w=8u l=1u +X23 a_3597_n881# a_n2573_n881# VDD VDD pfet_03v3 ad=4.8p pd=17.2u as=4.8p ps=17.2u w=8u l=1u +X24 VDD VDD VDD VDD pfet_03v3 ad=4.64p pd=17.16u as=0 ps=0 w=8u l=1u +X25 VDD VDD VDD VDD pfet_03v3 ad=4.64p pd=17.16u as=0 ps=0 w=8u l=1u +.ends + diff --git a/blocks/composite/regulated_cascoded_cmirror/LVS/lvs/BB/BB_pex.spice b/blocks/composite/regulated_cascoded_cmirror/LVS/lvs/BB/BB_pex.spice new file mode 100644 index 00000000..6f2aa508 --- /dev/null +++ b/blocks/composite/regulated_cascoded_cmirror/LVS/lvs/BB/BB_pex.spice @@ -0,0 +1,46 @@ +* NGSPICE file created from BB.ext - technology: gf180mcuD + +.subckt BB VIN VDD VOUT +X0 a_n2573_n881# a_n2573_n881# VDD VDD pfet_03v3 ad=4.8p pd=17.2u as=4.8p ps=17.2u w=8u l=1u +X1 VIN VIN a_n2573_n881# VDD pfet_03v3 ad=4.8p pd=17.2u as=4.8p ps=17.2u w=8u l=1u +X2 VIN VIN a_n2573_n881# VDD pfet_03v3 ad=4.8p pd=17.2u as=4.8p ps=17.2u w=8u l=1u +X3 a_n2573_n881# a_n2573_n881# VDD VDD pfet_03v3 ad=4.8p pd=17.2u as=4.8p ps=17.2u w=8u l=1u +X4 VIN VIN a_n2573_n881# VDD pfet_03v3 ad=4.8p pd=17.2u as=4.8p ps=17.2u w=8u l=1u +X5 a_n2573_n881# a_n2573_n881# VDD VDD pfet_03v3 ad=4.8p pd=17.2u as=4.8p ps=17.2u w=8u l=1u +X6 a_n2573_n881# a_n2573_n881# VDD VDD pfet_03v3 ad=4.8p pd=17.2u as=4.8p ps=17.2u w=8u l=1u +X7 VIN VIN a_n2573_n881# VDD pfet_03v3 ad=4.8p pd=17.2u as=4.8p ps=17.2u w=8u l=1u +X8 VIN VIN a_n2573_n881# VDD pfet_03v3 ad=4.8p pd=17.2u as=4.8p ps=17.2u w=8u l=1u +X9 a_n2573_n881# a_n2573_n881# VDD VDD pfet_03v3 ad=4.8p pd=17.2u as=4.8p ps=17.2u w=8u l=1u +X10 VIN VIN a_n2573_n881# VDD pfet_03v3 ad=4.8p pd=17.2u as=4.8p ps=17.2u w=8u l=1u +X11 a_n2573_n881# a_n2573_n881# VDD VDD pfet_03v3 ad=4.8p pd=17.2u as=4.8p ps=17.2u w=8u l=1u +X12 a_n2573_n881# a_n2573_n881# VDD VDD pfet_03v3 ad=4.8p pd=17.2u as=4.8p ps=17.2u w=8u l=1u +X13 VIN VIN a_n2573_n881# VDD pfet_03v3 ad=4.8p pd=17.2u as=4.8p ps=17.2u w=8u l=1u +X14 a_n2573_n881# a_n2573_n881# VDD VDD pfet_03v3 ad=4.8p pd=17.2u as=4.8p ps=17.2u w=8u l=1u +X15 VIN VIN a_n2573_n881# VDD pfet_03v3 ad=4.8p pd=17.2u as=4.8p ps=17.2u w=8u l=1u +X16 VDD VDD VDD VDD pfet_03v3 ad=4.64p pd=17.16u as=89.92p ps=0.32648m w=8u l=1u +X17 a_n2573_n881# a_n2573_n881# VDD VDD pfet_03v3 ad=4.8p pd=17.2u as=4.8p ps=17.2u w=8u l=1u +X18 a_n2573_n881# a_n2573_n881# VDD VDD pfet_03v3 ad=4.8p pd=17.2u as=4.8p ps=17.2u w=8u l=1u +X19 VDD VDD VDD VDD pfet_03v3 ad=4.64p pd=17.16u as=0 ps=0 w=8u l=1u +X20 VIN VIN a_n2573_n881# VDD pfet_03v3 ad=4.8p pd=17.2u as=4.8p ps=17.2u w=8u l=1u +X21 VIN VIN a_n2573_n881# VDD pfet_03v3 ad=4.8p pd=17.2u as=4.8p ps=17.2u w=8u l=1u +X22 VOUT VIN a_3597_n881# VDD pfet_03v3 ad=4.8p pd=17.2u as=4.8p ps=17.2u w=8u l=1u +X23 a_3597_n881# a_n2573_n881# VDD VDD pfet_03v3 ad=4.8p pd=17.2u as=4.8p ps=17.2u w=8u l=1u +X24 VDD VDD VDD VDD pfet_03v3 ad=4.64p pd=17.16u as=0 ps=0 w=8u l=1u +X25 VDD VDD VDD VDD pfet_03v3 ad=4.64p pd=17.16u as=0 ps=0 w=8u l=1u +C0 VOUT VDD 1.23344f +C1 VOUT VIN 0.28451f +C2 a_n2573_n881# VDD 38.1658f +C3 a_n2573_n881# VIN 26.1742f +C4 VOUT a_3597_n881# 0.98529f +C5 a_n2573_n881# a_3597_n881# 0.69742f +C6 VDD VIN 10.8047f +C7 a_3597_n881# VDD 2.86477f +C8 a_3597_n881# VIN 0.67137f +C9 a_n2573_n881# VOUT 0.0404f +C10 VOUT VSUBS 0.3446f +C11 VIN VSUBS 1.46761f +C12 VDD VSUBS 0.14229p +C13 a_3597_n881# VSUBS 0.29154f +C14 a_n2573_n881# VSUBS 1.45632f +.ends + diff --git a/blocks/composite/regulated_cascoded_cmirror/LVS/lvs/BB/BB_sim.spice b/blocks/composite/regulated_cascoded_cmirror/LVS/lvs/BB/BB_sim.spice new file mode 100644 index 00000000..87047006 --- /dev/null +++ b/blocks/composite/regulated_cascoded_cmirror/LVS/lvs/BB/BB_sim.spice @@ -0,0 +1,47 @@ +| units: 0.5 tech: gf180mcuD format: MIT +x a_n2573_n881# VDD a_n2573_n881# VDD s=192000,3440 d=192000,3440 l=200 w=1600 x=1677 y=1625 pfet_03v3 +x VIN a_n2573_n881# VIN VDD s=192000,3440 d=192000,3440 l=200 w=1600 x=1677 y=-880 pfet_03v3 +x VIN a_n2573_n881# VIN VDD s=192000,3440 d=192000,3440 l=200 w=1600 x=2857 y=-880 pfet_03v3 +x a_n2573_n881# VDD a_n2573_n881# VDD s=192000,3440 d=192000,3440 l=200 w=1600 x=2857 y=1625 pfet_03v3 +x VIN a_n2573_n881# VIN VDD s=192000,3440 d=192000,3440 l=200 w=1600 x=-1862 y=-880 pfet_03v3 +x a_n2573_n881# VDD a_n2573_n881# VDD s=192000,3440 d=192000,3440 l=200 w=1600 x=-1862 y=1625 pfet_03v3 +x a_n2573_n881# VDD a_n2573_n881# VDD s=192000,3440 d=192000,3440 l=200 w=1600 x=1087 y=1625 pfet_03v3 +x VIN a_n2573_n881# VIN VDD s=192000,3440 d=192000,3440 l=200 w=1600 x=1087 y=-880 pfet_03v3 +x VIN a_n2573_n881# VIN VDD s=192000,3440 d=192000,3440 l=200 w=1600 x=2267 y=-880 pfet_03v3 +x a_n2573_n881# VDD a_n2573_n881# VDD s=192000,3440 d=192000,3440 l=200 w=1600 x=2267 y=1625 pfet_03v3 +x VIN a_n2573_n881# VIN VDD s=192000,3440 d=192000,3440 l=200 w=1600 x=-1272 y=-880 pfet_03v3 +x a_n2573_n881# VDD a_n2573_n881# VDD s=192000,3440 d=192000,3440 l=200 w=1600 x=-2452 y=1625 pfet_03v3 +x a_n2573_n881# VDD a_n2573_n881# VDD s=192000,3440 d=192000,3440 l=200 w=1600 x=-1272 y=1625 pfet_03v3 +x VIN a_n2573_n881# VIN VDD s=192000,3440 d=192000,3440 l=200 w=1600 x=-2452 y=-880 pfet_03v3 +x a_n2573_n881# VDD a_n2573_n881# VDD s=192000,3440 d=192000,3440 l=200 w=1600 x=-92 y=1625 pfet_03v3 +x VIN a_n2573_n881# VIN VDD s=192000,3440 d=192000,3440 l=200 w=1600 x=-92 y=-880 pfet_03v3 +x VDD VDD VDD VDD d=185600,3432 l=200 w=1600 x=-3060 y=1625 pfet_03v3 +x a_n2573_n881# VDD a_n2573_n881# VDD s=192000,3440 d=192000,3440 l=200 w=1600 x=-682 y=1625 pfet_03v3 +x a_n2573_n881# VDD a_n2573_n881# VDD s=192000,3440 d=192000,3440 l=200 w=1600 x=497 y=1625 pfet_03v3 +x VDD VDD VDD VDD d=185600,3432 l=200 w=1600 x=-3060 y=-880 pfet_03v3 +x VIN a_n2573_n881# VIN VDD s=192000,3440 d=192000,3440 l=200 w=1600 x=-682 y=-880 pfet_03v3 +x VIN a_n2573_n881# VIN VDD s=192000,3440 d=192000,3440 l=200 w=1600 x=497 y=-880 pfet_03v3 +x VIN a_3597_n881# VOUT VDD s=192000,3440 d=192000,3440 l=200 w=1600 x=3717 y=-880 pfet_03v3 +x a_n2573_n881# VDD a_3597_n881# VDD s=192000,3440 d=192000,3440 l=200 w=1600 x=3717 y=1625 pfet_03v3 +x VDD VDD VDD VDD d=185600,3432 l=200 w=1600 x=4325 y=-880 pfet_03v3 +x VDD VDD VDD VDD d=185600,3432 l=200 w=1600 x=4325 y=1625 pfet_03v3 +C VDD VOUT 1.2 +C VDD VIN 10.8 +C a_n2573_n881# VOUT 0.0 +C a_n2573_n881# VIN 26.2 +C VIN VOUT 0.3 +C VDD a_3597_n881# 2.9 +C a_n2573_n881# a_3597_n881# 0.7 +C a_3597_n881# VOUT 1.0 +C a_3597_n881# VIN 0.7 +C VDD a_n2573_n881# 38.2 +C VOUT0 0.3 +R VOUT 99 +C VIN0 1.5 +R VIN 2035 +C VDD0 142.3 +R VDD 6445 +C a_3597_n881#0 0.3 +R a_3597_n881# 212 +C a_n2573_n881#0 1.5 +R a_n2573_n881# 3161 diff --git a/blocks/composite/regulated_cascoded_cmirror/LVS/lvs/BIAS_STAGE/BIAS_STAGE_lvs.rpt b/blocks/composite/regulated_cascoded_cmirror/LVS/lvs/BIAS_STAGE/BIAS_STAGE_lvs.rpt new file mode 100644 index 00000000..f0b39554 --- /dev/null +++ b/blocks/composite/regulated_cascoded_cmirror/LVS/lvs/BIAS_STAGE/BIAS_STAGE_lvs.rpt @@ -0,0 +1,57 @@ + +Circuit 1 cell nfet_03v3 and Circuit 2 cell nfet_03v3 are black boxes. +Warning: Equate pins: cell nfet_03v3 is a placeholder, treated as a black box. +Warning: Equate pins: cell nfet_03v3 is a placeholder, treated as a black box. + +Subcircuit pins: +Circuit 1: nfet_03v3 |Circuit 2: nfet_03v3 +-------------------------------------------|------------------------------------------- +1 |1 +2 |2 +3 |3 +4 |4 +--------------------------------------------------------------------------------------- +Cell pin lists are equivalent. +Device classes nfet_03v3 and nfet_03v3 are equivalent. + +Circuit 1 cell pfet_03v3 and Circuit 2 cell pfet_03v3 are black boxes. +Warning: Equate pins: cell pfet_03v3 is a placeholder, treated as a black box. +Warning: Equate pins: cell pfet_03v3 is a placeholder, treated as a black box. + +Subcircuit pins: +Circuit 1: pfet_03v3 |Circuit 2: pfet_03v3 +-------------------------------------------|------------------------------------------- +1 |1 +2 |2 +3 |3 +4 |4 +--------------------------------------------------------------------------------------- +Cell pin lists are equivalent. +Device classes pfet_03v3 and pfet_03v3 are equivalent. + +Class BIAS_STAGE (0): Merged 68 parallel devices. +Class BIAS_STAGE (1): Merged 2 parallel devices. +Subcircuit summary: +Circuit 1: BIAS_STAGE |Circuit 2: BIAS_STAGE +-------------------------------------------|------------------------------------------- +nfet_03v3 (26->5) |nfet_03v3 (26->5) +pfet_03v3 (58->11) |pfet_03v3 (58->11) +Number of devices: 16 |Number of devices: 16 +Number of nets: 13 |Number of nets: 13 +--------------------------------------------------------------------------------------- +Netlists match uniquely. + +Subcircuit pins: +Circuit 1: BIAS_STAGE |Circuit 2: BIAS_STAGE +-------------------------------------------|------------------------------------------- +EN |EN +VOUT |VOUT +VIN |VIN +VDD |VDD +VSS |VSS +--------------------------------------------------------------------------------------- +Cell pin lists are equivalent. +Device classes BIAS_STAGE and BIAS_STAGE are equivalent. + +Final result: Circuits match uniquely. +. diff --git a/blocks/composite/regulated_cascoded_cmirror/LVS/lvs/BIAS_STAGE/BIAS_STAGE_lvsmag.spice b/blocks/composite/regulated_cascoded_cmirror/LVS/lvs/BIAS_STAGE/BIAS_STAGE_lvsmag.spice new file mode 100644 index 00000000..3b17d107 --- /dev/null +++ b/blocks/composite/regulated_cascoded_cmirror/LVS/lvs/BIAS_STAGE/BIAS_STAGE_lvsmag.spice @@ -0,0 +1,89 @@ +* NGSPICE file created from BIAS_STAGE.ext - technology: gf180mcuD + +.subckt BIAS_STAGE VIN VSS VDD VOUT EN +X0 a_n6357_n2535# a_n6357_n2535# a_n3305_371# VSS nfet_03v3 ad=4.8p pd=17.2u as=4.8p ps=17.2u w=8u l=1u +X1 a_n6357_n2535# a_n6357_n2535# a_n3305_371# VSS nfet_03v3 ad=4.8p pd=17.2u as=4.8p ps=17.2u w=8u l=1u +X2 a_n15047_n2535# a_n15047_n2535# VDD VDD pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X3 VIN VIN a_n15047_n2535# VDD pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X4 VDD VDD VDD VDD pfet_03v3 ad=5.8p pd=21.16u as=0.2832n ps=1.01664m w=10u l=2u +X5 a_n6357_n2535# a_n6357_n2535# a_n3305_371# VSS nfet_03v3 ad=4.8p pd=17.2u as=4.8p ps=17.2u w=8u l=1u +X6 a_n3305_371# a_n3305_371# VSS VSS nfet_03v3 ad=4.8p pd=17.2u as=4.8p ps=17.2u w=8u l=1u +X7 VDD VDD VDD VDD pfet_03v3 ad=5.8p pd=21.16u as=0 ps=0 w=10u l=2u +X8 VOUT a_3185_371# a_14407_n2535# VDD pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X9 a_n15047_n2535# a_n15047_n2535# VDD VDD pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X10 VSS VSS VSS VSS nfet_03v3 ad=4.64p pd=17.16u as=89.92p ps=0.32648m w=8u l=1u +X11 a_6237_n2535# a_6237_n2535# VDD VDD pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X12 a_n15047_n2535# a_n15047_n2535# VDD VDD pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X13 a_3185_371# a_n6357_n2535# a_2865_371# VSS nfet_03v3 ad=4.8p pd=17.2u as=4.8p ps=17.2u w=8u l=1u +X14 a_2865_371# a_n3305_371# VSS VSS nfet_03v3 ad=4.8p pd=17.2u as=4.8p ps=17.2u w=8u l=1u +X15 VDD VDD VDD VDD pfet_03v3 ad=5.8p pd=21.16u as=0 ps=0 w=10u l=2u +X16 a_6237_n2535# a_6237_n2535# VDD VDD pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X17 a_3185_371# a_3185_371# a_6237_n2535# VDD pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X18 a_n15047_n2535# a_n15047_n2535# VDD VDD pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X19 a_n3305_371# a_n3305_371# VSS VSS nfet_03v3 ad=4.8p pd=17.2u as=4.8p ps=17.2u w=8u l=1u +X20 a_6237_n2535# a_6237_n2535# VDD VDD pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X21 a_3185_371# a_3185_371# a_6237_n2535# VDD pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X22 VIN VIN a_n15047_n2535# VDD pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X23 a_n3305_371# a_n3305_371# VSS VSS nfet_03v3 ad=4.8p pd=17.2u as=4.8p ps=17.2u w=8u l=1u +X24 VDD VDD VDD VDD pfet_03v3 ad=5.8p pd=21.16u as=0 ps=0 w=10u l=2u +X25 a_n6357_n2535# a_n6357_n2535# a_n3305_371# VSS nfet_03v3 ad=4.8p pd=17.2u as=4.8p ps=17.2u w=8u l=1u +X26 a_n3305_371# a_n3305_371# VSS VSS nfet_03v3 ad=4.8p pd=17.2u as=4.8p ps=17.2u w=8u l=1u +X27 a_14407_n2535# a_6237_n2535# VDD VDD pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X28 a_n3305_371# a_n3305_371# VSS VSS nfet_03v3 ad=4.8p pd=17.2u as=4.8p ps=17.2u w=8u l=1u +X29 VDD VDD VDD VDD pfet_03v3 ad=5.8p pd=21.16u as=0 ps=0 w=10u l=2u +X30 VIN VIN a_n15047_n2535# VDD pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X31 a_n6357_n2535# a_n6357_n2535# a_n3305_371# VSS nfet_03v3 ad=4.8p pd=17.2u as=4.8p ps=17.2u w=8u l=1u +X32 a_n3305_371# a_n3305_371# VSS VSS nfet_03v3 ad=4.8p pd=17.2u as=4.8p ps=17.2u w=8u l=1u +X33 VDD VDD VDD VDD pfet_03v3 ad=5.8p pd=21.16u as=0 ps=0 w=10u l=2u +X34 a_6237_n2535# a_6237_n2535# VDD VDD pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X35 a_3185_371# a_3185_371# a_6237_n2535# VDD pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X36 a_3185_371# a_3185_371# a_6237_n2535# VDD pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X37 VDD VDD VDD VDD pfet_03v3 ad=5.8p pd=21.16u as=0 ps=0 w=10u l=2u +X38 a_n15047_n2535# a_n15047_n2535# VDD VDD pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X39 VIN VIN a_n15047_n2535# VDD pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X40 VIN VIN a_n15047_n2535# VDD pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X41 VSS VSS VSS VSS nfet_03v3 ad=4.64p pd=17.16u as=0 ps=0 w=8u l=1u +X42 a_n3305_371# a_n3305_371# VSS VSS nfet_03v3 ad=4.8p pd=17.2u as=4.8p ps=17.2u w=8u l=1u +X43 a_3185_371# a_3185_371# a_6237_n2535# VDD pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X44 a_n6357_n2535# a_n6357_n2535# a_n3305_371# VSS nfet_03v3 ad=4.8p pd=17.2u as=4.8p ps=17.2u w=8u l=1u +X45 VDD VDD VDD VDD pfet_03v3 ad=5.8p pd=21.16u as=0 ps=0 w=10u l=2u +X46 a_n6357_n2535# VIN a_n6877_n2535# VDD pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X47 VSS VSS VSS VSS nfet_03v3 ad=4.64p pd=17.16u as=0 ps=0 w=8u l=1u +X48 a_n6357_n2535# a_n6357_n2535# a_n3305_371# VSS nfet_03v3 ad=4.8p pd=17.2u as=4.8p ps=17.2u w=8u l=1u +X49 a_6237_n2535# a_6237_n2535# VDD VDD pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X50 a_6237_n2535# a_6237_n2535# VDD VDD pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X51 a_n15047_n2535# a_n15047_n2535# VDD VDD pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X52 a_n6877_n2535# a_n15047_n2535# VDD VDD pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X53 VDD VDD VDD VDD pfet_03v3 ad=5.8p pd=21.16u as=0 ps=0 w=10u l=2u +X54 VIN VIN a_n15047_n2535# VDD pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X55 a_n3305_371# a_n3305_371# VSS VSS nfet_03v3 ad=4.8p pd=17.2u as=4.8p ps=17.2u w=8u l=1u +X56 a_n15047_n2535# EN VDD VDD pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X57 a_n15047_n2535# a_n15047_n2535# VDD VDD pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X58 VIN VIN a_n15047_n2535# VDD pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X59 a_n3305_371# a_n3305_371# VSS VSS nfet_03v3 ad=4.8p pd=17.2u as=4.8p ps=17.2u w=8u l=1u +X60 a_6237_n2535# a_6237_n2535# VDD VDD pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X61 a_n15047_n2535# a_n15047_n2535# VDD VDD pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X62 a_n3305_371# a_n3305_371# VSS VSS nfet_03v3 ad=4.8p pd=17.2u as=4.8p ps=17.2u w=8u l=1u +X63 a_6237_n2535# a_6237_n2535# VDD VDD pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X64 a_6237_n2535# EN VDD VDD pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X65 a_n6357_n2535# a_n6357_n2535# a_n3305_371# VSS nfet_03v3 ad=4.8p pd=17.2u as=4.8p ps=17.2u w=8u l=1u +X66 VSS VSS VSS VSS nfet_03v3 ad=4.64p pd=17.16u as=0 ps=0 w=8u l=1u +X67 a_6237_n2535# a_6237_n2535# VDD VDD pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X68 a_6237_n2535# a_6237_n2535# VDD VDD pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X69 a_3185_371# a_3185_371# a_6237_n2535# VDD pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X70 a_3185_371# a_3185_371# a_6237_n2535# VDD pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X71 a_3185_371# a_3185_371# a_6237_n2535# VDD pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X72 a_n15047_n2535# a_n15047_n2535# VDD VDD pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X73 VIN VIN a_n15047_n2535# VDD pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X74 VIN VIN a_n15047_n2535# VDD pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X75 a_n6357_n2535# a_n6357_n2535# a_n3305_371# VSS nfet_03v3 ad=4.8p pd=17.2u as=4.8p ps=17.2u w=8u l=1u +X76 a_n6357_n2535# a_n6357_n2535# a_n3305_371# VSS nfet_03v3 ad=4.8p pd=17.2u as=4.8p ps=17.2u w=8u l=1u +X77 VDD VDD VDD VDD pfet_03v3 ad=5.8p pd=21.16u as=0 ps=0 w=10u l=2u +X78 a_3185_371# a_3185_371# a_6237_n2535# VDD pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X79 a_n15047_n2535# a_n15047_n2535# VDD VDD pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X80 VDD VDD VDD VDD pfet_03v3 ad=5.8p pd=21.16u as=0 ps=0 w=10u l=2u +X81 VIN VIN a_n15047_n2535# VDD pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X82 a_3185_371# a_3185_371# a_6237_n2535# VDD pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X83 VDD VDD VDD VDD pfet_03v3 ad=5.8p pd=21.16u as=0 ps=0 w=10u l=2u +.ends + diff --git a/blocks/composite/regulated_cascoded_cmirror/LVS/lvs/BIAS_STAGE/BIAS_STAGE_pex.spice b/blocks/composite/regulated_cascoded_cmirror/LVS/lvs/BIAS_STAGE/BIAS_STAGE_pex.spice new file mode 100644 index 00000000..9aba4137 --- /dev/null +++ b/blocks/composite/regulated_cascoded_cmirror/LVS/lvs/BIAS_STAGE/BIAS_STAGE_pex.spice @@ -0,0 +1,132 @@ +* NGSPICE file created from BIAS_STAGE.ext - technology: gf180mcuD + +.subckt BIAS_STAGE VIN VSS VDD VOUT EN +X0 a_n6357_n2535# a_n6357_n2535# a_n3305_371# VSS nfet_03v3 ad=4.8p pd=17.2u as=4.8p ps=17.2u w=8u l=1u +X1 a_n6357_n2535# a_n6357_n2535# a_n3305_371# VSS nfet_03v3 ad=4.8p pd=17.2u as=4.8p ps=17.2u w=8u l=1u +X2 a_n15047_n2535# a_n15047_n2535# VDD VDD pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X3 VIN VIN a_n15047_n2535# VDD pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X4 VDD VDD VDD VDD pfet_03v3 ad=5.8p pd=21.16u as=0.2832n ps=1.01664m w=10u l=2u +X5 a_n6357_n2535# a_n6357_n2535# a_n3305_371# VSS nfet_03v3 ad=4.8p pd=17.2u as=4.8p ps=17.2u w=8u l=1u +X6 a_n3305_371# a_n3305_371# VSS VSS nfet_03v3 ad=4.8p pd=17.2u as=4.8p ps=17.2u w=8u l=1u +X7 VDD VDD VDD VDD pfet_03v3 ad=5.8p pd=21.16u as=0 ps=0 w=10u l=2u +X8 VOUT a_3185_371# a_14407_n2535# VDD pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X9 a_n15047_n2535# a_n15047_n2535# VDD VDD pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X10 VSS VSS VSS VSS nfet_03v3 ad=4.64p pd=17.16u as=89.92p ps=0.32648m w=8u l=1u +X11 a_6237_n2535# a_6237_n2535# VDD VDD pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X12 a_n15047_n2535# a_n15047_n2535# VDD VDD pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X13 a_3185_371# a_n6357_n2535# a_2865_371# VSS nfet_03v3 ad=4.8p pd=17.2u as=4.8p ps=17.2u w=8u l=1u +X14 a_2865_371# a_n3305_371# VSS VSS nfet_03v3 ad=4.8p pd=17.2u as=4.8p ps=17.2u w=8u l=1u +X15 VDD VDD VDD VDD pfet_03v3 ad=5.8p pd=21.16u as=0 ps=0 w=10u l=2u +X16 a_6237_n2535# a_6237_n2535# VDD VDD pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X17 a_3185_371# a_3185_371# a_6237_n2535# VDD pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X18 a_n15047_n2535# a_n15047_n2535# VDD VDD pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X19 a_n3305_371# a_n3305_371# VSS VSS nfet_03v3 ad=4.8p pd=17.2u as=4.8p ps=17.2u w=8u l=1u +X20 a_6237_n2535# a_6237_n2535# VDD VDD pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X21 a_3185_371# a_3185_371# a_6237_n2535# VDD pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X22 VIN VIN a_n15047_n2535# VDD pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X23 a_n3305_371# a_n3305_371# VSS VSS nfet_03v3 ad=4.8p pd=17.2u as=4.8p ps=17.2u w=8u l=1u +X24 VDD VDD VDD VDD pfet_03v3 ad=5.8p pd=21.16u as=0 ps=0 w=10u l=2u +X25 a_n6357_n2535# a_n6357_n2535# a_n3305_371# VSS nfet_03v3 ad=4.8p pd=17.2u as=4.8p ps=17.2u w=8u l=1u +X26 a_n3305_371# a_n3305_371# VSS VSS nfet_03v3 ad=4.8p pd=17.2u as=4.8p ps=17.2u w=8u l=1u +X27 a_14407_n2535# a_6237_n2535# VDD VDD pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X28 a_n3305_371# a_n3305_371# VSS VSS nfet_03v3 ad=4.8p pd=17.2u as=4.8p ps=17.2u w=8u l=1u +X29 VDD VDD VDD VDD pfet_03v3 ad=5.8p pd=21.16u as=0 ps=0 w=10u l=2u +X30 VIN VIN a_n15047_n2535# VDD pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X31 a_n6357_n2535# a_n6357_n2535# a_n3305_371# VSS nfet_03v3 ad=4.8p pd=17.2u as=4.8p ps=17.2u w=8u l=1u +X32 a_n3305_371# a_n3305_371# VSS VSS nfet_03v3 ad=4.8p pd=17.2u as=4.8p ps=17.2u w=8u l=1u +X33 VDD VDD VDD VDD pfet_03v3 ad=5.8p pd=21.16u as=0 ps=0 w=10u l=2u +X34 a_6237_n2535# a_6237_n2535# VDD VDD pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X35 a_3185_371# a_3185_371# a_6237_n2535# VDD pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X36 a_3185_371# a_3185_371# a_6237_n2535# VDD pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X37 VDD VDD VDD VDD pfet_03v3 ad=5.8p pd=21.16u as=0 ps=0 w=10u l=2u +X38 a_n15047_n2535# a_n15047_n2535# VDD VDD pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X39 VIN VIN a_n15047_n2535# VDD pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X40 VIN VIN a_n15047_n2535# VDD pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X41 VSS VSS VSS VSS nfet_03v3 ad=4.64p pd=17.16u as=0 ps=0 w=8u l=1u +X42 a_n3305_371# a_n3305_371# VSS VSS nfet_03v3 ad=4.8p pd=17.2u as=4.8p ps=17.2u w=8u l=1u +X43 a_3185_371# a_3185_371# a_6237_n2535# VDD pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X44 a_n6357_n2535# a_n6357_n2535# a_n3305_371# VSS nfet_03v3 ad=4.8p pd=17.2u as=4.8p ps=17.2u w=8u l=1u +X45 VDD VDD VDD VDD pfet_03v3 ad=5.8p pd=21.16u as=0 ps=0 w=10u l=2u +X46 a_n6357_n2535# VIN a_n6877_n2535# VDD pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X47 VSS VSS VSS VSS nfet_03v3 ad=4.64p pd=17.16u as=0 ps=0 w=8u l=1u +X48 a_n6357_n2535# a_n6357_n2535# a_n3305_371# VSS nfet_03v3 ad=4.8p pd=17.2u as=4.8p ps=17.2u w=8u l=1u +X49 a_6237_n2535# a_6237_n2535# VDD VDD pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X50 a_6237_n2535# a_6237_n2535# VDD VDD pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X51 a_n15047_n2535# a_n15047_n2535# VDD VDD pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X52 a_n6877_n2535# a_n15047_n2535# VDD VDD pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X53 VDD VDD VDD VDD pfet_03v3 ad=5.8p pd=21.16u as=0 ps=0 w=10u l=2u +X54 VIN VIN a_n15047_n2535# VDD pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X55 a_n3305_371# a_n3305_371# VSS VSS nfet_03v3 ad=4.8p pd=17.2u as=4.8p ps=17.2u w=8u l=1u +X56 a_n15047_n2535# EN VDD VDD pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X57 a_n15047_n2535# a_n15047_n2535# VDD VDD pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X58 VIN VIN a_n15047_n2535# VDD pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X59 a_n3305_371# a_n3305_371# VSS VSS nfet_03v3 ad=4.8p pd=17.2u as=4.8p ps=17.2u w=8u l=1u +X60 a_6237_n2535# a_6237_n2535# VDD VDD pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X61 a_n15047_n2535# a_n15047_n2535# VDD VDD pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X62 a_n3305_371# a_n3305_371# VSS VSS nfet_03v3 ad=4.8p pd=17.2u as=4.8p ps=17.2u w=8u l=1u +X63 a_6237_n2535# a_6237_n2535# VDD VDD pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X64 a_6237_n2535# EN VDD VDD pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X65 a_n6357_n2535# a_n6357_n2535# a_n3305_371# VSS nfet_03v3 ad=4.8p pd=17.2u as=4.8p ps=17.2u w=8u l=1u +X66 VSS VSS VSS VSS nfet_03v3 ad=4.64p pd=17.16u as=0 ps=0 w=8u l=1u +X67 a_6237_n2535# a_6237_n2535# VDD VDD pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X68 a_6237_n2535# a_6237_n2535# VDD VDD pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X69 a_3185_371# a_3185_371# a_6237_n2535# VDD pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X70 a_3185_371# a_3185_371# a_6237_n2535# VDD pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X71 a_3185_371# a_3185_371# a_6237_n2535# VDD pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X72 a_n15047_n2535# a_n15047_n2535# VDD VDD pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X73 VIN VIN a_n15047_n2535# VDD pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X74 VIN VIN a_n15047_n2535# VDD pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X75 a_n6357_n2535# a_n6357_n2535# a_n3305_371# VSS nfet_03v3 ad=4.8p pd=17.2u as=4.8p ps=17.2u w=8u l=1u +X76 a_n6357_n2535# a_n6357_n2535# a_n3305_371# VSS nfet_03v3 ad=4.8p pd=17.2u as=4.8p ps=17.2u w=8u l=1u +X77 VDD VDD VDD VDD pfet_03v3 ad=5.8p pd=21.16u as=0 ps=0 w=10u l=2u +X78 a_3185_371# a_3185_371# a_6237_n2535# VDD pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X79 a_n15047_n2535# a_n15047_n2535# VDD VDD pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X80 VDD VDD VDD VDD pfet_03v3 ad=5.8p pd=21.16u as=0 ps=0 w=10u l=2u +X81 VIN VIN a_n15047_n2535# VDD pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X82 a_3185_371# a_3185_371# a_6237_n2535# VDD pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X83 VDD VDD VDD VDD pfet_03v3 ad=5.8p pd=21.16u as=0 ps=0 w=10u l=2u +C0 a_3185_371# EN 0.01792f +C1 VOUT VDD 1.49117f +C2 a_n6357_n2535# a_2865_371# 0.86502f +C3 a_6237_n2535# VDD 48.8548f +C4 a_n15047_n2535# EN 0.74385f +C5 a_n15047_n2535# VIN 29.4793f +C6 a_3185_371# a_14407_n2535# 0.99903f +C7 EN VDD 6.10265f +C8 VIN VDD 15.1595f +C9 a_n6357_n2535# EN 0.01947f +C10 VOUT a_6237_n2535# 0.06695f +C11 a_n6357_n2535# VIN 0.50349f +C12 a_n15047_n2535# a_n6877_n2535# 0.98664f +C13 VDD a_n6877_n2535# 3.05677f +C14 a_n6357_n2535# a_n6877_n2535# 0.91714f +C15 EN a_6237_n2535# 0.70482f +C16 a_14407_n2535# VDD 3.05677f +C17 a_n6357_n2535# a_n3305_371# 36.6185f +C18 a_3185_371# VDD 15.4991f +C19 a_3185_371# a_n6357_n2535# 0.28491f +C20 VOUT a_14407_n2535# 0.8533f +C21 a_n3305_371# a_2865_371# 0.52252f +C22 VOUT a_3185_371# 0.50349f +C23 a_3185_371# a_2865_371# 1.13981f +C24 a_14407_n2535# a_6237_n2535# 0.98664f +C25 a_n15047_n2535# VDD 48.844f +C26 a_3185_371# a_6237_n2535# 29.4825f +C27 a_n6357_n2535# a_n15047_n2535# 0.07017f +C28 EN a_n6877_n2535# 0 +C29 VIN a_n6877_n2535# 0.99903f +C30 a_n6357_n2535# VDD 1.76606f +C31 VOUT VSS 0.40915f +C32 VIN VSS 2.742f +C33 EN VSS 6.69503f +C34 VDD VSS 0.53837p +C35 a_14407_n2535# VSS 0.29335f +C36 a_3185_371# VSS 4.92841f +C37 a_2865_371# VSS 2.7563f +C38 a_n3305_371# VSS 40.1544f +C39 a_n6357_n2535# VSS 12.9171f +C40 a_n6877_n2535# VSS 0.20081f +C41 a_6237_n2535# VSS 3.25173f +C42 a_n15047_n2535# VSS 3.2286f +.ends + diff --git a/blocks/composite/regulated_cascoded_cmirror/LVS/lvs/BIAS_STAGE/BIAS_STAGE_sim.spice b/blocks/composite/regulated_cascoded_cmirror/LVS/lvs/BIAS_STAGE/BIAS_STAGE_sim.spice new file mode 100644 index 00000000..4f32f12c --- /dev/null +++ b/blocks/composite/regulated_cascoded_cmirror/LVS/lvs/BIAS_STAGE/BIAS_STAGE_sim.spice @@ -0,0 +1,141 @@ +| units: 0.5 tech: gf180mcuD format: MIT +x a_n6357_n2535# a_n3305_371# a_n6357_n2535# VSS s=192000,3440 d=192000,3440 l=200 w=1600 x=-3184 y=371 nfet_03v3 +x a_n6357_n2535# a_n3305_371# a_n6357_n2535# VSS s=192000,3440 d=192000,3440 l=200 w=1600 x=-824 y=371 nfet_03v3 +x a_n15047_n2535# VDD a_n15047_n2535# VDD s=240000,4240 d=240000,4240 l=400 w=2000 x=-14136 y=371 pfet_03v3 +x VIN a_n15047_n2535# VIN VDD s=240000,4240 d=240000,4240 l=400 w=2000 x=-12556 y=-2534 pfet_03v3 +x VDD VDD VDD VDD d=232000,4232 l=400 w=2000 x=-5948 y=-2534 pfet_03v3 +x a_n6357_n2535# a_n3305_371# a_n6357_n2535# VSS s=192000,3440 d=192000,3440 l=200 w=1600 x=2125 y=371 nfet_03v3 +x a_n3305_371# VSS a_n3305_371# VSS s=192000,3440 d=192000,3440 l=200 w=1600 x=-824 y=-2134 nfet_03v3 +x VDD VDD VDD VDD d=232000,4232 l=400 w=2000 x=15335 y=371 pfet_03v3 +x a_3185_371# a_14407_n2535# VOUT VDD s=240000,4240 d=240000,4240 l=400 w=2000 x=14527 y=-2534 pfet_03v3 +x a_n15047_n2535# VDD a_n15047_n2535# VDD s=240000,4240 d=240000,4240 l=400 w=2000 x=-9396 y=371 pfet_03v3 +x VSS VSS VSS VSS d=185600,3432 l=200 w=1600 x=-3792 y=-2134 nfet_03v3 +x a_6237_n2535# VDD a_6237_n2535# VDD s=240000,4240 d=240000,4240 l=400 w=2000 x=6357 y=371 pfet_03v3 +x a_n15047_n2535# VDD a_n15047_n2535# VDD s=240000,4240 d=240000,4240 l=400 w=2000 x=-7816 y=371 pfet_03v3 +x a_n6357_n2535# a_2865_371# a_3185_371# VSS s=192000,3440 d=192000,3440 l=200 w=1600 x=2985 y=371 nfet_03v3 +x a_n3305_371# VSS a_2865_371# VSS s=192000,3440 d=192000,3440 l=200 w=1600 x=2985 y=-2134 nfet_03v3 +x VDD VDD VDD VDD d=232000,4232 l=400 w=2000 x=5549 y=4069 pfet_03v3 +x a_6237_n2535# VDD a_6237_n2535# VDD s=240000,4240 d=240000,4240 l=400 w=2000 x=8727 y=371 pfet_03v3 +x a_3185_371# a_6237_n2535# a_3185_371# VDD s=240000,4240 d=240000,4240 l=400 w=2000 x=13467 y=-2534 pfet_03v3 +x a_n15047_n2535# VDD a_n15047_n2535# VDD s=240000,4240 d=240000,4240 l=400 w=2000 x=-11766 y=371 pfet_03v3 +x a_n3305_371# VSS a_n3305_371# VSS s=192000,3440 d=192000,3440 l=200 w=1600 x=945 y=-2134 nfet_03v3 +x a_6237_n2535# VDD a_6237_n2535# VDD s=240000,4240 d=240000,4240 l=400 w=2000 x=12677 y=371 pfet_03v3 +x a_3185_371# a_6237_n2535# a_3185_371# VDD s=240000,4240 d=240000,4240 l=400 w=2000 x=9517 y=-2534 pfet_03v3 +x VIN a_n15047_n2535# VIN VDD s=240000,4240 d=240000,4240 l=400 w=2000 x=-10976 y=-2534 pfet_03v3 +x a_n3305_371# VSS a_n3305_371# VSS s=192000,3440 d=192000,3440 l=200 w=1600 x=-3184 y=-2134 nfet_03v3 +x VDD VDD VDD VDD d=232000,4232 l=400 w=2000 x=-15734 y=4069 pfet_03v3 +x a_n6357_n2535# a_n3305_371# a_n6357_n2535# VSS s=192000,3440 d=192000,3440 l=200 w=1600 x=945 y=371 nfet_03v3 +x a_n3305_371# VSS a_n3305_371# VSS s=192000,3440 d=192000,3440 l=200 w=1600 x=2125 y=-2134 nfet_03v3 +x a_6237_n2535# VDD a_14407_n2535# VDD s=240000,4240 d=240000,4240 l=400 w=2000 x=14527 y=371 pfet_03v3 +x a_n3305_371# VSS a_n3305_371# VSS s=192000,3440 d=192000,3440 l=200 w=1600 x=-2004 y=-2134 nfet_03v3 +x VDD VDD VDD VDD d=232000,4232 l=400 w=2000 x=7165 y=4069 pfet_03v3 +x VIN a_n15047_n2535# VIN VDD s=240000,4240 d=240000,4240 l=400 w=2000 x=-14926 y=-2534 pfet_03v3 +x a_n6357_n2535# a_n3305_371# a_n6357_n2535# VSS s=192000,3440 d=192000,3440 l=200 w=1600 x=-1414 y=371 nfet_03v3 +x a_n3305_371# VSS a_n3305_371# VSS s=192000,3440 d=192000,3440 l=200 w=1600 x=-234 y=-2134 nfet_03v3 +x VDD VDD VDD VDD d=232000,4232 l=400 w=2000 x=5549 y=371 pfet_03v3 +x a_6237_n2535# VDD a_6237_n2535# VDD s=240000,4240 d=240000,4240 l=400 w=2000 x=10307 y=371 pfet_03v3 +x a_3185_371# a_6237_n2535# a_3185_371# VDD s=240000,4240 d=240000,4240 l=400 w=2000 x=7937 y=-2534 pfet_03v3 +x a_3185_371# a_6237_n2535# a_3185_371# VDD s=240000,4240 d=240000,4240 l=400 w=2000 x=11887 y=-2534 pfet_03v3 +x VDD VDD VDD VDD d=232000,4232 l=400 w=2000 x=-14118 y=4069 pfet_03v3 +x a_n15047_n2535# VDD a_n15047_n2535# VDD s=240000,4240 d=240000,4240 l=400 w=2000 x=-13346 y=371 pfet_03v3 +x VIN a_n15047_n2535# VIN VDD s=240000,4240 d=240000,4240 l=400 w=2000 x=-13346 y=-2534 pfet_03v3 +x VIN a_n15047_n2535# VIN VDD s=240000,4240 d=240000,4240 l=400 w=2000 x=-7816 y=-2534 pfet_03v3 +x VSS VSS VSS VSS d=185600,3432 l=200 w=1600 x=3593 y=371 nfet_03v3 +x a_n3305_371# VSS a_n3305_371# VSS s=192000,3440 d=192000,3440 l=200 w=1600 x=355 y=-2134 nfet_03v3 +x a_3185_371# a_6237_n2535# a_3185_371# VDD s=240000,4240 d=240000,4240 l=400 w=2000 x=6357 y=-2534 pfet_03v3 +x a_n6357_n2535# a_n3305_371# a_n6357_n2535# VSS s=192000,3440 d=192000,3440 l=200 w=1600 x=-234 y=371 nfet_03v3 +x VDD VDD VDD VDD d=232000,4232 l=400 w=2000 x=15335 y=-2534 pfet_03v3 +x VIN a_n6877_n2535# a_n6357_n2535# VDD s=240000,4240 d=240000,4240 l=400 w=2000 x=-6756 y=-2534 pfet_03v3 +x VSS VSS VSS VSS d=185600,3432 l=200 w=1600 x=-3792 y=371 nfet_03v3 +x a_n6357_n2535# a_n3305_371# a_n6357_n2535# VSS s=192000,3440 d=192000,3440 l=200 w=1600 x=-2004 y=371 nfet_03v3 +x a_6237_n2535# VDD a_6237_n2535# VDD s=240000,4240 d=240000,4240 l=400 w=2000 x=7937 y=371 pfet_03v3 +x a_6237_n2535# VDD a_6237_n2535# VDD s=240000,4240 d=240000,4240 l=400 w=2000 x=11887 y=371 pfet_03v3 +x a_n15047_n2535# VDD a_n15047_n2535# VDD s=240000,4240 d=240000,4240 l=400 w=2000 x=-10976 y=371 pfet_03v3 +x a_n15047_n2535# VDD a_n6877_n2535# VDD s=240000,4240 d=240000,4240 l=400 w=2000 x=-6756 y=371 pfet_03v3 +x VDD VDD VDD VDD d=232000,4232 l=400 w=2000 x=-15734 y=371 pfet_03v3 +x VIN a_n15047_n2535# VIN VDD s=240000,4240 d=240000,4240 l=400 w=2000 x=-11766 y=-2534 pfet_03v3 +x a_n3305_371# VSS a_n3305_371# VSS s=192000,3440 d=192000,3440 l=200 w=1600 x=-2594 y=-2134 nfet_03v3 +x EN VDD a_n15047_n2535# VDD s=240000,4240 d=240000,4240 l=400 w=2000 x=-14926 y=4069 pfet_03v3 +x a_n15047_n2535# VDD a_n15047_n2535# VDD s=240000,4240 d=240000,4240 l=400 w=2000 x=-8606 y=371 pfet_03v3 +x VIN a_n15047_n2535# VIN VDD s=240000,4240 d=240000,4240 l=400 w=2000 x=-10186 y=-2534 pfet_03v3 +x a_n3305_371# VSS a_n3305_371# VSS s=192000,3440 d=192000,3440 l=200 w=1600 x=1535 y=-2134 nfet_03v3 +x a_6237_n2535# VDD a_6237_n2535# VDD s=240000,4240 d=240000,4240 l=400 w=2000 x=7147 y=371 pfet_03v3 +x a_n15047_n2535# VDD a_n15047_n2535# VDD s=240000,4240 d=240000,4240 l=400 w=2000 x=-10186 y=371 pfet_03v3 +x a_n3305_371# VSS a_n3305_371# VSS s=192000,3440 d=192000,3440 l=200 w=1600 x=-1414 y=-2134 nfet_03v3 +x a_6237_n2535# VDD a_6237_n2535# VDD s=240000,4240 d=240000,4240 l=400 w=2000 x=11097 y=371 pfet_03v3 +x EN VDD a_6237_n2535# VDD s=240000,4240 d=240000,4240 l=400 w=2000 x=6357 y=4069 pfet_03v3 +x a_n6357_n2535# a_n3305_371# a_n6357_n2535# VSS s=192000,3440 d=192000,3440 l=200 w=1600 x=-2594 y=371 nfet_03v3 +x VSS VSS VSS VSS d=185600,3432 l=200 w=1600 x=3593 y=-2134 nfet_03v3 +x a_6237_n2535# VDD a_6237_n2535# VDD s=240000,4240 d=240000,4240 l=400 w=2000 x=9517 y=371 pfet_03v3 +x a_6237_n2535# VDD a_6237_n2535# VDD s=240000,4240 d=240000,4240 l=400 w=2000 x=13467 y=371 pfet_03v3 +x a_3185_371# a_6237_n2535# a_3185_371# VDD s=240000,4240 d=240000,4240 l=400 w=2000 x=8727 y=-2534 pfet_03v3 +x a_3185_371# a_6237_n2535# a_3185_371# VDD s=240000,4240 d=240000,4240 l=400 w=2000 x=10307 y=-2534 pfet_03v3 +x a_3185_371# a_6237_n2535# a_3185_371# VDD s=240000,4240 d=240000,4240 l=400 w=2000 x=12677 y=-2534 pfet_03v3 +x a_n15047_n2535# VDD a_n15047_n2535# VDD s=240000,4240 d=240000,4240 l=400 w=2000 x=-12556 y=371 pfet_03v3 +x VIN a_n15047_n2535# VIN VDD s=240000,4240 d=240000,4240 l=400 w=2000 x=-14136 y=-2534 pfet_03v3 +x VIN a_n15047_n2535# VIN VDD s=240000,4240 d=240000,4240 l=400 w=2000 x=-8606 y=-2534 pfet_03v3 +x a_n6357_n2535# a_n3305_371# a_n6357_n2535# VSS s=192000,3440 d=192000,3440 l=200 w=1600 x=355 y=371 nfet_03v3 +x a_n6357_n2535# a_n3305_371# a_n6357_n2535# VSS s=192000,3440 d=192000,3440 l=200 w=1600 x=1535 y=371 nfet_03v3 +x VDD VDD VDD VDD d=232000,4232 l=400 w=2000 x=-15734 y=-2534 pfet_03v3 +x a_3185_371# a_6237_n2535# a_3185_371# VDD s=240000,4240 d=240000,4240 l=400 w=2000 x=11097 y=-2534 pfet_03v3 +x a_n15047_n2535# VDD a_n15047_n2535# VDD s=240000,4240 d=240000,4240 l=400 w=2000 x=-14926 y=371 pfet_03v3 +x VDD VDD VDD VDD d=232000,4232 l=400 w=2000 x=-5948 y=371 pfet_03v3 +x VIN a_n15047_n2535# VIN VDD s=240000,4240 d=240000,4240 l=400 w=2000 x=-9396 y=-2534 pfet_03v3 +x a_3185_371# a_6237_n2535# a_3185_371# VDD s=240000,4240 d=240000,4240 l=400 w=2000 x=7147 y=-2534 pfet_03v3 +x VDD VDD VDD VDD d=232000,4232 l=400 w=2000 x=5549 y=-2534 pfet_03v3 +C a_n6357_n2535# a_n3305_371# 36.6 +C VDD a_n6877_n2535# 3.1 +C EN a_n6877_n2535# 0.0 +C VOUT a_14407_n2535# 0.9 +C a_n15047_n2535# VDD 48.8 +C EN a_n15047_n2535# 0.7 +C a_14407_n2535# VDD 3.1 +C a_n6357_n2535# VIN 0.5 +C a_3185_371# a_14407_n2535# 1.0 +C a_3185_371# a_2865_371# 1.1 +C VOUT VDD 1.5 +C a_n6357_n2535# a_n6877_n2535# 0.9 +C EN VDD 6.1 +C VIN a_n6877_n2535# 1.0 +C a_3185_371# VOUT 0.5 +C a_n3305_371# a_2865_371# 0.5 +C a_14407_n2535# a_6237_n2535# 1.0 +C a_3185_371# VDD 15.5 +C a_3185_371# EN 0.0 +C a_n6357_n2535# a_n15047_n2535# 0.1 +C VIN a_n15047_n2535# 29.5 +C a_n6357_n2535# a_2865_371# 0.9 +C VOUT a_6237_n2535# 0.1 +C a_6237_n2535# VDD 48.9 +C EN a_6237_n2535# 0.7 +C a_n15047_n2535# a_n6877_n2535# 1.0 +C a_3185_371# a_6237_n2535# 29.5 +C a_n6357_n2535# VDD 1.8 +C EN a_n6357_n2535# 0.0 +C VIN VDD 15.2 +C a_3185_371# a_n6357_n2535# 0.3 +C VOUT0 0.4 +R VOUT 123 +C VIN0 2.7 +R VIN 1998 +C EN0 6.7 +R EN 120 +C VDD0 538.4 +R VDD 26821 +R VSS 4899 +C a_14407_n2535#0 0.3 +R a_14407_n2535# 260 +C a_3185_371#0 4.9 +R a_3185_371# 2090 +C a_2865_371#0 2.8 +R a_2865_371# 191 +C a_n3305_371#0 40.2 +R a_n3305_371# 2962 +C a_n6357_n2535#0 12.9 +R a_n6357_n2535# 2054 +C a_n6877_n2535#0 0.2 +R a_n6877_n2535# 260 +C a_6237_n2535#0 3.3 +R a_6237_n2535# 3505 +C a_n15047_n2535#0 3.2 +R a_n15047_n2535# 3505 diff --git a/blocks/composite/regulated_cascoded_cmirror/LVS/lvs/CM/CM_lvs.rpt b/blocks/composite/regulated_cascoded_cmirror/LVS/lvs/CM/CM_lvs.rpt new file mode 100644 index 00000000..f99c65f3 --- /dev/null +++ b/blocks/composite/regulated_cascoded_cmirror/LVS/lvs/CM/CM_lvs.rpt @@ -0,0 +1,38 @@ + +Circuit 1 cell nfet_03v3 and Circuit 2 cell nfet_03v3 are black boxes. +Warning: Equate pins: cell nfet_03v3 is a placeholder, treated as a black box. +Warning: Equate pins: cell nfet_03v3 is a placeholder, treated as a black box. + +Subcircuit pins: +Circuit 1: nfet_03v3 |Circuit 2: nfet_03v3 +-------------------------------------------|------------------------------------------- +1 |1 +2 |2 +3 |3 +4 |4 +--------------------------------------------------------------------------------------- +Cell pin lists are equivalent. +Device classes nfet_03v3 and nfet_03v3 are equivalent. + +Class CM (0): Merged 1 parallel devices. +Subcircuit summary: +Circuit 1: CM |Circuit 2: CM +-------------------------------------------|------------------------------------------- +nfet_03v3 (4->3) |nfet_03v3 (4->3) +Number of devices: 3 |Number of devices: 3 +Number of nets: 3 |Number of nets: 3 +--------------------------------------------------------------------------------------- +Netlists match uniquely. + +Subcircuit pins: +Circuit 1: CM |Circuit 2: CM +-------------------------------------------|------------------------------------------- +VOUT |VOUT +VIN |VIN +VSS |VSS +--------------------------------------------------------------------------------------- +Cell pin lists are equivalent. +Device classes CM and CM are equivalent. + +Final result: Circuits match uniquely. +. diff --git a/blocks/composite/regulated_cascoded_cmirror/LVS/lvs/CM/CM_lvsmag.spice b/blocks/composite/regulated_cascoded_cmirror/LVS/lvs/CM/CM_lvsmag.spice new file mode 100644 index 00000000..4e32c770 --- /dev/null +++ b/blocks/composite/regulated_cascoded_cmirror/LVS/lvs/CM/CM_lvsmag.spice @@ -0,0 +1,9 @@ +* NGSPICE file created from CM.ext - technology: gf180mcuD + +.subckt CM VIN VSS VOUT +X0 VSS VSS VSS VSS nfet_03v3 ad=2.32p pd=9.16u as=14.08p ps=55.04u w=4u l=1u +X1 VSS VSS VSS VSS nfet_03v3 ad=2.32p pd=9.16u as=0 ps=0 w=4u l=1u +X2 VIN VIN VSS VSS nfet_03v3 ad=2.4p pd=9.2u as=2.4p ps=9.2u w=4u l=1u +X3 VOUT VIN VSS VSS nfet_03v3 ad=2.4p pd=9.2u as=2.4p ps=9.2u w=4u l=1u +.ends + diff --git a/blocks/composite/regulated_cascoded_cmirror/LVS/lvs/CM/CM_pex.spice b/blocks/composite/regulated_cascoded_cmirror/LVS/lvs/CM/CM_pex.spice new file mode 100644 index 00000000..f0e9e7eb --- /dev/null +++ b/blocks/composite/regulated_cascoded_cmirror/LVS/lvs/CM/CM_pex.spice @@ -0,0 +1,12 @@ +* NGSPICE file created from CM.ext - technology: gf180mcuD + +.subckt CM VIN VSS VOUT +X0 VSS VSS VSS VSS nfet_03v3 ad=2.32p pd=9.16u as=14.08p ps=55.04u w=4u l=1u +X1 VSS VSS VSS VSS nfet_03v3 ad=2.32p pd=9.16u as=0 ps=0 w=4u l=1u +X2 VIN VIN VSS VSS nfet_03v3 ad=2.4p pd=9.2u as=2.4p ps=9.2u w=4u l=1u +X3 VOUT VIN VSS VSS nfet_03v3 ad=2.4p pd=9.2u as=2.4p ps=9.2u w=4u l=1u +C0 VOUT VIN 0.2042f +C1 VOUT VSS 3.0177f +C2 VIN VSS 5.9238f +.ends + diff --git a/blocks/composite/regulated_cascoded_cmirror/LVS/lvs/CM/CM_sim.spice b/blocks/composite/regulated_cascoded_cmirror/LVS/lvs/CM/CM_sim.spice new file mode 100644 index 00000000..569a115f --- /dev/null +++ b/blocks/composite/regulated_cascoded_cmirror/LVS/lvs/CM/CM_sim.spice @@ -0,0 +1,11 @@ +| units: 0.5 tech: gf180mcuD format: MIT +x VSS VSS VSS VSS d=92800,1832 l=200 w=800 x=-1002 y=-584 nfet_03v3 +x VSS VSS VSS VSS d=92800,1832 l=200 w=800 x=803 y=-584 nfet_03v3 +x VIN VSS VIN VSS s=96000,1840 d=96000,1840 l=200 w=800 x=-394 y=-584 nfet_03v3 +x VIN VSS VOUT VSS s=96000,1840 d=96000,1840 l=200 w=800 x=195 y=-584 nfet_03v3 +C VOUT VIN 0.2 +C VOUT0 3.0 +R VOUT 47 +C VIN0 5.9 +R VIN 159 +R VSS 1473 diff --git a/blocks/composite/regulated_cascoded_cmirror/LVS/lvs/INPUT_STAGE/INPUT_STAGE_lvs.rpt b/blocks/composite/regulated_cascoded_cmirror/LVS/lvs/INPUT_STAGE/INPUT_STAGE_lvs.rpt new file mode 100644 index 00000000..b903fa20 --- /dev/null +++ b/blocks/composite/regulated_cascoded_cmirror/LVS/lvs/INPUT_STAGE/INPUT_STAGE_lvs.rpt @@ -0,0 +1,45 @@ + +Circuit 1 cell pfet_03v3 and Circuit 2 cell pfet_03v3 are black boxes. +Warning: Equate pins: cell pfet_03v3 is a placeholder, treated as a black box. +Warning: Equate pins: cell pfet_03v3 is a placeholder, treated as a black box. + +Subcircuit pins: +Circuit 1: pfet_03v3 |Circuit 2: pfet_03v3 +-------------------------------------------|------------------------------------------- +1 |1 +2 |2 +3 |3 +4 |4 +--------------------------------------------------------------------------------------- +Cell pin lists are equivalent. +Device classes pfet_03v3 and pfet_03v3 are equivalent. + +Class INPUT_STAGE (0): Merged 8 parallel devices. +Class INPUT_STAGE (1): Merged 3 parallel devices. +Subcircuit summary: +Circuit 1: INPUT_STAGE |Circuit 2: INPUT_STAGE +-------------------------------------------|------------------------------------------- +pfet_03v3 (20->12) |pfet_03v3 (20->12) +Number of devices: 12 |Number of devices: 12 +Number of nets: 12 |Number of nets: 12 +--------------------------------------------------------------------------------------- +Resolving symmetries by property value. +Resolving symmetries by pin name. +Netlists match uniquely. + +Subcircuit pins: +Circuit 1: INPUT_STAGE |Circuit 2: INPUT_STAGE +-------------------------------------------|------------------------------------------- +VIN |VIN +EN |EN +VOUT_CCM |VOUT_CCM +VOUT_BCM |VOUT_BCM +VOUT_VIN |VOUT_VIN +VOUT_VCM |VOUT_VCM +VDD |VDD +--------------------------------------------------------------------------------------- +Cell pin lists are equivalent. +Device classes INPUT_STAGE and INPUT_STAGE are equivalent. + +Final result: Circuits match uniquely. +. diff --git a/blocks/composite/regulated_cascoded_cmirror/LVS/lvs/INPUT_STAGE/INPUT_STAGE_lvsmag.spice b/blocks/composite/regulated_cascoded_cmirror/LVS/lvs/INPUT_STAGE/INPUT_STAGE_lvsmag.spice new file mode 100644 index 00000000..22585262 --- /dev/null +++ b/blocks/composite/regulated_cascoded_cmirror/LVS/lvs/INPUT_STAGE/INPUT_STAGE_lvsmag.spice @@ -0,0 +1,25 @@ +* NGSPICE file created from INPUT_STAGE.ext - technology: gf180mcuD + +.subckt INPUT_STAGE VIN VDD VOUT_VIN VOUT_CCM VOUT_BCM VOUT_VCM EN +X0 VDD VDD VDD VDD pfet_03v3 ad=5.8p pd=21.16u as=0.1236n ps=0.44472m w=10u l=2u +X1 VOUT_VCM VIN a_n1110_n1500# VDD pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X2 a_n1900_n1500# EN VDD VDD pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X3 VOUT_VIN VIN a_1260_n1500# VDD pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X4 a_n320_n1500# a_n1900_n1500# VDD VDD pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X5 VDD VDD VDD VDD pfet_03v3 ad=5.8p pd=21.16u as=0 ps=0 w=10u l=2u +X6 VDD VDD VDD VDD pfet_03v3 ad=5.8p pd=21.16u as=0 ps=0 w=10u l=2u +X7 a_n1900_n1500# EN VDD VDD pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X8 VOUT_BCM VIN a_n320_n1500# VDD pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X9 a_n1900_n1500# EN VDD VDD pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X10 VIN VIN a_n1900_n1500# VDD pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X11 a_n1110_n1500# a_n1900_n1500# VDD VDD pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X12 VDD VDD VDD VDD pfet_03v3 ad=5.8p pd=21.16u as=0 ps=0 w=10u l=2u +X13 a_470_n1500# a_n1900_n1500# VDD VDD pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X14 a_n1900_n1500# EN VDD VDD pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X15 VDD VDD VDD VDD pfet_03v3 ad=5.8p pd=21.16u as=0 ps=0 w=10u l=2u +X16 VOUT_CCM VIN a_470_n1500# VDD pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X17 VDD VDD VDD VDD pfet_03v3 ad=5.8p pd=21.16u as=0 ps=0 w=10u l=2u +X18 a_n1900_n1500# a_n1900_n1500# VDD VDD pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X19 a_1260_n1500# a_n1900_n1500# VDD VDD pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +.ends + diff --git a/blocks/composite/regulated_cascoded_cmirror/LVS/lvs/INPUT_STAGE/INPUT_STAGE_pex.spice b/blocks/composite/regulated_cascoded_cmirror/LVS/lvs/INPUT_STAGE/INPUT_STAGE_pex.spice new file mode 100644 index 00000000..b9ec6548 --- /dev/null +++ b/blocks/composite/regulated_cascoded_cmirror/LVS/lvs/INPUT_STAGE/INPUT_STAGE_pex.spice @@ -0,0 +1,98 @@ +* NGSPICE file created from INPUT_STAGE.ext - technology: gf180mcuD + +.subckt INPUT_STAGE VIN VDD VOUT_VIN VOUT_CCM VOUT_BCM VOUT_VCM EN +X0 VDD VDD VDD VDD pfet_03v3 ad=5.8p pd=21.16u as=0.1236n ps=0.44472m w=10u l=2u +X1 VOUT_VCM VIN a_n1110_n1500# VDD pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X2 a_n1900_n1500# EN VDD VDD pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X3 VOUT_VIN VIN a_1260_n1500# VDD pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X4 a_n320_n1500# a_n1900_n1500# VDD VDD pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X5 VDD VDD VDD VDD pfet_03v3 ad=5.8p pd=21.16u as=0 ps=0 w=10u l=2u +X6 VDD VDD VDD VDD pfet_03v3 ad=5.8p pd=21.16u as=0 ps=0 w=10u l=2u +X7 a_n1900_n1500# EN VDD VDD pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X8 VOUT_BCM VIN a_n320_n1500# VDD pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X9 a_n1900_n1500# EN VDD VDD pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X10 VIN VIN a_n1900_n1500# VDD pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X11 a_n1110_n1500# a_n1900_n1500# VDD VDD pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X12 VDD VDD VDD VDD pfet_03v3 ad=5.8p pd=21.16u as=0 ps=0 w=10u l=2u +X13 a_470_n1500# a_n1900_n1500# VDD VDD pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X14 a_n1900_n1500# EN VDD VDD pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X15 VDD VDD VDD VDD pfet_03v3 ad=5.8p pd=21.16u as=0 ps=0 w=10u l=2u +X16 VOUT_CCM VIN a_470_n1500# VDD pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X17 VDD VDD VDD VDD pfet_03v3 ad=5.8p pd=21.16u as=0 ps=0 w=10u l=2u +X18 a_n1900_n1500# a_n1900_n1500# VDD VDD pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X19 a_1260_n1500# a_n1900_n1500# VDD VDD pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +C0 VOUT_VIN a_n1110_n1500# 0.13684f +C1 a_1260_n1500# a_n1110_n1500# 0.30103f +C2 VOUT_BCM VOUT_CCM 0.33028f +C3 VIN VOUT_VCM 0.63416f +C4 a_n1900_n1500# a_n1110_n1500# 1.80913f +C5 a_n320_n1500# VIN 0.63243f +C6 a_1260_n1500# EN 0.28741f +C7 VOUT_VIN a_470_n1500# 0.13662f +C8 a_470_n1500# a_1260_n1500# 0.80509f +C9 VOUT_VIN VDD 2.21442f +C10 VDD a_1260_n1500# 6.35462f +C11 EN a_n1900_n1500# 2.15734f +C12 a_470_n1500# a_n1900_n1500# 1.46461f +C13 VDD a_n1900_n1500# 44.9171f +C14 VOUT_BCM a_n1110_n1500# 0.17152f +C15 VOUT_VIN VIN 0.54995f +C16 a_1260_n1500# VIN 0.62105f +C17 VOUT_CCM a_n1110_n1500# 0.17047f +C18 a_n320_n1500# VOUT_VCM 2.30103f +C19 VIN a_n1900_n1500# 3.41485f +C20 a_470_n1500# VOUT_BCM 2.29847f +C21 a_470_n1500# VOUT_CCM 2.39829f +C22 VDD VOUT_BCM 1.12778f +C23 VDD VOUT_CCM 1.1279f +C24 VOUT_VIN VOUT_VCM 0.08091f +C25 a_1260_n1500# VOUT_VCM 0.10003f +C26 VOUT_VIN a_n320_n1500# 0.13558f +C27 a_n320_n1500# a_1260_n1500# 0.30154f +C28 VOUT_BCM VIN 0.62309f +C29 VIN VOUT_CCM 0.62193f +C30 a_n1900_n1500# VOUT_VCM 0.13364f +C31 EN a_n1110_n1500# 0.00563f +C32 a_n320_n1500# a_n1900_n1500# 1.46427f +C33 a_470_n1500# a_n1110_n1500# 0.34178f +C34 VDD a_n1110_n1500# 7.43338f +C35 a_470_n1500# EN 0.00915f +C36 VOUT_VIN a_1260_n1500# 2.35844f +C37 VDD EN 11.072f +C38 VDD a_470_n1500# 7.51371f +C39 VOUT_BCM VOUT_VCM 0.3303f +C40 VIN a_n1110_n1500# 2.86501f +C41 VOUT_CCM VOUT_VCM 0.09982f +C42 a_n320_n1500# VOUT_BCM 2.40482f +C43 VOUT_VIN a_n1900_n1500# 0.96309f +C44 a_1260_n1500# a_n1900_n1500# 2.37681f +C45 a_n320_n1500# VOUT_CCM 0.17025f +C46 a_470_n1500# VIN 0.62333f +C47 VDD VIN 14.5258f +C48 VOUT_VIN VOUT_BCM 0.08038f +C49 a_1260_n1500# VOUT_BCM 0.10042f +C50 VOUT_VIN VOUT_CCM 0.31084f +C51 a_1260_n1500# VOUT_CCM 2.29591f +C52 VOUT_VCM a_n1110_n1500# 2.41261f +C53 a_n320_n1500# a_n1110_n1500# 0.84535f +C54 VOUT_BCM a_n1900_n1500# 0.13521f +C55 a_n1900_n1500# VOUT_CCM 0.13973f +C56 a_470_n1500# VOUT_VCM 0.10043f +C57 a_n320_n1500# EN 0.0069f +C58 a_n320_n1500# a_470_n1500# 0.84407f +C59 VDD VOUT_VCM 1.21291f +C60 VDD a_n320_n1500# 7.43186f +C61 VOUT_VIN VSUBS 0.38142f +C62 VOUT_CCM VSUBS 0.15405f +C63 VOUT_BCM VSUBS 0.15363f +C64 VOUT_VCM VSUBS 0.28097f +C65 VIN VSUBS 2.45016f +C66 EN VSUBS 1.80875f +C67 VDD VSUBS 0.30456p +C68 a_1260_n1500# VSUBS 0.15844f +C69 a_470_n1500# VSUBS 0.03326f +C70 a_n320_n1500# VSUBS 0.03284f +C71 a_n1110_n1500# VSUBS 0.03295f +C72 a_n1900_n1500# VSUBS 3.20944f +.ends + diff --git a/blocks/composite/regulated_cascoded_cmirror/LVS/lvs/INPUT_STAGE/INPUT_STAGE_sim.spice b/blocks/composite/regulated_cascoded_cmirror/LVS/lvs/INPUT_STAGE/INPUT_STAGE_sim.spice new file mode 100644 index 00000000..185c45ed --- /dev/null +++ b/blocks/composite/regulated_cascoded_cmirror/LVS/lvs/INPUT_STAGE/INPUT_STAGE_sim.spice @@ -0,0 +1,106 @@ +| units: 0.5 tech: gf180mcuD format: MIT +x VDD VDD VDD VDD d=232000,4232 l=400 w=2000 x=-2587 y=-1499 pfet_03v3 +x VIN a_n1110_n1500# VOUT_VCM VDD s=240000,4240 d=240000,4240 l=400 w=2000 x=-989 y=-1499 pfet_03v3 +x EN VDD a_n1900_n1500# VDD s=240000,4240 d=240000,4240 l=400 w=2000 x=195 y=9300 pfet_03v3 +x VIN a_1260_n1500# VOUT_VIN VDD s=240000,4240 d=240000,4240 l=400 w=2000 x=1380 y=-1499 pfet_03v3 +x a_n1900_n1500# VDD a_n320_n1500# VDD s=240000,4240 d=240000,4240 l=400 w=2000 x=-199 y=3848 pfet_03v3 +x VDD VDD VDD VDD d=232000,4232 l=400 w=2000 x=2188 y=3848 pfet_03v3 +x VDD VDD VDD VDD d=232000,4232 l=400 w=2000 x=-2192 y=9300 pfet_03v3 +x EN VDD a_n1900_n1500# VDD s=240000,4240 d=240000,4240 l=400 w=2000 x=-594 y=9300 pfet_03v3 +x VIN a_n320_n1500# VOUT_BCM VDD s=240000,4240 d=240000,4240 l=400 w=2000 x=-199 y=-1499 pfet_03v3 +x EN VDD a_n1900_n1500# VDD s=240000,4240 d=240000,4240 l=400 w=2000 x=985 y=9300 pfet_03v3 +x VIN a_n1900_n1500# VIN VDD s=240000,4240 d=240000,4240 l=400 w=2000 x=-1779 y=-1499 pfet_03v3 +x a_n1900_n1500# VDD a_n1110_n1500# VDD s=240000,4240 d=240000,4240 l=400 w=2000 x=-989 y=3848 pfet_03v3 +x VDD VDD VDD VDD d=232000,4232 l=400 w=2000 x=-2587 y=3848 pfet_03v3 +x a_n1900_n1500# VDD a_470_n1500# VDD s=240000,4240 d=240000,4240 l=400 w=2000 x=590 y=3848 pfet_03v3 +x EN VDD a_n1900_n1500# VDD s=240000,4240 d=240000,4240 l=400 w=2000 x=-1384 y=9300 pfet_03v3 +x VDD VDD VDD VDD d=232000,4232 l=400 w=2000 x=1793 y=9300 pfet_03v3 +x VIN a_470_n1500# VOUT_CCM VDD s=240000,4240 d=240000,4240 l=400 w=2000 x=590 y=-1499 pfet_03v3 +x VDD VDD VDD VDD d=232000,4232 l=400 w=2000 x=2188 y=-1499 pfet_03v3 +x a_n1900_n1500# VDD a_n1900_n1500# VDD s=240000,4240 d=240000,4240 l=400 w=2000 x=-1779 y=3848 pfet_03v3 +x a_n1900_n1500# VDD a_1260_n1500# VDD s=240000,4240 d=240000,4240 l=400 w=2000 x=1380 y=3848 pfet_03v3 +C a_n320_n1500# a_1260_n1500# 0.3 +C VOUT_VIN a_n1900_n1500# 1.0 +C VOUT_VIN VIN 0.5 +C VDD a_470_n1500# 7.5 +C VOUT_CCM a_1260_n1500# 2.3 +C a_n1900_n1500# VOUT_VCM 0.1 +C VOUT_BCM a_n1900_n1500# 0.1 +C VIN VOUT_VCM 0.6 +C VOUT_BCM VIN 0.6 +C a_n320_n1500# VOUT_VIN 0.1 +C EN a_n1110_n1500# 0.0 +C VDD a_n1900_n1500# 44.9 +C a_n320_n1500# VOUT_VCM 2.3 +C VOUT_CCM VOUT_VIN 0.3 +C VDD VIN 14.5 +C VOUT_BCM a_n320_n1500# 2.4 +C VOUT_CCM VOUT_VCM 0.1 +C VOUT_BCM VOUT_CCM 0.3 +C a_1260_n1500# a_n1110_n1500# 0.3 +C VDD a_n320_n1500# 7.4 +C a_470_n1500# a_n1900_n1500# 1.5 +C a_470_n1500# VIN 0.6 +C VDD VOUT_CCM 1.1 +C VOUT_VIN a_n1110_n1500# 0.1 +C a_n320_n1500# a_470_n1500# 0.8 +C VOUT_VCM a_n1110_n1500# 2.4 +C VOUT_BCM a_n1110_n1500# 0.2 +C a_1260_n1500# EN 0.3 +C a_n1900_n1500# VIN 3.4 +C VOUT_CCM a_470_n1500# 2.4 +C VDD a_n1110_n1500# 7.4 +C a_n320_n1500# a_n1900_n1500# 1.5 +C a_n320_n1500# VIN 0.6 +C VOUT_CCM a_n1900_n1500# 0.1 +C VOUT_CCM VIN 0.6 +C a_470_n1500# a_n1110_n1500# 0.3 +C VOUT_VIN a_1260_n1500# 2.4 +C a_n320_n1500# VOUT_CCM 0.2 +C VDD EN 11.1 +C a_1260_n1500# VOUT_VCM 0.1 +C VOUT_BCM a_1260_n1500# 0.1 +C a_n1900_n1500# a_n1110_n1500# 1.8 +C VIN a_n1110_n1500# 2.9 +C VDD a_1260_n1500# 6.4 +C a_470_n1500# EN 0.0 +C VOUT_VIN VOUT_VCM 0.1 +C VOUT_BCM VOUT_VIN 0.1 +C a_n320_n1500# a_n1110_n1500# 0.8 +C VOUT_BCM VOUT_VCM 0.3 +C VOUT_CCM a_n1110_n1500# 0.2 +C VDD VOUT_VIN 2.2 +C a_470_n1500# a_1260_n1500# 0.8 +C EN a_n1900_n1500# 2.2 +C VDD VOUT_VCM 1.2 +C VDD VOUT_BCM 1.1 +C a_n320_n1500# EN 0.0 +C a_470_n1500# VOUT_VIN 0.1 +C a_1260_n1500# a_n1900_n1500# 2.4 +C a_1260_n1500# VIN 0.6 +C a_470_n1500# VOUT_VCM 0.1 +C VOUT_BCM a_470_n1500# 2.3 +C VOUT_VIN0 0.4 +R VOUT_VIN 128 +C VOUT_CCM0 0.2 +R VOUT_CCM 128 +C VOUT_BCM0 0.2 +R VOUT_BCM 128 +C VOUT_VCM0 0.3 +R VOUT_VCM 128 +C VIN0 2.5 +R VIN 515 +C EN0 1.8 +R EN 289 +C VDD0 304.6 +R VDD 9768 +C a_1260_n1500#0 0.2 +R a_1260_n1500# 272 +C a_470_n1500#0 0.0 +R a_470_n1500# 272 +C a_n320_n1500#0 0.0 +R a_n320_n1500# 272 +C a_n1110_n1500#0 0.0 +R a_n1110_n1500# 272 +C a_n1900_n1500#0 3.2 +R a_n1900_n1500# 1220 diff --git a/blocks/composite/regulated_cascoded_cmirror/LVS/lvs/M/M_lvs.rpt b/blocks/composite/regulated_cascoded_cmirror/LVS/lvs/M/M_lvs.rpt new file mode 100644 index 00000000..55013a56 --- /dev/null +++ b/blocks/composite/regulated_cascoded_cmirror/LVS/lvs/M/M_lvs.rpt @@ -0,0 +1,66 @@ + +Circuit 1 cell pfet_03v3 and Circuit 2 cell pfet_03v3 are black boxes. +Warning: Equate pins: cell pfet_03v3 is a placeholder, treated as a black box. +Warning: Equate pins: cell pfet_03v3 is a placeholder, treated as a black box. + +Subcircuit pins: +Circuit 1: pfet_03v3 |Circuit 2: pfet_03v3 +-------------------------------------------|------------------------------------------- +1 |1 +2 |2 +3 |3 +4 |4 +--------------------------------------------------------------------------------------- +Cell pin lists are equivalent. +Device classes pfet_03v3 and pfet_03v3 are equivalent. + +Circuit 1 cell nfet_03v3 and Circuit 2 cell nfet_03v3 are black boxes. +Warning: Equate pins: cell nfet_03v3 is a placeholder, treated as a black box. +Warning: Equate pins: cell nfet_03v3 is a placeholder, treated as a black box. + +Subcircuit pins: +Circuit 1: nfet_03v3 |Circuit 2: nfet_03v3 +-------------------------------------------|------------------------------------------- +1 |1 +2 |2 +3 |3 +4 |4 +--------------------------------------------------------------------------------------- +Cell pin lists are equivalent. +Device classes nfet_03v3 and nfet_03v3 are equivalent. +Flattening unmatched subcell INPUT in circuit M (1)(1 instance) +Flattening unmatched subcell BIAS in circuit M (1)(1 instance) +Flattening unmatched subcell VCM in circuit M (1)(1 instance) +Flattening unmatched subcell SBCM in circuit M (1)(1 instance) +Flattening unmatched subcell RCCM in circuit M (1)(1 instance) + +Class M (0): Merged 95 parallel devices. +Class M (1): Merged 9 parallel devices. +Subcircuit summary: +Circuit 1: M |Circuit 2: M +-------------------------------------------|------------------------------------------- +pfet_03v3 (78->22) |pfet_03v3 (78->22) +nfet_03v3 (56->17) |nfet_03v3 (56->17) +Number of devices: 39 |Number of devices: 39 +Number of nets: 30 |Number of nets: 30 +--------------------------------------------------------------------------------------- +Netlists match uniquely. + +Subcircuit pins: +Circuit 1: M |Circuit 2: M +-------------------------------------------|------------------------------------------- +VOUT_VIN |VOUT_VIN +VOUT_VCM |VOUT_VCM +VOUT_SBCM |VOUT_SBCM +VOUT_RCCM |VOUT_RCCM +EN |EN +VAUX |VAUX +VIN |VIN +VSS |VSS +VDD |VDD +--------------------------------------------------------------------------------------- +Cell pin lists are equivalent. +Device classes M and M are equivalent. + +Final result: Circuits match uniquely. +. diff --git a/blocks/composite/regulated_cascoded_cmirror/LVS/lvs/M/M_lvsmag.spice b/blocks/composite/regulated_cascoded_cmirror/LVS/lvs/M/M_lvsmag.spice new file mode 100644 index 00000000..aa7229f4 --- /dev/null +++ b/blocks/composite/regulated_cascoded_cmirror/LVS/lvs/M/M_lvsmag.spice @@ -0,0 +1,139 @@ +* NGSPICE file created from M.ext - technology: gf180mcuD + +.subckt M VIN VSS VDD VOUT_VIN VOUT_RCCM VOUT_SBCM VOUT_VCM VAUX EN +X0 a_n1900_n6686# a_n1900_n6686# VDD VDD pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X1 a_n28653_8045# a_n28653_8045# a_n25601_10951# VSS nfet_03v3 ad=4.8p pd=17.2u as=4.8p ps=17.2u w=8u l=1u +X2 a_990_n6686# VIN a_470_n6686# VDD pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X3 a_n1900_n6686# EN VDD VDD pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X4 VSS VSS VSS VSS nfet_03v3 ad=2.32p pd=9.16u as=0.1744n ps=0.65672m w=4u l=1u +X5 VSS VSS VSS VSS nfet_03v3 ad=4.64p pd=17.16u as=0 ps=0 w=8u l=1u +X6 a_6447_5389# a_990_n6686# VSS VSS nfet_03v3 ad=2.4p pd=9.2u as=2.4p ps=9.2u w=4u l=1u +X7 a_n37343_8045# a_n37343_8045# VDD VDD pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X8 VDD VDD VDD VDD pfet_03v3 ad=5.8p pd=21.16u as=0.4068n ps=1.46136m w=10u l=2u +X9 a_7083_483# a_7083_483# VSS VSS nfet_03v3 ad=2.4p pd=9.2u as=2.4p ps=9.2u w=4u l=1u +X10 a_6447_5389# a_990_n6686# VSS VSS nfet_03v3 ad=2.4p pd=9.2u as=2.4p ps=9.2u w=4u l=1u +X11 VDD VDD VDD VDD pfet_03v3 ad=5.8p pd=21.16u as=0 ps=0 w=10u l=2u +X12 VAUX VAUX a_n37343_8045# VDD pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X13 a_n16059_8045# a_n16059_8045# VDD VDD pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X14 a_n25601_10951# a_n25601_10951# VSS VSS nfet_03v3 ad=4.8p pd=17.2u as=4.8p ps=17.2u w=8u l=1u +X15 a_n19111_10951# a_n19111_10951# a_n16059_8045# VDD pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X16 a_n25601_10951# a_n25601_10951# VSS VSS nfet_03v3 ad=4.8p pd=17.2u as=4.8p ps=17.2u w=8u l=1u +X17 a_n28653_8045# a_n28653_8045# a_n25601_10951# VSS nfet_03v3 ad=4.8p pd=17.2u as=4.8p ps=17.2u w=8u l=1u +X18 VDD VDD VDD VDD pfet_03v3 ad=5.8p pd=21.16u as=0 ps=0 w=10u l=2u +X19 VAUX VAUX a_n37343_8045# VDD pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X20 VSS VSS VSS VSS nfet_03v3 ad=2.32p pd=9.16u as=0 ps=0 w=4u l=1u +X21 VSS VSS VSS VSS nfet_03v3 ad=4.64p pd=17.16u as=0 ps=0 w=8u l=1u +X22 a_n590_n6686# VIN a_n1110_n6686# VDD pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X23 a_n19111_10951# a_n19111_10951# a_n16059_8045# VDD pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X24 VDD VDD VDD VDD pfet_03v3 ad=5.8p pd=21.16u as=0 ps=0 w=10u l=2u +X25 a_n1900_n6686# EN VDD VDD pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X26 a_n16059_8045# EN VDD VDD pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X27 a_n28653_8045# a_n28653_8045# a_n25601_10951# VSS nfet_03v3 ad=4.8p pd=17.2u as=4.8p ps=17.2u w=8u l=1u +X28 VSS VSS VSS VSS nfet_03v3 ad=2.32p pd=9.16u as=0 ps=0 w=4u l=1u +X29 VDD VDD VDD VDD pfet_03v3 ad=5.8p pd=21.16u as=0 ps=0 w=10u l=2u +X30 a_n25601_10951# a_n25601_10951# VSS VSS nfet_03v3 ad=4.8p pd=17.2u as=4.8p ps=17.2u w=8u l=1u +X31 VAUX VAUX a_n37343_8045# VDD pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X32 VSS VSS VSS VSS nfet_03v3 ad=4.64p pd=17.16u as=0 ps=0 w=8u l=1u +X33 a_n37343_8045# a_n37343_8045# VDD VDD pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X34 a_n7369_8045# a_n19111_10951# a_n7889_8045# VDD pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X35 a_n37343_8045# EN VDD VDD pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X36 a_n590_n6686# a_n590_n6686# VSS VSS nfet_03v3 ad=2.4p pd=9.2u as=2.4p ps=9.2u w=4u l=1u +X37 a_n28653_8045# a_n28653_8045# a_n25601_10951# VSS nfet_03v3 ad=4.8p pd=17.2u as=4.8p ps=17.2u w=8u l=1u +X38 VSS VSS VSS VSS nfet_03v3 ad=2.32p pd=9.16u as=0 ps=0 w=4u l=1u +X39 a_n16059_8045# a_n16059_8045# VDD VDD pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X40 VSS VSS VSS VSS nfet_03v3 ad=4.64p pd=17.16u as=0 ps=0 w=8u l=1u +X41 a_470_n6686# a_n1900_n6686# VDD VDD pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X42 a_n37343_8045# a_n37343_8045# VDD VDD pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X43 VOUT_VIN VIN a_1260_n6686# VDD pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X44 VDD VDD VDD VDD pfet_03v3 ad=5.8p pd=21.16u as=0 ps=0 w=10u l=2u +X45 VSS VSS VSS VSS nfet_03v3 ad=2.32p pd=9.16u as=0 ps=0 w=4u l=1u +X46 a_n1900_n6686# EN VDD VDD pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X47 VOUT_RCCM a_n7369_8045# a_6447_5389# VSS nfet_03v3 ad=2.4p pd=9.2u as=2.4p ps=9.2u w=4u l=1u +X48 a_n19431_10951# a_n25601_10951# VSS VSS nfet_03v3 ad=4.8p pd=17.2u as=4.8p ps=17.2u w=8u l=1u +X49 VAUX VAUX a_n37343_8045# VDD pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X50 VAUX VAUX a_n37343_8045# VDD pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X51 VOUT_RCCM a_n7369_8045# a_6447_5389# VSS nfet_03v3 ad=2.4p pd=9.2u as=2.4p ps=9.2u w=4u l=1u +X52 VDD VDD VDD VDD pfet_03v3 ad=5.8p pd=21.16u as=0 ps=0 w=10u l=2u +X53 a_n25601_10951# a_n25601_10951# VSS VSS nfet_03v3 ad=4.8p pd=17.2u as=4.8p ps=17.2u w=8u l=1u +X54 a_7673_483# a_7083_483# VSS VSS nfet_03v3 ad=2.4p pd=9.2u as=2.4p ps=9.2u w=4u l=1u +X55 a_n16059_8045# a_n16059_8045# VDD VDD pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X56 a_n28653_8045# a_n28653_8045# a_n25601_10951# VSS nfet_03v3 ad=4.8p pd=17.2u as=4.8p ps=17.2u w=8u l=1u +X57 a_n19111_10951# a_n19111_10951# a_n16059_8045# VDD pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X58 a_n37343_8045# a_n37343_8045# VDD VDD pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X59 VSS VSS VSS VSS nfet_03v3 ad=2.32p pd=9.16u as=0 ps=0 w=4u l=1u +X60 a_n37343_8045# a_n37343_8045# VDD VDD pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X61 VSS VSS VSS VSS nfet_03v3 ad=2.32p pd=9.16u as=0 ps=0 w=4u l=1u +X62 a_n19111_10951# a_n19111_10951# a_n16059_8045# VDD pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X63 a_n1110_n6686# a_n1900_n6686# VDD VDD pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X64 a_n19111_10951# a_n19111_10951# a_n16059_8045# VDD pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X65 VDD VDD VDD VDD pfet_03v3 ad=5.8p pd=21.16u as=0 ps=0 w=10u l=2u +X66 a_n16059_8045# a_n16059_8045# VDD VDD pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X67 a_n16059_8045# a_n16059_8045# VDD VDD pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X68 a_n37343_8045# a_n37343_8045# VDD VDD pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X69 VSS VSS VSS VSS nfet_03v3 ad=2.32p pd=9.16u as=0 ps=0 w=4u l=1u +X70 VDD VDD VDD VDD pfet_03v3 ad=5.8p pd=21.16u as=0 ps=0 w=10u l=2u +X71 VAUX VAUX a_n37343_8045# VDD pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X72 a_n28653_8045# a_n28653_8045# a_n25601_10951# VSS nfet_03v3 ad=4.8p pd=17.2u as=4.8p ps=17.2u w=8u l=1u +X73 VSS VSS VSS VSS nfet_03v3 ad=2.32p pd=9.16u as=0 ps=0 w=4u l=1u +X74 a_n7369_8045# a_6447_5389# VSS VSS nfet_03v3 ad=2.4p pd=9.2u as=2.4p ps=9.2u w=4u l=1u +X75 a_n19111_10951# a_n19111_10951# a_n16059_8045# VDD pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X76 a_n7369_8045# a_6567_9285# VSS VSS nfet_03v3 ad=2.4p pd=9.2u as=2.4p ps=9.2u w=4u l=1u +X77 a_n7369_8045# a_6447_5389# VSS VSS nfet_03v3 ad=2.4p pd=9.2u as=2.4p ps=9.2u w=4u l=1u +X78 a_n7369_8045# a_6567_9285# VSS VSS nfet_03v3 ad=2.4p pd=9.2u as=2.4p ps=9.2u w=4u l=1u +X79 VDD VDD VDD VDD pfet_03v3 ad=5.8p pd=21.16u as=0 ps=0 w=10u l=2u +X80 VOUT_VCM a_n590_n6686# VSS VSS nfet_03v3 ad=2.4p pd=9.2u as=2.4p ps=9.2u w=4u l=1u +X81 a_n1900_n6686# EN VDD VDD pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X82 a_n28653_8045# a_n28653_8045# a_n25601_10951# VSS nfet_03v3 ad=4.8p pd=17.2u as=4.8p ps=17.2u w=8u l=1u +X83 a_1260_n6686# a_n1900_n6686# VDD VDD pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X84 a_n7889_8045# a_n16059_8045# VDD VDD pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X85 a_n37343_8045# a_n37343_8045# VDD VDD pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X86 a_n28653_8045# VAUX a_n29173_8045# VDD pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X87 VSS VSS VSS VSS nfet_03v3 ad=2.32p pd=9.16u as=0 ps=0 w=4u l=1u +X88 a_n29173_8045# a_n37343_8045# VDD VDD pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X89 a_200_n6686# VIN a_n320_n6686# VDD pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X90 VIN VIN a_n1900_n6686# VDD pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X91 a_n16059_8045# a_n16059_8045# VDD VDD pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X92 a_n28653_8045# a_n28653_8045# a_n25601_10951# VSS nfet_03v3 ad=4.8p pd=17.2u as=4.8p ps=17.2u w=8u l=1u +X93 VAUX VAUX a_n37343_8045# VDD pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X94 a_n16059_8045# a_n16059_8045# VDD VDD pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X95 a_n25601_10951# a_n25601_10951# VSS VSS nfet_03v3 ad=4.8p pd=17.2u as=4.8p ps=17.2u w=8u l=1u +X96 a_n19111_10951# a_n28653_8045# a_n19431_10951# VSS nfet_03v3 ad=4.8p pd=17.2u as=4.8p ps=17.2u w=8u l=1u +X97 a_n37343_8045# a_n37343_8045# VDD VDD pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X98 VDD VDD VDD VDD pfet_03v3 ad=5.8p pd=21.16u as=0 ps=0 w=10u l=2u +X99 VDD VDD VDD VDD pfet_03v3 ad=5.8p pd=21.16u as=0 ps=0 w=10u l=2u +X100 a_n25601_10951# a_n25601_10951# VSS VSS nfet_03v3 ad=4.8p pd=17.2u as=4.8p ps=17.2u w=8u l=1u +X101 a_200_n6686# a_200_n6686# a_7083_483# VSS nfet_03v3 ad=2.4p pd=9.2u as=2.4p ps=9.2u w=4u l=1u +X102 a_990_n6686# a_n7369_8045# a_6567_9285# VSS nfet_03v3 ad=2.4p pd=9.2u as=2.4p ps=9.2u w=4u l=1u +X103 VAUX VAUX a_n37343_8045# VDD pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X104 VSS VSS VSS VSS nfet_03v3 ad=2.32p pd=9.16u as=0 ps=0 w=4u l=1u +X105 a_990_n6686# a_n7369_8045# a_6567_9285# VSS nfet_03v3 ad=2.4p pd=9.2u as=2.4p ps=9.2u w=4u l=1u +X106 VDD VDD VDD VDD pfet_03v3 ad=5.8p pd=21.16u as=0 ps=0 w=10u l=2u +X107 a_n16059_8045# a_n16059_8045# VDD VDD pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X108 a_n19111_10951# a_n19111_10951# a_n16059_8045# VDD pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X109 VAUX VAUX a_n37343_8045# VDD pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X110 VSS VSS VSS VSS nfet_03v3 ad=2.32p pd=9.16u as=0 ps=0 w=4u l=1u +X111 a_n19111_10951# a_n19111_10951# a_n16059_8045# VDD pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X112 VDD VDD VDD VDD pfet_03v3 ad=5.8p pd=21.16u as=0 ps=0 w=10u l=2u +X113 a_n28653_8045# a_n28653_8045# a_n25601_10951# VSS nfet_03v3 ad=4.8p pd=17.2u as=4.8p ps=17.2u w=8u l=1u +X114 VAUX VAUX a_n37343_8045# VDD pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X115 a_6567_9285# a_990_n6686# VSS VSS nfet_03v3 ad=2.4p pd=9.2u as=2.4p ps=9.2u w=4u l=1u +X116 a_n28653_8045# a_n28653_8045# a_n25601_10951# VSS nfet_03v3 ad=4.8p pd=17.2u as=4.8p ps=17.2u w=8u l=1u +X117 a_n19111_10951# a_n19111_10951# a_n16059_8045# VDD pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X118 VDD VDD VDD VDD pfet_03v3 ad=5.8p pd=21.16u as=0 ps=0 w=10u l=2u +X119 a_6567_9285# a_990_n6686# VSS VSS nfet_03v3 ad=2.4p pd=9.2u as=2.4p ps=9.2u w=4u l=1u +X120 a_n25601_10951# a_n25601_10951# VSS VSS nfet_03v3 ad=4.8p pd=17.2u as=4.8p ps=17.2u w=8u l=1u +X121 a_n16059_8045# a_n16059_8045# VDD VDD pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X122 a_n16059_8045# a_n16059_8045# VDD VDD pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X123 a_n25601_10951# a_n25601_10951# VSS VSS nfet_03v3 ad=4.8p pd=17.2u as=4.8p ps=17.2u w=8u l=1u +X124 VDD VDD VDD VDD pfet_03v3 ad=5.8p pd=21.16u as=0 ps=0 w=10u l=2u +X125 a_n19111_10951# a_n19111_10951# a_n16059_8045# VDD pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X126 a_n37343_8045# a_n37343_8045# VDD VDD pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X127 a_n25601_10951# a_n25601_10951# VSS VSS nfet_03v3 ad=4.8p pd=17.2u as=4.8p ps=17.2u w=8u l=1u +X128 VDD VDD VDD VDD pfet_03v3 ad=5.8p pd=21.16u as=0 ps=0 w=10u l=2u +X129 a_n37343_8045# a_n37343_8045# VDD VDD pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X130 a_n25601_10951# a_n25601_10951# VSS VSS nfet_03v3 ad=4.8p pd=17.2u as=4.8p ps=17.2u w=8u l=1u +X131 VOUT_SBCM a_200_n6686# a_7673_483# VSS nfet_03v3 ad=2.4p pd=9.2u as=2.4p ps=9.2u w=4u l=1u +X132 VDD VDD VDD VDD pfet_03v3 ad=5.8p pd=21.16u as=0 ps=0 w=10u l=2u +X133 a_n320_n6686# a_n1900_n6686# VDD VDD pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +.ends + diff --git a/blocks/composite/regulated_cascoded_cmirror/LVS/lvs/M/M_pex.spice b/blocks/composite/regulated_cascoded_cmirror/LVS/lvs/M/M_pex.spice new file mode 100644 index 00000000..8b6a9fa7 --- /dev/null +++ b/blocks/composite/regulated_cascoded_cmirror/LVS/lvs/M/M_pex.spice @@ -0,0 +1,286 @@ +* NGSPICE file created from M.ext - technology: gf180mcuD + +.subckt M VIN VSS VDD VOUT_VIN VOUT_RCCM VOUT_SBCM VOUT_VCM VAUX EN +X0 a_n1900_n6686# a_n1900_n6686# VDD VDD pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X1 a_n28653_8045# a_n28653_8045# a_n25601_10951# VSS nfet_03v3 ad=4.8p pd=17.2u as=4.8p ps=17.2u w=8u l=1u +X2 a_990_n6686# VIN a_470_n6686# VDD pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X3 a_n1900_n6686# EN VDD VDD pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X4 VSS VSS VSS VSS nfet_03v3 ad=2.32p pd=9.16u as=0.1744n ps=0.65672m w=4u l=1u +X5 VSS VSS VSS VSS nfet_03v3 ad=4.64p pd=17.16u as=0 ps=0 w=8u l=1u +X6 a_6447_5389# a_990_n6686# VSS VSS nfet_03v3 ad=2.4p pd=9.2u as=2.4p ps=9.2u w=4u l=1u +X7 a_n37343_8045# a_n37343_8045# VDD VDD pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X8 VDD VDD VDD VDD pfet_03v3 ad=5.8p pd=21.16u as=0.4068n ps=1.46136m w=10u l=2u +X9 a_7083_483# a_7083_483# VSS VSS nfet_03v3 ad=2.4p pd=9.2u as=2.4p ps=9.2u w=4u l=1u +X10 a_6447_5389# a_990_n6686# VSS VSS nfet_03v3 ad=2.4p pd=9.2u as=2.4p ps=9.2u w=4u l=1u +X11 VDD VDD VDD VDD pfet_03v3 ad=5.8p pd=21.16u as=0 ps=0 w=10u l=2u +X12 VAUX VAUX a_n37343_8045# VDD pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X13 a_n16059_8045# a_n16059_8045# VDD VDD pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X14 a_n25601_10951# a_n25601_10951# VSS VSS nfet_03v3 ad=4.8p pd=17.2u as=4.8p ps=17.2u w=8u l=1u +X15 a_n19111_10951# a_n19111_10951# a_n16059_8045# VDD pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X16 a_n25601_10951# a_n25601_10951# VSS VSS nfet_03v3 ad=4.8p pd=17.2u as=4.8p ps=17.2u w=8u l=1u +X17 a_n28653_8045# a_n28653_8045# a_n25601_10951# VSS nfet_03v3 ad=4.8p pd=17.2u as=4.8p ps=17.2u w=8u l=1u +X18 VDD VDD VDD VDD pfet_03v3 ad=5.8p pd=21.16u as=0 ps=0 w=10u l=2u +X19 VAUX VAUX a_n37343_8045# VDD pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X20 VSS VSS VSS VSS nfet_03v3 ad=2.32p pd=9.16u as=0 ps=0 w=4u l=1u +X21 VSS VSS VSS VSS nfet_03v3 ad=4.64p pd=17.16u as=0 ps=0 w=8u l=1u +X22 a_n590_n6686# VIN a_n1110_n6686# VDD pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X23 a_n19111_10951# a_n19111_10951# a_n16059_8045# VDD pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X24 VDD VDD VDD VDD pfet_03v3 ad=5.8p pd=21.16u as=0 ps=0 w=10u l=2u +X25 a_n1900_n6686# EN VDD VDD pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X26 a_n16059_8045# EN VDD VDD pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X27 a_n28653_8045# a_n28653_8045# a_n25601_10951# VSS nfet_03v3 ad=4.8p pd=17.2u as=4.8p ps=17.2u w=8u l=1u +X28 VSS VSS VSS VSS nfet_03v3 ad=2.32p pd=9.16u as=0 ps=0 w=4u l=1u +X29 VDD VDD VDD VDD pfet_03v3 ad=5.8p pd=21.16u as=0 ps=0 w=10u l=2u +X30 a_n25601_10951# a_n25601_10951# VSS VSS nfet_03v3 ad=4.8p pd=17.2u as=4.8p ps=17.2u w=8u l=1u +X31 VAUX VAUX a_n37343_8045# VDD pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X32 VSS VSS VSS VSS nfet_03v3 ad=4.64p pd=17.16u as=0 ps=0 w=8u l=1u +X33 a_n37343_8045# a_n37343_8045# VDD VDD pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X34 a_n7369_8045# a_n19111_10951# a_n7889_8045# VDD pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X35 a_n37343_8045# EN VDD VDD pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X36 a_n590_n6686# a_n590_n6686# VSS VSS nfet_03v3 ad=2.4p pd=9.2u as=2.4p ps=9.2u w=4u l=1u +X37 a_n28653_8045# a_n28653_8045# a_n25601_10951# VSS nfet_03v3 ad=4.8p pd=17.2u as=4.8p ps=17.2u w=8u l=1u +X38 VSS VSS VSS VSS nfet_03v3 ad=2.32p pd=9.16u as=0 ps=0 w=4u l=1u +X39 a_n16059_8045# a_n16059_8045# VDD VDD pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X40 VSS VSS VSS VSS nfet_03v3 ad=4.64p pd=17.16u as=0 ps=0 w=8u l=1u +X41 a_470_n6686# a_n1900_n6686# VDD VDD pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X42 a_n37343_8045# a_n37343_8045# VDD VDD pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X43 VOUT_VIN VIN a_1260_n6686# VDD pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X44 VDD VDD VDD VDD pfet_03v3 ad=5.8p pd=21.16u as=0 ps=0 w=10u l=2u +X45 VSS VSS VSS VSS nfet_03v3 ad=2.32p pd=9.16u as=0 ps=0 w=4u l=1u +X46 a_n1900_n6686# EN VDD VDD pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X47 VOUT_RCCM a_n7369_8045# a_6447_5389# VSS nfet_03v3 ad=2.4p pd=9.2u as=2.4p ps=9.2u w=4u l=1u +X48 a_n19431_10951# a_n25601_10951# VSS VSS nfet_03v3 ad=4.8p pd=17.2u as=4.8p ps=17.2u w=8u l=1u +X49 VAUX VAUX a_n37343_8045# VDD pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X50 VAUX VAUX a_n37343_8045# VDD pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X51 VOUT_RCCM a_n7369_8045# a_6447_5389# VSS nfet_03v3 ad=2.4p pd=9.2u as=2.4p ps=9.2u w=4u l=1u +X52 VDD VDD VDD VDD pfet_03v3 ad=5.8p pd=21.16u as=0 ps=0 w=10u l=2u +X53 a_n25601_10951# a_n25601_10951# VSS VSS nfet_03v3 ad=4.8p pd=17.2u as=4.8p ps=17.2u w=8u l=1u +X54 a_7673_483# a_7083_483# VSS VSS nfet_03v3 ad=2.4p pd=9.2u as=2.4p ps=9.2u w=4u l=1u +X55 a_n16059_8045# a_n16059_8045# VDD VDD pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X56 a_n28653_8045# a_n28653_8045# a_n25601_10951# VSS nfet_03v3 ad=4.8p pd=17.2u as=4.8p ps=17.2u w=8u l=1u +X57 a_n19111_10951# a_n19111_10951# a_n16059_8045# VDD pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X58 a_n37343_8045# a_n37343_8045# VDD VDD pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X59 VSS VSS VSS VSS nfet_03v3 ad=2.32p pd=9.16u as=0 ps=0 w=4u l=1u +X60 a_n37343_8045# a_n37343_8045# VDD VDD pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X61 VSS VSS VSS VSS nfet_03v3 ad=2.32p pd=9.16u as=0 ps=0 w=4u l=1u +X62 a_n19111_10951# a_n19111_10951# a_n16059_8045# VDD pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X63 a_n1110_n6686# a_n1900_n6686# VDD VDD pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X64 a_n19111_10951# a_n19111_10951# a_n16059_8045# VDD pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X65 VDD VDD VDD VDD pfet_03v3 ad=5.8p pd=21.16u as=0 ps=0 w=10u l=2u +X66 a_n16059_8045# a_n16059_8045# VDD VDD pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X67 a_n16059_8045# a_n16059_8045# VDD VDD pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X68 a_n37343_8045# a_n37343_8045# VDD VDD pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X69 VSS VSS VSS VSS nfet_03v3 ad=2.32p pd=9.16u as=0 ps=0 w=4u l=1u +X70 VDD VDD VDD VDD pfet_03v3 ad=5.8p pd=21.16u as=0 ps=0 w=10u l=2u +X71 VAUX VAUX a_n37343_8045# VDD pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X72 a_n28653_8045# a_n28653_8045# a_n25601_10951# VSS nfet_03v3 ad=4.8p pd=17.2u as=4.8p ps=17.2u w=8u l=1u +X73 VSS VSS VSS VSS nfet_03v3 ad=2.32p pd=9.16u as=0 ps=0 w=4u l=1u +X74 a_n7369_8045# a_6447_5389# VSS VSS nfet_03v3 ad=2.4p pd=9.2u as=2.4p ps=9.2u w=4u l=1u +X75 a_n19111_10951# a_n19111_10951# a_n16059_8045# VDD pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X76 a_n7369_8045# a_6567_9285# VSS VSS nfet_03v3 ad=2.4p pd=9.2u as=2.4p ps=9.2u w=4u l=1u +X77 a_n7369_8045# a_6447_5389# VSS VSS nfet_03v3 ad=2.4p pd=9.2u as=2.4p ps=9.2u w=4u l=1u +X78 a_n7369_8045# a_6567_9285# VSS VSS nfet_03v3 ad=2.4p pd=9.2u as=2.4p ps=9.2u w=4u l=1u +X79 VDD VDD VDD VDD pfet_03v3 ad=5.8p pd=21.16u as=0 ps=0 w=10u l=2u +X80 VOUT_VCM a_n590_n6686# VSS VSS nfet_03v3 ad=2.4p pd=9.2u as=2.4p ps=9.2u w=4u l=1u +X81 a_n1900_n6686# EN VDD VDD pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X82 a_n28653_8045# a_n28653_8045# a_n25601_10951# VSS nfet_03v3 ad=4.8p pd=17.2u as=4.8p ps=17.2u w=8u l=1u +X83 a_1260_n6686# a_n1900_n6686# VDD VDD pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X84 a_n7889_8045# a_n16059_8045# VDD VDD pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X85 a_n37343_8045# a_n37343_8045# VDD VDD pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X86 a_n28653_8045# VAUX a_n29173_8045# VDD pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X87 VSS VSS VSS VSS nfet_03v3 ad=2.32p pd=9.16u as=0 ps=0 w=4u l=1u +X88 a_n29173_8045# a_n37343_8045# VDD VDD pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X89 a_200_n6686# VIN a_n320_n6686# VDD pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X90 VIN VIN a_n1900_n6686# VDD pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X91 a_n16059_8045# a_n16059_8045# VDD VDD pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X92 a_n28653_8045# a_n28653_8045# a_n25601_10951# VSS nfet_03v3 ad=4.8p pd=17.2u as=4.8p ps=17.2u w=8u l=1u +X93 VAUX VAUX a_n37343_8045# VDD pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X94 a_n16059_8045# a_n16059_8045# VDD VDD pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X95 a_n25601_10951# a_n25601_10951# VSS VSS nfet_03v3 ad=4.8p pd=17.2u as=4.8p ps=17.2u w=8u l=1u +X96 a_n19111_10951# a_n28653_8045# a_n19431_10951# VSS nfet_03v3 ad=4.8p pd=17.2u as=4.8p ps=17.2u w=8u l=1u +X97 a_n37343_8045# a_n37343_8045# VDD VDD pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X98 VDD VDD VDD VDD pfet_03v3 ad=5.8p pd=21.16u as=0 ps=0 w=10u l=2u +X99 VDD VDD VDD VDD pfet_03v3 ad=5.8p pd=21.16u as=0 ps=0 w=10u l=2u +X100 a_n25601_10951# a_n25601_10951# VSS VSS nfet_03v3 ad=4.8p pd=17.2u as=4.8p ps=17.2u w=8u l=1u +X101 a_200_n6686# a_200_n6686# a_7083_483# VSS nfet_03v3 ad=2.4p pd=9.2u as=2.4p ps=9.2u w=4u l=1u +X102 a_990_n6686# a_n7369_8045# a_6567_9285# VSS nfet_03v3 ad=2.4p pd=9.2u as=2.4p ps=9.2u w=4u l=1u +X103 VAUX VAUX a_n37343_8045# VDD pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X104 VSS VSS VSS VSS nfet_03v3 ad=2.32p pd=9.16u as=0 ps=0 w=4u l=1u +X105 a_990_n6686# a_n7369_8045# a_6567_9285# VSS nfet_03v3 ad=2.4p pd=9.2u as=2.4p ps=9.2u w=4u l=1u +X106 VDD VDD VDD VDD pfet_03v3 ad=5.8p pd=21.16u as=0 ps=0 w=10u l=2u +X107 a_n16059_8045# a_n16059_8045# VDD VDD pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X108 a_n19111_10951# a_n19111_10951# a_n16059_8045# VDD pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X109 VAUX VAUX a_n37343_8045# VDD pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X110 VSS VSS VSS VSS nfet_03v3 ad=2.32p pd=9.16u as=0 ps=0 w=4u l=1u +X111 a_n19111_10951# a_n19111_10951# a_n16059_8045# VDD pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X112 VDD VDD VDD VDD pfet_03v3 ad=5.8p pd=21.16u as=0 ps=0 w=10u l=2u +X113 a_n28653_8045# a_n28653_8045# a_n25601_10951# VSS nfet_03v3 ad=4.8p pd=17.2u as=4.8p ps=17.2u w=8u l=1u +X114 VAUX VAUX a_n37343_8045# VDD pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X115 a_6567_9285# a_990_n6686# VSS VSS nfet_03v3 ad=2.4p pd=9.2u as=2.4p ps=9.2u w=4u l=1u +X116 a_n28653_8045# a_n28653_8045# a_n25601_10951# VSS nfet_03v3 ad=4.8p pd=17.2u as=4.8p ps=17.2u w=8u l=1u +X117 a_n19111_10951# a_n19111_10951# a_n16059_8045# VDD pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X118 VDD VDD VDD VDD pfet_03v3 ad=5.8p pd=21.16u as=0 ps=0 w=10u l=2u +X119 a_6567_9285# a_990_n6686# VSS VSS nfet_03v3 ad=2.4p pd=9.2u as=2.4p ps=9.2u w=4u l=1u +X120 a_n25601_10951# a_n25601_10951# VSS VSS nfet_03v3 ad=4.8p pd=17.2u as=4.8p ps=17.2u w=8u l=1u +X121 a_n16059_8045# a_n16059_8045# VDD VDD pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X122 a_n16059_8045# a_n16059_8045# VDD VDD pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X123 a_n25601_10951# a_n25601_10951# VSS VSS nfet_03v3 ad=4.8p pd=17.2u as=4.8p ps=17.2u w=8u l=1u +X124 VDD VDD VDD VDD pfet_03v3 ad=5.8p pd=21.16u as=0 ps=0 w=10u l=2u +X125 a_n19111_10951# a_n19111_10951# a_n16059_8045# VDD pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X126 a_n37343_8045# a_n37343_8045# VDD VDD pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X127 a_n25601_10951# a_n25601_10951# VSS VSS nfet_03v3 ad=4.8p pd=17.2u as=4.8p ps=17.2u w=8u l=1u +X128 VDD VDD VDD VDD pfet_03v3 ad=5.8p pd=21.16u as=0 ps=0 w=10u l=2u +X129 a_n37343_8045# a_n37343_8045# VDD VDD pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X130 a_n25601_10951# a_n25601_10951# VSS VSS nfet_03v3 ad=4.8p pd=17.2u as=4.8p ps=17.2u w=8u l=1u +X131 VOUT_SBCM a_200_n6686# a_7673_483# VSS nfet_03v3 ad=2.4p pd=9.2u as=2.4p ps=9.2u w=4u l=1u +X132 VDD VDD VDD VDD pfet_03v3 ad=5.8p pd=21.16u as=0 ps=0 w=10u l=2u +X133 a_n320_n6686# a_n1900_n6686# VDD VDD pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +C0 a_470_n6686# a_990_n6686# 2.39829f +C1 a_n590_n6686# a_990_n6686# 0.10021f +C2 a_6567_9285# a_6447_5389# 0.36393f +C3 a_n28653_8045# a_n37343_8045# 0.07017f +C4 VIN VDD 14.5927f +C5 a_990_n6686# a_n7369_8045# 1.5128f +C6 VDD a_200_n6686# 1.12778f +C7 VIN EN 0.08902f +C8 a_n7889_8045# a_n7369_8045# 0.8533f +C9 VDD VAUX 16.3092f +C10 VOUT_VIN a_n1110_n6686# 0.13684f +C11 EN VAUX 0.00331f +C12 a_n19111_10951# a_n7369_8045# 0.50349f +C13 a_990_n6686# a_n1900_n6686# 0.59986f +C14 a_1260_n6686# a_n320_n6686# 0.30154f +C15 a_470_n6686# VOUT_VIN 0.13662f +C16 a_470_n6686# a_n1110_n6686# 0.34178f +C17 a_n19431_10951# a_n19111_10951# 1.13981f +C18 a_n590_n6686# VOUT_VIN 0.08091f +C19 a_n590_n6686# a_n1110_n6686# 2.41261f +C20 VAUX a_n29173_8045# 0.99903f +C21 VIN a_990_n6686# 0.62193f +C22 a_200_n6686# a_990_n6686# 0.33183f +C23 VOUT_VIN a_n7369_8045# 0.2166f +C24 VDD a_n37343_8045# 48.8544f +C25 a_990_n6686# a_6447_5389# 0.85546f +C26 a_6567_9285# VOUT_RCCM 0.0136f +C27 EN a_n37343_8045# 0.74385f +C28 a_470_n6686# a_n590_n6686# 0.10043f +C29 VDD a_n320_n6686# 7.43186f +C30 EN a_n320_n6686# 0.0069f +C31 VOUT_SBCM a_7083_483# 0.0849f +C32 VOUT_VIN a_n1900_n6686# 0.98673f +C33 a_n1110_n6686# a_n1900_n6686# 1.80913f +C34 a_200_n6686# a_7083_483# 1.85176f +C35 VDD a_n28653_8045# 1.76606f +C36 EN a_n28653_8045# 0.01878f +C37 a_n29173_8045# a_n37343_8045# 0.98664f +C38 a_470_n6686# a_n1900_n6686# 1.46461f +C39 VIN VOUT_VIN 0.63897f +C40 VIN a_n1110_n6686# 2.86501f +C41 a_n590_n6686# a_n1900_n6686# 0.13364f +C42 a_200_n6686# VOUT_VIN 0.08038f +C43 a_200_n6686# a_n1110_n6686# 0.17152f +C44 a_990_n6686# a_n320_n6686# 0.17025f +C45 a_1260_n6686# VDD 6.35462f +C46 VDD a_n16059_8045# 48.8285f +C47 a_n28653_8045# a_n29173_8045# 0.91714f +C48 a_1260_n6686# EN 0.28741f +C49 a_470_n6686# VIN 0.62333f +C50 a_990_n6686# VOUT_RCCM 0.00933f +C51 a_470_n6686# a_200_n6686# 2.29847f +C52 VIN a_n590_n6686# 0.63416f +C53 EN a_n16059_8045# 0.7554f +C54 a_n590_n6686# a_200_n6686# 0.58599f +C55 VOUT_VCM a_n590_n6686# 0.20751f +C56 a_n28653_8045# a_n19111_10951# 0.28491f +C57 a_6447_5389# a_n7369_8045# 3.29507f +C58 VDD EN 19.3145f +C59 VIN a_n1900_n6686# 3.41485f +C60 a_7673_483# a_7083_483# 0.36588f +C61 VOUT_VIN a_n320_n6686# 0.13558f +C62 a_n1110_n6686# a_n320_n6686# 0.84535f +C63 a_1260_n6686# a_990_n6686# 2.29591f +C64 a_200_n6686# a_n1900_n6686# 0.13521f +C65 a_n7889_8045# a_n16059_8045# 0.98664f +C66 a_6567_9285# a_990_n6686# 3.00275f +C67 VDD a_n29173_8045# 3.05677f +C68 a_n19431_10951# a_n25601_10951# 0.52252f +C69 a_n19111_10951# a_n16059_8045# 29.4825f +C70 a_470_n6686# a_n320_n6686# 0.84407f +C71 VIN VOUT_SBCM 0.09167f +C72 EN a_n29173_8045# 0 +C73 a_200_n6686# VOUT_SBCM 0.2042f +C74 a_n590_n6686# a_n320_n6686# 2.30103f +C75 VIN a_200_n6686# 0.62309f +C76 VDD a_990_n6686# 1.72336f +C77 VIN VAUX 0.04936f +C78 VDD a_n7889_8045# 3.05677f +C79 EN a_n7889_8045# 0 +C80 VIN VOUT_VCM 0.09167f +C81 VDD a_n19111_10951# 15.504f +C82 EN a_n19111_10951# 0.01792f +C83 a_1260_n6686# a_n1110_n6686# 0.30103f +C84 a_1260_n6686# VOUT_VIN 2.35844f +C85 VOUT_RCCM a_n7369_8045# 0.57687f +C86 a_n1900_n6686# a_n320_n6686# 1.46427f +C87 a_6567_9285# VOUT_VIN 0 +C88 a_1260_n6686# a_470_n6686# 0.80509f +C89 a_1260_n6686# a_n590_n6686# 0.10003f +C90 VDD VOUT_VIN 2.87066f +C91 VDD a_n1110_n6686# 7.43338f +C92 a_n19431_10951# a_n28653_8045# 0.86502f +C93 VIN a_n320_n6686# 0.63243f +C94 EN a_n1110_n6686# 0.00563f +C95 VAUX a_n37343_8045# 29.489f +C96 a_200_n6686# a_n320_n6686# 2.40482f +C97 a_n7889_8045# a_n19111_10951# 0.99903f +C98 a_n7369_8045# a_n16059_8045# 0.06706f +C99 VIN VOUT_RCCM 0.09259f +C100 a_6567_9285# a_n7369_8045# 3.58908f +C101 a_470_n6686# VDD 7.51371f +C102 VDD a_n590_n6686# 1.21291f +C103 a_6447_5389# VOUT_RCCM 2.17202f +C104 a_470_n6686# EN 0.00915f +C105 a_7673_483# VOUT_SBCM 1.15251f +C106 a_1260_n6686# a_n1900_n6686# 2.37681f +C107 a_7673_483# a_200_n6686# 1.45997f +C108 VAUX a_n28653_8045# 0.50349f +C109 VDD a_n7369_8045# 1.56533f +C110 EN a_n7369_8045# 0.04936f +C111 a_n28653_8045# a_n25601_10951# 36.6185f +C112 a_990_n6686# VOUT_VIN 2.48301f +C113 a_990_n6686# a_n1110_n6686# 0.17047f +C114 a_1260_n6686# VIN 0.62105f +C115 a_1260_n6686# a_200_n6686# 0.10042f +C116 VDD a_n1900_n6686# 44.8668f +C117 EN a_n1900_n6686# 2.15734f +C118 VOUT_VCM VSS 6.08797f +C119 VOUT_SBCM VSS 4.73981f +C120 VOUT_RCCM VSS 5.9534f +C121 VOUT_VIN VSS 10.4914f +C122 VIN VSS 33.1407f +C123 VAUX VSS 25.3616f +C124 EN VSS 24.0789f +C125 VDD VSS 0.95p +C126 a_7673_483# VSS 2.90137f +C127 a_7083_483# VSS 6.39712f +C128 a_6447_5389# VSS 8.54632f +C129 a_6567_9285# VSS 7.6582f +C130 a_990_n6686# VSS 11.5475f +C131 a_200_n6686# VSS 5.05938f +C132 a_n590_n6686# VSS 7.97268f +C133 a_1260_n6686# VSS 0.15844f +C134 a_470_n6686# VSS 0.03326f +C135 a_n320_n6686# VSS 0.03284f +C136 a_n1110_n6686# VSS 0.03295f +C137 a_n1900_n6686# VSS 2.60775f +C138 a_n7369_8045# VSS 18.1527f +C139 a_n7889_8045# VSS 0.29295f +C140 a_n19111_10951# VSS 4.92556f +C141 a_n19431_10951# VSS 2.7563f +C142 a_n25601_10951# VSS 40.1477f +C143 a_n28653_8045# VSS 12.9247f +C144 a_n29173_8045# VSS 0.20081f +C145 a_n16059_8045# VSS 3.24753f +C146 a_n37343_8045# VSS 3.20723f +.ends + diff --git a/blocks/composite/regulated_cascoded_cmirror/LVS/lvs/M/M_sim.spice b/blocks/composite/regulated_cascoded_cmirror/LVS/lvs/M/M_sim.spice new file mode 100644 index 00000000..21b6da0f --- /dev/null +++ b/blocks/composite/regulated_cascoded_cmirror/LVS/lvs/M/M_sim.spice @@ -0,0 +1,312 @@ +| units: 0.5 tech: gf180mcuD format: MIT +x a_n1900_n6686# VDD a_n1900_n6686# VDD s=240000,4240 d=240000,4240 l=400 w=2000 x=-1779 y=-1337 pfet_03v3 +x a_n28653_8045# a_n25601_10951# a_n28653_8045# VSS s=192000,3440 d=192000,3440 l=200 w=1600 x=-23120 y=10951 nfet_03v3 +x VIN a_470_n6686# a_990_n6686# VDD s=240000,4240 d=240000,4240 l=400 w=2000 x=590 y=-6685 pfet_03v3 +x EN VDD a_n1900_n6686# VDD s=240000,4240 d=240000,4240 l=400 w=2000 x=195 y=4114 pfet_03v3 +x VSS VSS VSS VSS d=92800,1832 l=200 w=800 x=6595 y=-1654 nfet_03v3 +x VSS VSS VSS VSS d=185600,3432 l=200 w=1600 x=-18702 y=10951 nfet_03v3 +x a_990_n6686# VSS a_6447_5389# VSS s=96000,1840 d=96000,1840 l=200 w=800 x=7157 y=7527 nfet_03v3 +x a_n37343_8045# VDD a_n37343_8045# VDD s=240000,4240 d=240000,4240 l=400 w=2000 x=-36432 y=10951 pfet_03v3 +x VDD VDD VDD VDD d=232000,4232 l=400 w=2000 x=-28244 y=8045 pfet_03v3 +x a_7083_483# VSS a_7083_483# VSS s=96000,1840 d=96000,1840 l=200 w=800 x=7203 y=-1654 nfet_03v3 +x a_990_n6686# VSS a_6447_5389# VSS s=96000,1840 d=96000,1840 l=200 w=800 x=8337 y=7527 nfet_03v3 +x VDD VDD VDD VDD d=232000,4232 l=400 w=2000 x=2188 y=-6685 pfet_03v3 +x VAUX a_n37343_8045# VAUX VDD s=240000,4240 d=240000,4240 l=400 w=2000 x=-33272 y=8045 pfet_03v3 +x a_n16059_8045# VDD a_n16059_8045# VDD s=240000,4240 d=240000,4240 l=400 w=2000 x=-13568 y=10951 pfet_03v3 +x a_n25601_10951# VSS a_n25601_10951# VSS s=192000,3440 d=192000,3440 l=200 w=1600 x=-23120 y=8445 nfet_03v3 +x a_n19111_10951# a_n16059_8045# a_n19111_10951# VDD s=240000,4240 d=240000,4240 l=400 w=2000 x=-8828 y=8045 pfet_03v3 +x a_n25601_10951# VSS a_n25601_10951# VSS s=192000,3440 d=192000,3440 l=200 w=1600 x=-24300 y=8445 nfet_03v3 +x a_n28653_8045# a_n25601_10951# a_n28653_8045# VSS s=192000,3440 d=192000,3440 l=200 w=1600 x=-21350 y=10951 nfet_03v3 +x VDD VDD VDD VDD d=232000,4232 l=400 w=2000 x=-28244 y=10951 pfet_03v3 +x VAUX a_n37343_8045# VAUX VDD s=240000,4240 d=240000,4240 l=400 w=2000 x=-34852 y=8045 pfet_03v3 +x VSS VSS VSS VSS d=92800,1832 l=200 w=800 x=6595 y=483 nfet_03v3 +x VSS VSS VSS VSS d=185600,3432 l=200 w=1600 x=-26088 y=10951 nfet_03v3 +x VIN a_n1110_n6686# a_n590_n6686# VDD s=240000,4240 d=240000,4240 l=400 w=2000 x=-989 y=-6685 pfet_03v3 +x a_n19111_10951# a_n16059_8045# a_n19111_10951# VDD s=240000,4240 d=240000,4240 l=400 w=2000 x=-13568 y=8045 pfet_03v3 +x VDD VDD VDD VDD d=232000,4232 l=400 w=2000 x=-2587 y=-6685 pfet_03v3 +x EN VDD a_n1900_n6686# VDD s=240000,4240 d=240000,4240 l=400 w=2000 x=-594 y=4114 pfet_03v3 +x EN VDD a_n16059_8045# VDD s=240000,4240 d=240000,4240 l=400 w=2000 x=-15938 y=14649 pfet_03v3 +x a_n28653_8045# a_n25601_10951# a_n28653_8045# VSS s=192000,3440 d=192000,3440 l=200 w=1600 x=-25480 y=10951 nfet_03v3 +x VSS VSS VSS VSS d=92800,1832 l=200 w=800 x=6595 y=-8696 nfet_03v3 +x VDD VDD VDD VDD d=232000,4232 l=400 w=2000 x=-2192 y=4114 pfet_03v3 +x a_n25601_10951# VSS a_n25601_10951# VSS s=192000,3440 d=192000,3440 l=200 w=1600 x=-24890 y=8445 nfet_03v3 +x VAUX a_n37343_8045# VAUX VDD s=240000,4240 d=240000,4240 l=400 w=2000 x=-37222 y=8045 pfet_03v3 +x VSS VSS VSS VSS d=185600,3432 l=200 w=1600 x=-26088 y=8445 nfet_03v3 +x a_n37343_8045# VDD a_n37343_8045# VDD s=240000,4240 d=240000,4240 l=400 w=2000 x=-34852 y=10951 pfet_03v3 +x a_n19111_10951# a_n7889_8045# a_n7369_8045# VDD s=240000,4240 d=240000,4240 l=400 w=2000 x=-7768 y=8045 pfet_03v3 +x EN VDD a_n37343_8045# VDD s=240000,4240 d=240000,4240 l=400 w=2000 x=-37222 y=14649 pfet_03v3 +x a_n590_n6686# VSS a_n590_n6686# VSS s=96000,1840 d=96000,1840 l=200 w=800 x=7203 y=-8696 nfet_03v3 +x a_n28653_8045# a_n25601_10951# a_n28653_8045# VSS s=192000,3440 d=192000,3440 l=200 w=1600 x=-24300 y=10951 nfet_03v3 +x VSS VSS VSS VSS d=92800,1832 l=200 w=800 x=5959 y=5389 nfet_03v3 +x a_n16059_8045# VDD a_n16059_8045# VDD s=240000,4240 d=240000,4240 l=400 w=2000 x=-11988 y=10951 pfet_03v3 +x VSS VSS VSS VSS d=185600,3432 l=200 w=1600 x=-18702 y=8445 nfet_03v3 +x a_n1900_n6686# VDD a_470_n6686# VDD s=240000,4240 d=240000,4240 l=400 w=2000 x=590 y=-1337 pfet_03v3 +x a_n37343_8045# VDD a_n37343_8045# VDD s=240000,4240 d=240000,4240 l=400 w=2000 x=-33272 y=10951 pfet_03v3 +x VIN a_1260_n6686# VOUT_VIN VDD s=240000,4240 d=240000,4240 l=400 w=2000 x=1380 y=-6685 pfet_03v3 +x VDD VDD VDD VDD d=232000,4232 l=400 w=2000 x=-15130 y=14649 pfet_03v3 +x VSS VSS VSS VSS d=92800,1832 l=200 w=800 x=8945 y=5389 nfet_03v3 +x EN VDD a_n1900_n6686# VDD s=240000,4240 d=240000,4240 l=400 w=2000 x=985 y=4114 pfet_03v3 +x a_n7369_8045# a_6447_5389# VOUT_RCCM VSS s=96000,1840 d=96000,1840 l=200 w=800 x=6567 y=5389 nfet_03v3 +x a_n25601_10951# VSS a_n19431_10951# VSS s=192000,3440 d=192000,3440 l=200 w=1600 x=-19310 y=8445 nfet_03v3 +x VAUX a_n37343_8045# VAUX VDD s=240000,4240 d=240000,4240 l=400 w=2000 x=-32482 y=8045 pfet_03v3 +x VAUX a_n37343_8045# VAUX VDD s=240000,4240 d=240000,4240 l=400 w=2000 x=-30112 y=8045 pfet_03v3 +x a_n7369_8045# a_6447_5389# VOUT_RCCM VSS s=96000,1840 d=96000,1840 l=200 w=800 x=7747 y=5389 nfet_03v3 +x VDD VDD VDD VDD d=232000,4232 l=400 w=2000 x=2188 y=-1337 pfet_03v3 +x a_n25601_10951# VSS a_n25601_10951# VSS s=192000,3440 d=192000,3440 l=200 w=1600 x=-25480 y=8445 nfet_03v3 +x a_7083_483# VSS a_7673_483# VSS s=96000,1840 d=96000,1840 l=200 w=800 x=7793 y=-1654 nfet_03v3 +x a_n16059_8045# VDD a_n16059_8045# VDD s=240000,4240 d=240000,4240 l=400 w=2000 x=-15938 y=10951 pfet_03v3 +x a_n28653_8045# a_n25601_10951# a_n28653_8045# VSS s=192000,3440 d=192000,3440 l=200 w=1600 x=-22530 y=10951 nfet_03v3 +x a_n19111_10951# a_n16059_8045# a_n19111_10951# VDD s=240000,4240 d=240000,4240 l=400 w=2000 x=-11198 y=8045 pfet_03v3 +x a_n37343_8045# VDD a_n37343_8045# VDD s=240000,4240 d=240000,4240 l=400 w=2000 x=-37222 y=10951 pfet_03v3 +x VSS VSS VSS VSS d=92800,1832 l=200 w=800 x=8401 y=-1654 nfet_03v3 +x a_n37343_8045# VDD a_n37343_8045# VDD s=240000,4240 d=240000,4240 l=400 w=2000 x=-30902 y=10951 pfet_03v3 +x VSS VSS VSS VSS d=92800,1832 l=200 w=800 x=5959 y=9665 nfet_03v3 +x a_n19111_10951# a_n16059_8045# a_n19111_10951# VDD s=240000,4240 d=240000,4240 l=400 w=2000 x=-12778 y=8045 pfet_03v3 +x a_n1900_n6686# VDD a_n1110_n6686# VDD s=240000,4240 d=240000,4240 l=400 w=2000 x=-989 y=-1337 pfet_03v3 +x a_n19111_10951# a_n16059_8045# a_n19111_10951# VDD s=240000,4240 d=240000,4240 l=400 w=2000 x=-10408 y=8045 pfet_03v3 +x VDD VDD VDD VDD d=232000,4232 l=400 w=2000 x=-2587 y=-1337 pfet_03v3 +x a_n16059_8045# VDD a_n16059_8045# VDD s=240000,4240 d=240000,4240 l=400 w=2000 x=-8828 y=10951 pfet_03v3 +x a_n16059_8045# VDD a_n16059_8045# VDD s=240000,4240 d=240000,4240 l=400 w=2000 x=-14358 y=10951 pfet_03v3 +x a_n37343_8045# VDD a_n37343_8045# VDD s=240000,4240 d=240000,4240 l=400 w=2000 x=-31692 y=10951 pfet_03v3 +x VSS VSS VSS VSS d=92800,1832 l=200 w=800 x=8945 y=9665 nfet_03v3 +x VDD VDD VDD VDD d=232000,4232 l=400 w=2000 x=-16746 y=8045 pfet_03v3 +x VAUX a_n37343_8045# VAUX VDD s=240000,4240 d=240000,4240 l=400 w=2000 x=-36432 y=8045 pfet_03v3 +x a_n28653_8045# a_n25601_10951# a_n28653_8045# VSS s=192000,3440 d=192000,3440 l=200 w=1600 x=-20760 y=10951 nfet_03v3 +x VSS VSS VSS VSS d=92800,1832 l=200 w=800 x=8401 y=483 nfet_03v3 +x a_6447_5389# VSS a_n7369_8045# VSS s=96000,1840 d=96000,1840 l=200 w=800 x=7157 y=5389 nfet_03v3 +x a_n19111_10951# a_n16059_8045# a_n19111_10951# VDD s=240000,4240 d=240000,4240 l=400 w=2000 x=-15148 y=8045 pfet_03v3 +x a_6567_9285# VSS a_n7369_8045# VSS s=96000,1840 d=96000,1840 l=200 w=800 x=6567 y=9665 nfet_03v3 +x a_6447_5389# VSS a_n7369_8045# VSS s=96000,1840 d=96000,1840 l=200 w=800 x=8337 y=5389 nfet_03v3 +x a_6567_9285# VSS a_n7369_8045# VSS s=96000,1840 d=96000,1840 l=200 w=800 x=7747 y=9665 nfet_03v3 +x VDD VDD VDD VDD d=232000,4232 l=400 w=2000 x=1793 y=4114 pfet_03v3 +x a_n590_n6686# VSS VOUT_VCM VSS s=96000,1840 d=96000,1840 l=200 w=800 x=7793 y=-8696 nfet_03v3 +x EN VDD a_n1900_n6686# VDD s=240000,4240 d=240000,4240 l=400 w=2000 x=-1384 y=4114 pfet_03v3 +x a_n28653_8045# a_n25601_10951# a_n28653_8045# VSS s=192000,3440 d=192000,3440 l=200 w=1600 x=-24890 y=10951 nfet_03v3 +x a_n1900_n6686# VDD a_1260_n6686# VDD s=240000,4240 d=240000,4240 l=400 w=2000 x=1380 y=-1337 pfet_03v3 +x a_n16059_8045# VDD a_n7889_8045# VDD s=240000,4240 d=240000,4240 l=400 w=2000 x=-7768 y=10951 pfet_03v3 +x a_n37343_8045# VDD a_n37343_8045# VDD s=240000,4240 d=240000,4240 l=400 w=2000 x=-35642 y=10951 pfet_03v3 +x VAUX a_n29173_8045# a_n28653_8045# VDD s=240000,4240 d=240000,4240 l=400 w=2000 x=-29052 y=8045 pfet_03v3 +x VSS VSS VSS VSS d=92800,1832 l=200 w=800 x=8401 y=-8696 nfet_03v3 +x a_n37343_8045# VDD a_n29173_8045# VDD s=240000,4240 d=240000,4240 l=400 w=2000 x=-29052 y=10951 pfet_03v3 +x VIN a_n320_n6686# a_200_n6686# VDD s=240000,4240 d=240000,4240 l=400 w=2000 x=-199 y=-6685 pfet_03v3 +x VIN a_n1900_n6686# VIN VDD s=240000,4240 d=240000,4240 l=400 w=2000 x=-1779 y=-6685 pfet_03v3 +x a_n16059_8045# VDD a_n16059_8045# VDD s=240000,4240 d=240000,4240 l=400 w=2000 x=-12778 y=10951 pfet_03v3 +x a_n28653_8045# a_n25601_10951# a_n28653_8045# VSS s=192000,3440 d=192000,3440 l=200 w=1600 x=-23710 y=10951 nfet_03v3 +x VAUX a_n37343_8045# VAUX VDD s=240000,4240 d=240000,4240 l=400 w=2000 x=-31692 y=8045 pfet_03v3 +x a_n16059_8045# VDD a_n16059_8045# VDD s=240000,4240 d=240000,4240 l=400 w=2000 x=-10408 y=10951 pfet_03v3 +x a_n25601_10951# VSS a_n25601_10951# VSS s=192000,3440 d=192000,3440 l=200 w=1600 x=-20760 y=8445 nfet_03v3 +x a_n28653_8045# a_n19431_10951# a_n19111_10951# VSS s=192000,3440 d=192000,3440 l=200 w=1600 x=-19310 y=10951 nfet_03v3 +x a_n37343_8045# VDD a_n37343_8045# VDD s=240000,4240 d=240000,4240 l=400 w=2000 x=-34062 y=10951 pfet_03v3 +x VDD VDD VDD VDD d=232000,4232 l=400 w=2000 x=-16746 y=14649 pfet_03v3 +x VDD VDD VDD VDD d=232000,4232 l=400 w=2000 x=-36414 y=14649 pfet_03v3 +x a_n25601_10951# VSS a_n25601_10951# VSS s=192000,3440 d=192000,3440 l=200 w=1600 x=-21940 y=8445 nfet_03v3 +x a_200_n6686# a_7083_483# a_200_n6686# VSS s=96000,1840 d=96000,1840 l=200 w=800 x=7203 y=483 nfet_03v3 +x a_n7369_8045# a_6567_9285# a_990_n6686# VSS s=96000,1840 d=96000,1840 l=200 w=800 x=7157 y=9665 nfet_03v3 +x VAUX a_n37343_8045# VAUX VDD s=240000,4240 d=240000,4240 l=400 w=2000 x=-30902 y=8045 pfet_03v3 +x VSS VSS VSS VSS d=92800,1832 l=200 w=800 x=5959 y=7527 nfet_03v3 +x a_n7369_8045# a_6567_9285# a_990_n6686# VSS s=96000,1840 d=96000,1840 l=200 w=800 x=8337 y=9665 nfet_03v3 +x VDD VDD VDD VDD d=232000,4232 l=400 w=2000 x=-38030 y=14649 pfet_03v3 +x a_n16059_8045# VDD a_n16059_8045# VDD s=240000,4240 d=240000,4240 l=400 w=2000 x=-11198 y=10951 pfet_03v3 +x a_n19111_10951# a_n16059_8045# a_n19111_10951# VDD s=240000,4240 d=240000,4240 l=400 w=2000 x=-11988 y=8045 pfet_03v3 +x VAUX a_n37343_8045# VAUX VDD s=240000,4240 d=240000,4240 l=400 w=2000 x=-34062 y=8045 pfet_03v3 +x VSS VSS VSS VSS d=92800,1832 l=200 w=800 x=8945 y=7527 nfet_03v3 +x a_n19111_10951# a_n16059_8045# a_n19111_10951# VDD s=240000,4240 d=240000,4240 l=400 w=2000 x=-9618 y=8045 pfet_03v3 +x VDD VDD VDD VDD d=232000,4232 l=400 w=2000 x=-38030 y=8045 pfet_03v3 +x a_n28653_8045# a_n25601_10951# a_n28653_8045# VSS s=192000,3440 d=192000,3440 l=200 w=1600 x=-21940 y=10951 nfet_03v3 +x VAUX a_n37343_8045# VAUX VDD s=240000,4240 d=240000,4240 l=400 w=2000 x=-35642 y=8045 pfet_03v3 +x a_990_n6686# VSS a_6567_9285# VSS s=96000,1840 d=96000,1840 l=200 w=800 x=6567 y=7527 nfet_03v3 +x a_n28653_8045# a_n25601_10951# a_n28653_8045# VSS s=192000,3440 d=192000,3440 l=200 w=1600 x=-20170 y=10951 nfet_03v3 +x a_n19111_10951# a_n16059_8045# a_n19111_10951# VDD s=240000,4240 d=240000,4240 l=400 w=2000 x=-14358 y=8045 pfet_03v3 +x VDD VDD VDD VDD d=232000,4232 l=400 w=2000 x=-6960 y=10951 pfet_03v3 +x a_990_n6686# VSS a_6567_9285# VSS s=96000,1840 d=96000,1840 l=200 w=800 x=7747 y=7527 nfet_03v3 +x a_n25601_10951# VSS a_n25601_10951# VSS s=192000,3440 d=192000,3440 l=200 w=1600 x=-20170 y=8445 nfet_03v3 +x a_n16059_8045# VDD a_n16059_8045# VDD s=240000,4240 d=240000,4240 l=400 w=2000 x=-9618 y=10951 pfet_03v3 +x a_n16059_8045# VDD a_n16059_8045# VDD s=240000,4240 d=240000,4240 l=400 w=2000 x=-15148 y=10951 pfet_03v3 +x a_n25601_10951# VSS a_n25601_10951# VSS s=192000,3440 d=192000,3440 l=200 w=1600 x=-21350 y=8445 nfet_03v3 +x VDD VDD VDD VDD d=232000,4232 l=400 w=2000 x=-6960 y=8045 pfet_03v3 +x a_n19111_10951# a_n16059_8045# a_n19111_10951# VDD s=240000,4240 d=240000,4240 l=400 w=2000 x=-15938 y=8045 pfet_03v3 +x a_n37343_8045# VDD a_n37343_8045# VDD s=240000,4240 d=240000,4240 l=400 w=2000 x=-32482 y=10951 pfet_03v3 +x a_n25601_10951# VSS a_n25601_10951# VSS s=192000,3440 d=192000,3440 l=200 w=1600 x=-22530 y=8445 nfet_03v3 +x VDD VDD VDD VDD d=232000,4232 l=400 w=2000 x=-16746 y=10951 pfet_03v3 +x a_n37343_8045# VDD a_n37343_8045# VDD s=240000,4240 d=240000,4240 l=400 w=2000 x=-30112 y=10951 pfet_03v3 +x a_n25601_10951# VSS a_n25601_10951# VSS s=192000,3440 d=192000,3440 l=200 w=1600 x=-23710 y=8445 nfet_03v3 +x a_200_n6686# a_7673_483# VOUT_SBCM VSS s=96000,1840 d=96000,1840 l=200 w=800 x=7793 y=483 nfet_03v3 +x VDD VDD VDD VDD d=232000,4232 l=400 w=2000 x=-38030 y=10951 pfet_03v3 +x a_n1900_n6686# VDD a_n320_n6686# VDD s=240000,4240 d=240000,4240 l=400 w=2000 x=-199 y=-1337 pfet_03v3 +C a_n29173_8045# VAUX 1.0 +C a_1260_n6686# a_470_n6686# 0.8 +C EN a_470_n6686# 0.0 +C a_7673_483# a_7083_483# 0.4 +C a_n1110_n6686# VIN 2.9 +C a_990_n6686# VIN 0.6 +C VOUT_VIN a_470_n6686# 0.1 +C a_n7889_8045# VDD 3.1 +C a_n590_n6686# VIN 0.6 +C a_1260_n6686# a_200_n6686# 0.1 +C a_n19111_10951# a_n16059_8045# 29.5 +C a_n28653_8045# EN 0.0 +C VDD a_470_n6686# 7.5 +C a_200_n6686# VOUT_VIN 0.1 +C VOUT_RCCM a_6567_9285# 0.0 +C a_n25601_10951# a_n19431_10951# 0.5 +C a_n37343_8045# a_n28653_8045# 0.1 +C VDD a_200_n6686# 1.1 +C a_6567_9285# a_6447_5389# 0.4 +C a_1260_n6686# a_n1110_n6686# 0.3 +C a_n28653_8045# VDD 1.8 +C EN a_n19111_10951# 0.0 +C a_990_n6686# a_1260_n6686# 2.3 +C a_1260_n6686# a_n590_n6686# 0.1 +C EN a_n1110_n6686# 0.0 +C EN a_n29173_8045# 0.0 +C a_n1110_n6686# VOUT_VIN 0.1 +C a_990_n6686# VOUT_VIN 2.5 +C a_n590_n6686# VOUT_VIN 0.1 +C a_n37343_8045# a_n29173_8045# 1.0 +C a_n19111_10951# VDD 15.5 +C VDD a_n1110_n6686# 7.4 +C a_n1900_n6686# a_n320_n6686# 1.5 +C a_990_n6686# VDD 1.7 +C a_7673_483# VOUT_SBCM 1.2 +C VDD a_n29173_8045# 3.1 +C a_990_n6686# a_6567_9285# 3.0 +C a_200_n6686# a_470_n6686# 2.3 +C a_n590_n6686# VDD 1.2 +C VOUT_SBCM a_7083_483# 0.1 +C VOUT_RCCM a_6447_5389# 2.2 +C a_n19111_10951# a_n7889_8045# 1.0 +C a_n16059_8045# a_n7369_8045# 0.1 +C VIN a_n320_n6686# 0.6 +C a_n1110_n6686# a_470_n6686# 0.3 +C a_990_n6686# a_470_n6686# 2.4 +C a_n590_n6686# a_470_n6686# 0.1 +C a_990_n6686# VOUT_RCCM 0.0 +C a_n1900_n6686# VIN 3.4 +C a_200_n6686# a_n1110_n6686# 0.2 +C EN a_n7369_8045# 0.0 +C a_n28653_8045# a_n19111_10951# 0.3 +C VAUX VIN 0.0 +C a_990_n6686# a_200_n6686# 0.3 +C a_990_n6686# a_6447_5389# 0.9 +C a_n590_n6686# a_200_n6686# 0.6 +C a_n28653_8045# a_n29173_8045# 0.9 +C a_n7369_8045# VOUT_VIN 0.2 +C a_1260_n6686# a_n320_n6686# 0.3 +C a_n590_n6686# VOUT_VCM 0.2 +C EN a_n320_n6686# 0.0 +C VOUT_SBCM VIN 0.1 +C a_n320_n6686# VOUT_VIN 0.1 +C VDD a_n7369_8045# 1.6 +C a_n7369_8045# a_6567_9285# 3.6 +C a_n1900_n6686# a_1260_n6686# 2.4 +C a_990_n6686# a_n1110_n6686# 0.2 +C a_n590_n6686# a_n1110_n6686# 2.4 +C EN a_n1900_n6686# 2.2 +C a_990_n6686# a_n590_n6686# 0.1 +C VDD a_n320_n6686# 7.4 +C a_n1900_n6686# VOUT_VIN 1.0 +C a_n7889_8045# a_n7369_8045# 0.9 +C EN VAUX 0.0 +C a_n25601_10951# a_n28653_8045# 36.6 +C a_1260_n6686# VIN 0.6 +C a_n1900_n6686# VDD 44.9 +C EN VIN 0.1 +C a_n37343_8045# VAUX 29.5 +C VOUT_RCCM a_n7369_8045# 0.6 +C a_7673_483# a_200_n6686# 1.5 +C VIN VOUT_VIN 0.6 +C VDD VAUX 16.3 +C a_200_n6686# a_7083_483# 1.9 +C a_n320_n6686# a_470_n6686# 0.8 +C EN a_n16059_8045# 0.8 +C a_n7369_8045# a_6447_5389# 3.3 +C VDD VIN 14.6 +C a_200_n6686# a_n320_n6686# 2.4 +C a_n1900_n6686# a_470_n6686# 1.5 +C a_n16059_8045# VDD 48.8 +C EN a_1260_n6686# 0.3 +C a_n19111_10951# a_n7369_8045# 0.5 +C a_1260_n6686# VOUT_VIN 2.4 +C a_990_n6686# a_n7369_8045# 1.5 +C a_n1900_n6686# a_200_n6686# 0.1 +C VIN a_470_n6686# 0.6 +C a_n7889_8045# a_n16059_8045# 1.0 +C a_n37343_8045# EN 0.7 +C a_n1110_n6686# a_n320_n6686# 0.8 +C a_1260_n6686# VDD 6.4 +C VOUT_RCCM VIN 0.1 +C a_n28653_8045# a_n19431_10951# 0.9 +C a_990_n6686# a_n320_n6686# 0.2 +C a_n28653_8045# VAUX 0.5 +C a_n590_n6686# a_n320_n6686# 2.3 +C EN VDD 19.3 +C VDD VOUT_VIN 2.9 +C a_6567_9285# VOUT_VIN 0.0 +C a_200_n6686# VIN 0.6 +C VOUT_SBCM a_200_n6686# 0.2 +C a_n1900_n6686# a_n1110_n6686# 1.8 +C VOUT_VCM VIN 0.1 +C a_n37343_8045# VDD 48.9 +C a_990_n6686# a_n1900_n6686# 0.6 +C a_n1900_n6686# a_n590_n6686# 0.1 +C EN a_n7889_8045# 0.0 +C a_n19111_10951# a_n19431_10951# 1.1 +C VOUT_VCM0 6.1 +R VOUT_VCM 55 +C VOUT_SBCM0 4.7 +R VOUT_SBCM 55 +C VOUT_RCCM0 6.0 +R VOUT_RCCM 114 +C VOUT_VIN0 10.5 +R VOUT_VIN 154 +C VIN0 33.1 +R VIN 573 +C VAUX0 25.4 +R VAUX 2060 +C EN0 24.1 +R EN 462 +C VDD0 950.0 +R VDD 38605 +R VSS 12140 +C a_7673_483#0 2.9 +R a_7673_483# 107 +C a_7083_483#0 6.4 +R a_7083_483# 219 +C a_6447_5389#0 8.5 +R a_6447_5389# 340 +C a_6567_9285#0 7.7 +R a_6567_9285# 335 +C a_990_n6686#0 11.5 +R a_990_n6686# 489 +C a_200_n6686#0 5.1 +R a_200_n6686# 293 +C a_n590_n6686#0 8.0 +R a_n590_n6686# 292 +C a_1260_n6686#0 0.2 +R a_1260_n6686# 272 +C a_470_n6686#0 0.0 +R a_470_n6686# 272 +C a_n320_n6686#0 0.0 +R a_n320_n6686# 272 +C a_n1110_n6686#0 0.0 +R a_n1110_n6686# 272 +C a_n1900_n6686#0 2.6 +R a_n1900_n6686# 1220 +C a_n7369_8045#0 18.2 +R a_n7369_8045# 603 +C a_n7889_8045#0 0.3 +R a_n7889_8045# 260 +C a_n19111_10951#0 4.9 +R a_n19111_10951# 2090 +C a_n19431_10951#0 2.8 +R a_n19431_10951# 191 +C a_n25601_10951#0 40.1 +R a_n25601_10951# 2962 +C a_n28653_8045#0 12.9 +R a_n28653_8045# 2054 +C a_n29173_8045#0 0.2 +R a_n29173_8045# 260 +C a_n16059_8045#0 3.2 +R a_n16059_8045# 3505 +C a_n37343_8045#0 3.2 +R a_n37343_8045# 3505 diff --git a/blocks/composite/regulated_cascoded_cmirror/LVS/lvs/RCM/RCM_lvs.rpt b/blocks/composite/regulated_cascoded_cmirror/LVS/lvs/RCM/RCM_lvs.rpt new file mode 100644 index 00000000..e8e9e528 --- /dev/null +++ b/blocks/composite/regulated_cascoded_cmirror/LVS/lvs/RCM/RCM_lvs.rpt @@ -0,0 +1,39 @@ + +Circuit 1 cell nfet_03v3 and Circuit 2 cell nfet_03v3 are black boxes. +Warning: Equate pins: cell nfet_03v3 is a placeholder, treated as a black box. +Warning: Equate pins: cell nfet_03v3 is a placeholder, treated as a black box. + +Subcircuit pins: +Circuit 1: nfet_03v3 |Circuit 2: nfet_03v3 +-------------------------------------------|------------------------------------------- +1 |1 +2 |2 +3 |3 +4 |4 +--------------------------------------------------------------------------------------- +Cell pin lists are equivalent. +Device classes nfet_03v3 and nfet_03v3 are equivalent. + +Class RCM (0): Merged 11 parallel devices. +Subcircuit summary: +Circuit 1: RCM |Circuit 2: RCM +-------------------------------------------|------------------------------------------- +nfet_03v3 (18->7) |nfet_03v3 (18->7) +Number of devices: 7 |Number of devices: 7 +Number of nets: 6 |Number of nets: 6 +--------------------------------------------------------------------------------------- +Netlists match uniquely. + +Subcircuit pins: +Circuit 1: RCM |Circuit 2: RCM +-------------------------------------------|------------------------------------------- +VOUT |VOUT +VSS |VSS +VIN |VIN +VAUX |VAUX +--------------------------------------------------------------------------------------- +Cell pin lists are equivalent. +Device classes RCM and RCM are equivalent. + +Final result: Circuits match uniquely. +. diff --git a/blocks/composite/regulated_cascoded_cmirror/LVS/lvs/RCM/RCM_lvsmag.spice b/blocks/composite/regulated_cascoded_cmirror/LVS/lvs/RCM/RCM_lvsmag.spice new file mode 100644 index 00000000..1cb80284 --- /dev/null +++ b/blocks/composite/regulated_cascoded_cmirror/LVS/lvs/RCM/RCM_lvsmag.spice @@ -0,0 +1,23 @@ +* NGSPICE file created from RCM.ext - technology: gf180mcuD + +.subckt RCM VIN VSS VAUX VOUT +X0 VAUX a_n985_3311# VSS VSS nfet_03v3 ad=2.4p pd=9.2u as=2.4p ps=9.2u w=4u l=1u +X1 a_n1105_n585# VIN VSS VSS nfet_03v3 ad=2.4p pd=9.2u as=2.4p ps=9.2u w=4u l=1u +X2 VSS VSS VSS VSS nfet_03v3 ad=2.32p pd=9.16u as=47.04p ps=0.18352m w=4u l=1u +X3 a_n985_3311# VIN VSS VSS nfet_03v3 ad=2.4p pd=9.2u as=2.4p ps=9.2u w=4u l=1u +X4 VSS VSS VSS VSS nfet_03v3 ad=2.32p pd=9.16u as=0 ps=0 w=4u l=1u +X5 VOUT VAUX a_n1105_n585# VSS nfet_03v3 ad=2.4p pd=9.2u as=2.4p ps=9.2u w=4u l=1u +X6 VSS VSS VSS VSS nfet_03v3 ad=2.32p pd=9.16u as=0 ps=0 w=4u l=1u +X7 VAUX a_n985_3311# VSS VSS nfet_03v3 ad=2.4p pd=9.2u as=2.4p ps=9.2u w=4u l=1u +X8 VAUX a_n1105_n585# VSS VSS nfet_03v3 ad=2.4p pd=9.2u as=2.4p ps=9.2u w=4u l=1u +X9 VSS VSS VSS VSS nfet_03v3 ad=2.32p pd=9.16u as=0 ps=0 w=4u l=1u +X10 VSS VSS VSS VSS nfet_03v3 ad=2.32p pd=9.16u as=0 ps=0 w=4u l=1u +X11 VIN VAUX a_n985_3311# VSS nfet_03v3 ad=2.4p pd=9.2u as=2.4p ps=9.2u w=4u l=1u +X12 VAUX a_n1105_n585# VSS VSS nfet_03v3 ad=2.4p pd=9.2u as=2.4p ps=9.2u w=4u l=1u +X13 a_n985_3311# VIN VSS VSS nfet_03v3 ad=2.4p pd=9.2u as=2.4p ps=9.2u w=4u l=1u +X14 VIN VAUX a_n985_3311# VSS nfet_03v3 ad=2.4p pd=9.2u as=2.4p ps=9.2u w=4u l=1u +X15 VOUT VAUX a_n1105_n585# VSS nfet_03v3 ad=2.4p pd=9.2u as=2.4p ps=9.2u w=4u l=1u +X16 VSS VSS VSS VSS nfet_03v3 ad=2.32p pd=9.16u as=0 ps=0 w=4u l=1u +X17 a_n1105_n585# VIN VSS VSS nfet_03v3 ad=2.4p pd=9.2u as=2.4p ps=9.2u w=4u l=1u +.ends + diff --git a/blocks/composite/regulated_cascoded_cmirror/LVS/lvs/RCM/RCM_pex.spice b/blocks/composite/regulated_cascoded_cmirror/LVS/lvs/RCM/RCM_pex.spice new file mode 100644 index 00000000..17cc7ee0 --- /dev/null +++ b/blocks/composite/regulated_cascoded_cmirror/LVS/lvs/RCM/RCM_pex.spice @@ -0,0 +1,38 @@ +* NGSPICE file created from RCM.ext - technology: gf180mcuD + +.subckt RCM VIN VSS VAUX VOUT +X0 VAUX a_n985_3311# VSS VSS nfet_03v3 ad=2.4p pd=9.2u as=2.4p ps=9.2u w=4u l=1u +X1 a_n1105_n585# VIN VSS VSS nfet_03v3 ad=2.4p pd=9.2u as=2.4p ps=9.2u w=4u l=1u +X2 VSS VSS VSS VSS nfet_03v3 ad=2.32p pd=9.16u as=47.04p ps=0.18352m w=4u l=1u +X3 a_n985_3311# VIN VSS VSS nfet_03v3 ad=2.4p pd=9.2u as=2.4p ps=9.2u w=4u l=1u +X4 VSS VSS VSS VSS nfet_03v3 ad=2.32p pd=9.16u as=0 ps=0 w=4u l=1u +X5 VOUT VAUX a_n1105_n585# VSS nfet_03v3 ad=2.4p pd=9.2u as=2.4p ps=9.2u w=4u l=1u +X6 VSS VSS VSS VSS nfet_03v3 ad=2.32p pd=9.16u as=0 ps=0 w=4u l=1u +X7 VAUX a_n985_3311# VSS VSS nfet_03v3 ad=2.4p pd=9.2u as=2.4p ps=9.2u w=4u l=1u +X8 VAUX a_n1105_n585# VSS VSS nfet_03v3 ad=2.4p pd=9.2u as=2.4p ps=9.2u w=4u l=1u +X9 VSS VSS VSS VSS nfet_03v3 ad=2.32p pd=9.16u as=0 ps=0 w=4u l=1u +X10 VSS VSS VSS VSS nfet_03v3 ad=2.32p pd=9.16u as=0 ps=0 w=4u l=1u +X11 VIN VAUX a_n985_3311# VSS nfet_03v3 ad=2.4p pd=9.2u as=2.4p ps=9.2u w=4u l=1u +X12 VAUX a_n1105_n585# VSS VSS nfet_03v3 ad=2.4p pd=9.2u as=2.4p ps=9.2u w=4u l=1u +X13 a_n985_3311# VIN VSS VSS nfet_03v3 ad=2.4p pd=9.2u as=2.4p ps=9.2u w=4u l=1u +X14 VIN VAUX a_n985_3311# VSS nfet_03v3 ad=2.4p pd=9.2u as=2.4p ps=9.2u w=4u l=1u +X15 VOUT VAUX a_n1105_n585# VSS nfet_03v3 ad=2.4p pd=9.2u as=2.4p ps=9.2u w=4u l=1u +X16 VSS VSS VSS VSS nfet_03v3 ad=2.32p pd=9.16u as=0 ps=0 w=4u l=1u +X17 a_n1105_n585# VIN VSS VSS nfet_03v3 ad=2.4p pd=9.2u as=2.4p ps=9.2u w=4u l=1u +C0 VAUX a_n985_3311# 3.58908f +C1 a_n985_3311# a_n1105_n585# 0.36393f +C2 VIN a_n985_3311# 3.00275f +C3 VOUT a_n985_3311# 0.0136f +C4 VAUX a_n1105_n585# 3.29507f +C5 VAUX VIN 1.44115f +C6 VOUT VAUX 0.57679f +C7 VIN a_n1105_n585# 0.85546f +C8 VOUT a_n1105_n585# 2.17202f +C9 VOUT VIN 0.00933f +C10 VOUT VSS 3.08137f +C11 VIN VSS 7.81372f +C12 VAUX VSS 12.7612f +C13 a_n1105_n585# VSS 8.53412f +C14 a_n985_3311# VSS 7.65736f +.ends + diff --git a/blocks/composite/regulated_cascoded_cmirror/LVS/lvs/RCM/RCM_sim.spice b/blocks/composite/regulated_cascoded_cmirror/LVS/lvs/RCM/RCM_sim.spice new file mode 100644 index 00000000..4d4fb943 --- /dev/null +++ b/blocks/composite/regulated_cascoded_cmirror/LVS/lvs/RCM/RCM_sim.spice @@ -0,0 +1,40 @@ +| units: 0.5 tech: gf180mcuD format: MIT +x a_n985_3311# VSS VAUX VSS s=96000,1840 d=96000,1840 l=200 w=800 x=195 y=3691 nfet_03v3 +x VIN VSS a_n1105_n585# VSS s=96000,1840 d=96000,1840 l=200 w=800 x=785 y=1553 nfet_03v3 +x VSS VSS VSS VSS d=92800,1832 l=200 w=800 x=-1592 y=-584 nfet_03v3 +x VIN VSS a_n985_3311# VSS s=96000,1840 d=96000,1840 l=200 w=800 x=195 y=1553 nfet_03v3 +x VSS VSS VSS VSS d=92800,1832 l=200 w=800 x=-1592 y=3691 nfet_03v3 +x VAUX a_n1105_n585# VOUT VSS s=96000,1840 d=96000,1840 l=200 w=800 x=-984 y=-584 nfet_03v3 +x VSS VSS VSS VSS d=92800,1832 l=200 w=800 x=1393 y=-584 nfet_03v3 +x a_n985_3311# VSS VAUX VSS s=96000,1840 d=96000,1840 l=200 w=800 x=-984 y=3691 nfet_03v3 +x a_n1105_n585# VSS VAUX VSS s=96000,1840 d=96000,1840 l=200 w=800 x=-394 y=-584 nfet_03v3 +x VSS VSS VSS VSS d=92800,1832 l=200 w=800 x=1393 y=3691 nfet_03v3 +x VSS VSS VSS VSS d=92800,1832 l=200 w=800 x=-1592 y=1553 nfet_03v3 +x VAUX a_n985_3311# VIN VSS s=96000,1840 d=96000,1840 l=200 w=800 x=-394 y=3691 nfet_03v3 +x a_n1105_n585# VSS VAUX VSS s=96000,1840 d=96000,1840 l=200 w=800 x=785 y=-584 nfet_03v3 +x VIN VSS a_n985_3311# VSS s=96000,1840 d=96000,1840 l=200 w=800 x=-984 y=1553 nfet_03v3 +x VAUX a_n985_3311# VIN VSS s=96000,1840 d=96000,1840 l=200 w=800 x=785 y=3691 nfet_03v3 +x VAUX a_n1105_n585# VOUT VSS s=96000,1840 d=96000,1840 l=200 w=800 x=195 y=-584 nfet_03v3 +x VSS VSS VSS VSS d=92800,1832 l=200 w=800 x=1393 y=1553 nfet_03v3 +x VIN VSS a_n1105_n585# VSS s=96000,1840 d=96000,1840 l=200 w=800 x=-394 y=1553 nfet_03v3 +C VOUT a_n985_3311# 0.0 +C VIN a_n985_3311# 3.0 +C a_n1105_n585# VOUT 2.2 +C a_n1105_n585# VIN 0.9 +C VIN VOUT 0.0 +C VAUX a_n985_3311# 3.6 +C VAUX a_n1105_n585# 3.3 +C VAUX VOUT 0.6 +C VAUX VIN 1.4 +C a_n1105_n585# a_n985_3311# 0.4 +C VOUT0 3.1 +R VOUT 107 +C VIN0 7.8 +R VIN 347 +C VAUX0 12.8 +R VAUX 469 +R VSS 3589 +C a_n1105_n585#0 8.5 +R a_n1105_n585# 340 +C a_n985_3311#0 7.7 +R a_n985_3311# 335 diff --git a/blocks/composite/regulated_cascoded_cmirror/LVS/lvs/SCM/SCM_lvs.rpt b/blocks/composite/regulated_cascoded_cmirror/LVS/lvs/SCM/SCM_lvs.rpt new file mode 100644 index 00000000..b01e54d6 --- /dev/null +++ b/blocks/composite/regulated_cascoded_cmirror/LVS/lvs/SCM/SCM_lvs.rpt @@ -0,0 +1,38 @@ + +Circuit 1 cell nfet_03v3 and Circuit 2 cell nfet_03v3 are black boxes. +Warning: Equate pins: cell nfet_03v3 is a placeholder, treated as a black box. +Warning: Equate pins: cell nfet_03v3 is a placeholder, treated as a black box. + +Subcircuit pins: +Circuit 1: nfet_03v3 |Circuit 2: nfet_03v3 +-------------------------------------------|------------------------------------------- +1 |1 +2 |2 +3 |3 +4 |4 +--------------------------------------------------------------------------------------- +Cell pin lists are equivalent. +Device classes nfet_03v3 and nfet_03v3 are equivalent. + +Class SCM (0): Merged 3 parallel devices. +Subcircuit summary: +Circuit 1: SCM |Circuit 2: SCM +-------------------------------------------|------------------------------------------- +nfet_03v3 (8->5) |nfet_03v3 (8->5) +Number of devices: 5 |Number of devices: 5 +Number of nets: 5 |Number of nets: 5 +--------------------------------------------------------------------------------------- +Netlists match uniquely. + +Subcircuit pins: +Circuit 1: SCM |Circuit 2: SCM +-------------------------------------------|------------------------------------------- +VIN |VIN +VOUT |VOUT +VSS |VSS +--------------------------------------------------------------------------------------- +Cell pin lists are equivalent. +Device classes SCM and SCM are equivalent. + +Final result: Circuits match uniquely. +. diff --git a/blocks/composite/regulated_cascoded_cmirror/LVS/lvs/SCM/SCM_lvsmag.spice b/blocks/composite/regulated_cascoded_cmirror/LVS/lvs/SCM/SCM_lvsmag.spice new file mode 100644 index 00000000..67d2125f --- /dev/null +++ b/blocks/composite/regulated_cascoded_cmirror/LVS/lvs/SCM/SCM_lvsmag.spice @@ -0,0 +1,13 @@ +* NGSPICE file created from SCM.ext - technology: gf180mcuD + +.subckt SCM VIN VSS VOUT +X0 VSS VSS VSS VSS nfet_03v3 ad=2.32p pd=9.16u as=23.36p ps=91.68u w=4u l=1u +X1 VOUT VIN a_75_1553# VSS nfet_03v3 ad=2.4p pd=9.2u as=2.4p ps=9.2u w=4u l=1u +X2 VSS VSS VSS VSS nfet_03v3 ad=2.32p pd=9.16u as=0 ps=0 w=4u l=1u +X3 VSS VSS VSS VSS nfet_03v3 ad=2.32p pd=9.16u as=0 ps=0 w=4u l=1u +X4 a_n515_1553# a_n515_1553# VSS VSS nfet_03v3 ad=2.4p pd=9.2u as=2.4p ps=9.2u w=4u l=1u +X5 VSS VSS VSS VSS nfet_03v3 ad=2.32p pd=9.16u as=0 ps=0 w=4u l=1u +X6 a_75_1553# a_n515_1553# VSS VSS nfet_03v3 ad=2.4p pd=9.2u as=2.4p ps=9.2u w=4u l=1u +X7 VIN VIN a_n515_1553# VSS nfet_03v3 ad=2.4p pd=9.2u as=2.4p ps=9.2u w=4u l=1u +.ends + diff --git a/blocks/composite/regulated_cascoded_cmirror/LVS/lvs/SCM/SCM_pex.spice b/blocks/composite/regulated_cascoded_cmirror/LVS/lvs/SCM/SCM_pex.spice new file mode 100644 index 00000000..4565fc2c --- /dev/null +++ b/blocks/composite/regulated_cascoded_cmirror/LVS/lvs/SCM/SCM_pex.spice @@ -0,0 +1,23 @@ +* NGSPICE file created from SCM.ext - technology: gf180mcuD + +.subckt SCM VIN VSS VOUT +X0 VSS VSS VSS VSS nfet_03v3 ad=2.32p pd=9.16u as=23.36p ps=91.68u w=4u l=1u +X1 VOUT VIN a_75_1553# VSS nfet_03v3 ad=2.4p pd=9.2u as=2.4p ps=9.2u w=4u l=1u +X2 VSS VSS VSS VSS nfet_03v3 ad=2.32p pd=9.16u as=0 ps=0 w=4u l=1u +X3 VSS VSS VSS VSS nfet_03v3 ad=2.32p pd=9.16u as=0 ps=0 w=4u l=1u +X4 a_n515_1553# a_n515_1553# VSS VSS nfet_03v3 ad=2.4p pd=9.2u as=2.4p ps=9.2u w=4u l=1u +X5 VSS VSS VSS VSS nfet_03v3 ad=2.32p pd=9.16u as=0 ps=0 w=4u l=1u +X6 a_75_1553# a_n515_1553# VSS VSS nfet_03v3 ad=2.4p pd=9.2u as=2.4p ps=9.2u w=4u l=1u +X7 VIN VIN a_n515_1553# VSS nfet_03v3 ad=2.4p pd=9.2u as=2.4p ps=9.2u w=4u l=1u +C0 a_n515_1553# a_75_1553# 0.36588f +C1 a_75_1553# VIN 1.45666f +C2 a_n515_1553# VIN 1.80119f +C3 VOUT a_75_1553# 1.15251f +C4 a_n515_1553# VOUT 0.0849f +C5 VOUT VIN 0.2042f +C6 VOUT VSS 1.66471f +C7 VIN VSS 2.65167f +C8 a_75_1553# VSS 2.90565f +C9 a_n515_1553# VSS 6.45698f +.ends + diff --git a/blocks/composite/regulated_cascoded_cmirror/LVS/lvs/SCM/SCM_sim.spice b/blocks/composite/regulated_cascoded_cmirror/LVS/lvs/SCM/SCM_sim.spice new file mode 100644 index 00000000..717666fd --- /dev/null +++ b/blocks/composite/regulated_cascoded_cmirror/LVS/lvs/SCM/SCM_sim.spice @@ -0,0 +1,24 @@ +| units: 0.5 tech: gf180mcuD format: MIT +x VSS VSS VSS VSS d=92800,1832 l=200 w=800 x=-1002 y=-584 nfet_03v3 +x VIN a_75_1553# VOUT VSS s=96000,1840 d=96000,1840 l=200 w=800 x=195 y=1553 nfet_03v3 +x VSS VSS VSS VSS d=92800,1832 l=200 w=800 x=803 y=-584 nfet_03v3 +x VSS VSS VSS VSS d=92800,1832 l=200 w=800 x=-1002 y=1553 nfet_03v3 +x a_n515_1553# VSS a_n515_1553# VSS s=96000,1840 d=96000,1840 l=200 w=800 x=-394 y=-584 nfet_03v3 +x VSS VSS VSS VSS d=92800,1832 l=200 w=800 x=803 y=1553 nfet_03v3 +x a_n515_1553# VSS a_75_1553# VSS s=96000,1840 d=96000,1840 l=200 w=800 x=195 y=-584 nfet_03v3 +x VIN a_n515_1553# VIN VSS s=96000,1840 d=96000,1840 l=200 w=800 x=-394 y=1553 nfet_03v3 +C VIN VOUT 0.2 +C a_75_1553# VOUT 1.2 +C a_75_1553# VIN 1.5 +C VOUT a_n515_1553# 0.1 +C VIN a_n515_1553# 1.8 +C a_75_1553# a_n515_1553# 0.4 +C VOUT0 1.7 +R VOUT 47 +C VIN0 2.7 +R VIN 159 +R VSS 2236 +C a_75_1553#0 2.9 +R a_75_1553# 107 +C a_n515_1553#0 6.5 +R a_n515_1553# 219 diff --git a/blocks/composite/regulated_cascoded_cmirror/LVS/lvs/TOP/TOP_lvs.rpt b/blocks/composite/regulated_cascoded_cmirror/LVS/lvs/TOP/TOP_lvs.rpt new file mode 100644 index 00000000..1178966d --- /dev/null +++ b/blocks/composite/regulated_cascoded_cmirror/LVS/lvs/TOP/TOP_lvs.rpt @@ -0,0 +1,152 @@ + +Circuit 1 cell pfet_05v0 and Circuit 2 cell pfet_05v0 are black boxes. +Warning: Equate pins: cell pfet_05v0 is a placeholder, treated as a black box. +Warning: Equate pins: cell pfet_05v0 is a placeholder, treated as a black box. + +Subcircuit pins: +Circuit 1: pfet_05v0 |Circuit 2: pfet_05v0 +-------------------------------------------|------------------------------------------- +1 |1 +2 |2 +3 |3 +4 |4 +--------------------------------------------------------------------------------------- +Cell pin lists are equivalent. +Device classes pfet_05v0 and pfet_05v0 are equivalent. + +Circuit 1 cell nfet_05v0 and Circuit 2 cell nfet_05v0 are black boxes. +Warning: Equate pins: cell nfet_05v0 is a placeholder, treated as a black box. +Warning: Equate pins: cell nfet_05v0 is a placeholder, treated as a black box. + +Subcircuit pins: +Circuit 1: nfet_05v0 |Circuit 2: nfet_05v0 +-------------------------------------------|------------------------------------------- +1 |1 +2 |2 +3 |3 +4 |4 +--------------------------------------------------------------------------------------- +Cell pin lists are equivalent. +Device classes nfet_05v0 and nfet_05v0 are equivalent. + +Circuit 1 cell ppolyf_u and Circuit 2 cell ppolyf_u are black boxes. +Warning: Equate pins: cell ppolyf_u is a placeholder, treated as a black box. +Warning: Equate pins: cell ppolyf_u is a placeholder, treated as a black box. + +Subcircuit pins: +Circuit 1: ppolyf_u |Circuit 2: ppolyf_u +-------------------------------------------|------------------------------------------- +1 |1 +2 |2 +3 |3 +--------------------------------------------------------------------------------------- +Cell pin lists are equivalent. +Device classes ppolyf_u and ppolyf_u are equivalent. + +Circuit 1 cell nfet_03v3 and Circuit 2 cell nfet_03v3 are black boxes. +Warning: Equate pins: cell nfet_03v3 is a placeholder, treated as a black box. +Warning: Equate pins: cell nfet_03v3 is a placeholder, treated as a black box. + +Subcircuit pins: +Circuit 1: nfet_03v3 |Circuit 2: nfet_03v3 +-------------------------------------------|------------------------------------------- +1 |1 +2 |2 +3 |3 +4 |4 +--------------------------------------------------------------------------------------- +Cell pin lists are equivalent. +Device classes nfet_03v3 and nfet_03v3 are equivalent. + +Circuit 1 cell pfet_03v3 and Circuit 2 cell pfet_03v3 are black boxes. +Warning: Equate pins: cell pfet_03v3 is a placeholder, treated as a black box. +Warning: Equate pins: cell pfet_03v3 is a placeholder, treated as a black box. + +Subcircuit pins: +Circuit 1: pfet_03v3 |Circuit 2: pfet_03v3 +-------------------------------------------|------------------------------------------- +1 |1 +2 |2 +3 |3 +4 |4 +--------------------------------------------------------------------------------------- +Cell pin lists are equivalent. +Device classes pfet_03v3 and pfet_03v3 are equivalent. +Flattening unmatched subcell sc_tieh_tiel$1 in circuit TOP (0)(1 instance) +Flattening unmatched subcell gf180mcu_fd_sc_mcu9t5v0__tieh$2 in circuit TOP (0)(1 instance) +Flattening unmatched subcell gf180mcu_fd_sc_mcu9t5v0__tiel$3 in circuit TOP (0)(1 instance) +Flattening unmatched subcell io_secondary_5p0$1 in circuit TOP (0)(1 instance) +Flattening unmatched subcell ppolyf_u_9H3LNU$2 in circuit TOP (0)(1 instance) +Flattening unmatched subcell diode_nd2ps_06v0_MV3SZ3$2 in circuit TOP (0)(1 instance) +Flattening unmatched subcell diode_pd2nw_06v0_5DG9HC$2 in circuit TOP (0)(1 instance) +Flattening unmatched subcell M in circuit TOP (0)(1 instance) +Flattening unmatched subcell tieH in circuit TOP (1)(1 instance) +Flattening unmatched subcell tieL in circuit TOP (1)(1 instance) +Flattening unmatched subcell io_secondary_5p0 in circuit TOP (1)(3 instances) +Flattening unmatched subcell top_level in circuit TOP (1)(1 instance) +Flattening unmatched subcell vanilla_cm in circuit TOP (1)(1 instance) +Flattening unmatched subcell biased_cm in circuit TOP (1)(1 instance) +Flattening unmatched subcell cascode_cm in circuit TOP (1)(1 instance) +Flattening unmatched subcell bias in circuit TOP (1)(1 instance) + +Class TOP (0): Merged 113 parallel devices. +Class TOP (1): Merged 7 parallel devices. +Subcircuit summary: +Circuit 1: TOP |Circuit 2: TOP +-------------------------------------------|------------------------------------------- +pfet_05v0 (2) |pfet_05v0 (2) +nfet_05v0 (2) |nfet_05v0 (2) +ppolyf_u (3) |ppolyf_u (3) +diode_nd2ps_06v0 (12->3) |diode_nd2ps_06v0 (12->3) +diode_pd2nw_06v0 (12->3) |diode_pd2nw_06v0 (12->3) +pfet_03v3 (78->22) |pfet_03v3 (42->22) +nfet_03v3 (56->17) |nfet_03v3 (32->17) +Number of devices: 52 |Number of devices: 52 +Number of nets: 37 |Number of nets: 37 +--------------------------------------------------------------------------------------- +Netlists match uniquely with property errors. +ppolyf_u:0 vs. io_secondary_5p0:IO1/ppolyf_u:R1: + r_length circuit1: 1e-05 circuit2: 4e-06 (delta=85.7%, cutoff=1%) + r_width circuit1: 4e-05 circuit2: 1.6e-05 (delta=85.7%, cutoff=1%) +ppolyf_u:1 vs. io_secondary_5p0:IO2/ppolyf_u:R1: + r_length circuit1: 1e-05 circuit2: 4e-06 (delta=85.7%, cutoff=1%) + r_width circuit1: 4e-05 circuit2: 1.6e-05 (delta=85.7%, cutoff=1%) +io_secondary_5p0$1_0/ppolyf_u_9H3LNU$2:ppolyf_u_9H3LNU_0/ppolyf_u:0 vs. io_secondary_5p0:IO8/ppolyf_u:R1: + r_length circuit1: 1e-05 circuit2: 4e-06 (delta=85.7%, cutoff=1%) + r_width circuit1: 4e-05 circuit2: 1.6e-05 (delta=85.7%, cutoff=1%) +sc_tieh_tiel$1_0//gf180mcu_fd_sc_mcu9t5v0__tieh$2_0/nfet_05v0:1 vs. tieH:2/nfet_05v0:M2: + l circuit1: 6e-07 circuit2: 7e-07 (delta=15.4%, cutoff=1%) + w circuit1: 6.6e-07 circuit2: 1e-06 (delta=41%, cutoff=1%) +sc_tieh_tiel$1_0//gf180mcu_fd_sc_mcu9t5v0__tiel$3_0/nfet_05v0:0 vs. tieL:3/nfet_05v0:M4: + l circuit1: 6e-07 circuit2: 7e-07 (delta=15.4%, cutoff=1%) + w circuit1: 6.6e-07 circuit2: 1e-06 (delta=41%, cutoff=1%) +sc_tieh_tiel$1_0//gf180mcu_fd_sc_mcu9t5v0__tieh$2_0/pfet_05v0:0 vs. tieH:2/pfet_05v0:M1: + l circuit1: 5e-07 circuit2: 5.5e-07 (delta=9.52%, cutoff=1%) + w circuit1: 9e-07 circuit2: 2e-06 (delta=75.9%, cutoff=1%) +sc_tieh_tiel$1_0//gf180mcu_fd_sc_mcu9t5v0__tiel$3_0/pfet_05v0:1 vs. tieL:3/pfet_05v0:M3: + l circuit1: 5e-07 circuit2: 5.5e-07 (delta=9.52%, cutoff=1%) + w circuit1: 9e-07 circuit2: 2e-06 (delta=75.9%, cutoff=1%) + +Subcircuit pins: +Circuit 1: TOP |Circuit 2: TOP +-------------------------------------------|------------------------------------------- +VSS |VSS +VDD |VDD +PD |PD +PU |PU +VCM_OUT |VCM_OUT +BCM_OUT |BCM_OUT +CCM_OUT |CCM_OUT +VIN_OUT |VIN_OUT +VIN |VIN +VBIAS |VBIAS +EN |EN +--------------------------------------------------------------------------------------- +Cell pin lists are equivalent. +Device classes TOP and TOP are equivalent. + +Final result: Circuits match uniquely. +Property errors were found. + +The following cells had property errors: + TOP diff --git a/blocks/composite/regulated_cascoded_cmirror/LVS/lvs/TOP/TOP_lvsmag.spice b/blocks/composite/regulated_cascoded_cmirror/LVS/lvs/TOP/TOP_lvsmag.spice new file mode 100644 index 00000000..c54f3fe3 --- /dev/null +++ b/blocks/composite/regulated_cascoded_cmirror/LVS/lvs/TOP/TOP_lvsmag.spice @@ -0,0 +1,209 @@ +* NGSPICE file created from TOP.ext - technology: gf180mcuD + +.subckt gf180mcu_fd_sc_mcu9t5v0__tieh$2 VDD VSS Z VNW VPW +X0 Z a_125_157# VDD VNW pfet_05v0 ad=0.396p pd=2.68u as=0.396p ps=2.68u w=0.9u l=0.5u +X1 a_125_157# a_125_157# VSS VPW nfet_05v0 ad=0.2904p pd=2.2u as=0.2904p ps=2.2u w=0.66u l=0.6u +.ends + +.subckt gf180mcu_fd_sc_mcu9t5v0__tiel$3 VDD VSS ZN VNW VPW +X0 ZN a_124_157# VSS VPW nfet_05v0 ad=0.2904p pd=2.2u as=0.2904p ps=2.2u w=0.66u l=0.6u +X1 a_124_157# a_124_157# VDD VNW pfet_05v0 ad=0.396p pd=2.68u as=0.396p ps=2.68u w=0.9u l=0.5u +.ends + +.subckt sc_tieh_tiel$1 tieH tieL VDD VSS +Xgf180mcu_fd_sc_mcu9t5v0__tieh$2_0 VDD VSS tieH VDD VSS gf180mcu_fd_sc_mcu9t5v0__tieh$2 +Xgf180mcu_fd_sc_mcu9t5v0__tiel$3_0 VDD VSS tieL VDD VSS gf180mcu_fd_sc_mcu9t5v0__tiel$3 +.ends + +.subckt ppolyf_u_9H3LNU$2 a_n224793_504053# w_n225009_503837# a_n224793_506155# +X0 a_n224793_506155# a_n224793_504053# w_n225009_503837# ppolyf_u r_width=40u r_length=10u +.ends + +.subckt diode_nd2ps_06v0_MV3SZ3$2 a_505271_219793# a_503039_219793# a_507503_219793# ++ a_500807_219793# a_500655_219641# +D0 a_500655_219641# a_505271_219793# diode_nd2ps_06v0 pj=40u area=99.99999p +D1 a_500655_219641# a_500807_219793# diode_nd2ps_06v0 pj=40u area=99.99999p +D2 a_500655_219641# a_503039_219793# diode_nd2ps_06v0 pj=40u area=99.99999p +D3 a_500655_219641# a_507503_219793# diode_nd2ps_06v0 pj=40u area=99.99999p +.ends + +.subckt diode_pd2nw_06v0_5DG9HC$2 a_507479_219793# a_500831_219793# w_500655_219617# ++ a_503047_219793# a_505263_219793# +D0 a_500831_219793# w_500655_219617# diode_pd2nw_06v0 pj=40u area=99.99999p +D1 a_507479_219793# w_500655_219617# diode_pd2nw_06v0 pj=40u area=99.99999p +D2 a_503047_219793# w_500655_219617# diode_pd2nw_06v0 pj=40u area=99.99999p +D3 a_505263_219793# w_500655_219617# diode_pd2nw_06v0 pj=40u area=99.99999p +.ends + +.subckt io_secondary_5p0$1 m1_499212_228525# m1_497955_232243# m1_512035_219553# VSUBS +Xppolyf_u_9H3LNU_0 m1_499212_228525# m1_497955_232243# m1_512035_219553# ppolyf_u_9H3LNU$2 +Xdiode_nd2ps_06v0_MV3SZ3_0 m1_499212_228525# m1_499212_228525# m1_499212_228525# m1_499212_228525# ++ VSUBS diode_nd2ps_06v0_MV3SZ3$2 +Xdiode_pd2nw_06v0_5DG9HC_0 m1_499212_228525# m1_499212_228525# m1_497955_232243# m1_499212_228525# ++ m1_499212_228525# diode_pd2nw_06v0_5DG9HC$2 +.ends + +.subckt M a_408568_255933# a_365828_259091# a_411044_251737# a_409618_256263# a_404831_244568# ++ a_401271_243528# a_409818_256643# a_365828_265695# a_376520_259212# a_395682_259299# ++ a_411044_242557# w_364522_258756# +X0 w_364522_258756# w_364522_258756# w_364522_258756# w_364522_258756# pfet_03v3 ad=5.8p pd=21.16u as=0.4068n ps=1.46136m w=10u l=2u +X1 a_365708_259299# a_365708_259299# w_364522_258756# w_364522_258756# pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X2 a_365708_259299# a_365708_259299# w_364522_258756# w_364522_258756# pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X3 a_402461_244568# a_401271_243528# a_401941_244568# w_364522_258756# pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X4 w_364522_258756# w_364522_258756# w_364522_258756# w_364522_258756# pfet_03v3 ad=5.8p pd=21.16u as=0 ps=0 w=10u l=2u +X5 w_364522_258756# w_364522_258756# w_364522_258756# w_364522_258756# pfet_03v3 ad=5.8p pd=21.16u as=0 ps=0 w=10u l=2u +X6 a_404311_244568# a_401151_244568# w_364522_258756# w_364522_258756# pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X7 w_364522_258756# w_364522_258756# w_364522_258756# w_364522_258756# pfet_03v3 ad=5.8p pd=21.16u as=0 ps=0 w=10u l=2u +X8 a_374398_259299# a_365828_259091# a_373878_259299# w_364522_258756# pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X9 a_386992_259299# a_386992_259299# w_364522_258756# w_364522_258756# pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X10 w_364522_258756# w_364522_258756# w_364522_258756# w_364522_258756# pfet_03v3 ad=5.8p pd=21.16u as=0 ps=0 w=10u l=2u +X11 a_383940_262205# a_383940_262205# a_386992_259299# w_364522_258756# pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X12 w_364522_258756# w_364522_258756# w_364522_258756# w_364522_258756# pfet_03v3 ad=5.8p pd=21.16u as=0 ps=0 w=10u l=2u +X13 a_401151_244568# a_401151_244568# w_364522_258756# w_364522_258756# pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X14 a_404041_244568# a_409618_256263# a_409618_260539# a_376520_259212# nfet_03v3 ad=2.4p pd=9.2u as=2.4p ps=9.2u w=4u l=1u +X15 a_376520_259212# a_376520_259212# a_376520_259212# a_376520_259212# nfet_03v3 ad=4.64p pd=17.16u as=0.1744n ps=0.65672m w=8u l=1u +X16 a_376520_259212# a_376520_259212# a_376520_259212# a_376520_259212# nfet_03v3 ad=2.32p pd=9.16u as=0 ps=0 w=4u l=1u +X17 a_365828_259091# a_365828_259091# a_365708_259299# w_364522_258756# pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X18 a_409618_256263# a_409618_260539# a_376520_259212# a_376520_259212# nfet_03v3 ad=2.4p pd=9.2u as=2.4p ps=9.2u w=4u l=1u +X19 a_365828_259091# a_365828_259091# a_365708_259299# w_364522_258756# pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X20 a_409618_256263# a_409498_256643# a_376520_259212# a_376520_259212# nfet_03v3 ad=2.4p pd=9.2u as=2.4p ps=9.2u w=4u l=1u +X21 a_377450_262205# a_377450_262205# a_376520_259212# a_376520_259212# nfet_03v3 ad=4.8p pd=17.2u as=4.8p ps=17.2u w=8u l=1u +X22 a_376520_259212# a_376520_259212# a_376520_259212# a_376520_259212# nfet_03v3 ad=4.64p pd=17.16u as=0 ps=0 w=8u l=1u +X23 a_376520_259212# a_376520_259212# a_376520_259212# a_376520_259212# nfet_03v3 ad=2.32p pd=9.16u as=0 ps=0 w=4u l=1u +X24 a_409618_256263# a_409618_260539# a_376520_259212# a_376520_259212# nfet_03v3 ad=2.4p pd=9.2u as=2.4p ps=9.2u w=4u l=1u +X25 a_377450_262205# a_377450_262205# a_376520_259212# a_376520_259212# nfet_03v3 ad=4.8p pd=17.2u as=4.8p ps=17.2u w=8u l=1u +X26 a_401151_244568# a_365828_265695# w_364522_258756# w_364522_258756# pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X27 w_364522_258756# w_364522_258756# w_364522_258756# w_364522_258756# pfet_03v3 ad=5.8p pd=21.16u as=0 ps=0 w=10u l=2u +X28 a_376520_259212# a_376520_259212# a_376520_259212# a_376520_259212# nfet_03v3 ad=4.64p pd=17.16u as=0 ps=0 w=8u l=1u +X29 a_365708_259299# a_365708_259299# w_364522_258756# w_364522_258756# pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X30 a_374398_259299# a_374398_259299# a_377450_262205# a_376520_259212# nfet_03v3 ad=4.8p pd=17.2u as=4.8p ps=17.2u w=8u l=1u +X31 a_401151_244568# a_365828_265695# w_364522_258756# w_364522_258756# pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X32 a_383940_262205# a_383940_262205# a_386992_259299# w_364522_258756# pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X33 a_376520_259212# a_376520_259212# a_376520_259212# a_376520_259212# nfet_03v3 ad=2.32p pd=9.16u as=0 ps=0 w=4u l=1u +X34 a_404041_244568# a_401271_243528# a_403521_244568# w_364522_258756# pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X35 a_395162_259299# a_386992_259299# w_364522_258756# w_364522_258756# pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X36 a_386992_259299# a_386992_259299# w_364522_258756# w_364522_258756# pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X37 a_376520_259212# a_376520_259212# a_376520_259212# a_376520_259212# nfet_03v3 ad=2.32p pd=9.16u as=0 ps=0 w=4u l=1u +X38 a_374398_259299# a_374398_259299# a_377450_262205# a_376520_259212# nfet_03v3 ad=4.8p pd=17.2u as=4.8p ps=17.2u w=8u l=1u +X39 a_377450_262205# a_377450_262205# a_376520_259212# a_376520_259212# nfet_03v3 ad=4.8p pd=17.2u as=4.8p ps=17.2u w=8u l=1u +X40 a_376520_259212# a_376520_259212# a_376520_259212# a_376520_259212# nfet_03v3 ad=4.64p pd=17.16u as=0 ps=0 w=8u l=1u +X41 a_365708_259299# a_365708_259299# w_364522_258756# w_364522_258756# pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X42 a_365708_259299# a_365708_259299# w_364522_258756# w_364522_258756# pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X43 a_377450_262205# a_377450_262205# a_376520_259212# a_376520_259212# nfet_03v3 ad=4.8p pd=17.2u as=4.8p ps=17.2u w=8u l=1u +X44 a_386992_259299# a_386992_259299# w_364522_258756# w_364522_258756# pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X45 w_364522_258756# w_364522_258756# w_364522_258756# w_364522_258756# pfet_03v3 ad=5.8p pd=21.16u as=0 ps=0 w=10u l=2u +X46 a_374398_259299# a_374398_259299# a_377450_262205# a_376520_259212# nfet_03v3 ad=4.8p pd=17.2u as=4.8p ps=17.2u w=8u l=1u +X47 a_365708_259299# a_365708_259299# w_364522_258756# w_364522_258756# pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X48 a_402731_244568# a_401151_244568# w_364522_258756# w_364522_258756# pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X49 a_365708_259299# a_365828_265695# w_364522_258756# w_364522_258756# pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X50 a_374398_259299# a_374398_259299# a_377450_262205# a_376520_259212# nfet_03v3 ad=4.8p pd=17.2u as=4.8p ps=17.2u w=8u l=1u +X51 a_365828_259091# a_365828_259091# a_365708_259299# w_364522_258756# pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X52 a_376520_259212# a_376520_259212# a_376520_259212# a_376520_259212# nfet_03v3 ad=2.32p pd=9.16u as=0 ps=0 w=4u l=1u +X53 a_386992_259299# a_386992_259299# w_364522_258756# w_364522_258756# pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X54 a_376520_259212# a_376520_259212# a_376520_259212# a_376520_259212# nfet_03v3 ad=2.32p pd=9.16u as=0 ps=0 w=4u l=1u +X55 w_364522_258756# w_364522_258756# w_364522_258756# w_364522_258756# pfet_03v3 ad=5.8p pd=21.16u as=0 ps=0 w=10u l=2u +X56 a_376520_259212# a_376520_259212# a_376520_259212# a_376520_259212# nfet_03v3 ad=2.32p pd=9.16u as=0 ps=0 w=4u l=1u +X57 a_409498_256643# a_404041_244568# a_376520_259212# a_376520_259212# nfet_03v3 ad=2.4p pd=9.2u as=2.4p ps=9.2u w=4u l=1u +X58 a_395682_259299# a_383940_262205# a_395162_259299# w_364522_258756# pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X59 a_383940_262205# a_383940_262205# a_386992_259299# w_364522_258756# pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X60 w_364522_258756# w_364522_258756# w_364522_258756# w_364522_258756# pfet_03v3 ad=5.8p pd=21.16u as=0 ps=0 w=10u l=2u +X61 a_409618_260539# a_404041_244568# a_376520_259212# a_376520_259212# nfet_03v3 ad=2.4p pd=9.2u as=2.4p ps=9.2u w=4u l=1u +X62 a_401941_244568# a_401151_244568# w_364522_258756# w_364522_258756# pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X63 w_364522_258756# w_364522_258756# w_364522_258756# w_364522_258756# pfet_03v3 ad=5.8p pd=21.16u as=0 ps=0 w=10u l=2u +X64 a_365708_259299# a_365708_259299# w_364522_258756# w_364522_258756# pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X65 w_364522_258756# w_364522_258756# w_364522_258756# w_364522_258756# pfet_03v3 ad=5.8p pd=21.16u as=0 ps=0 w=10u l=2u +X66 a_376520_259212# a_376520_259212# a_376520_259212# a_376520_259212# nfet_03v3 ad=2.32p pd=9.16u as=0 ps=0 w=4u l=1u +X67 a_376520_259212# a_376520_259212# a_376520_259212# a_376520_259212# nfet_03v3 ad=2.32p pd=9.16u as=0 ps=0 w=4u l=1u +X68 a_365828_259091# a_365828_259091# a_365708_259299# w_364522_258756# pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X69 a_377450_262205# a_377450_262205# a_376520_259212# a_376520_259212# nfet_03v3 ad=4.8p pd=17.2u as=4.8p ps=17.2u w=8u l=1u +X70 a_365828_259091# a_365828_259091# a_365708_259299# w_364522_258756# pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X71 a_409618_260539# a_404041_244568# a_376520_259212# a_376520_259212# nfet_03v3 ad=2.4p pd=9.2u as=2.4p ps=9.2u w=4u l=1u +X72 w_364522_258756# w_364522_258756# w_364522_258756# w_364522_258756# pfet_03v3 ad=5.8p pd=21.16u as=0 ps=0 w=10u l=2u +X73 a_383940_262205# a_383940_262205# a_386992_259299# w_364522_258756# pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X74 a_377450_262205# a_377450_262205# a_376520_259212# a_376520_259212# nfet_03v3 ad=4.8p pd=17.2u as=4.8p ps=17.2u w=8u l=1u +X75 a_411044_242557# a_402461_244568# a_376520_259212# a_376520_259212# nfet_03v3 ad=2.4p pd=9.2u as=2.4p ps=9.2u w=4u l=1u +X76 a_376520_259212# a_376520_259212# a_376520_259212# a_376520_259212# nfet_03v3 ad=2.32p pd=9.16u as=0 ps=0 w=4u l=1u +X77 a_365828_259091# a_365828_259091# a_365708_259299# w_364522_258756# pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X78 a_401151_244568# a_365828_265695# w_364522_258756# w_364522_258756# pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X79 a_377450_262205# a_377450_262205# a_376520_259212# a_376520_259212# nfet_03v3 ad=4.8p pd=17.2u as=4.8p ps=17.2u w=8u l=1u +X80 a_374398_259299# a_374398_259299# a_377450_262205# a_376520_259212# nfet_03v3 ad=4.8p pd=17.2u as=4.8p ps=17.2u w=8u l=1u +X81 a_402461_244568# a_402461_244568# a_376520_259212# a_376520_259212# nfet_03v3 ad=2.4p pd=9.2u as=2.4p ps=9.2u w=4u l=1u +X82 w_364522_258756# w_364522_258756# w_364522_258756# w_364522_258756# pfet_03v3 ad=5.8p pd=21.16u as=0 ps=0 w=10u l=2u +X83 a_383940_262205# a_383940_262205# a_386992_259299# w_364522_258756# pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X84 a_374398_259299# a_374398_259299# a_377450_262205# a_376520_259212# nfet_03v3 ad=4.8p pd=17.2u as=4.8p ps=17.2u w=8u l=1u +X85 w_364522_258756# w_364522_258756# w_364522_258756# w_364522_258756# pfet_03v3 ad=5.8p pd=21.16u as=0 ps=0 w=10u l=2u +X86 a_404041_244568# a_409618_256263# a_409618_260539# a_376520_259212# nfet_03v3 ad=2.4p pd=9.2u as=2.4p ps=9.2u w=4u l=1u +X87 a_386992_259299# a_386992_259299# w_364522_258756# w_364522_258756# pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X88 a_404831_244568# a_401271_243528# a_404311_244568# w_364522_258756# pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X89 a_386992_259299# a_386992_259299# w_364522_258756# w_364522_258756# pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X90 w_364522_258756# w_364522_258756# w_364522_258756# w_364522_258756# pfet_03v3 ad=5.8p pd=21.16u as=0 ps=0 w=10u l=2u +X91 a_374398_259299# a_374398_259299# a_377450_262205# a_376520_259212# nfet_03v3 ad=4.8p pd=17.2u as=4.8p ps=17.2u w=8u l=1u +X92 a_386992_259299# a_386992_259299# w_364522_258756# w_364522_258756# pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X93 a_365828_259091# a_365828_259091# a_365708_259299# w_364522_258756# pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X94 a_365708_259299# a_365708_259299# w_364522_258756# w_364522_258756# pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X95 a_365708_259299# a_365708_259299# w_364522_258756# w_364522_258756# pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X96 a_401271_243528# a_401271_243528# a_401151_244568# w_364522_258756# pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X97 a_386992_259299# a_386992_259299# w_364522_258756# w_364522_258756# pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X98 a_403521_244568# a_401151_244568# w_364522_258756# w_364522_258756# pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X99 a_386992_259299# a_386992_259299# w_364522_258756# w_364522_258756# pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X100 a_365708_259299# a_365708_259299# w_364522_258756# w_364522_258756# pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X101 a_410724_251737# a_410134_251737# a_376520_259212# a_376520_259212# nfet_03v3 ad=2.4p pd=9.2u as=2.4p ps=9.2u w=4u l=1u +X102 a_409618_256263# a_409498_256643# a_376520_259212# a_376520_259212# nfet_03v3 ad=2.4p pd=9.2u as=2.4p ps=9.2u w=4u l=1u +X103 a_411044_251737# a_403251_244568# a_410724_251737# a_376520_259212# nfet_03v3 ad=2.4p pd=9.2u as=2.4p ps=9.2u w=4u l=1u +X104 a_409818_256643# a_409618_256263# a_409498_256643# a_376520_259212# nfet_03v3 ad=2.4p pd=9.2u as=2.4p ps=9.2u w=4u l=1u +X105 a_386992_259299# a_365828_265695# w_364522_258756# w_364522_258756# pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X106 a_383940_262205# a_383940_262205# a_386992_259299# w_364522_258756# pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X107 a_410134_251737# a_410134_251737# a_376520_259212# a_376520_259212# nfet_03v3 ad=2.4p pd=9.2u as=2.4p ps=9.2u w=4u l=1u +X108 a_403251_244568# a_403251_244568# a_410134_251737# a_376520_259212# nfet_03v3 ad=2.4p pd=9.2u as=2.4p ps=9.2u w=4u l=1u +X109 a_383940_262205# a_383940_262205# a_386992_259299# w_364522_258756# pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X110 a_383940_262205# a_383940_262205# a_386992_259299# w_364522_258756# pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X111 a_409818_256643# a_409618_256263# a_409498_256643# a_376520_259212# nfet_03v3 ad=2.4p pd=9.2u as=2.4p ps=9.2u w=4u l=1u +X112 a_365828_259091# a_365828_259091# a_365708_259299# w_364522_258756# pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X113 a_376520_259212# a_376520_259212# a_376520_259212# a_376520_259212# nfet_03v3 ad=2.32p pd=9.16u as=0 ps=0 w=4u l=1u +X114 a_377450_262205# a_377450_262205# a_376520_259212# a_376520_259212# nfet_03v3 ad=4.8p pd=17.2u as=4.8p ps=17.2u w=8u l=1u +X115 a_377450_262205# a_377450_262205# a_376520_259212# a_376520_259212# nfet_03v3 ad=4.8p pd=17.2u as=4.8p ps=17.2u w=8u l=1u +X116 a_365828_259091# a_365828_259091# a_365708_259299# w_364522_258756# pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X117 a_383940_262205# a_383940_262205# a_386992_259299# w_364522_258756# pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X118 a_376520_259212# a_376520_259212# a_376520_259212# a_376520_259212# nfet_03v3 ad=2.32p pd=9.16u as=0 ps=0 w=4u l=1u +X119 a_383940_262205# a_383940_262205# a_386992_259299# w_364522_258756# pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X120 a_365828_259091# a_365828_259091# a_365708_259299# w_364522_258756# pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X121 a_383620_262205# a_377450_262205# a_376520_259212# a_376520_259212# nfet_03v3 ad=4.8p pd=17.2u as=4.8p ps=17.2u w=8u l=1u +X122 a_377450_262205# a_377450_262205# a_376520_259212# a_376520_259212# nfet_03v3 ad=4.8p pd=17.2u as=4.8p ps=17.2u w=8u l=1u +X123 a_373878_259299# a_365708_259299# w_364522_258756# w_364522_258756# pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X124 a_374398_259299# a_374398_259299# a_377450_262205# a_376520_259212# nfet_03v3 ad=4.8p pd=17.2u as=4.8p ps=17.2u w=8u l=1u +X125 a_409498_256643# a_404041_244568# a_376520_259212# a_376520_259212# nfet_03v3 ad=2.4p pd=9.2u as=2.4p ps=9.2u w=4u l=1u +X126 a_401151_244568# a_365828_265695# w_364522_258756# w_364522_258756# pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X127 a_374398_259299# a_374398_259299# a_377450_262205# a_376520_259212# nfet_03v3 ad=4.8p pd=17.2u as=4.8p ps=17.2u w=8u l=1u +X128 w_364522_258756# w_364522_258756# w_364522_258756# w_364522_258756# pfet_03v3 ad=5.8p pd=21.16u as=0 ps=0 w=10u l=2u +X129 w_364522_258756# w_364522_258756# w_364522_258756# w_364522_258756# pfet_03v3 ad=5.8p pd=21.16u as=0 ps=0 w=10u l=2u +X130 a_403251_244568# a_401271_243528# a_402731_244568# w_364522_258756# pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X131 a_386992_259299# a_386992_259299# w_364522_258756# w_364522_258756# pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X132 a_383940_262205# a_374398_259299# a_383620_262205# a_376520_259212# nfet_03v3 ad=4.8p pd=17.2u as=4.8p ps=17.2u w=8u l=1u +X133 a_374398_259299# a_374398_259299# a_377450_262205# a_376520_259212# nfet_03v3 ad=4.8p pd=17.2u as=4.8p ps=17.2u w=8u l=1u +.ends + +.subckt TOP CCM_OUT PU VDD VSS VIN_OUT BCM_OUT VCM_OUT VIN VBIAS EN PD +Xsc_tieh_tiel$1_0 PD PU VDD VSS sc_tieh_tiel$1 +Xio_secondary_5p0$1_0 m3_419992_265695# VDD EN VSS io_secondary_5p0$1 +XM_0 VSS a_499016_248165# BCM_OUT m4_400150_261569# VIN_OUT a_498947_268180# CCM_OUT ++ m3_419992_265695# VSS m4_400150_261569# VCM_OUT VDD M +D0 a_498947_268180# VDD diode_pd2nw_06v0 pj=40u area=99.99999p +D1 a_498947_268180# VDD diode_pd2nw_06v0 pj=40u area=99.99999p +D2 VSS a_499016_248165# diode_nd2ps_06v0 pj=40u area=99.99999p +X0 a_498947_268180# VIN VDD ppolyf_u r_width=40u r_length=10u +D3 a_499016_248165# VDD diode_pd2nw_06v0 pj=40u area=99.99999p +D4 a_499016_248165# VDD diode_pd2nw_06v0 pj=40u area=99.99999p +D5 VSS a_499016_248165# diode_nd2ps_06v0 pj=40u area=99.99999p +D6 a_498947_268180# VDD diode_pd2nw_06v0 pj=40u area=99.99999p +D7 VSS a_498947_268180# diode_nd2ps_06v0 pj=40u area=99.99999p +D8 a_499016_248165# VDD diode_pd2nw_06v0 pj=40u area=99.99999p +D9 a_499016_248165# VDD diode_pd2nw_06v0 pj=40u area=99.99999p +D10 VSS a_498947_268180# diode_nd2ps_06v0 pj=40u area=99.99999p +D11 VSS a_499016_248165# diode_nd2ps_06v0 pj=40u area=99.99999p +D12 VSS a_498947_268180# diode_nd2ps_06v0 pj=40u area=99.99999p +D13 a_498947_268180# VDD diode_pd2nw_06v0 pj=40u area=99.99999p +X1 a_499016_248165# VBIAS VDD ppolyf_u r_width=40u r_length=10u +D14 VSS a_499016_248165# diode_nd2ps_06v0 pj=40u area=99.99999p +D15 VSS a_498947_268180# diode_nd2ps_06v0 pj=40u area=99.99999p +.ends + diff --git a/blocks/composite/regulated_cascoded_cmirror/LVS/lvs/TOP/TOP_pex.spice b/blocks/composite/regulated_cascoded_cmirror/LVS/lvs/TOP/TOP_pex.spice new file mode 100644 index 00000000..fd1c07a8 --- /dev/null +++ b/blocks/composite/regulated_cascoded_cmirror/LVS/lvs/TOP/TOP_pex.spice @@ -0,0 +1,2069 @@ +* NGSPICE file created from TOP.ext - technology: gf180mcuD + +.subckt gf180mcu_fd_sc_mcu9t5v0__tieh$2 VDD VSS Z VNW VPW a_125_157# +X0 Z a_125_157# VDD VNW pfet_05v0 ad=0.396p pd=2.68u as=0.396p ps=2.68u w=0.9u l=0.5u +X1 a_125_157# a_125_157# VSS VPW nfet_05v0 ad=0.2904p pd=2.2u as=0.2904p ps=2.2u w=0.66u l=0.6u +C0 VDD Z 0.05696f +C1 VSS a_125_157# 0.05594f +C2 VDD VSS 0.02071f +C3 VNW a_125_157# 0.13984f +C4 VNW VDD 0.13685f +C5 VDD a_125_157# 0.02505f +C6 VNW Z 0.01694f +C7 Z a_125_157# 0.0165f +C8 VNW VSS 0.01055f +C9 VSS VPW 0.31582f +C10 Z VPW 0.02933f +C11 VDD VPW 0.23581f +C12 VNW VPW 1.19226f +C13 a_125_157# VPW 0.37323f +.ends + +.subckt gf180mcu_fd_sc_mcu9t5v0__tiel$3 VDD VSS ZN VNW VPW a_124_157# +X0 ZN a_124_157# VSS VPW nfet_05v0 ad=0.2904p pd=2.2u as=0.2904p ps=2.2u w=0.66u l=0.6u +X1 a_124_157# a_124_157# VDD VNW pfet_05v0 ad=0.396p pd=2.68u as=0.396p ps=2.68u w=0.9u l=0.5u +C0 VDD VSS 0.02032f +C1 ZN a_124_157# 0.02544f +C2 VDD ZN 0 +C3 VNW a_124_157# 0.15591f +C4 VSS ZN 0.03448f +C5 VNW VDD 0.13657f +C6 VDD a_124_157# 0.08266f +C7 VNW VSS 0.01117f +C8 VSS a_124_157# 0.03129f +C9 VNW ZN 0 +C10 ZN VPW 0.02686f +C11 VSS VPW 0.31286f +C12 VDD VPW 0.23555f +C13 VNW VPW 1.19226f +C14 a_124_157# VPW 0.3723f +.ends + +.subckt sc_tieh_tiel$1 tieH tieL gf180mcu_fd_sc_mcu9t5v0__tieh$2_0/a_125_157# VDD ++ gf180mcu_fd_sc_mcu9t5v0__tiel$3_0/a_124_157# VSS +Xgf180mcu_fd_sc_mcu9t5v0__tieh$2_0 VDD VSS tieH VDD VSS gf180mcu_fd_sc_mcu9t5v0__tieh$2_0/a_125_157# ++ gf180mcu_fd_sc_mcu9t5v0__tieh$2 +Xgf180mcu_fd_sc_mcu9t5v0__tiel$3_0 VDD VSS tieL VDD VSS gf180mcu_fd_sc_mcu9t5v0__tiel$3_0/a_124_157# ++ gf180mcu_fd_sc_mcu9t5v0__tiel$3 +C0 tieH VSS 0.01457f +C1 gf180mcu_fd_sc_mcu9t5v0__tiel$3_0/a_124_157# VDD 0.02329f +C2 gf180mcu_fd_sc_mcu9t5v0__tieh$2_0/a_125_157# VDD 0.00888f +C3 gf180mcu_fd_sc_mcu9t5v0__tiel$3_0/a_124_157# tieL 0.01483f +C4 VDD VSS 0.29762f +C5 gf180mcu_fd_sc_mcu9t5v0__tieh$2_0/a_125_157# tieL 0 +C6 tieL VSS 0.08309f +C7 gf180mcu_fd_sc_mcu9t5v0__tiel$3_0/a_124_157# gf180mcu_fd_sc_mcu9t5v0__tieh$2_0/a_125_157# 0.0027f +C8 tieH VDD 0.08219f +C9 gf180mcu_fd_sc_mcu9t5v0__tiel$3_0/a_124_157# VSS 0.01505f +C10 tieH tieL 0.01031f +C11 gf180mcu_fd_sc_mcu9t5v0__tieh$2_0/a_125_157# VSS 0.02873f +C12 tieL VDD 0.03191f +C13 tieH gf180mcu_fd_sc_mcu9t5v0__tieh$2_0/a_125_157# 0.00414f +C14 VSS 0 1.29627f +C15 VDD 0 3.38527f +C16 tieL 0 0.16778f +C17 gf180mcu_fd_sc_mcu9t5v0__tiel$3_0/a_124_157# 0 0.3723f +C18 tieH 0 0.13137f +C19 gf180mcu_fd_sc_mcu9t5v0__tieh$2_0/a_125_157# 0 0.37323f +.ends + +.subckt ppolyf_u_9H3LNU$2 a_n224793_504053# w_n225009_503837# a_n224793_506155# VSUBS +X0 a_n224793_506155# a_n224793_504053# w_n225009_503837# ppolyf_u r_width=40u r_length=10u +C0 a_n224793_504053# w_n225009_503837# 6.29946f +C1 a_n224793_506155# w_n225009_503837# 6.29946f +C2 a_n224793_504053# VSUBS 4.5322f +C3 a_n224793_506155# VSUBS 4.5322f +C4 w_n225009_503837# VSUBS 72.7085f +.ends + +.subckt diode_nd2ps_06v0_MV3SZ3$2 a_505271_219793# a_503039_219793# a_507503_219793# ++ a_500807_219793# a_500655_219641# +D0 a_500655_219641# a_505271_219793# diode_nd2ps_06v0 pj=40u area=99.99999p +D1 a_500655_219641# a_500807_219793# diode_nd2ps_06v0 pj=40u area=99.99999p +D2 a_500655_219641# a_503039_219793# diode_nd2ps_06v0 pj=40u area=99.99999p +D3 a_500655_219641# a_507503_219793# diode_nd2ps_06v0 pj=40u area=99.99999p +C0 a_507503_219793# a_500655_219641# 3.83321f +C1 a_505271_219793# a_500655_219641# 3.83321f +C2 a_503039_219793# a_500655_219641# 3.83321f +C3 a_500807_219793# a_500655_219641# 3.83321f +.ends + +.subckt diode_pd2nw_06v0_5DG9HC$2 a_507479_219793# a_500831_219793# w_500655_219617# ++ a_503047_219793# a_505263_219793# a_500511_219473# +D0 a_500831_219793# w_500655_219617# diode_pd2nw_06v0 pj=40u area=99.99999p +D1 a_507479_219793# w_500655_219617# diode_pd2nw_06v0 pj=40u area=99.99999p +D2 a_503047_219793# w_500655_219617# diode_pd2nw_06v0 pj=40u area=99.99999p +D3 a_505263_219793# w_500655_219617# diode_pd2nw_06v0 pj=40u area=99.99999p +C0 w_500655_219617# a_503047_219793# 4.17112f +C1 a_505263_219793# w_500655_219617# 4.17112f +C2 a_500831_219793# w_500655_219617# 4.17112f +C3 a_507479_219793# w_500655_219617# 4.17112f +C4 w_500655_219617# a_500511_219473# 73.4915f +.ends + +.subckt io_secondary_5p0$1 m1_512035_219553# m1_499212_228525# VSUBS m1_497955_232243# +Xppolyf_u_9H3LNU_0 m1_499212_228525# m1_497955_232243# m1_512035_219553# VSUBS ppolyf_u_9H3LNU$2 +Xdiode_nd2ps_06v0_MV3SZ3_0 m1_499212_228525# m1_499212_228525# m1_499212_228525# m1_499212_228525# ++ VSUBS diode_nd2ps_06v0_MV3SZ3$2 +Xdiode_pd2nw_06v0_5DG9HC_0 m1_499212_228525# m1_499212_228525# m1_497955_232243# m1_499212_228525# ++ m1_499212_228525# VSUBS diode_pd2nw_06v0_5DG9HC$2 +C0 m1_499212_228525# m1_497955_232243# 16.86721f +C1 m1_512035_219553# m1_497955_232243# 11.99056f +C2 m1_499212_228525# VSUBS 0.15225p +C3 m1_512035_219553# VSUBS 5.38418f +C4 m1_497955_232243# VSUBS 0.17048p +.ends + +.subckt M a_402461_244568# a_410134_251737# a_408568_255933# a_403521_244568# a_365828_259091# ++ a_411044_251737# a_409618_256263# a_409618_260539# a_404831_244568# a_401271_243528# ++ a_409818_256643# a_403251_244568# a_365828_265695# a_404311_244568# a_376520_259212# ++ a_401941_244568# a_395682_259299# a_404041_244568# a_409498_256643# a_402731_244568# ++ a_401151_244568# a_411044_242557# w_364522_258756# +X0 w_364522_258756# w_364522_258756# w_364522_258756# w_364522_258756# pfet_03v3 ad=5.8p pd=21.16u as=0.4068n ps=1.46136m w=10u l=2u +X1 a_365708_259299# a_365708_259299# w_364522_258756# w_364522_258756# pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X2 a_365708_259299# a_365708_259299# w_364522_258756# w_364522_258756# pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X3 a_402461_244568# a_401271_243528# a_401941_244568# w_364522_258756# pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X4 w_364522_258756# w_364522_258756# w_364522_258756# w_364522_258756# pfet_03v3 ad=5.8p pd=21.16u as=0 ps=0 w=10u l=2u +X5 w_364522_258756# w_364522_258756# w_364522_258756# w_364522_258756# pfet_03v3 ad=5.8p pd=21.16u as=0 ps=0 w=10u l=2u +X6 a_404311_244568# a_401151_244568# w_364522_258756# w_364522_258756# pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X7 w_364522_258756# w_364522_258756# w_364522_258756# w_364522_258756# pfet_03v3 ad=5.8p pd=21.16u as=0 ps=0 w=10u l=2u +X8 a_374398_259299# a_365828_259091# a_373878_259299# w_364522_258756# pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X9 a_386992_259299# a_386992_259299# w_364522_258756# w_364522_258756# pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X10 w_364522_258756# w_364522_258756# w_364522_258756# w_364522_258756# pfet_03v3 ad=5.8p pd=21.16u as=0 ps=0 w=10u l=2u +X11 a_383940_262205# a_383940_262205# a_386992_259299# w_364522_258756# pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X12 w_364522_258756# w_364522_258756# w_364522_258756# w_364522_258756# pfet_03v3 ad=5.8p pd=21.16u as=0 ps=0 w=10u l=2u +X13 a_401151_244568# a_401151_244568# w_364522_258756# w_364522_258756# pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X14 a_404041_244568# a_409618_256263# a_409618_260539# a_376520_259212# nfet_03v3 ad=2.4p pd=9.2u as=2.4p ps=9.2u w=4u l=1u +X15 a_376520_259212# a_376520_259212# a_376520_259212# a_376520_259212# nfet_03v3 ad=4.64p pd=17.16u as=0.1744n ps=0.65672m w=8u l=1u +X16 a_376520_259212# a_376520_259212# a_376520_259212# a_376520_259212# nfet_03v3 ad=2.32p pd=9.16u as=0 ps=0 w=4u l=1u +X17 a_365828_259091# a_365828_259091# a_365708_259299# w_364522_258756# pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X18 a_409618_256263# a_409618_260539# a_376520_259212# a_376520_259212# nfet_03v3 ad=2.4p pd=9.2u as=2.4p ps=9.2u w=4u l=1u +X19 a_365828_259091# a_365828_259091# a_365708_259299# w_364522_258756# pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X20 a_409618_256263# a_409498_256643# a_376520_259212# a_376520_259212# nfet_03v3 ad=2.4p pd=9.2u as=2.4p ps=9.2u w=4u l=1u +X21 a_377450_262205# a_377450_262205# a_376520_259212# a_376520_259212# nfet_03v3 ad=4.8p pd=17.2u as=4.8p ps=17.2u w=8u l=1u +X22 a_376520_259212# a_376520_259212# a_376520_259212# a_376520_259212# nfet_03v3 ad=4.64p pd=17.16u as=0 ps=0 w=8u l=1u +X23 a_376520_259212# a_376520_259212# a_376520_259212# a_376520_259212# nfet_03v3 ad=2.32p pd=9.16u as=0 ps=0 w=4u l=1u +X24 a_409618_256263# a_409618_260539# a_376520_259212# a_376520_259212# nfet_03v3 ad=2.4p pd=9.2u as=2.4p ps=9.2u w=4u l=1u +X25 a_377450_262205# a_377450_262205# a_376520_259212# a_376520_259212# nfet_03v3 ad=4.8p pd=17.2u as=4.8p ps=17.2u w=8u l=1u +X26 a_401151_244568# a_365828_265695# w_364522_258756# w_364522_258756# pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X27 w_364522_258756# w_364522_258756# w_364522_258756# w_364522_258756# pfet_03v3 ad=5.8p pd=21.16u as=0 ps=0 w=10u l=2u +X28 a_376520_259212# a_376520_259212# a_376520_259212# a_376520_259212# nfet_03v3 ad=4.64p pd=17.16u as=0 ps=0 w=8u l=1u +X29 a_365708_259299# a_365708_259299# w_364522_258756# w_364522_258756# pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X30 a_374398_259299# a_374398_259299# a_377450_262205# a_376520_259212# nfet_03v3 ad=4.8p pd=17.2u as=4.8p ps=17.2u w=8u l=1u +X31 a_401151_244568# a_365828_265695# w_364522_258756# w_364522_258756# pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X32 a_383940_262205# a_383940_262205# a_386992_259299# w_364522_258756# pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X33 a_376520_259212# a_376520_259212# a_376520_259212# a_376520_259212# nfet_03v3 ad=2.32p pd=9.16u as=0 ps=0 w=4u l=1u +X34 a_404041_244568# a_401271_243528# a_403521_244568# w_364522_258756# pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X35 a_395162_259299# a_386992_259299# w_364522_258756# w_364522_258756# pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X36 a_386992_259299# a_386992_259299# w_364522_258756# w_364522_258756# pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X37 a_376520_259212# a_376520_259212# a_376520_259212# a_376520_259212# nfet_03v3 ad=2.32p pd=9.16u as=0 ps=0 w=4u l=1u +X38 a_374398_259299# a_374398_259299# a_377450_262205# a_376520_259212# nfet_03v3 ad=4.8p pd=17.2u as=4.8p ps=17.2u w=8u l=1u +X39 a_377450_262205# a_377450_262205# a_376520_259212# a_376520_259212# nfet_03v3 ad=4.8p pd=17.2u as=4.8p ps=17.2u w=8u l=1u +X40 a_376520_259212# a_376520_259212# a_376520_259212# a_376520_259212# nfet_03v3 ad=4.64p pd=17.16u as=0 ps=0 w=8u l=1u +X41 a_365708_259299# a_365708_259299# w_364522_258756# w_364522_258756# pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X42 a_365708_259299# a_365708_259299# w_364522_258756# w_364522_258756# pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X43 a_377450_262205# a_377450_262205# a_376520_259212# a_376520_259212# nfet_03v3 ad=4.8p pd=17.2u as=4.8p ps=17.2u w=8u l=1u +X44 a_386992_259299# a_386992_259299# w_364522_258756# w_364522_258756# pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X45 w_364522_258756# w_364522_258756# w_364522_258756# w_364522_258756# pfet_03v3 ad=5.8p pd=21.16u as=0 ps=0 w=10u l=2u +X46 a_374398_259299# a_374398_259299# a_377450_262205# a_376520_259212# nfet_03v3 ad=4.8p pd=17.2u as=4.8p ps=17.2u w=8u l=1u +X47 a_365708_259299# a_365708_259299# w_364522_258756# w_364522_258756# pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X48 a_402731_244568# a_401151_244568# w_364522_258756# w_364522_258756# pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X49 a_365708_259299# a_365828_265695# w_364522_258756# w_364522_258756# pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X50 a_374398_259299# a_374398_259299# a_377450_262205# a_376520_259212# nfet_03v3 ad=4.8p pd=17.2u as=4.8p ps=17.2u w=8u l=1u +X51 a_365828_259091# a_365828_259091# a_365708_259299# w_364522_258756# pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X52 a_376520_259212# a_376520_259212# a_376520_259212# a_376520_259212# nfet_03v3 ad=2.32p pd=9.16u as=0 ps=0 w=4u l=1u +X53 a_386992_259299# a_386992_259299# w_364522_258756# w_364522_258756# pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X54 a_376520_259212# a_376520_259212# a_376520_259212# a_376520_259212# nfet_03v3 ad=2.32p pd=9.16u as=0 ps=0 w=4u l=1u +X55 w_364522_258756# w_364522_258756# w_364522_258756# w_364522_258756# pfet_03v3 ad=5.8p pd=21.16u as=0 ps=0 w=10u l=2u +X56 a_376520_259212# a_376520_259212# a_376520_259212# a_376520_259212# nfet_03v3 ad=2.32p pd=9.16u as=0 ps=0 w=4u l=1u +X57 a_409498_256643# a_404041_244568# a_376520_259212# a_376520_259212# nfet_03v3 ad=2.4p pd=9.2u as=2.4p ps=9.2u w=4u l=1u +X58 a_395682_259299# a_383940_262205# a_395162_259299# w_364522_258756# pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X59 a_383940_262205# a_383940_262205# a_386992_259299# w_364522_258756# pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X60 w_364522_258756# w_364522_258756# w_364522_258756# w_364522_258756# pfet_03v3 ad=5.8p pd=21.16u as=0 ps=0 w=10u l=2u +X61 a_409618_260539# a_404041_244568# a_376520_259212# a_376520_259212# nfet_03v3 ad=2.4p pd=9.2u as=2.4p ps=9.2u w=4u l=1u +X62 a_401941_244568# a_401151_244568# w_364522_258756# w_364522_258756# pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X63 w_364522_258756# w_364522_258756# w_364522_258756# w_364522_258756# pfet_03v3 ad=5.8p pd=21.16u as=0 ps=0 w=10u l=2u +X64 a_365708_259299# a_365708_259299# w_364522_258756# w_364522_258756# pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X65 w_364522_258756# w_364522_258756# w_364522_258756# w_364522_258756# pfet_03v3 ad=5.8p pd=21.16u as=0 ps=0 w=10u l=2u +X66 a_376520_259212# a_376520_259212# a_376520_259212# a_376520_259212# nfet_03v3 ad=2.32p pd=9.16u as=0 ps=0 w=4u l=1u +X67 a_376520_259212# a_376520_259212# a_376520_259212# a_376520_259212# nfet_03v3 ad=2.32p pd=9.16u as=0 ps=0 w=4u l=1u +X68 a_365828_259091# a_365828_259091# a_365708_259299# w_364522_258756# pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X69 a_377450_262205# a_377450_262205# a_376520_259212# a_376520_259212# nfet_03v3 ad=4.8p pd=17.2u as=4.8p ps=17.2u w=8u l=1u +X70 a_365828_259091# a_365828_259091# a_365708_259299# w_364522_258756# pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X71 a_409618_260539# a_404041_244568# a_376520_259212# a_376520_259212# nfet_03v3 ad=2.4p pd=9.2u as=2.4p ps=9.2u w=4u l=1u +X72 w_364522_258756# w_364522_258756# w_364522_258756# w_364522_258756# pfet_03v3 ad=5.8p pd=21.16u as=0 ps=0 w=10u l=2u +X73 a_383940_262205# a_383940_262205# a_386992_259299# w_364522_258756# pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X74 a_377450_262205# a_377450_262205# a_376520_259212# a_376520_259212# nfet_03v3 ad=4.8p pd=17.2u as=4.8p ps=17.2u w=8u l=1u +X75 a_411044_242557# a_402461_244568# a_376520_259212# a_376520_259212# nfet_03v3 ad=2.4p pd=9.2u as=2.4p ps=9.2u w=4u l=1u +X76 a_376520_259212# a_376520_259212# a_376520_259212# a_376520_259212# nfet_03v3 ad=2.32p pd=9.16u as=0 ps=0 w=4u l=1u +X77 a_365828_259091# a_365828_259091# a_365708_259299# w_364522_258756# pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X78 a_401151_244568# a_365828_265695# w_364522_258756# w_364522_258756# pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X79 a_377450_262205# a_377450_262205# a_376520_259212# a_376520_259212# nfet_03v3 ad=4.8p pd=17.2u as=4.8p ps=17.2u w=8u l=1u +X80 a_374398_259299# a_374398_259299# a_377450_262205# a_376520_259212# nfet_03v3 ad=4.8p pd=17.2u as=4.8p ps=17.2u w=8u l=1u +X81 a_402461_244568# a_402461_244568# a_376520_259212# a_376520_259212# nfet_03v3 ad=2.4p pd=9.2u as=2.4p ps=9.2u w=4u l=1u +X82 w_364522_258756# w_364522_258756# w_364522_258756# w_364522_258756# pfet_03v3 ad=5.8p pd=21.16u as=0 ps=0 w=10u l=2u +X83 a_383940_262205# a_383940_262205# a_386992_259299# w_364522_258756# pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X84 a_374398_259299# a_374398_259299# a_377450_262205# a_376520_259212# nfet_03v3 ad=4.8p pd=17.2u as=4.8p ps=17.2u w=8u l=1u +X85 w_364522_258756# w_364522_258756# w_364522_258756# w_364522_258756# pfet_03v3 ad=5.8p pd=21.16u as=0 ps=0 w=10u l=2u +X86 a_404041_244568# a_409618_256263# a_409618_260539# a_376520_259212# nfet_03v3 ad=2.4p pd=9.2u as=2.4p ps=9.2u w=4u l=1u +X87 a_386992_259299# a_386992_259299# w_364522_258756# w_364522_258756# pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X88 a_404831_244568# a_401271_243528# a_404311_244568# w_364522_258756# pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X89 a_386992_259299# a_386992_259299# w_364522_258756# w_364522_258756# pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X90 w_364522_258756# w_364522_258756# w_364522_258756# w_364522_258756# pfet_03v3 ad=5.8p pd=21.16u as=0 ps=0 w=10u l=2u +X91 a_374398_259299# a_374398_259299# a_377450_262205# a_376520_259212# nfet_03v3 ad=4.8p pd=17.2u as=4.8p ps=17.2u w=8u l=1u +X92 a_386992_259299# a_386992_259299# w_364522_258756# w_364522_258756# pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X93 a_365828_259091# a_365828_259091# a_365708_259299# w_364522_258756# pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X94 a_365708_259299# a_365708_259299# w_364522_258756# w_364522_258756# pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X95 a_365708_259299# a_365708_259299# w_364522_258756# w_364522_258756# pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X96 a_401271_243528# a_401271_243528# a_401151_244568# w_364522_258756# pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X97 a_386992_259299# a_386992_259299# w_364522_258756# w_364522_258756# pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X98 a_403521_244568# a_401151_244568# w_364522_258756# w_364522_258756# pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X99 a_386992_259299# a_386992_259299# w_364522_258756# w_364522_258756# pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X100 a_365708_259299# a_365708_259299# w_364522_258756# w_364522_258756# pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X101 a_410724_251737# a_410134_251737# a_376520_259212# a_376520_259212# nfet_03v3 ad=2.4p pd=9.2u as=2.4p ps=9.2u w=4u l=1u +X102 a_409618_256263# a_409498_256643# a_376520_259212# a_376520_259212# nfet_03v3 ad=2.4p pd=9.2u as=2.4p ps=9.2u w=4u l=1u +X103 a_411044_251737# a_403251_244568# a_410724_251737# a_376520_259212# nfet_03v3 ad=2.4p pd=9.2u as=2.4p ps=9.2u w=4u l=1u +X104 a_409818_256643# a_409618_256263# a_409498_256643# a_376520_259212# nfet_03v3 ad=2.4p pd=9.2u as=2.4p ps=9.2u w=4u l=1u +X105 a_386992_259299# a_365828_265695# w_364522_258756# w_364522_258756# pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X106 a_383940_262205# a_383940_262205# a_386992_259299# w_364522_258756# pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X107 a_410134_251737# a_410134_251737# a_376520_259212# a_376520_259212# nfet_03v3 ad=2.4p pd=9.2u as=2.4p ps=9.2u w=4u l=1u +X108 a_403251_244568# a_403251_244568# a_410134_251737# a_376520_259212# nfet_03v3 ad=2.4p pd=9.2u as=2.4p ps=9.2u w=4u l=1u +X109 a_383940_262205# a_383940_262205# a_386992_259299# w_364522_258756# pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X110 a_383940_262205# a_383940_262205# a_386992_259299# w_364522_258756# pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X111 a_409818_256643# a_409618_256263# a_409498_256643# a_376520_259212# nfet_03v3 ad=2.4p pd=9.2u as=2.4p ps=9.2u w=4u l=1u +X112 a_365828_259091# a_365828_259091# a_365708_259299# w_364522_258756# pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X113 a_376520_259212# a_376520_259212# a_376520_259212# a_376520_259212# nfet_03v3 ad=2.32p pd=9.16u as=0 ps=0 w=4u l=1u +X114 a_377450_262205# a_377450_262205# a_376520_259212# a_376520_259212# nfet_03v3 ad=4.8p pd=17.2u as=4.8p ps=17.2u w=8u l=1u +X115 a_377450_262205# a_377450_262205# a_376520_259212# a_376520_259212# nfet_03v3 ad=4.8p pd=17.2u as=4.8p ps=17.2u w=8u l=1u +X116 a_365828_259091# a_365828_259091# a_365708_259299# w_364522_258756# pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X117 a_383940_262205# a_383940_262205# a_386992_259299# w_364522_258756# pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X118 a_376520_259212# a_376520_259212# a_376520_259212# a_376520_259212# nfet_03v3 ad=2.32p pd=9.16u as=0 ps=0 w=4u l=1u +X119 a_383940_262205# a_383940_262205# a_386992_259299# w_364522_258756# pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X120 a_365828_259091# a_365828_259091# a_365708_259299# w_364522_258756# pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X121 a_383620_262205# a_377450_262205# a_376520_259212# a_376520_259212# nfet_03v3 ad=4.8p pd=17.2u as=4.8p ps=17.2u w=8u l=1u +X122 a_377450_262205# a_377450_262205# a_376520_259212# a_376520_259212# nfet_03v3 ad=4.8p pd=17.2u as=4.8p ps=17.2u w=8u l=1u +X123 a_373878_259299# a_365708_259299# w_364522_258756# w_364522_258756# pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X124 a_374398_259299# a_374398_259299# a_377450_262205# a_376520_259212# nfet_03v3 ad=4.8p pd=17.2u as=4.8p ps=17.2u w=8u l=1u +X125 a_409498_256643# a_404041_244568# a_376520_259212# a_376520_259212# nfet_03v3 ad=2.4p pd=9.2u as=2.4p ps=9.2u w=4u l=1u +X126 a_401151_244568# a_365828_265695# w_364522_258756# w_364522_258756# pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X127 a_374398_259299# a_374398_259299# a_377450_262205# a_376520_259212# nfet_03v3 ad=4.8p pd=17.2u as=4.8p ps=17.2u w=8u l=1u +X128 w_364522_258756# w_364522_258756# w_364522_258756# w_364522_258756# pfet_03v3 ad=5.8p pd=21.16u as=0 ps=0 w=10u l=2u +X129 w_364522_258756# w_364522_258756# w_364522_258756# w_364522_258756# pfet_03v3 ad=5.8p pd=21.16u as=0 ps=0 w=10u l=2u +X130 a_403251_244568# a_401271_243528# a_402731_244568# w_364522_258756# pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X131 a_386992_259299# a_386992_259299# w_364522_258756# w_364522_258756# pfet_03v3 ad=6p pd=21.2u as=6p ps=21.2u w=10u l=2u +X132 a_383940_262205# a_374398_259299# a_383620_262205# a_376520_259212# nfet_03v3 ad=4.8p pd=17.2u as=4.8p ps=17.2u w=8u l=1u +X133 a_374398_259299# a_374398_259299# a_377450_262205# a_376520_259212# nfet_03v3 ad=4.8p pd=17.2u as=4.8p ps=17.2u w=8u l=1u +C0 a_401941_244568# a_404831_244568# 0.13684f +C1 a_403521_244568# a_402731_244568# 0.84407f +C2 a_409618_256263# a_404041_244568# 1.45171f +C3 a_404041_244568# a_403251_244568# 0.33183f +C4 a_365828_265695# a_365708_259299# 0.74385f +C5 a_404041_244568# a_409618_260539# 3.00275f +C6 a_403521_244568# a_401941_244568# 0.34178f +C7 a_365828_265695# a_402731_244568# 0.0069f +C8 a_401941_244568# a_365828_265695# 0.00563f +C9 a_404041_244568# w_364522_258756# 1.72336f +C10 a_365828_265695# a_365828_259091# 0.00331f +C11 a_373878_259299# a_365708_259299# 0.98664f +C12 a_404311_244568# a_402731_244568# 0.30154f +C13 a_404311_244568# a_401941_244568# 0.30103f +C14 a_373878_259299# a_365828_259091# 0.99903f +C15 a_386992_259299# a_365828_265695# 0.7554f +C16 a_410724_251737# a_411044_251737# 1.15251f +C17 a_410134_251737# a_411044_251737# 0.0849f +C18 a_401271_243528# a_402731_244568# 0.63243f +C19 a_410134_251737# a_410724_251737# 0.36588f +C20 a_411044_242557# a_402461_244568# 0.20751f +C21 a_401941_244568# a_401271_243528# 2.86501f +C22 a_404041_244568# a_404831_244568# 2.48301f +C23 a_374398_259299# a_365708_259299# 0.07017f +C24 a_404041_244568# a_403521_244568# 2.39829f +C25 a_411044_251737# a_403251_244568# 0.2042f +C26 a_365828_259091# a_374398_259299# 0.50349f +C27 a_410724_251737# a_403251_244568# 1.45997f +C28 a_409498_256643# a_409818_256643# 2.17202f +C29 a_410134_251737# a_403251_244568# 1.85176f +C30 a_401151_244568# a_402461_244568# 0.13364f +C31 w_364522_258756# a_383940_262205# 15.504f +C32 a_409618_256263# a_409818_256643# 0.57687f +C33 a_409818_256643# a_409618_260539# 0.0136f +C34 a_404311_244568# a_404041_244568# 2.29591f +C35 a_401151_244568# a_403251_244568# 0.13521f +C36 a_409618_256263# a_409498_256643# 3.29507f +C37 a_409498_256643# a_409618_260539# 0.36393f +C38 a_395682_259299# a_383940_262205# 0.50349f +C39 a_403251_244568# a_402461_244568# 0.58599f +C40 a_401151_244568# w_364522_258756# 44.8668f +C41 a_386992_259299# a_395162_259299# 0.98664f +C42 a_401941_244568# a_402731_244568# 0.84535f +C43 a_409618_256263# a_409618_260539# 3.58908f +C44 a_365828_259091# a_365708_259299# 29.489f +C45 w_364522_258756# a_402461_244568# 1.21291f +C46 a_403251_244568# w_364522_258756# 1.12778f +C47 a_404041_244568# a_401271_243528# 0.62193f +C48 a_383620_262205# a_383940_262205# 1.13981f +C49 a_395682_259299# w_364522_258756# 1.49117f +C50 a_365828_265695# a_383940_262205# 0.01792f +C51 a_401151_244568# a_404831_244568# 0.98673f +C52 a_401151_244568# a_403521_244568# 1.46461f +C53 a_404831_244568# a_402461_244568# 0.08091f +C54 a_401151_244568# a_365828_265695# 2.15734f +C55 a_409618_256263# a_404831_244568# 0.12451f +C56 a_403521_244568# a_402461_244568# 0.10043f +C57 a_404041_244568# a_402731_244568# 0.17025f +C58 a_403251_244568# a_404831_244568# 0.08038f +C59 a_404831_244568# a_409618_260539# 0 +C60 a_403251_244568# a_403521_244568# 2.29847f +C61 a_404041_244568# a_401941_244568# 0.17047f +C62 w_364522_258756# a_404831_244568# 2.87066f +C63 a_403521_244568# w_364522_258756# 7.51371f +C64 a_401151_244568# a_404311_244568# 2.37681f +C65 w_364522_258756# a_365828_265695# 19.3145f +C66 a_404311_244568# a_402461_244568# 0.10003f +C67 a_383620_262205# a_377450_262205# 0.52252f +C68 a_404311_244568# a_403251_244568# 0.10042f +C69 a_374398_259299# a_383940_262205# 0.28491f +C70 a_373878_259299# w_364522_258756# 3.05677f +C71 a_404311_244568# w_364522_258756# 6.35462f +C72 a_401151_244568# a_401271_243528# 3.41485f +C73 a_383940_262205# a_395162_259299# 0.99903f +C74 a_401271_243528# a_402461_244568# 0.63416f +C75 a_403251_244568# a_401271_243528# 0.62309f +C76 a_403521_244568# a_404831_244568# 0.13662f +C77 w_364522_258756# a_401271_243528# 14.5258f +C78 a_403521_244568# a_365828_265695# 0.00915f +C79 w_364522_258756# a_374398_259299# 1.76606f +C80 w_364522_258756# a_395162_259299# 3.05677f +C81 a_401151_244568# a_402731_244568# 1.46427f +C82 a_404311_244568# a_404831_244568# 2.35844f +C83 a_401151_244568# a_401941_244568# 1.80913f +C84 a_404311_244568# a_403521_244568# 0.80509f +C85 a_402731_244568# a_402461_244568# 2.30103f +C86 a_395682_259299# a_395162_259299# 0.8533f +C87 a_373878_259299# a_365828_265695# 0 +C88 a_404311_244568# a_365828_265695# 0.28741f +C89 a_401941_244568# a_402461_244568# 2.41261f +C90 a_403251_244568# a_402731_244568# 2.40482f +C91 a_386992_259299# a_383940_262205# 29.4825f +C92 a_403251_244568# a_401941_244568# 0.17152f +C93 w_364522_258756# a_365708_259299# 48.8544f +C94 a_377450_262205# a_374398_259299# 36.6185f +C95 w_364522_258756# a_402731_244568# 7.43186f +C96 a_401271_243528# a_404831_244568# 0.54995f +C97 a_383620_262205# a_374398_259299# 0.86502f +C98 a_401941_244568# w_364522_258756# 7.43338f +C99 a_403521_244568# a_401271_243528# 0.62333f +C100 w_364522_258756# a_365828_259091# 16.3092f +C101 a_365828_265695# a_374398_259299# 0.01878f +C102 a_365828_265695# a_395162_259299# 0 +C103 a_386992_259299# w_364522_258756# 48.8285f +C104 a_404311_244568# a_401271_243528# 0.62105f +C105 a_409818_256643# a_404041_244568# 0.00933f +C106 a_401151_244568# a_404041_244568# 0.59986f +C107 a_409498_256643# a_404041_244568# 0.85546f +C108 a_373878_259299# a_374398_259299# 0.91714f +C109 a_395682_259299# a_386992_259299# 0.06695f +C110 a_404831_244568# a_402731_244568# 0.13558f +C111 a_404041_244568# a_402461_244568# 0.10021f +C112 a_411044_242557# a_376520_259212# 6.1069f +C113 a_411044_251737# a_376520_259212# 4.75873f +C114 a_410724_251737# a_376520_259212# 2.90137f +C115 a_410134_251737# a_376520_259212# 6.39712f +C116 a_409818_256643# a_376520_259212# 5.97383f +C117 a_409498_256643# a_376520_259212# 8.54632f +C118 a_409618_256263# a_376520_259212# 12.5882f +C119 a_409618_260539# a_376520_259212# 7.6582f +C120 a_404831_244568# a_376520_259212# 10.5405f +C121 a_404041_244568# a_376520_259212# 11.5785f +C122 a_403251_244568# a_376520_259212# 5.05938f +C123 a_402461_244568# a_376520_259212# 7.97268f +C124 a_401271_243528# a_376520_259212# 2.45016f +C125 a_404311_244568# a_376520_259212# 0.15844f +C126 a_403521_244568# a_376520_259212# 0.03326f +C127 a_402731_244568# a_376520_259212# 0.03284f +C128 a_401941_244568# a_376520_259212# 0.03295f +C129 a_401151_244568# a_376520_259212# 2.60775f +C130 a_395682_259299# a_376520_259212# 0.40915f +C131 a_395162_259299# a_376520_259212# 0.29295f +C132 a_383940_262205# a_376520_259212# 4.92556f +C133 a_383620_262205# a_376520_259212# 2.7563f +C134 a_377450_262205# a_376520_259212# 40.1477f +C135 a_374398_259299# a_376520_259212# 12.9247f +C136 a_365828_259091# a_376520_259212# 25.3712f +C137 a_373878_259299# a_376520_259212# 0.20081f +C138 a_386992_259299# a_376520_259212# 3.24772f +C139 a_365708_259299# a_376520_259212# 3.20723f +C140 a_365828_265695# a_376520_259212# 24.117f +C141 w_364522_258756# a_376520_259212# 0.94999p +.ends + +.subckt TOP CCM_OUT PU VDD VSS VIN_OUT BCM_OUT VCM_OUT VIN VBIAS EN PD +Xsc_tieh_tiel$1_0 PD PU sc_tieh_tiel$1_0/gf180mcu_fd_sc_mcu9t5v0__tieh$2_0/a_125_157# ++ VDD sc_tieh_tiel$1_0/gf180mcu_fd_sc_mcu9t5v0__tiel$3_0/a_124_157# VSS sc_tieh_tiel$1 +Xio_secondary_5p0$1_0 EN m3_419992_265695# VSS VDD io_secondary_5p0$1 +XM_0 M_0/a_402461_244568# M_0/a_410134_251737# VSS M_0/a_403521_244568# a_499016_248165# ++ BCM_OUT m4_400150_261569# M_0/a_409618_260539# VIN_OUT a_498947_268180# CCM_OUT ++ M_0/a_403251_244568# m3_419992_265695# M_0/a_404311_244568# VSS M_0/a_401941_244568# ++ m4_400150_261569# M_0/a_404041_244568# M_0/a_409498_256643# M_0/a_402731_244568# ++ M_0/a_401151_244568# VCM_OUT VDD M +D0 a_498947_268180# VDD diode_pd2nw_06v0 pj=40u area=99.99999p +D1 a_498947_268180# VDD diode_pd2nw_06v0 pj=40u area=99.99999p +D2 VSS a_499016_248165# diode_nd2ps_06v0 pj=40u area=99.99999p +X0 a_498947_268180# VIN VDD ppolyf_u r_width=40u r_length=10u +D3 a_499016_248165# VDD diode_pd2nw_06v0 pj=40u area=99.99999p +D4 a_499016_248165# VDD diode_pd2nw_06v0 pj=40u area=99.99999p +D5 VSS a_499016_248165# diode_nd2ps_06v0 pj=40u area=99.99999p +D6 a_498947_268180# VDD diode_pd2nw_06v0 pj=40u area=99.99999p +D7 VSS a_498947_268180# diode_nd2ps_06v0 pj=40u area=99.99999p +D8 a_499016_248165# VDD diode_pd2nw_06v0 pj=40u area=99.99999p +D9 a_499016_248165# VDD diode_pd2nw_06v0 pj=40u area=99.99999p +D10 VSS a_498947_268180# diode_nd2ps_06v0 pj=40u area=99.99999p +D11 VSS a_499016_248165# diode_nd2ps_06v0 pj=40u area=99.99999p +D12 VSS a_498947_268180# diode_nd2ps_06v0 pj=40u area=99.99999p +D13 a_498947_268180# VDD diode_pd2nw_06v0 pj=40u area=99.99999p +X1 a_499016_248165# VBIAS VDD ppolyf_u r_width=40u r_length=10u +D14 VSS a_499016_248165# diode_nd2ps_06v0 pj=40u area=99.99999p +D15 VSS a_498947_268180# diode_nd2ps_06v0 pj=40u area=99.99999p +C0 TEXT$22_0/m2_7200_0# TEXT$9_0/m1_2880_0# 0 +C1 TEXT$1_0/m1_6000_0# TEXT$1_0/m1_7200_0# 0.2838f +C2 TEXT$21_0/m4_10800_0# TEXT$21_0/m4_11700_0# 0.14096f +C3 TEXT$24_0/m3_960_0# TEXT$9_0/m1_2160_0# 0 +C4 TEXT$24_0/m3_2160_0# TEXT$9_0/m1_960_0# 0 +C5 sc_tieh_tiel$1_0/gf180mcu_fd_sc_mcu9t5v0__tiel$3_0/a_124_157# PD 0.00624f +C6 TEXT$21_0/m4_2160_0# TEXT$22_0/m2_1440_0# 0 +C7 TEXT$1_0/m1_2400_0# TEXT$6_0/m4_2400_0# 0.00679f +C8 TEXT$3_0/m2_4800_0# TEXT$20_0/m3_7920_720# 0 +C9 TEXT$24_0/m3_9600_0# TEXT$9_0/m1_9600_0# 0.01567f +C10 TEXT$24_0/m3_5760_0# TEXT$21_0/m4_9360_0# 0 +C11 TEXT$21_0/m4_7920_720# TEXT$9_0/m1_3840_0# -0 +C12 M_0/a_409618_260539# m4_400150_261569# -0 +C13 TEXT$24_0/m3_5760_0# TEXT$7_0/m2_4800_960# 0.00343f +C14 TEXT$23_0/m1_1440_0# TEXT$22_0/m2_720_0# 0.00168f +C15 TEXT$20_0/m3_7200_0# TEXT$20_0/m3_7920_720# 0.12093f +C16 TEXT$8_0/m4_6720_0# TEXT$20_0/m3_10800_0# 0 +C17 TEXT$23_0/m1_3780_0# TEXT$20_0/m3_3780_0# 0.00157f +C18 TEXT$22_0/m2_9360_0# TEXT$20_0/m3_9360_0# 0.42195f +C19 TEXT$21_0/m4_16560_0# TEXT$21_0/m4_17280_0# 0.15155f +C20 TEXT$24_0/m3_10560_0# TEXT$20_0/m3_14400_0# 0.01775f +C21 TEXT$23_0/m1_5760_0# TEXT$1_0/m1_3600_0# 0.00988f +C22 TEXT$21_0/m4_10080_0# TEXT$20_0/m3_10080_0# 0.40607f +C23 TEXT$22_0/m2_5760_0# TEXT$6_0/m4_3600_0# 0 +C24 TEXT$23_0/m1_7920_720# TEXT$23_0/m1_7200_0# 0.10344f +C25 TEXT$23_0/m1_10800_0# TEXT$20_0/m3_10800_0# 0.0029f +C26 TEXT$8_0/m4_10560_0# TEXT$9_0/m1_9600_0# -0 +C27 TEXT$24_0/m3_3840_0# TEXT$22_0/m2_8640_0# 0.00169f +C28 TEXT$4_0/m3_7200_0# TEXT$22_0/m2_9360_0# 0 +C29 TEXT$21_0/m4_1440_0# TEXT$20_0/m3_1440_0# 0.36769f +C30 TEXT$23_0/m1_6480_0# TEXT$6_0/m4_3600_0# 0 +C31 TEXT$3_0/m2_0_0# TEXT$23_0/m1_2880_720# 0 +C32 TEXT$4_0/m3_7200_0# TEXT$1_0/m1_6000_0# 0.00242f +C33 TEXT$24_0/m3_4800_960# TEXT$21_0/m4_9360_0# 0 +C34 TEXT$24_0/m3_9600_0# TEXT$23_0/m1_13680_0# 0 +C35 TEXT$24_0/m3_4800_960# TEXT$7_0/m2_4800_960# 0.42246f +C36 TEXT$21_0/m4_16560_0# TEXT$20_0/m3_16560_0# 0.40081f +C37 TEXT$23_0/m1_14400_0# TEXT$9_0/m1_10560_0# 0.01107f +C38 TEXT$4_0/m3_0_0# TEXT$21_0/m4_2160_0# 0 +C39 TEXT$22_0/m2_9360_0# TEXT$3_0/m2_7200_0# 0.01999f +C40 TEXT$23_0/m1_2880_720# TEXT$20_0/m3_3780_0# 0 +C41 TEXT$23_0/m1_3780_0# TEXT$20_0/m3_2880_720# 0 +C42 TEXT$9_0/m1_5760_0# TEXT$8_0/m4_5760_0# 0.00251f +C43 TEXT$8_0/m4_10560_0# TEXT$20_0/m3_15120_0# 0 +C44 TEXT$1_0/m1_10800_0# TEXT$3_0/m2_10800_0# 1.16108f +C45 TEXT$7_0/m2_9600_0# TEXT$7_0/m2_10560_0# 0.13915f +C46 TEXT$20_0/m3_12960_0# TEXT$3_0/m2_10800_0# 0 +C47 TEXT$1_0/m1_6000_0# TEXT$3_0/m2_7200_0# 0.007f +C48 TEXT$22_0/m2_17280_0# TEXT$22_0/m2_18000_0# 0.17402f +C49 TEXT$9_0/m1_4800_960# TEXT$7_0/m2_5760_0# 0 +C50 TEXT$3_0/m2_2400_0# TEXT$6_0/m4_2400_0# 0.00713f +C51 TEXT$20_0/m3_8640_0# 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+C1618 TEXT$24_0/m3_6720_0# VSS 0.53604f +C1619 TEXT$24_0/m3_5760_0# VSS 0.50746f +C1620 TEXT$24_0/m3_4800_960# VSS 0.40695f +C1621 TEXT$24_0/m3_3840_0# VSS 0.55397f +C1622 TEXT$24_0/m3_2880_0# VSS 0.48843f +C1623 TEXT$24_0/m3_2160_0# VSS 0.28113f +C1624 TEXT$24_0/m3_960_0# VSS 0.53366f +C1625 TEXT$24_0/m3_0_0# VSS 0.62072f +C1626 TEXT$8_0/m4_10560_0# VSS 0.58619f +C1627 TEXT$8_0/m4_9600_0# VSS 0.52311f +C1628 TEXT$8_0/m4_7680_0# VSS 0.46028f +C1629 TEXT$8_0/m4_6720_0# VSS 0.45506f +C1630 TEXT$8_0/m4_5760_0# VSS 0.42745f +C1631 TEXT$8_0/m4_4800_960# VSS 0.35093f +C1632 TEXT$8_0/m4_3840_0# VSS 0.46517f +C1633 TEXT$8_0/m4_2880_0# VSS 0.41267f +C1634 TEXT$8_0/m4_2160_0# VSS 0.23197f +C1635 TEXT$8_0/m4_960_0# VSS 0.44746f +C1636 TEXT$8_0/m4_0_0# VSS 0.54263f +C1637 VDD VSS 2.42752p +C1638 PU VSS 5.85351f +C1639 sc_tieh_tiel$1_0/gf180mcu_fd_sc_mcu9t5v0__tiel$3_0/a_124_157# VSS 0.3723f +C1640 sc_tieh_tiel$1_0/gf180mcu_fd_sc_mcu9t5v0__tieh$2_0/a_125_157# VSS 0.37323f +.ends + diff --git a/blocks/composite/regulated_cascoded_cmirror/LVS/lvs/TOP/TOP_sim.spice b/blocks/composite/regulated_cascoded_cmirror/LVS/lvs/TOP/TOP_sim.spice new file mode 100644 index 00000000..28d9f394 --- /dev/null +++ b/blocks/composite/regulated_cascoded_cmirror/LVS/lvs/TOP/TOP_sim.spice @@ -0,0 +1,2052 @@ +| units: 0.5 tech: gf180mcuD format: MIT +x sc_tieh_tiel$1_0/gf180mcu_fd_sc_mcu9t5v0__tieh$2_0/a_125_157# VDD PD VDD s=15840,536 d=15840,536 l=100 w=180 x=514986 y=227349 pfet_05v0 +x sc_tieh_tiel$1_0/gf180mcu_fd_sc_mcu9t5v0__tieh$2_0/a_125_157# TEXT$9_0/VSUBS sc_tieh_tiel$1_0/gf180mcu_fd_sc_mcu9t5v0__tieh$2_0/a_125_157# TEXT$9_0/VSUBS s=11616,440 d=11616,440 l=120 w=132 x=514986 y=227721 nfet_05v0 +x sc_tieh_tiel$1_0/gf180mcu_fd_sc_mcu9t5v0__tiel$3_0/a_124_157# TEXT$9_0/VSUBS PU TEXT$9_0/VSUBS s=11616,440 d=11616,440 l=120 w=132 x=514985 y=226108 nfet_05v0 +x sc_tieh_tiel$1_0/gf180mcu_fd_sc_mcu9t5v0__tiel$3_0/a_124_157# VDD sc_tieh_tiel$1_0/gf180mcu_fd_sc_mcu9t5v0__tiel$3_0/a_124_157# VDD s=15840,536 d=15840,536 l=100 w=180 x=515005 y=226480 pfet_05v0 +x io_secondary_5p0$1_0/ppolyf_u_9H3LNU_0/a_n224793_504155# EN m3_419992_265695# VDD s=816000,16204 d=816000,16204 l=2000 w=8000 x=510003 y=227557 ppolyf_u +x m3_419992_265695# TEXT$9_0/VSUBS l=0 w=0 x=503355 y=217079 diode_nd2ps_06v0 +x m3_419992_265695# TEXT$9_0/VSUBS l=0 w=0 x=498891 y=217079 diode_nd2ps_06v0 +x m3_419992_265695# TEXT$9_0/VSUBS l=0 w=0 x=501123 y=217079 diode_nd2ps_06v0 +x m3_419992_265695# TEXT$9_0/VSUBS l=0 w=0 x=505587 y=217079 diode_nd2ps_06v0 +x m3_419992_265695# VDD s=21168000,22704 l=0 w=0 x=498887 y=228335 diode_pd2nw_06v0 +x m3_419992_265695# VDD s=21168000,22704 l=0 w=0 x=505535 y=228335 diode_pd2nw_06v0 +x m3_419992_265695# VDD s=21168000,22704 l=0 w=0 x=501103 y=228335 diode_pd2nw_06v0 +x m3_419992_265695# VDD s=21168000,22704 l=0 w=0 x=503319 y=228335 diode_pd2nw_06v0 +x VDD VDD VDD VDD d=232000,4232 l=400 w=2000 x=387920 y=265903 pfet_03v3 +x M_0/a_365708_259299# VDD M_0/a_365708_259299# VDD s=240000,4240 d=240000,4240 l=400 w=2000 x=371358 y=262205 pfet_03v3 +x M_0/a_365708_259299# VDD M_0/a_365708_259299# VDD s=240000,4240 d=240000,4240 l=400 w=2000 x=367408 y=262205 pfet_03v3 +x a_498947_268180# M_0/a_401941_244568# M_0/a_402461_244568# VDD s=240000,4240 d=240000,4240 l=400 w=2000 x=402061 y=244568 pfet_03v3 +x VDD VDD VDD VDD d=232000,4232 l=400 w=2000 x=366636 y=265903 pfet_03v3 +x VDD VDD VDD VDD d=232000,4232 l=400 w=2000 x=400463 y=244568 pfet_03v3 +x M_0/a_401151_244568# VDD M_0/a_404311_244568# VDD s=240000,4240 d=240000,4240 l=400 w=2000 x=404431 y=249916 pfet_03v3 +x VDD VDD VDD VDD d=232000,4232 l=400 w=2000 x=386304 y=262205 pfet_03v3 +x a_499016_248165# M_0/a_373878_259299# M_0/a_374398_259299# VDD s=240000,4240 d=240000,4240 l=400 w=2000 x=373998 y=259299 pfet_03v3 +x M_0/a_386992_259299# VDD M_0/a_386992_259299# VDD s=240000,4240 d=240000,4240 l=400 w=2000 x=388692 y=262205 pfet_03v3 +x VDD VDD VDD VDD d=232000,4232 l=400 w=2000 x=396090 y=259299 pfet_03v3 +x M_0/a_383940_262205# M_0/a_386992_259299# M_0/a_383940_262205# VDD s=240000,4240 d=240000,4240 l=400 w=2000 x=392642 y=259299 pfet_03v3 +x VDD VDD VDD VDD d=232000,4232 l=400 w=2000 x=386304 y=265903 pfet_03v3 +x M_0/a_401151_244568# VDD M_0/a_401151_244568# VDD s=240000,4240 d=240000,4240 l=400 w=2000 x=401271 y=249916 pfet_03v3 +x m4_400150_261569# M_0/a_409618_260539# M_0/a_404041_244568# TEXT$9_0/VSUBS s=96000,1840 d=96000,1840 l=200 w=800 x=410208 y=260919 nfet_03v3 +x TEXT$9_0/VSUBS TEXT$9_0/VSUBS TEXT$9_0/VSUBS TEXT$9_0/VSUBS d=185600,3432 l=200 w=1600 x=376962 y=259699 nfet_03v3 +x TEXT$9_0/VSUBS TEXT$9_0/VSUBS TEXT$9_0/VSUBS TEXT$9_0/VSUBS d=92800,1832 l=200 w=800 x=411996 y=258781 nfet_03v3 +x a_499016_248165# M_0/a_365708_259299# a_499016_248165# VDD s=240000,4240 d=240000,4240 l=400 w=2000 x=371358 y=259299 pfet_03v3 +x M_0/a_409618_260539# TEXT$9_0/VSUBS m4_400150_261569# TEXT$9_0/VSUBS s=96000,1840 d=96000,1840 l=200 w=800 x=409618 y=260919 nfet_03v3 +x a_499016_248165# M_0/a_365708_259299# a_499016_248165# VDD s=240000,4240 d=240000,4240 l=400 w=2000 x=367408 y=259299 pfet_03v3 +x M_0/a_409498_256643# TEXT$9_0/VSUBS m4_400150_261569# TEXT$9_0/VSUBS s=96000,1840 d=96000,1840 l=200 w=800 x=411388 y=256643 nfet_03v3 +x M_0/a_377450_262205# TEXT$9_0/VSUBS M_0/a_377450_262205# TEXT$9_0/VSUBS s=192000,3440 d=192000,3440 l=200 w=1600 x=378750 y=259699 nfet_03v3 +x TEXT$9_0/VSUBS TEXT$9_0/VSUBS TEXT$9_0/VSUBS TEXT$9_0/VSUBS d=185600,3432 l=200 w=1600 x=376962 y=262205 nfet_03v3 +x TEXT$9_0/VSUBS TEXT$9_0/VSUBS TEXT$9_0/VSUBS TEXT$9_0/VSUBS d=92800,1832 l=200 w=800 x=411452 y=242557 nfet_03v3 +x M_0/a_409618_260539# TEXT$9_0/VSUBS m4_400150_261569# TEXT$9_0/VSUBS s=96000,1840 d=96000,1840 l=200 w=800 x=410798 y=260919 nfet_03v3 +x M_0/a_377450_262205# TEXT$9_0/VSUBS M_0/a_377450_262205# TEXT$9_0/VSUBS s=192000,3440 d=192000,3440 l=200 w=1600 x=378160 y=259699 nfet_03v3 +x m3_419992_265695# VDD M_0/a_401151_244568# VDD s=240000,4240 d=240000,4240 l=400 w=2000 x=401666 y=255368 pfet_03v3 +x VDD VDD VDD VDD d=232000,4232 l=400 w=2000 x=386304 y=259299 pfet_03v3 +x TEXT$9_0/VSUBS TEXT$9_0/VSUBS TEXT$9_0/VSUBS TEXT$9_0/VSUBS d=185600,3432 l=200 w=1600 x=384348 y=259699 nfet_03v3 +x M_0/a_365708_259299# VDD M_0/a_365708_259299# VDD s=240000,4240 d=240000,4240 l=400 w=2000 x=372938 y=262205 pfet_03v3 +x M_0/a_374398_259299# M_0/a_377450_262205# M_0/a_374398_259299# TEXT$9_0/VSUBS s=192000,3440 d=192000,3440 l=200 w=1600 x=378750 y=262205 nfet_03v3 +x m3_419992_265695# VDD M_0/a_401151_244568# VDD s=240000,4240 d=240000,4240 l=400 w=2000 x=404036 y=255368 pfet_03v3 +x M_0/a_383940_262205# M_0/a_386992_259299# M_0/a_383940_262205# VDD s=240000,4240 d=240000,4240 l=400 w=2000 x=388692 y=259299 pfet_03v3 +x TEXT$9_0/VSUBS TEXT$9_0/VSUBS TEXT$9_0/VSUBS TEXT$9_0/VSUBS d=92800,1832 l=200 w=800 x=409010 y=260919 nfet_03v3 +x a_498947_268180# M_0/a_403521_244568# M_0/a_404041_244568# VDD s=240000,4240 d=240000,4240 l=400 w=2000 x=403641 y=244568 pfet_03v3 +x M_0/a_386992_259299# VDD M_0/a_395162_259299# VDD s=240000,4240 d=240000,4240 l=400 w=2000 x=395282 y=262205 pfet_03v3 +x M_0/a_386992_259299# VDD M_0/a_386992_259299# VDD s=240000,4240 d=240000,4240 l=400 w=2000 x=393432 y=262205 pfet_03v3 +x TEXT$9_0/VSUBS TEXT$9_0/VSUBS TEXT$9_0/VSUBS TEXT$9_0/VSUBS d=92800,1832 l=200 w=800 x=409646 y=242557 nfet_03v3 +x M_0/a_374398_259299# M_0/a_377450_262205# M_0/a_374398_259299# TEXT$9_0/VSUBS s=192000,3440 d=192000,3440 l=200 w=1600 x=378160 y=262205 nfet_03v3 +x M_0/a_377450_262205# TEXT$9_0/VSUBS M_0/a_377450_262205# TEXT$9_0/VSUBS s=192000,3440 d=192000,3440 l=200 w=1600 x=382880 y=259699 nfet_03v3 +x TEXT$9_0/VSUBS TEXT$9_0/VSUBS TEXT$9_0/VSUBS TEXT$9_0/VSUBS d=185600,3432 l=200 w=1600 x=384348 y=262205 nfet_03v3 +x M_0/a_365708_259299# VDD M_0/a_365708_259299# VDD s=240000,4240 d=240000,4240 l=400 w=2000 x=372148 y=262205 pfet_03v3 +x M_0/a_365708_259299# VDD M_0/a_365708_259299# VDD s=240000,4240 d=240000,4240 l=400 w=2000 x=365828 y=262205 pfet_03v3 +x M_0/a_377450_262205# TEXT$9_0/VSUBS M_0/a_377450_262205# TEXT$9_0/VSUBS s=192000,3440 d=192000,3440 l=200 w=1600 x=382290 y=259699 nfet_03v3 +x M_0/a_386992_259299# VDD M_0/a_386992_259299# VDD s=240000,4240 d=240000,4240 l=400 w=2000 x=390272 y=262205 pfet_03v3 +x VDD VDD VDD VDD d=232000,4232 l=400 w=2000 x=405239 y=249916 pfet_03v3 +x M_0/a_374398_259299# M_0/a_377450_262205# M_0/a_374398_259299# TEXT$9_0/VSUBS s=192000,3440 d=192000,3440 l=200 w=1600 x=382880 y=262205 nfet_03v3 +x M_0/a_365708_259299# VDD M_0/a_365708_259299# VDD s=240000,4240 d=240000,4240 l=400 w=2000 x=368988 y=262205 pfet_03v3 +x M_0/a_401151_244568# VDD M_0/a_402731_244568# VDD s=240000,4240 d=240000,4240 l=400 w=2000 x=402851 y=249916 pfet_03v3 +x m3_419992_265695# VDD M_0/a_365708_259299# VDD s=240000,4240 d=240000,4240 l=400 w=2000 x=365828 y=265903 pfet_03v3 +x M_0/a_374398_259299# M_0/a_377450_262205# M_0/a_374398_259299# TEXT$9_0/VSUBS s=192000,3440 d=192000,3440 l=200 w=1600 x=382290 y=262205 nfet_03v3 +x a_499016_248165# M_0/a_365708_259299# a_499016_248165# VDD s=240000,4240 d=240000,4240 l=400 w=2000 x=372938 y=259299 pfet_03v3 +x TEXT$9_0/VSUBS TEXT$9_0/VSUBS TEXT$9_0/VSUBS TEXT$9_0/VSUBS d=92800,1832 l=200 w=800 x=411452 y=249599 nfet_03v3 +x M_0/a_386992_259299# VDD M_0/a_386992_259299# VDD s=240000,4240 d=240000,4240 l=400 w=2000 x=389482 y=262205 pfet_03v3 +x TEXT$9_0/VSUBS TEXT$9_0/VSUBS TEXT$9_0/VSUBS TEXT$9_0/VSUBS d=92800,1832 l=200 w=800 x=411452 y=251737 nfet_03v3 +x VDD VDD VDD VDD d=232000,4232 l=400 w=2000 x=374806 y=262205 pfet_03v3 +x TEXT$9_0/VSUBS TEXT$9_0/VSUBS TEXT$9_0/VSUBS TEXT$9_0/VSUBS d=92800,1832 l=200 w=800 x=411996 y=256643 nfet_03v3 +x M_0/a_404041_244568# TEXT$9_0/VSUBS M_0/a_409498_256643# TEXT$9_0/VSUBS s=96000,1840 d=96000,1840 l=200 w=800 x=410208 y=258781 nfet_03v3 +x M_0/a_383940_262205# M_0/a_395162_259299# m4_400150_261569# VDD s=240000,4240 d=240000,4240 l=400 w=2000 x=395282 y=259299 pfet_03v3 +x M_0/a_383940_262205# M_0/a_386992_259299# M_0/a_383940_262205# VDD s=240000,4240 d=240000,4240 l=400 w=2000 x=393432 y=259299 pfet_03v3 +x VDD VDD VDD VDD d=232000,4232 l=400 w=2000 x=365020 y=262205 pfet_03v3 +x M_0/a_404041_244568# TEXT$9_0/VSUBS M_0/a_409618_260539# TEXT$9_0/VSUBS s=96000,1840 d=96000,1840 l=200 w=800 x=409618 y=258781 nfet_03v3 +x M_0/a_401151_244568# VDD M_0/a_401941_244568# VDD s=240000,4240 d=240000,4240 l=400 w=2000 x=402061 y=249916 pfet_03v3 +x VDD VDD VDD VDD d=232000,4232 l=400 w=2000 x=404844 y=255368 pfet_03v3 +x M_0/a_365708_259299# VDD M_0/a_365708_259299# VDD s=240000,4240 d=240000,4240 l=400 w=2000 x=368198 y=262205 pfet_03v3 +x VDD VDD VDD VDD d=232000,4232 l=400 w=2000 x=400463 y=249916 pfet_03v3 +x TEXT$9_0/VSUBS TEXT$9_0/VSUBS TEXT$9_0/VSUBS TEXT$9_0/VSUBS d=92800,1832 l=200 w=800 x=409646 y=249599 nfet_03v3 +x TEXT$9_0/VSUBS TEXT$9_0/VSUBS TEXT$9_0/VSUBS TEXT$9_0/VSUBS d=92800,1832 l=200 w=800 x=409646 y=251737 nfet_03v3 +x a_499016_248165# M_0/a_365708_259299# a_499016_248165# VDD s=240000,4240 d=240000,4240 l=400 w=2000 x=372148 y=259299 pfet_03v3 +x M_0/a_377450_262205# TEXT$9_0/VSUBS M_0/a_377450_262205# TEXT$9_0/VSUBS s=192000,3440 d=192000,3440 l=200 w=1600 x=380520 y=259699 nfet_03v3 +x a_499016_248165# M_0/a_365708_259299# a_499016_248165# VDD s=240000,4240 d=240000,4240 l=400 w=2000 x=365828 y=259299 pfet_03v3 +x M_0/a_404041_244568# TEXT$9_0/VSUBS M_0/a_409618_260539# TEXT$9_0/VSUBS s=96000,1840 d=96000,1840 l=200 w=800 x=410798 y=258781 nfet_03v3 +x VDD VDD VDD VDD d=232000,4232 l=400 w=2000 x=365020 y=265903 pfet_03v3 +x M_0/a_383940_262205# M_0/a_386992_259299# M_0/a_383940_262205# VDD s=240000,4240 d=240000,4240 l=400 w=2000 x=390272 y=259299 pfet_03v3 +x M_0/a_377450_262205# TEXT$9_0/VSUBS M_0/a_377450_262205# TEXT$9_0/VSUBS s=192000,3440 d=192000,3440 l=200 w=1600 x=379930 y=259699 nfet_03v3 +x M_0/a_402461_244568# TEXT$9_0/VSUBS VCM_OUT TEXT$9_0/VSUBS s=96000,1840 d=96000,1840 l=200 w=800 x=410844 y=242557 nfet_03v3 +x TEXT$9_0/VSUBS TEXT$9_0/VSUBS TEXT$9_0/VSUBS TEXT$9_0/VSUBS d=92800,1832 l=200 w=800 x=409010 y=258781 nfet_03v3 +x a_499016_248165# M_0/a_365708_259299# a_499016_248165# VDD s=240000,4240 d=240000,4240 l=400 w=2000 x=368988 y=259299 pfet_03v3 +x m3_419992_265695# VDD M_0/a_401151_244568# VDD s=240000,4240 d=240000,4240 l=400 w=2000 x=402456 y=255368 pfet_03v3 +x M_0/a_377450_262205# TEXT$9_0/VSUBS M_0/a_377450_262205# TEXT$9_0/VSUBS s=192000,3440 d=192000,3440 l=200 w=1600 x=379340 y=259699 nfet_03v3 +x M_0/a_374398_259299# M_0/a_377450_262205# M_0/a_374398_259299# TEXT$9_0/VSUBS s=192000,3440 d=192000,3440 l=200 w=1600 x=380520 y=262205 nfet_03v3 +x M_0/a_402461_244568# TEXT$9_0/VSUBS M_0/a_402461_244568# TEXT$9_0/VSUBS s=96000,1840 d=96000,1840 l=200 w=800 x=410254 y=242557 nfet_03v3 +x VDD VDD VDD VDD d=232000,4232 l=400 w=2000 x=400858 y=255368 pfet_03v3 +x M_0/a_383940_262205# M_0/a_386992_259299# M_0/a_383940_262205# VDD s=240000,4240 d=240000,4240 l=400 w=2000 x=389482 y=259299 pfet_03v3 +x M_0/a_374398_259299# M_0/a_377450_262205# M_0/a_374398_259299# TEXT$9_0/VSUBS s=192000,3440 d=192000,3440 l=200 w=1600 x=379930 y=262205 nfet_03v3 +x VDD VDD VDD VDD d=232000,4232 l=400 w=2000 x=374806 y=259299 pfet_03v3 +x m4_400150_261569# M_0/a_409618_260539# M_0/a_404041_244568# TEXT$9_0/VSUBS s=96000,1840 d=96000,1840 l=200 w=800 x=411388 y=260919 nfet_03v3 +x M_0/a_386992_259299# VDD M_0/a_386992_259299# VDD s=240000,4240 d=240000,4240 l=400 w=2000 x=391852 y=262205 pfet_03v3 +x a_498947_268180# M_0/a_404311_244568# VIN_OUT VDD s=240000,4240 d=240000,4240 l=400 w=2000 x=404431 y=244568 pfet_03v3 +x M_0/a_386992_259299# VDD M_0/a_386992_259299# VDD s=240000,4240 d=240000,4240 l=400 w=2000 x=394222 y=262205 pfet_03v3 +x VDD VDD VDD VDD d=232000,4232 l=400 w=2000 x=365020 y=259299 pfet_03v3 +x M_0/a_374398_259299# M_0/a_377450_262205# M_0/a_374398_259299# TEXT$9_0/VSUBS s=192000,3440 d=192000,3440 l=200 w=1600 x=379340 y=262205 nfet_03v3 +x M_0/a_386992_259299# VDD M_0/a_386992_259299# VDD s=240000,4240 d=240000,4240 l=400 w=2000 x=387902 y=262205 pfet_03v3 +x a_499016_248165# M_0/a_365708_259299# a_499016_248165# VDD s=240000,4240 d=240000,4240 l=400 w=2000 x=368198 y=259299 pfet_03v3 +x M_0/a_365708_259299# VDD M_0/a_365708_259299# VDD s=240000,4240 d=240000,4240 l=400 w=2000 x=370568 y=262205 pfet_03v3 +x M_0/a_365708_259299# VDD M_0/a_365708_259299# VDD s=240000,4240 d=240000,4240 l=400 w=2000 x=366618 y=262205 pfet_03v3 +x a_498947_268180# M_0/a_401151_244568# a_498947_268180# VDD s=240000,4240 d=240000,4240 l=400 w=2000 x=401271 y=244568 pfet_03v3 +x M_0/a_386992_259299# VDD M_0/a_386992_259299# VDD s=240000,4240 d=240000,4240 l=400 w=2000 x=391062 y=262205 pfet_03v3 +x M_0/a_401151_244568# VDD M_0/a_403521_244568# VDD s=240000,4240 d=240000,4240 l=400 w=2000 x=403641 y=249916 pfet_03v3 +x M_0/a_386992_259299# VDD M_0/a_386992_259299# VDD s=240000,4240 d=240000,4240 l=400 w=2000 x=387112 y=262205 pfet_03v3 +x M_0/a_365708_259299# VDD M_0/a_365708_259299# VDD s=240000,4240 d=240000,4240 l=400 w=2000 x=369778 y=262205 pfet_03v3 +x M_0/a_410134_251737# TEXT$9_0/VSUBS M_0/a_410724_251737# TEXT$9_0/VSUBS s=96000,1840 d=96000,1840 l=200 w=800 x=410844 y=249599 nfet_03v3 +x M_0/a_409498_256643# TEXT$9_0/VSUBS m4_400150_261569# TEXT$9_0/VSUBS s=96000,1840 d=96000,1840 l=200 w=800 x=410208 y=256643 nfet_03v3 +x M_0/a_403251_244568# M_0/a_410724_251737# BCM_OUT TEXT$9_0/VSUBS s=96000,1840 d=96000,1840 l=200 w=800 x=410844 y=251737 nfet_03v3 +x m4_400150_261569# M_0/a_409498_256643# CCM_OUT TEXT$9_0/VSUBS s=96000,1840 d=96000,1840 l=200 w=800 x=409618 y=256643 nfet_03v3 +x m3_419992_265695# VDD M_0/a_386992_259299# VDD s=240000,4240 d=240000,4240 l=400 w=2000 x=387112 y=265903 pfet_03v3 +x M_0/a_383940_262205# M_0/a_386992_259299# M_0/a_383940_262205# VDD s=240000,4240 d=240000,4240 l=400 w=2000 x=391852 y=259299 pfet_03v3 +x M_0/a_410134_251737# TEXT$9_0/VSUBS M_0/a_410134_251737# TEXT$9_0/VSUBS s=96000,1840 d=96000,1840 l=200 w=800 x=410254 y=249599 nfet_03v3 +x M_0/a_403251_244568# M_0/a_410134_251737# M_0/a_403251_244568# TEXT$9_0/VSUBS s=96000,1840 d=96000,1840 l=200 w=800 x=410254 y=251737 nfet_03v3 +x M_0/a_383940_262205# M_0/a_386992_259299# M_0/a_383940_262205# VDD s=240000,4240 d=240000,4240 l=400 w=2000 x=394222 y=259299 pfet_03v3 +x M_0/a_383940_262205# M_0/a_386992_259299# M_0/a_383940_262205# VDD s=240000,4240 d=240000,4240 l=400 w=2000 x=387902 y=259299 pfet_03v3 +x m4_400150_261569# M_0/a_409498_256643# CCM_OUT TEXT$9_0/VSUBS s=96000,1840 d=96000,1840 l=200 w=800 x=410798 y=256643 nfet_03v3 +x a_499016_248165# M_0/a_365708_259299# a_499016_248165# VDD s=240000,4240 d=240000,4240 l=400 w=2000 x=370568 y=259299 pfet_03v3 +x TEXT$9_0/VSUBS TEXT$9_0/VSUBS TEXT$9_0/VSUBS TEXT$9_0/VSUBS d=92800,1832 l=200 w=800 x=409010 y=256643 nfet_03v3 +x M_0/a_377450_262205# TEXT$9_0/VSUBS M_0/a_377450_262205# TEXT$9_0/VSUBS s=192000,3440 d=192000,3440 l=200 w=1600 x=381700 y=259699 nfet_03v3 +x M_0/a_377450_262205# TEXT$9_0/VSUBS M_0/a_377450_262205# TEXT$9_0/VSUBS s=192000,3440 d=192000,3440 l=200 w=1600 x=377570 y=259699 nfet_03v3 +x a_499016_248165# M_0/a_365708_259299# a_499016_248165# VDD s=240000,4240 d=240000,4240 l=400 w=2000 x=366618 y=259299 pfet_03v3 +x M_0/a_383940_262205# M_0/a_386992_259299# M_0/a_383940_262205# VDD s=240000,4240 d=240000,4240 l=400 w=2000 x=391062 y=259299 pfet_03v3 +x TEXT$9_0/VSUBS TEXT$9_0/VSUBS TEXT$9_0/VSUBS TEXT$9_0/VSUBS d=92800,1832 l=200 w=800 x=411996 y=260919 nfet_03v3 +x M_0/a_383940_262205# M_0/a_386992_259299# M_0/a_383940_262205# VDD s=240000,4240 d=240000,4240 l=400 w=2000 x=387112 y=259299 pfet_03v3 +x a_499016_248165# M_0/a_365708_259299# a_499016_248165# VDD s=240000,4240 d=240000,4240 l=400 w=2000 x=369778 y=259299 pfet_03v3 +x M_0/a_377450_262205# TEXT$9_0/VSUBS M_0/a_383620_262205# TEXT$9_0/VSUBS s=192000,3440 d=192000,3440 l=200 w=1600 x=383740 y=259699 nfet_03v3 +x M_0/a_377450_262205# TEXT$9_0/VSUBS M_0/a_377450_262205# TEXT$9_0/VSUBS s=192000,3440 d=192000,3440 l=200 w=1600 x=381110 y=259699 nfet_03v3 +x M_0/a_365708_259299# VDD M_0/a_373878_259299# VDD s=240000,4240 d=240000,4240 l=400 w=2000 x=373998 y=262205 pfet_03v3 +x M_0/a_374398_259299# M_0/a_377450_262205# M_0/a_374398_259299# TEXT$9_0/VSUBS s=192000,3440 d=192000,3440 l=200 w=1600 x=377570 y=262205 nfet_03v3 +x M_0/a_404041_244568# TEXT$9_0/VSUBS M_0/a_409498_256643# TEXT$9_0/VSUBS s=96000,1840 d=96000,1840 l=200 w=800 x=411388 y=258781 nfet_03v3 +x m3_419992_265695# VDD M_0/a_401151_244568# VDD s=240000,4240 d=240000,4240 l=400 w=2000 x=403246 y=255368 pfet_03v3 +x M_0/a_374398_259299# M_0/a_377450_262205# M_0/a_374398_259299# TEXT$9_0/VSUBS s=192000,3440 d=192000,3440 l=200 w=1600 x=381700 y=262205 nfet_03v3 +x VDD VDD VDD VDD d=232000,4232 l=400 w=2000 x=405239 y=244568 pfet_03v3 +x VDD VDD VDD VDD d=232000,4232 l=400 w=2000 x=396090 y=262205 pfet_03v3 +x a_498947_268180# M_0/a_402731_244568# M_0/a_403251_244568# VDD s=240000,4240 d=240000,4240 l=400 w=2000 x=402851 y=244568 pfet_03v3 +x M_0/a_386992_259299# VDD M_0/a_386992_259299# VDD s=240000,4240 d=240000,4240 l=400 w=2000 x=392642 y=262205 pfet_03v3 +x M_0/a_374398_259299# M_0/a_383620_262205# M_0/a_383940_262205# TEXT$9_0/VSUBS s=192000,3440 d=192000,3440 l=200 w=1600 x=383740 y=262205 nfet_03v3 +x M_0/a_374398_259299# M_0/a_377450_262205# M_0/a_374398_259299# TEXT$9_0/VSUBS s=192000,3440 d=192000,3440 l=200 w=1600 x=381110 y=262205 nfet_03v3 +x a_498947_268180# VDD s=21168000,22704 l=0 w=0 x=505595 y=268180 diode_pd2nw_06v0 +x a_498947_268180# VDD s=21168000,22704 l=0 w=0 x=501163 y=268180 diode_pd2nw_06v0 +x a_499016_248165# TEXT$9_0/VSUBS l=0 w=0 x=505716 y=236909 diode_nd2ps_06v0 +x a_510063_259404# a_498947_268180# VIN VDD s=816000,16204 d=816000,16204 l=2000 w=8000 x=510063 y=259404 ppolyf_u +x a_499016_248165# VDD s=21168000,22704 l=0 w=0 x=499016 y=248165 diode_pd2nw_06v0 +x a_499016_248165# VDD s=21168000,22704 l=0 w=0 x=503448 y=248165 diode_pd2nw_06v0 +x a_499016_248165# TEXT$9_0/VSUBS l=0 w=0 x=499020 y=236909 diode_nd2ps_06v0 +x a_498947_268180# VDD s=21168000,22704 l=0 w=0 x=498947 y=268180 diode_pd2nw_06v0 +x a_498947_268180# TEXT$9_0/VSUBS l=0 w=0 x=498951 y=256924 diode_nd2ps_06v0 +x a_499016_248165# VDD s=21168000,22704 l=0 w=0 x=505664 y=248165 diode_pd2nw_06v0 +x a_499016_248165# VDD s=21168000,22704 l=0 w=0 x=501232 y=248165 diode_pd2nw_06v0 +x a_498947_268180# TEXT$9_0/VSUBS l=0 w=0 x=501183 y=256924 diode_nd2ps_06v0 +x a_499016_248165# TEXT$9_0/VSUBS l=0 w=0 x=503484 y=236909 diode_nd2ps_06v0 +x a_498947_268180# TEXT$9_0/VSUBS l=0 w=0 x=505647 y=256924 diode_nd2ps_06v0 +x a_498947_268180# VDD s=21168000,22704 l=0 w=0 x=503379 y=268180 diode_pd2nw_06v0 +x a_510132_239389# a_499016_248165# VBIAS VDD s=816000,16204 d=816000,16204 l=2000 w=8000 x=510132 y=239389 ppolyf_u +x a_499016_248165# TEXT$9_0/VSUBS l=0 w=0 x=501252 y=236909 diode_nd2ps_06v0 +x a_498947_268180# TEXT$9_0/VSUBS l=0 w=0 x=503415 y=256924 diode_nd2ps_06v0 +C TEXT$23_0/m1_15120_0# TEXT$21_0/m4_15840_0# 0.0 +C TEXT$20_0/m3_8640_0# TEXT$3_0/m2_6000_0# 0.0 +C TEXT$20_0/m3_6480_0# TEXT$6_0/m4_3600_0# 0.0 +C TEXT$20_0/m3_10800_0# TEXT$23_0/m1_10800_0# 0.0 +C TEXT$8_0/m4_4800_960# TEXT$9_0/m1_5760_0# 0.0 +C TEXT$4_0/m3_4800_0# TEXT$3_0/m2_4800_0# 1.1 +C TEXT$1_0/m1_12000_0# TEXT$20_0/m3_15120_0# 0.0 +C TEXT$6_0/m4_1200_0# TEXT$22_0/m2_3780_0# 0.0 +C TEXT$1_0/m1_2400_0# TEXT$4_0/m3_2400_0# 0.0 +C M_0/a_403251_244568# VDD 1.1 +C TEXT$22_0/m2_8640_0# TEXT$8_0/m4_4800_960# 0.0 +C TEXT$1_0/m1_2400_0# TEXT$22_0/m2_4320_0# 0.0 +C TEXT$1_0/m1_7200_0# TEXT$6_0/m4_8400_0# 0.0 +C TEXT$1_0/m1_8400_0# TEXT$6_0/m4_7200_0# 0.0 +C TEXT$7_0/m2_960_0# TEXT$9_0/m1_0_0# 0.0 +C TEXT$7_0/m2_0_0# TEXT$9_0/m1_960_0# 0.0 +C TEXT$6_0/m4_8400_0# TEXT$3_0/m2_8400_0# 0.0 +C TEXT$24_0/m3_3840_0# TEXT$23_0/m1_7920_720# 0.0 +C TEXT$1_0/m1_9600_0# TEXT$4_0/m3_8400_0# 0.0 +C TEXT$4_0/m3_9600_0# TEXT$3_0/m2_9600_0# 1.0 +C TEXT$1_0/m1_8400_0# TEXT$4_0/m3_9600_0# 0.0 +C TEXT$1_0/m1_8400_0# TEXT$23_0/m1_11700_0# 0.0 +C TEXT$23_0/m1_11700_0# TEXT$3_0/m2_9600_0# 0.0 +C TEXT$23_0/m1_18000_0# TEXT$21_0/m4_18000_0# 0.0 +C VDD TEXT$24_0/m3_6720_0# 0.0 +C TEXT$20_0/m3_11700_0# TEXT$9_0/m1_7680_0# 0.0 +C TEXT$20_0/m3_1440_0# TEXT$22_0/m2_720_0# 0.0 +C TEXT$23_0/m1_3780_0# TEXT$3_0/m2_1200_0# 0.0 +C TEXT$20_0/m3_2160_0# TEXT$22_0/m2_2160_0# 0.4 +C TEXT$23_0/m1_15840_0# TEXT$23_0/m1_16560_0# 0.3 +C TEXT$6_0/m4_3600_0# TEXT$6_0/m4_4800_0# 0.3 +C TEXT$21_0/m4_5760_0# TEXT$21_0/m4_4320_0# 0.0 +C TEXT$9_0/m1_5760_0# TEXT$7_0/m2_5760_0# 0.7 +C TEXT$4_0/m3_6000_0# TEXT$6_0/m4_4800_0# 0.0 +C VDD m4_400150_261569# 1.5 +C TEXT$21_0/m4_10800_0# TEXT$23_0/m1_10080_0# 0.0 +C TEXT$20_0/m3_8640_0# TEXT$9_0/m1_3840_0# 0.0 +C TEXT$22_0/m2_9360_0# TEXT$6_0/m4_7200_0# 0.0 +C TEXT$4_0/m3_0_0# TEXT$6_0/m4_0_0# 1.1 +C M_0/a_402461_244568# VDD 1.2 +C TEXT$20_0/m3_720_0# TEXT$23_0/m1_720_0# 0.0 +C TEXT$20_0/m3_4320_0# TEXT$3_0/m2_2400_0# 0.0 +C TEXT$4_0/m3_6000_0# TEXT$4_0/m3_7200_0# 0.3 +C TEXT$1_0/m1_6000_0# TEXT$23_0/m1_7920_720# 0.0 +C TEXT$7_0/m2_2880_0# TEXT$7_0/m2_3840_0# 0.1 +C TEXT$20_0/m3_14400_0# TEXT$3_0/m2_12000_0# 0.0 +C TEXT$22_0/m2_17280_0# TEXT$20_0/m3_17280_0# 0.4 +C TEXT$8_0/m4_6720_0# TEXT$24_0/m3_6720_0# 0.7 +C TEXT$20_0/m3_12960_0# TEXT$22_0/m2_12960_0# 0.4 +C TEXT$20_0/m3_17280_0# TEXT$21_0/m4_17280_0# 0.4 +C TEXT$1_0/m1_6000_0# TEXT$3_0/m2_6000_0# 1.1 +C TEXT$3_0/m2_7200_0# TEXT$3_0/m2_6000_0# 0.3 +C TEXT$21_0/m4_10800_0# TEXT$9_0/m1_6720_0# 0.0 +C TEXT$24_0/m3_6720_0# TEXT$7_0/m2_6720_0# 0.7 +C TEXT$20_0/m3_7200_0# TEXT$8_0/m4_2880_0# 0.0 +C TEXT$6_0/m4_1200_0# TEXT$21_0/m4_3780_0# 0.0 +C TEXT$24_0/m3_3840_0# TEXT$9_0/m1_3840_0# 0.0 +C TEXT$20_0/m3_8640_0# TEXT$8_0/m4_3840_0# 0.0 +C TEXT$21_0/m4_7200_0# TEXT$3_0/m2_4800_0# 0.0 +C TEXT$1_0/m1_12000_0# TEXT$6_0/m4_12000_0# 0.0 +C TEXT$20_0/m3_15120_0# TEXT$20_0/m3_14400_0# 0.3 +C TEXT$21_0/m4_9360_0# TEXT$8_0/m4_4800_960# 0.0 +C TEXT$20_0/m3_10800_0# TEXT$6_0/m4_8400_0# 0.0 +C TEXT$4_0/m3_2400_0# TEXT$22_0/m2_4320_0# 0.0 +C m4_400150_261569# m3_419992_265695# 0.1 +C VDD M_0/a_395162_259299# 3.1 +C TEXT$24_0/m3_7680_0# TEXT$8_0/m4_9600_0# 0.0 +C TEXT$4_0/m3_9600_0# TEXT$20_0/m3_11700_0# 0.0 +C TEXT$22_0/m2_17280_0# TEXT$22_0/m2_16560_0# 0.1 +C TEXT$20_0/m3_3780_0# TEXT$22_0/m2_3780_0# 0.2 +C a_498947_268180# VDD 57.0 +C TEXT$20_0/m3_720_0# TEXT$21_0/m4_1440_0# 0.0 +C TEXT$6_0/m4_4800_0# TEXT$23_0/m1_7200_0# 0.0 +C TEXT$23_0/m1_11700_0# TEXT$20_0/m3_11700_0# 0.0 +C TEXT$22_0/m2_16560_0# TEXT$21_0/m4_17280_0# 0.0 +C TEXT$8_0/m4_3840_0# TEXT$24_0/m3_3840_0# 0.7 +C TEXT$22_0/m2_11700_0# TEXT$9_0/m1_6720_0# 0.0 +C TEXT$20_0/m3_6480_0# TEXT$20_0/m3_7200_0# 0.3 +C TEXT$22_0/m2_14400_0# TEXT$8_0/m4_10560_0# 0.0 +C TEXT$8_0/m4_2160_0# TEXT$24_0/m3_2880_0# 0.0 +C TEXT$20_0/m3_2160_0# TEXT$21_0/m4_2160_0# 0.4 +C TEXT$1_0/m1_1200_0# TEXT$3_0/m2_1200_0# 1.1 +C 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TEXT$6_0/m4_4800_0# TEXT$21_0/m4_7920_720# 0.0 +C TEXT$22_0/m2_10080_0# TEXT$22_0/m2_10800_0# 0.2 +C TEXT$20_0/m3_11700_0# TEXT$21_0/m4_10800_0# 0.0 +C TEXT$8_0/m4_4800_960# TEXT$24_0/m3_5760_0# 0.0 +C TEXT$20_0/m3_10800_0# TEXT$9_0/m1_6720_0# 0.0 +C TEXT$7_0/m2_960_0# TEXT$23_0/m1_5760_0# 0.0 +C TEXT$20_0/m3_720_0# TEXT$22_0/m2_0_0# 0.0 +C TEXT$1_0/m1_2400_0# TEXT$21_0/m4_4320_0# 0.0 +C TEXT$24_0/m3_2160_0# TEXT$8_0/m4_960_0# 0.0 +C TEXT$1_0/m1_0_0# TEXT$23_0/m1_2880_720# 0.0 +C VDD PD 0.2 +C TEXT$21_0/m4_11700_0# TEXT$3_0/m2_8400_0# 0.0 +C TEXT$21_0/m4_10080_0# TEXT$8_0/m4_5760_0# 0.0 +C TEXT$20_0/m3_9360_0# TEXT$8_0/m4_4800_960# 0.0 +C TEXT$7_0/m2_4800_960# TEXT$9_0/m1_5760_0# 0.0 +C TEXT$8_0/m4_3840_0# TEXT$9_0/m1_3840_0# 0.0 +C TEXT$22_0/m2_6480_0# TEXT$23_0/m1_6480_0# 0.4 +C TEXT$8_0/m4_2160_0# TEXT$9_0/m1_2880_0# 0.0 +C TEXT$6_0/m4_0_0# TEXT$22_0/m2_2160_0# 0.0 +C TEXT$22_0/m2_8640_0# TEXT$6_0/m4_6000_0# 0.0 +C TEXT$8_0/m4_9600_0# TEXT$8_0/m4_10560_0# 0.2 +C TEXT$22_0/m2_7920_720# TEXT$20_0/m3_7200_0# 0.0 +C TEXT$22_0/m2_7200_0# TEXT$20_0/m3_7920_720# 0.0 +C TEXT$20_0/m3_3780_0# TEXT$3_0/m2_1200_0# 0.0 +C TEXT$4_0/m3_7200_0# TEXT$22_0/m2_9360_0# 0.0 +C TEXT$7_0/m2_2160_0# TEXT$7_0/m2_2880_0# 0.1 +C TEXT$22_0/m2_8640_0# TEXT$7_0/m2_4800_960# 0.0 +C TEXT$1_0/m1_10800_0# TEXT$20_0/m3_12960_0# 0.0 +C TEXT$20_0/m3_11700_0# TEXT$22_0/m2_11700_0# 0.2 +C TEXT$1_0/m1_0_0# TEXT$1_0/m1_1200_0# 0.2 +C TEXT$20_0/m3_16560_0# TEXT$21_0/m4_16560_0# 0.4 +C TEXT$1_0/m1_4800_0# TEXT$3_0/m2_4800_0# 1.1 +C TEXT$21_0/m4_10080_0# TEXT$21_0/m4_10800_0# 0.2 +C TEXT$3_0/m2_8400_0# TEXT$23_0/m1_10800_0# 0.0 +C TEXT$8_0/m4_4800_960# TEXT$24_0/m3_4800_960# 0.4 +C VDD TEXT$24_0/m3_3840_0# 0.0 +C TEXT$24_0/m3_5760_0# TEXT$7_0/m2_5760_0# 0.7 +C TEXT$24_0/m3_2880_0# TEXT$9_0/m1_2880_0# 0.0 +C TEXT$22_0/m2_10080_0# TEXT$23_0/m1_9360_0# 0.0 +C TEXT$20_0/m3_11700_0# TEXT$24_0/m3_7680_0# 0.0 +C TEXT$21_0/m4_6480_0# TEXT$3_0/m2_3600_0# 0.0 +C TEXT$3_0/m2_10800_0# TEXT$6_0/m4_12000_0# 0.0 +C TEXT$23_0/m1_11700_0# TEXT$24_0/m3_6720_0# 0.0 +C TEXT$20_0/m3_7920_720# TEXT$21_0/m4_8640_0# 0.0 +C TEXT$20_0/m3_10080_0# TEXT$6_0/m4_7200_0# 0.0 +C TEXT$4_0/m3_8400_0# TEXT$20_0/m3_10800_0# 0.0 +C TEXT$22_0/m2_7920_720# TEXT$6_0/m4_6000_0# 0.0 +C TEXT$22_0/m2_10800_0# TEXT$21_0/m4_10800_0# 0.0 +C TEXT$20_0/m3_0_0# TEXT$21_0/m4_720_0# 0.0 +C TEXT$22_0/m2_15840_0# TEXT$21_0/m4_16560_0# 0.0 +C TEXT$20_0/m3_5760_0# TEXT$20_0/m3_6480_0# 0.2 +C TEXT$1_0/m1_0_0# TEXT$3_0/m2_0_0# 1.1 +C TEXT$4_0/m3_2400_0# TEXT$21_0/m4_4320_0# 0.0 +C TEXT$6_0/m4_2400_0# TEXT$3_0/m2_2400_0# 0.0 +C M_0/a_404041_244568# VDD 1.7 +C TEXT$23_0/m1_14400_0# TEXT$7_0/m2_10560_0# 0.0 +C TEXT$20_0/m3_4320_0# TEXT$23_0/m1_4320_0# 0.0 +C TEXT$22_0/m2_4320_0# TEXT$21_0/m4_4320_0# 0.0 +C TEXT$20_0/m3_10800_0# TEXT$21_0/m4_11700_0# 0.0 +C TEXT$24_0/m3_9600_0# TEXT$8_0/m4_10560_0# 0.0 +C TEXT$6_0/m4_0_0# TEXT$21_0/m4_2160_0# 0.0 +C TEXT$22_0/m2_10080_0# TEXT$23_0/m1_10080_0# 0.4 +C TEXT$24_0/m3_960_0# TEXT$7_0/m2_0_0# 0.0 +C TEXT$8_0/m4_2880_0# TEXT$7_0/m2_2880_0# 0.0 +C TEXT$21_0/m4_7200_0# TEXT$23_0/m1_6480_0# 0.0 +C TEXT$20_0/m3_5760_0# TEXT$23_0/m1_5760_0# 0.0 +C TEXT$20_0/m3_7920_720# TEXT$21_0/m4_7920_720# 0.2 +C TEXT$1_0/m1_10800_0# TEXT$1_0/m1_12000_0# 0.1 +C TEXT$21_0/m4_15120_0# TEXT$7_0/m2_10560_0# 0.0 +C TEXT$1_0/m1_12000_0# TEXT$3_0/m2_12000_0# 1.1 +C TEXT$4_0/m3_7200_0# TEXT$21_0/m4_10080_0# 0.0 +C TEXT$22_0/m2_12960_0# TEXT$3_0/m2_10800_0# 0.0 +C TEXT$22_0/m2_10800_0# TEXT$22_0/m2_11700_0# 0.1 +C TEXT$21_0/m4_6480_0# TEXT$9_0/m1_2160_0# 0.0 +C TEXT$21_0/m4_9360_0# TEXT$7_0/m2_4800_960# 0.0 +C TEXT$20_0/m3_12960_0# TEXT$20_0/m3_13680_0# 0.2 +C PD0 2.4 +R PD 22 += PD via_dev_0/m1_0_0# += PD sc_tieh_tiel$1_0/tieH += PD sc_tieh_tiel$1_0/gf180mcu_fd_sc_mcu9t5v0__tieh$2_0/Z += PD via_dev$42_0/m2_0_0# += PD m2_516942_218066# +C VBIAS0 21.4 +R VBIAS 578 +C VIN0 21.6 +R VIN 578 +C VCM_OUT0 90.4 +R VCM_OUT 135 += VCM_OUT via_dev$35_2/m2_0_0# += VCM_OUT m4_420113_244057# += VCM_OUT via_dev$34_0/m2_0_0# += VCM_OUT M_0/a_411044_242557# +C BCM_OUT0 83.5 +R BCM_OUT 135 += BCM_OUT via_dev$35_3/m2_0_0# += BCM_OUT m4_420120_253237# += BCM_OUT via_dev$34_1/m2_0_0# += BCM_OUT M_0/a_411044_251737# +C CCM_OUT0 77.4 +R CCM_OUT 192 += CCM_OUT via_dev$35_5/m2_0_0# += CCM_OUT m4_420104_257713# += CCM_OUT via_dev$34_2/m2_0_0# += CCM_OUT M_0/a_409818_256643# +C VIN_OUT0 75.9 +R VIN_OUT 223 += VIN_OUT via_dev$35_4/m2_0_0# += VIN_OUT m4_420119_263354# += VIN_OUT via_dev$34_3/m2_0_0# += VIN_OUT M_0/a_404831_244568# +R a_510132_239389# 1400 +R a_510063_259404# 1400 +C TEXT$1_0/m1_12000_0#0 1.7 +C TEXT$1_0/m1_10800_0#0 1.6 +C TEXT$1_0/m1_9600_0#0 1.5 +C TEXT$1_0/m1_8400_0#0 1.6 +C TEXT$1_0/m1_7200_0#0 1.0 +C TEXT$1_0/m1_6000_0#0 1.5 +C TEXT$1_0/m1_4800_0#0 1.4 +C TEXT$1_0/m1_3600_0#0 1.5 +C TEXT$1_0/m1_2400_0#0 1.4 +C TEXT$1_0/m1_1200_0#0 1.5 +C TEXT$1_0/m1_0_0#0 1.6 +C M_0/a_410724_251737#0 2.9 +R M_0/a_410724_251737# 107 +C M_0/a_410134_251737#0 6.4 +R M_0/a_410134_251737# 219 +C M_0/a_409498_256643#0 8.5 +R M_0/a_409498_256643# 340 +C M_0/a_409618_260539#0 8.4 +R M_0/a_409618_260539# 335 +C M_0/a_404041_244568#0 14.1 +R M_0/a_404041_244568# 489 +C M_0/a_403251_244568#0 5.1 +R M_0/a_403251_244568# 293 +C M_0/a_402461_244568#0 8.1 +R M_0/a_402461_244568# 292 +C a_498947_268180#0 209.0 +R a_498947_268180# 881 += a_498947_268180# via_dev$35_6/m2_0_0# += a_498947_268180# m4_399395_244477# += a_498947_268180# via_dev$35_7/m2_0_0# += a_498947_268180# m2_399395_243478# += a_498947_268180# M_0/a_401271_243528# +C M_0/a_404311_244568#0 0.2 +R M_0/a_404311_244568# 272 +C M_0/a_403521_244568#0 0.0 +R M_0/a_403521_244568# 272 +C M_0/a_402731_244568#0 0.0 +R M_0/a_402731_244568# 272 +C M_0/a_401941_244568#0 0.0 +R M_0/a_401941_244568# 272 +C M_0/a_401151_244568#0 2.6 +R M_0/a_401151_244568# 1220 +C m4_400150_261569#0 16.5 +R m4_400150_261569# 601 += m4_400150_261569# via_dev$35_1/m2_0_0# += m4_400150_261569# M_0/a_409618_256263# += m4_400150_261569# via_dev$35_0/m2_0_0# += m4_400150_261569# m2_397020_261569# += m4_400150_261569# M_0/a_395682_259299# +C M_0/a_395162_259299#0 0.3 +R M_0/a_395162_259299# 260 +C M_0/a_383940_262205#0 4.9 +R M_0/a_383940_262205# 2090 +C M_0/a_383620_262205#0 2.8 +R M_0/a_383620_262205# 191 +C M_0/a_377450_262205#0 40.1 +R M_0/a_377450_262205# 2962 +C M_0/a_374398_259299#0 12.9 +R M_0/a_374398_259299# 2054 +C a_499016_248165#0 232.3 +R a_499016_248165# 2377 += a_499016_248165# via_dev$32_1/m2_0_0# += a_499016_248165# m3_420393_272672# += a_499016_248165# M_0/a_365828_259091# +C M_0/a_373878_259299#0 0.2 +R M_0/a_373878_259299# 260 +C M_0/a_386992_259299#0 3.2 +R M_0/a_386992_259299# 3505 +C M_0/a_365708_259299#0 3.2 +R M_0/a_365708_259299# 3505 +C TEXT$3_0/m2_12000_0#0 1.1 +C TEXT$3_0/m2_10800_0#0 1.0 +C TEXT$3_0/m2_9600_0#0 0.9 +C TEXT$3_0/m2_8400_0#0 1.0 +C TEXT$3_0/m2_7200_0#0 0.7 +C TEXT$3_0/m2_6000_0#0 0.9 +C TEXT$3_0/m2_4800_0#0 0.8 +C TEXT$3_0/m2_3600_0#0 0.9 +C TEXT$3_0/m2_2400_0#0 0.9 +C TEXT$3_0/m2_1200_0#0 0.9 +C TEXT$3_0/m2_0_0#0 1.0 +C TEXT$21_0/m4_18000_0#0 0.4 +C TEXT$21_0/m4_17280_0#0 0.3 +C TEXT$21_0/m4_16560_0#0 0.3 +C TEXT$21_0/m4_15840_0#0 0.3 +C TEXT$21_0/m4_15120_0#0 0.3 +C TEXT$21_0/m4_14400_0#0 0.3 +C TEXT$21_0/m4_13680_0#0 0.3 +C TEXT$21_0/m4_12960_0#0 0.3 +C TEXT$21_0/m4_11700_0#0 0.2 +C TEXT$21_0/m4_10800_0#0 0.3 +C TEXT$21_0/m4_10080_0#0 0.3 +C TEXT$21_0/m4_9360_0#0 0.3 +C TEXT$21_0/m4_8640_0#0 0.3 +C TEXT$21_0/m4_7920_720#0 0.2 +C TEXT$21_0/m4_7200_0#0 0.3 +C TEXT$21_0/m4_6480_0#0 0.3 +C TEXT$21_0/m4_5760_0#0 0.3 +C TEXT$21_0/m4_4320_0#0 0.3 +C TEXT$21_0/m4_3780_0#0 0.2 +C TEXT$21_0/m4_2880_720#0 0.2 +C TEXT$21_0/m4_2160_0#0 0.3 +C TEXT$21_0/m4_1440_0#0 0.3 +C TEXT$21_0/m4_720_0#0 0.3 +C TEXT$21_0/m4_0_0#0 0.4 +C TEXT$23_0/m1_18000_0#0 0.7 +C TEXT$23_0/m1_17280_0#0 0.7 +C TEXT$23_0/m1_16560_0#0 0.6 +C TEXT$23_0/m1_15840_0#0 0.7 +C TEXT$23_0/m1_15120_0#0 0.6 +C TEXT$23_0/m1_14400_0#0 0.7 +C TEXT$23_0/m1_13680_0#0 0.6 +C TEXT$23_0/m1_12960_0#0 0.7 +C TEXT$23_0/m1_11700_0#0 0.4 +C TEXT$23_0/m1_10800_0#0 0.7 +C TEXT$23_0/m1_10080_0#0 0.7 +C TEXT$23_0/m1_9360_0#0 0.7 +C TEXT$23_0/m1_8640_0#0 0.7 +C TEXT$23_0/m1_7920_720#0 0.5 +C TEXT$23_0/m1_7200_0#0 0.6 +C TEXT$23_0/m1_6480_0#0 0.7 +C TEXT$23_0/m1_5760_0#0 0.7 +C TEXT$23_0/m1_4320_0#0 0.7 +C TEXT$23_0/m1_3780_0#0 0.4 +C TEXT$23_0/m1_2880_720#0 0.5 +C TEXT$23_0/m1_2160_0#0 0.7 +C TEXT$23_0/m1_1440_0#0 0.7 +C TEXT$23_0/m1_720_0#0 0.6 +C TEXT$23_0/m1_0_0#0 0.8 +C m3_419992_265695#0 234.5 +R m3_419992_265695# 783 += m3_419992_265695# via_dev$32_0/m2_0_0# += m3_419992_265695# m2_477527_223220# += m3_419992_265695# via_dev$33_0/m2_0_0# += m3_419992_265695# M_0/a_365828_265695# += m3_419992_265695# io_secondary_5p0$1_0/m1_499212_228525# += m3_419992_265695# io_secondary_5p0$1_0/diode_pd2nw_06v0_5DG9HC_0/a_507479_219793# += m3_419992_265695# io_secondary_5p0$1_0/diode_pd2nw_06v0_5DG9HC_0/a_505263_219793# += m3_419992_265695# io_secondary_5p0$1_0/diode_pd2nw_06v0_5DG9HC_0/a_503047_219793# += m3_419992_265695# io_secondary_5p0$1_0/diode_pd2nw_06v0_5DG9HC_0/a_500831_219793# += m3_419992_265695# io_secondary_5p0$1_0/ppolyf_u_9H3LNU_0/a_n224793_504053# += m3_419992_265695# io_secondary_5p0$1_0/diode_nd2ps_06v0_MV3SZ3_0/a_507503_219793# += m3_419992_265695# io_secondary_5p0$1_0/diode_nd2ps_06v0_MV3SZ3_0/a_505271_219793# += m3_419992_265695# io_secondary_5p0$1_0/diode_nd2ps_06v0_MV3SZ3_0/a_503039_219793# += m3_419992_265695# io_secondary_5p0$1_0/diode_nd2ps_06v0_MV3SZ3_0/a_500807_219793# +R io_secondary_5p0$1_0/ppolyf_u_9H3LNU_0/a_n224793_504155# 1400 +C EN0 6.2 +R EN 584 += EN io_secondary_5p0$1_0/m1_512035_219553# += EN io_secondary_5p0$1_0/ppolyf_u_9H3LNU_0/a_n224793_506155# +C TEXT$7_0/m2_10560_0#0 0.8 +C TEXT$7_0/m2_9600_0#0 0.7 +C TEXT$7_0/m2_7680_0#0 0.7 +C TEXT$7_0/m2_6720_0#0 0.7 +C TEXT$7_0/m2_5760_0#0 0.7 +C TEXT$7_0/m2_4800_960#0 0.5 +C TEXT$7_0/m2_3840_0#0 0.7 +C TEXT$7_0/m2_2880_0#0 0.6 +C TEXT$7_0/m2_2160_0#0 0.4 +C TEXT$7_0/m2_960_0#0 0.7 +C TEXT$7_0/m2_0_0#0 0.7 +C TEXT$9_0/m1_10560_0#0 1.2 +C TEXT$9_0/m1_9600_0#0 1.1 +C TEXT$9_0/m1_7680_0#0 1.1 +C TEXT$9_0/m1_6720_0#0 1.1 +C TEXT$9_0/m1_5760_0#0 1.0 +C TEXT$9_0/m1_4800_960#0 0.8 +C TEXT$9_0/m1_3840_0#0 1.1 +C TEXT$9_0/m1_2880_0#0 1.0 +C TEXT$9_0/m1_2160_0#0 0.6 +C TEXT$9_0/m1_960_0#0 1.1 +C TEXT$9_0/m1_0_0#0 1.1 +R TEXT$9_0/VSUBS 72427 += TEXT$9_0/VSUBS DNWell_Rect_0/w_407433_240888# += TEXT$9_0/VSUBS w_407433_240888# += TEXT$9_0/VSUBS via_dev$35_4/VSUBS += TEXT$9_0/VSUBS via_dev$34_3/VSUBS += TEXT$9_0/VSUBS via_dev$35_1/VSUBS += TEXT$9_0/VSUBS via_dev$35_0/VSUBS += TEXT$9_0/VSUBS via_dev$35_5/VSUBS += TEXT$9_0/VSUBS via_dev$34_2/VSUBS += TEXT$9_0/VSUBS via_dev$37_2/VSUBS += TEXT$9_0/VSUBS via_dev$37_2/m1_0_0# += TEXT$9_0/VSUBS via_dev$35_3/VSUBS += TEXT$9_0/VSUBS via_dev$34_1/VSUBS += TEXT$9_0/VSUBS via_dev$41_1/VSUBS += TEXT$9_0/VSUBS via_dev$35_7/VSUBS += TEXT$9_0/VSUBS via_dev$35_2/VSUBS += TEXT$9_0/VSUBS via_dev$34_0/VSUBS += TEXT$9_0/VSUBS M_0/a_376520_259212# += TEXT$9_0/VSUBS DNWell_Rect_0/a_406361_239816# += TEXT$9_0/VSUBS via_dev$37_1/VSUBS += TEXT$9_0/VSUBS via_dev$37_1/m1_0_0# += TEXT$9_0/VSUBS via_dev$45_0/m1_0_0# += TEXT$9_0/VSUBS m2_514376_217140# += TEXT$9_0/VSUBS via_dev$37_0/m1_0_0# += TEXT$9_0/VSUBS m1_507881_217140# += TEXT$9_0/VSUBS m3_410146_285414# += TEXT$9_0/VSUBS via_dev$41_0/VSUBS += TEXT$9_0/VSUBS via_dev_0/VSUBS += TEXT$9_0/VSUBS via_dev$44_0/VSUBS += TEXT$9_0/VSUBS sc_tieh_tiel_0/VSUBS += TEXT$9_0/VSUBS sc_tieh_tiel$1_0/VSS += TEXT$9_0/VSUBS sc_tieh_tiel$1_0/gf180mcu_fd_sc_mcu9t5v0__tieh$2_0/VPW += TEXT$9_0/VSUBS sc_tieh_tiel$1_0/gf180mcu_fd_sc_mcu9t5v0__tieh$2_0/VSS += TEXT$9_0/VSUBS sc_tieh_tiel$1_0/gf180mcu_fd_sc_mcu9t5v0__tiel$3_0/VPW += TEXT$9_0/VSUBS sc_tieh_tiel$1_0/gf180mcu_fd_sc_mcu9t5v0__tiel$3_0/VSS += TEXT$9_0/VSUBS sc_tieh_tiel$1_0/gf180mcu_fd_sc_mcu9t5v0__filltie$1_1/VSS += TEXT$9_0/VSUBS sc_tieh_tiel$1_0/gf180mcu_fd_sc_mcu9t5v0__filltie$1_0/VSS += TEXT$9_0/VSUBS sc_tieh_tiel$1_0/via_dev$43_1/VSUBS += TEXT$9_0/VSUBS sc_tieh_tiel$1_0/via_dev$43_0/VSUBS += TEXT$9_0/VSUBS sc_tieh_tiel$1_0/VSUBS += TEXT$9_0/VSUBS sc_tieh_tiel$1_0/via_dev$43_1/m1_0_0# += TEXT$9_0/VSUBS sc_tieh_tiel$1_0/m1_396908_517398# += TEXT$9_0/VSUBS sc_tieh_tiel$1_0/via_dev$43_0/m1_0_0# += TEXT$9_0/VSUBS sc_tieh_tiel$1_0/m2_396908_515382# += TEXT$9_0/VSUBS via_dev$42_0/VSUBS += TEXT$9_0/VSUBS via_dev$45_0/VSUBS += TEXT$9_0/VSUBS TEXT$6_0/VSUBS += TEXT$9_0/VSUBS TEXT$4_0/VSUBS += TEXT$9_0/VSUBS TEXT$3_0/VSUBS += TEXT$9_0/VSUBS TEXT$1_0/VSUBS += TEXT$9_0/VSUBS via_dev$37_0/VSUBS += TEXT$9_0/VSUBS io_secondary_5p0$1_0/VSUBS += TEXT$9_0/VSUBS io_secondary_5p0$1_0/diode_pd2nw_06v0_5DG9HC_0/a_500511_219473# += TEXT$9_0/VSUBS io_secondary_5p0$1_0/ppolyf_u_9H3LNU_0/VSUBS += TEXT$9_0/VSUBS io_secondary_5p0$1_0/diode_nd2ps_06v0_MV3SZ3_0/a_500655_219641# += TEXT$9_0/VSUBS io_secondary_5p0$1_0/m1_497955_215963# += TEXT$9_0/VSUBS TEXT$21_0/VSUBS += TEXT$9_0/VSUBS TEXT$20_0/VSUBS += TEXT$9_0/VSUBS TEXT$22_0/VSUBS += TEXT$9_0/VSUBS TEXT$23_0/VSUBS += TEXT$9_0/VSUBS TEXT$8_0/VSUBS += TEXT$9_0/VSUBS TEXT$24_0/VSUBS += TEXT$9_0/VSUBS TEXT$7_0/VSUBS += TEXT$9_0/VSUBS a_344599_211617# +C TEXT$20_0/m3_18000_0#0 0.4 +C TEXT$20_0/m3_17280_0#0 0.3 +C TEXT$20_0/m3_16560_0#0 0.3 +C TEXT$20_0/m3_15840_0#0 0.3 +C TEXT$20_0/m3_15120_0#0 0.3 +C TEXT$20_0/m3_14400_0#0 0.3 +C TEXT$20_0/m3_13680_0#0 0.3 +C TEXT$20_0/m3_12960_0#0 0.4 +C TEXT$20_0/m3_11700_0#0 0.2 +C TEXT$20_0/m3_10800_0#0 0.3 +C TEXT$20_0/m3_10080_0#0 0.3 +C TEXT$20_0/m3_9360_0#0 0.3 +C TEXT$20_0/m3_8640_0#0 0.3 +C TEXT$20_0/m3_7920_720#0 0.3 +C TEXT$20_0/m3_7200_0#0 0.3 +C TEXT$20_0/m3_6480_0#0 0.3 +C TEXT$20_0/m3_5760_0#0 0.4 +C TEXT$20_0/m3_4320_0#0 0.4 +C TEXT$20_0/m3_3780_0#0 0.2 +C TEXT$20_0/m3_2880_720#0 0.3 +C TEXT$20_0/m3_2160_0#0 0.3 +C TEXT$20_0/m3_1440_0#0 0.3 +C TEXT$20_0/m3_720_0#0 0.3 +C TEXT$20_0/m3_0_0#0 0.4 +C TEXT$4_0/m3_12000_0#0 0.9 +C TEXT$4_0/m3_10800_0#0 0.7 +C TEXT$4_0/m3_9600_0#0 0.7 +C TEXT$4_0/m3_8400_0#0 0.8 +C TEXT$4_0/m3_7200_0#0 0.5 +C TEXT$4_0/m3_6000_0#0 0.7 +C TEXT$4_0/m3_4800_0#0 0.6 +C TEXT$4_0/m3_3600_0#0 0.7 +C TEXT$4_0/m3_2400_0#0 0.7 +C TEXT$4_0/m3_1200_0#0 0.7 +C TEXT$4_0/m3_0_0#0 0.8 +C TEXT$22_0/m2_18000_0#0 0.5 +C TEXT$22_0/m2_17280_0#0 0.4 +C TEXT$22_0/m2_16560_0#0 0.4 +C TEXT$22_0/m2_15840_0#0 0.4 +C TEXT$22_0/m2_15120_0#0 0.4 +C TEXT$22_0/m2_14400_0#0 0.4 +C TEXT$22_0/m2_13680_0#0 0.4 +C TEXT$22_0/m2_12960_0#0 0.5 +C TEXT$22_0/m2_11700_0#0 0.3 +C TEXT$22_0/m2_10800_0#0 0.4 +C TEXT$22_0/m2_10080_0#0 0.4 +C TEXT$22_0/m2_9360_0#0 0.4 +C TEXT$22_0/m2_8640_0#0 0.4 +C TEXT$22_0/m2_7920_720#0 0.4 +C TEXT$22_0/m2_7200_0#0 0.4 +C TEXT$22_0/m2_6480_0#0 0.4 +C TEXT$22_0/m2_5760_0#0 0.5 +C TEXT$22_0/m2_4320_0#0 0.5 +C TEXT$22_0/m2_3780_0#0 0.3 +C TEXT$22_0/m2_2880_720#0 0.4 +C TEXT$22_0/m2_2160_0#0 0.4 +C TEXT$22_0/m2_1440_0#0 0.4 +C TEXT$22_0/m2_720_0#0 0.4 +C TEXT$22_0/m2_0_0#0 0.5 +C TEXT$6_0/m4_12000_0#0 0.8 +C TEXT$6_0/m4_10800_0#0 0.6 +C TEXT$6_0/m4_9600_0#0 0.6 +C TEXT$6_0/m4_8400_0#0 0.7 +C TEXT$6_0/m4_7200_0#0 0.5 +C TEXT$6_0/m4_6000_0#0 0.6 +C TEXT$6_0/m4_4800_0#0 0.5 +C TEXT$6_0/m4_3600_0#0 0.6 +C TEXT$6_0/m4_2400_0#0 0.5 +C TEXT$6_0/m4_1200_0#0 0.6 +C TEXT$6_0/m4_0_0#0 0.7 +C TEXT$24_0/m3_10560_0#0 0.7 +C TEXT$24_0/m3_9600_0#0 0.6 +C TEXT$24_0/m3_7680_0#0 0.5 +C TEXT$24_0/m3_6720_0#0 0.5 +C TEXT$24_0/m3_5760_0#0 0.5 +C TEXT$24_0/m3_4800_960#0 0.4 +C TEXT$24_0/m3_3840_0#0 0.6 +C TEXT$24_0/m3_2880_0#0 0.5 +C TEXT$24_0/m3_2160_0#0 0.3 +C TEXT$24_0/m3_960_0#0 0.5 +C TEXT$24_0/m3_0_0#0 0.6 +C TEXT$8_0/m4_10560_0#0 0.6 +C TEXT$8_0/m4_9600_0#0 0.5 +C TEXT$8_0/m4_7680_0#0 0.5 +C TEXT$8_0/m4_6720_0#0 0.5 +C TEXT$8_0/m4_5760_0#0 0.4 +C TEXT$8_0/m4_4800_960#0 0.4 +C TEXT$8_0/m4_3840_0#0 0.5 +C TEXT$8_0/m4_2880_0#0 0.4 +C TEXT$8_0/m4_2160_0#0 0.2 +C TEXT$8_0/m4_960_0#0 0.4 +C TEXT$8_0/m4_0_0#0 0.5 +C VDD0 2432.8 +R VDD 555999 += VDD via_dev$39_0/m2_0_0# += VDD via_dev$15_0/m2_0_0# += VDD via_dev$29_0/m1_0_0# += VDD m4_409998_292651# += VDD M_0/w_364522_258756# += VDD w_345212_212189# += VDD sc_tieh_tiel$1_0/VDD += VDD via_dev$41_2/m1_0_0# += VDD w_498771_268004# += VDD via_dev$41_1/m1_0_0# += VDD w_498840_247989# += VDD via_dev$41_0/m1_0_0# += VDD m3_510297_218284# += VDD io_secondary_5p0$1_0/m1_497955_232243# += VDD io_secondary_5p0$1_0/diode_pd2nw_06v0_5DG9HC_0/w_500655_219617# += VDD io_secondary_5p0$1_0/ppolyf_u_9H3LNU_0/w_n225009_503837# += VDD m1_512118_230975# += VDD sc_tieh_tiel_0/m1_514121_226826# += VDD sc_tieh_tiel$1_0/gf180mcu_fd_sc_mcu9t5v0__tieh$2_0/VDD += VDD sc_tieh_tiel$1_0/gf180mcu_fd_sc_mcu9t5v0__tieh$2_0/VNW += VDD sc_tieh_tiel$1_0/gf180mcu_fd_sc_mcu9t5v0__tiel$3_0/VDD += VDD sc_tieh_tiel$1_0/gf180mcu_fd_sc_mcu9t5v0__tiel$3_0/VNW += VDD sc_tieh_tiel$1_0/gf180mcu_fd_sc_mcu9t5v0__filltie$1_1/VDD += VDD sc_tieh_tiel$1_0/gf180mcu_fd_sc_mcu9t5v0__filltie$1_0/VDD +C PU0 6.0 +R PU 28 += PU via_dev$44_0/m1_0_0# += PU sc_tieh_tiel$1_0/tieL += PU sc_tieh_tiel$1_0/gf180mcu_fd_sc_mcu9t5v0__tiel$3_0/ZN +C sc_tieh_tiel$1_0/gf180mcu_fd_sc_mcu9t5v0__tiel$3_0/a_124_157#0 0.4 +R sc_tieh_tiel$1_0/gf180mcu_fd_sc_mcu9t5v0__tiel$3_0/a_124_157# 61 +C sc_tieh_tiel$1_0/gf180mcu_fd_sc_mcu9t5v0__tieh$2_0/a_125_157#0 0.5 +R sc_tieh_tiel$1_0/gf180mcu_fd_sc_mcu9t5v0__tieh$2_0/a_125_157# 72 += VSS via_dev$39_0/VSUBS += VSS via_dev$15_0/VSUBS += VSS via_dev$29_0/VSUBS += VSS via_dev$14_0/VSUBS += VSS via_dev$14_0/m2_0_0# += VSS via_dev$11_0/VSUBS += VSS via_dev$11_0/m1_0_0# += VSS via_dev$36_0/VSUBS += VSS via_dev$36_0/m1_0_0# += VSS via_dev$38_0/VSUBS += VSS via_dev$41_2/VSUBS += VSS via_dev$38_0/m2_0_0# += VSS via_dev$35_6/VSUBS += VSS via_dev$32_1/VSUBS += VSS via_dev$33_0/VSUBS += VSS via_dev$32_0/VSUBS diff --git a/blocks/composite/regulated_cascoded_cmirror/README.md b/blocks/composite/regulated_cascoded_cmirror/README.md new file mode 100644 index 00000000..4738c7e2 --- /dev/null +++ b/blocks/composite/regulated_cascoded_cmirror/README.md @@ -0,0 +1,134 @@ +## Team Mahowalders Open-Source Silicon Project, Chipathon 2025 +### Project: Towards Precision Current Mirrors + +![](./design_proposal/_images//Top.png) + +**Motivation:** With the rise of analog computation for low-power edge intelligence and sensor systems, the demand for robust bias generation circuits has significantly increased. Bias current sources are fundamental to analog and mixed-signal designs, enabling precise control in amplifiers, comparators, sensor front-ends, and a wide range of other analog building blocks. Ideally, current sources deliver a quasi-constant current when transistors operate in the saturation region, where the output current is largely independent of the drain-to-source voltage. Achieving bias current sources that closely approximate this ideal behaviour is essential to ensure proper circuit operation. However, traditional current mirrors, though widely used, exhibit poor output impedance and limited voltage headroom, which can result in unstable biasing under varying conditions. When the output voltage exceeds the linear range, the current mirror output continues to increase linearly in the saturation region instead of reaching a plateau. This non-ideal behaviour makes such mirrors unsuitable for delivering stable bias currents, often leading to degraded performance in circuits that rely on precise biasing. + +**Objective:** This project proposes the automated design and layout of a high-impedance, energy-efficient bias generation block using regulated current mirror architectures. Integrated into the gLayout toolchain (Python2GDS), this design aims to enhance layout portability, stability, and scalability across process corners. + +**Design:** +We compare three bias current mirror architectures: + +* Vanilla Current Mirror (VCM), as a reference +* Self-Biased Common-Source CM (SB-CM), with improved impedance, moderate complexity +* Regulated Cascode CM (RC-CM), with high output impedance, better stability, but requires auxiliary bias + +All three versions will be parametrically instantiated via gLayout, enabling on-demand generation and automated layout. A testbench OTA stage will be used to convert an input voltage into current, allowing characterisation of each mirror’s response and stability under load. + +**Contributions:** + +* gLayout-compatible IP blocks for advanced analog biasing +* On-silicon testing of all three architectures, with a focus on RC-CM +* Performance benchmarking and trade-off analysis (stability, impedance, layout area, and bias dependencies) + +**Applications:** +The proposed IP targets analog designs where stable biasing is critical, such as sensor front-ends, neural interface systems, and low-frequency amplifiers. The RC-CM in particular can significantly improve performance in circuits sensitive to bias drift, without requiring extensive overhead. The regulated cascode current mirror provides a more robust stable current source than vanilla current mirrors that are usually used as is in analog circuits using biasin. By using this improved version, a wide range of analog circuits applications such as bias current generators, op-amps or sensor front-end where stable and accurate biasing is crucial to ensure the expected functioning of the circuit can benefit from the improved current mirror. + +### **Full Design Schematic:** + +![](./design_proposal/_images/finalS.png) + +This schematic illustrates a **high-performance, multi-output current mirroring system** designed for precision analog applications. The design centers on replicating and regulating an input current, utilizing a reference bias network to set the operational parameters for three distinct current mirror topologies. + +--- + +### Input and Bias Network + +* **Inputs:** The circuit accepts several primary inputs: + * **VDD:** The main power supply rail. + * **EN (Enable):** A digital control signal to power-gate the entire system. + * **V_IN:** The primary **Analog Input** voltage or current source that the system is designed to replicate. + * **V_AUX_CCM:** An auxiliary analog input specifically used to establish the control voltage for the **Regulated Cascode Current Mirror**. +* **Bias Generation (1/1000x Bias):** A dedicated sub-circuit generates a highly stable, low-current **reference bias** (bias_out}). This reference current is scaled (indicated as $1/1000\times$) and distributed to set the accurate operational point for all three current mirror stages, ensuring robust current matching and temperature stability. + +--- + +### Current Distribution Array (Top Section) + +The components connected to the VDD and EN lines, labeled with instances, form a current distribution or steering array. This section likely consists of matched transistors and resistors that use **V_IN** and the main current path to generate the input currents for the mirroring stages below. The matching of these components is crucial for the subsequent accuracy of the mirrored currents. + +--- + +### Parallel Current Mirror Stages + +The design incorporates three parallel current mirror blocks, each providing a different level of performance and complexity: + +1. **Vanilla Current Mirror (vanilla\_cm):** + * **Function:** This is the most basic implementation, providing a simple, proportional replication of the input current. + * **Output:** **V\_OUT\_VCM**. + * **Characteristics:** Moderate output impedance and matching, suitable where lower complexity is prioritized. + +2. **Self-Biased Current Mirror (biased\_cm):** + * **Function:** Features an internal feedback mechanism (self-biasing) to make the output current more immune to variations in the supply voltage (**VDD**) and less sensitive to transistor channel length modulation. + * **Output:** **V\_OUT\_BCM**. + * **Characteristics:** Improved current regulation and better current matching compared to the Vanilla type. + +3. **Regulated Cascode Current Mirror (cascode\_cm):** + * **Function:** This is the highest-precision stage. It uses a cascode transistor driven by an operational amplifier (or similar regulating circuit, potentially fed by **V\_AUX\_CCM**) to create an extremely high output impedance. + * **Output:** **V\_OUT\_CCM**. + * **Characteristics:** Provides the **highest accuracy** and regulation of the mirrored current, minimizing the impact of load voltage changes. + +--- + +### Outputs + +The circuit provides four outputs: + +* **V\_OUT\_VIN:** This output appears to be a buffered or regulated version of the original input **V\_IN**. +* **V\_OUT\_VCM:** Output from the Vanilla Current Mirror. +* **V\_OUT\_BCM:** Output from the Self-Biased Current Mirror. +* **V\_OUT\_CCM:** Output from the Regulated Cascode Current Mirror. + +--- + +Would you like a separate section for your Readme detailing the pin-out table and pin functionalities? + +### **Block: Vanilla Current Mirror (VCM)** +![](./design_proposal/_images/vcm.png) +A classical current mirror consists of two transistors: the first Q20 has its drain and gate connected (forming a diode-connected structure) and receives the input current, while the second transistor Q21 mirrors this current at its output. The output current is ideally a scaled replica of the input, determined by the ratio of the transistors' width-to-length (W/L) dimensions. + +### **Block: Self-biased Common Source Current Mirror** +![](./design_proposal/_images/sbcm.png) +The self-biased common-source current mirror uses a feedback mechanism to improve current stability and output impedance. Q22 receives the reference current through a diode connection, setting the gate voltage shared with Q24, which mirrors the current. Q23 and Q25, connected in a common-source configuration, form a self-biasing loop that regulates the source voltage of the upper transistors. This feedback stabilises the gate-source voltage, reducing output current variation and enhancing performance compared to a basic current mirror. + +### **Block: Regulated Cascoded Current Mirror** +![](./design_proposal/_images/rccm.png) +The regulated cascode current mirror shown uses an auxiliary biasing loop to significantly boost output impedance and current stability. Q26 and Q27 form a standard current mirror, while Q28 and Q30 act as cascode transistors, shielding the mirroring devices from output voltage swings. Q29 senses the drain voltage of Q28 and regulates it via Q31, creating a feedback loop that stabilizes the cascode node. This regulation ensures minimal variation in output current despite changes in output voltage, making the design ideal for precision analog applications demanding high output resistance and improved bias accuracy. + +### **Diagram: Top Integration and Expected Behaviour:** +![](./design_proposal/_images/tops.png) +![](./design_proposal/_images/sim.png) + + +### **Pinlist:** + +| Pin No (in Padframe): | Pin Name | Pin Type | Direction | Group | GF180mcu Cell | +|---|:----------|:-----------|:--------------|:---------------|:------------------------| +| 47| VSS | Ground | Bidirectional | A3 Mahowalders | gr180mcu_fd_io_dvss | +| 48| VCM_OUT | Analog | Output | A3 Mahowalders | gr180mcu_fd_io_asig_5p0 | +| 49| BCM_OUT | Analog | Output | A3 Mahowalders | gr180mcu_fd_io_asig_5p0 | +| 50| CCM_OUT | Analog | Output | A3 Mahowalders | gr180mcu_fd_io_asig_5p0 | +| 51| V_BIAS_IN | Analog | Output | A3 Mahowalders | gr180mcu_fd_io_asig_5p0 | +| 52| EN | Digital | Input | A3 Mahowalders | gr180mcu_fd_io_in_c | +| 53| V_AUX | Analog | Input | A3 Mahowalders | gr180mcu_fd_io_asig_5p0 | +| 54| V_IN | Analog | Input | A3 Mahowalders | gr180mcu_fd_io_asig_5p0 | +| 55| VSS | Ground | Bidirectional | A3 Mahowalders | gr180mcu_fd_io_dvss | +| 56| VDD_3V3 | 3V Power | Bidirectional | A3 Mahowalders | gr180mcu_fd_io_dvd | +#### **Layout:** + +![](./design_proposal/_images/l1.png) +![](./design_proposal/_images/l2.png) +![](./design_proposal/_images/l3.png) +![](./design_proposal/_images/l4.png) + + +### **Current Status:** +![](./design_proposal/_images/status.png) + +### Reference: + +1. Michal, Vratislav. "Regulated Cascode Current Mirror with Improved Voltage Swing." 2022 International Conference on Applied Electronics (AE). IEEE, 2022\. DOI : 10.1109/AE54730.2022.9920096 +2. Garde, M. Pilar, et al. "Wide-Swing Class AB Regulated Cascode Current Mirror." *2020 IEEE International Symposium on Circuits and Systems (ISCAS)*. IEEE, 2020\. +3. Pretl, Harald, and Matthias Eberlein. "Fifty nifty variations of two-transistor circuits: A tribute to the versatility of MOSFETs." *IEEE Solid-State Circuits Magazine* 13.3 (2021): 38-46 and *references therein* +4. GF180 PadFrame Document: [PADFrame \- Chipathon 2023](https://docs.google.com/presentation/d/12w4WBoleFAE4UePdoUf-bxsZR_BttwY3wknBPPJrEHE/edit?usp=sharing) diff --git a/blocks/composite/regulated_cascoded_cmirror/__init__.py b/blocks/composite/regulated_cascoded_cmirror/__init__.py new file mode 100644 index 00000000..57fc9cf9 --- /dev/null +++ b/blocks/composite/regulated_cascoded_cmirror/__init__.py @@ -0,0 +1,3 @@ +from glayout.flow.blocks.composite.regulated_cascoded_current_mirror.regulated_cascoded_current_mirror import CurrentMirror, generate_current_mirror_netlist,sky130_add_current_mirror_labels +from glayout.flow.blocks.elementary.cascode_common_source.cascode_common_source import cascode_common_source, cascode_common_source_netlist +from glayout.flow.blocks.elementary.cascode_common_source.cascode_common_source import regulated_cascode, regulated_cascode_netlist diff --git a/blocks/composite/regulated_cascoded_cmirror/bias.py b/blocks/composite/regulated_cascoded_cmirror/bias.py new file mode 100644 index 00000000..af9b97ce --- /dev/null +++ b/blocks/composite/regulated_cascoded_cmirror/bias.py @@ -0,0 +1,533 @@ +from glayout import MappedPDK, sky130, gf180 +from glayout import nmos, pmos, tapring, via_stack + +from gdsfactory.port import Port + +# from glayout.placement.two_transistor_interdigitized import two_nfet_interdigitized, two_pfet_interdigitized +from bias_base import biased_base +from gdsfactory import cell +from gdsfactory.component import Component +from gdsfactory.components import text_freetype, rectangle +from pathlib import Path + +from glayout.routing import c_route, L_route, straight_route +from glayout.spice.netlist import Netlist + +from glayout.util.port_utils import add_ports_perimeter, rename_ports_by_orientation +from glayout.util.comp_utils import ( + evaluate_bbox, + prec_center, + prec_ref_center, + align_comp_to_port, +) +from glayout.util.snap_to_grid import component_snap_to_grid +from typing import Optional, Union + +###### Only Required for IIC-OSIC Docker +import os +import subprocess + +# Run a shell, source .bashrc, then printenv +cmd = 'bash -c "source ~/.bashrc && printenv"' +result = subprocess.run(cmd, shell=True, text=True, capture_output=True) +env_vars = {} +for line in result.stdout.splitlines(): + if "=" in line: + key, value = line.split("=", 1) + env_vars[key] = value + +# Now, update os.environ with these +os.environ.update(env_vars) + + +# @validate_arguments +def generate_bias_netlist( + pdk, + prefix: str, + in_net: str, + en_net: str, + out_net: str, + show_netlist: bool = False, + *, + # NMOS (bottom block) sizing + n_w: float = 8.0, + n_l: float = 1.0, + n_m_ab: int = 10, # m for A and B devices + n_m_cd: int = 1, # m for C and D devices + n_dummy_m: int = 4, + include_n_dummy: bool = True, + # PMOS (left/right blocks) sizing + p_w: float = 10.0, + p_l: float = 2.0, + p_m_ab: int = 10, # m for A and B devices + p_m_cd: int = 1, # m for C and D devices + p_dummy_m: int = 4, + include_p_dummy: bool = True, + # Extra PFETs that tap internal nodes of the left/right blocks + tap_left: str = "VTBL", # "VTBL" or "VTBR" + tap_right: str = "VTBR", # "VTBL" or "VTBR" + tap_p_w: float = 10.0, + tap_p_l: float = 2.0, + tap_p_m: int = 1, +) -> Netlist: + """ + Flat netlist of the bias stage: + Pins: VSS VDD + + Topology: + LEFT (PFET block): in_net -> N1 + BOTTOM(NFET block): N1 -> N2 + RIGHT (PFET block): N2 -> out_net + + Each block uses the same 4-device (A,B,C,D) structure you provided, with bulks: + - PFET blocks: bulk = VDD + - NFET block: bulk = VSS + + Extra PFETs: + - XMPL: D = chosen internal node of LEFT block (VTBL_L or VTBR_L) + - XMPR: D = chosen internal node of RIGHT block (VTBL_R or VTBR_R) + - Gates = EN, Source/Bulk = VDD + """ + nmos_name = pdk.models["nfet"] + pmos_name = pdk.models["pfet"] + VSS, VDD = "VSS", "VDD" + + # Internal stitch nets between blocks + N1 = f"{prefix}_N1" + N2 = f"{prefix}_N2" + + # Helper to emit one block with A/B/C/D using your pattern, choosing model & bulk by type + # Assumes device node order = D G S B (change if your PDK differs). + def emit_block( + block_id: str, # "L", "B", "R" + in_node: str, + out_node: str, + kind: str, # "pfet" or "nfet" + ) -> tuple[str, str, str]: + VTBL = f"VTBL_{block_id}" + VTBR = f"VTBR_{block_id}" + if kind == "pfet": + model = pmos_name + w, l = p_w, p_l + m_ab, m_cd = p_m_ab, p_m_cd + bulk = VDD + include_dummy = include_p_dummy + dummy_m = p_dummy_m + else: + model = nmos_name + w, l = n_w, n_l + m_ab, m_cd = n_m_ab, n_m_cd + bulk = VSS + include_dummy = include_n_dummy + dummy_m = n_dummy_m + + lines = [] + # A: D=in, G=in, S=VTBL, B=bulk + lines.append(f"X{block_id}_A {in_node} {in_node} {VTBL} {bulk} {model} l={l} w={w} m={m_ab}") + # B: D=VTBL, G=VTBL, S=bulk, B=bulk + lines.append(f"X{block_id}_B {VTBL} {VTBL} {bulk} {bulk} {model} l={l} w={w} m={m_ab}") + # C: D=out, G=in, S=VTBR, B=bulk + lines.append(f"X{block_id}_C {out_node} {in_node} {VTBR} {bulk} {model} l={l} w={w} m={m_cd}") + # D: D=VTBR, G=VTBL, S=bulk, B=bulk + lines.append(f"X{block_id}_D {VTBR} {VTBL} {bulk} {bulk} {model} l={l} w={w} m={m_cd}") + if include_dummy: + lines.append(f"X{block_id}_DUMMY {bulk} {bulk} {bulk} {bulk} {model} l={l} w={w} m={dummy_m}") + + return ("\n".join(lines), VTBL, VTBR) + + # Build flat subckt text + top_pins = [in_net, VSS, VDD, out_net, en_net] + txt = [f".subckt {prefix} " + " ".join(top_pins)] + + # LEFT = PFET block + left_text, VTBL_L, VTBR_L = emit_block("L", in_node=in_net, out_node=N1, kind="pfet") + txt.append(left_text) + + # BOTTOM = NFET block + bottom_text, VTBL_B, VTBR_B = emit_block("B", in_node=N1, out_node=N2, kind="nfet") + txt.append(bottom_text) + + # RIGHT = PFET block + right_text, VTBL_R, VTBR_R = emit_block("R", in_node=N2, out_node=out_net, kind="pfet") + txt.append(right_text) + + # Choose which internal nodes to tap with the extra PFET drains + def pick_tap(which: str, VTBL_name: str, VTBR_name: str) -> str: + which = which.upper() + if which not in ("VTBL", "VTBR"): + raise ValueError("tap selection must be 'VTBL' or 'VTBR'") + return VTBL_name if which == "VTBL" else VTBR_name + + tap_left_node = pick_tap(tap_left, VTBL_L, VTBR_L) + tap_right_node = pick_tap(tap_left, VTBL_R, VTBR_R) + + # Extra PFETs (D G S B) → drains to taps, gate EN, source/bulk VDD + txt.append(f"XMPL {tap_left_node} {en_net} {VDD} {VDD} {pmos_name} l={tap_p_l} w={tap_p_w} m={tap_p_m}") + txt.append(f"XMPR {tap_right_node} {en_net} {VDD} {VDD} {pmos_name} l={tap_p_l} w={tap_p_w} m={tap_p_m}") + txt.append(f"Xextra_DUMMY {VDD} {VDD} {VDD} {VDD} {pmos_name} l={tap_p_l} w={tap_p_w} m={4}") + + txt.append(f".ends {prefix}") + source_netlist = "\n".join(txt) + + net = Netlist( + circuit_name=prefix, + nodes=top_pins, + source_netlist=source_netlist, + instance_format="X{name} {nodes} {circuit_name}", # kept for API symmetry + parameters={ + "nmos_model": nmos_name, "pmos_model": pmos_name, + "n_w": n_w, "n_l": n_l, "n_m_ab": n_m_ab, "n_m_cd": n_m_cd, + "p_w": p_w, "p_l": p_l, "p_m_ab": p_m_ab, "p_m_cd": p_m_cd, + "tap_p_w": tap_p_w, "tap_p_l": tap_p_l, "tap_p_m": tap_p_m, + }, + ) + + if show_netlist: + print(source_netlist) + + return net + + +# @validate_arguments +def bias_stage( + pdk: MappedPDK, + Width: float = 1, + Length: Optional[float] = 1, + num_cols: int = 1, + fingers: int = 1, + multipliers: int = 1, + type: Optional[str] = "pfet", + with_substrate_tap: Optional[bool] = False, + with_tie: Optional[bool] = True, + with_dummy: Optional[bool] = False, + tie_layers: tuple[str, str] = ("met2", "met1"), + show_netlist: Optional[bool] = False, + add_labels = True, + **kwargs, +) -> Component: + """An instantiable self biased casoded current mirror that returns a Component object.""" + + pdk.activate() + maxmet_sep = pdk.util_max_metal_seperation() + n_well_sep = maxmet_sep + psize = (0.35, 0.35) + + # Create the current mirror component + top_level = Component(name="bias_stage") + top_level.name = "bias_stage" + Length = Length if Length is not None else pdk.get_grule("poly")["min_width"] + top_ref = prec_ref_center(top_level) + + # ------------------------------------------------------------------------------------------------------------------------------------------------------------ + # BOTTOM BASE + # ------------------------------------------------------------------------------------------------------------------------------------------------------------ + + print("Creating base bottom of BIAS stage...") + base_bottom = biased_base( + pdk, + device="nfet", + width=(8, 8), + length=1, + fingers=(10,1), + with_substrate_tap=False, + with_tie=True, + ) + + + base_bottom_ref = prec_ref_center(base_bottom) + base_bottom_ref.move(top_ref.center) + top_level.add(base_bottom_ref) + + top_level.add_ports(base_bottom_ref.get_ports_list(), prefix="base_bottom_") + + core1 = base_bottom.copy().flatten() # so we don't mutate while measuring + + xmin1, xmax1 = core1.xmin, core1.xmax + ymin1, ymax1 = core1.ymin, core1.ymax + + viam2m3 = via_stack(pdk, "met2", "met3", centered=True) + viam1m2 = via_stack(pdk, "met1", "met2", centered=True) + + + # ------------------------------------------------------------------------------------------------------------------------------------------------------------ + # TOP LEFT BASE + # ------------------------------------------------------------------------------------------------------------------------------------------------------------ + print("Creating base top of BIAS stage...") + base_top = biased_base( + pdk, + device="pfet", + width=(10, 10), + length=2, + fingers=(10,1), + with_substrate_tap=False, + with_tie=True, + ) + + core2 = base_top.copy().flatten() # so we don't mutate while measuring + + xmin2, xmax2 = core2.xmin, core2.xmax + ymin2, ymax2 = core2.ymin, core2.ymax + + base_left_ref = prec_ref_center(base_top) + # base_left_ref.move(base_bottom_ref.center).movey( + # (ymax1-ymin1) + 4 * n_well_sep + 4*maxmet_sep + # ).movex(-(xmax1 - xmin1)/2 - (xmax2 - xmin2)/2 - 2*n_well_sep - 2*maxmet_sep) + base_left_ref.move(base_bottom_ref.center).movex(-(xmax1 - xmin1)/2 - (xmax2 - xmin2)/2 - 2*n_well_sep - 2*maxmet_sep) + top_level.add(base_left_ref) + + top_level.add_ports(base_left_ref.get_ports_list(), prefix="base_left_") + + # ------------------------------------------------------------------------------------------------------------------------------------------------------------ + # TOP RIGHT BASE + # ------------------------------------------------------------------------------------------------------------------------------------------------------------ + + + base_right_ref = prec_ref_center(base_top) + # base_right_ref.move(base_bottom_ref.center).movey( + # (ymax1-ymin1) + 4 * n_well_sep + 4*maxmet_sep + # ).movex((xmax1 - xmin1)/2 + (xmax2 - xmin2)/2 + 2*n_well_sep + 2*maxmet_sep) + base_right_ref.move(base_bottom_ref.center).movex((xmax1 - xmin1)/2 + (xmax2 - xmin2)/2 + 2*n_well_sep + 2*maxmet_sep) + top_level.add(base_right_ref) + + top_level.add_ports(base_right_ref.get_ports_list(), prefix="base_right_") + + + # ------------------------------------------------------------------------------------------------------------------------------------------------------------ + # INTERCONNECTIONS + # ------------------------------------------------------------------------------------------------------------------------------------------------------------ + + top_level << L_route( + pdk, base_left_ref.ports["OUT_top_met_S"], base_bottom_ref.ports["IN_top_met_W"] + ) + + top_level << L_route( + pdk, base_right_ref.ports["IN_top_met_S"], base_bottom_ref.ports["OUT_top_met_E"] + ) + + ## Adding Enable FETs + fet = pmos(pdk, width=10, length=2, fingers=1, with_tie=True, with_substrate_tap=False) + + fet_ref_left = prec_ref_center(fet) + + # fet_ref_right = prec_ref_center(fet) + + fet_ref_left.move(base_left_ref.ports["GATE_CONN_top_met_N"].center).movey(4*maxmet_sep + 1.5*evaluate_bbox(fet_ref_left)[1] + 2*n_well_sep) + top_level.add(fet_ref_left) + + top_level.add_ports(fet_ref_left.get_ports_list(), prefix="fet_left_") + + + dist_DS = ( + abs( + top_level.ports[f"fet_left_multiplier_0_drain_E"].center[0] + - top_level.ports[f"fet_left_multiplier_0_drain_W"].center[0] + ) + / 2 + ) + + drain_gate_via = top_level << viam2m3 + drain_gate_via.move(top_level.ports[f"fet_left_multiplier_0_drain_W"].center).movex(dist_DS) + + top_level << straight_route(pdk, drain_gate_via.ports["top_met_S"], base_left_ref.ports["GATE_CONN_top_met_N"], glayer1="met3", glayer2="met3") + + fet_ref_right = prec_ref_center(fet) + fet_ref_right.move(base_right_ref.ports["GATE_CONN_top_met_N"].center).movey(4*maxmet_sep + 1.5*evaluate_bbox(fet_ref_right)[1] + 2*n_well_sep) + top_level.add(fet_ref_right) + + top_level.add_ports(fet_ref_right.get_ports_list(), prefix="fet_right_") + + drain_gate_via = top_level << viam2m3 + drain_gate_via.move(top_level.ports[f"fet_right_multiplier_0_drain_W"].center).movex(dist_DS) + + top_level << straight_route(pdk, drain_gate_via.ports["top_met_S"], base_right_ref.ports["GATE_CONN_top_met_N"], glayer1="met3", glayer2="met3") + + ## DRC Problem + top_level << straight_route(pdk, fet_ref_left.ports["tie_S_top_met_S"], base_left_ref.ports["welltie_N_top_met_N"], width=6) + top_level << straight_route(pdk, fet_ref_right.ports["tie_S_top_met_S"], base_right_ref.ports["welltie_N_top_met_N"], width=6) + ###### + + # Create two m1m2 vias to connect the gates of the pfets + + gate_left_via = top_level << viam1m2 + gate_left_via.move((base_bottom_ref.ports["welltie_W_top_met_W"].center[0], fet_ref_left.ports["multiplier_0_gate_E"].center[1])) + + gate_right_via = top_level << viam1m2 + gate_right_via.move((base_bottom_ref.ports["welltie_E_top_met_E"].center[0], fet_ref_right.ports["multiplier_0_gate_W"].center[1])) + + top_level << straight_route(pdk, fet_ref_left.ports["multiplier_0_gate_E"], gate_left_via.ports["top_met_W"], glayer1="met2", glayer2="met2") + + top_level << straight_route(pdk, gate_left_via.ports["top_met_E"], gate_right_via.ports["top_met_W"], glayer1="met1", glayer2="met1") + + top_level << straight_route(pdk, gate_right_via.ports["top_met_E"], fet_ref_right.ports["multiplier_0_gate_W"], glayer1="met2", glayer2="met2") + + # Connect pfets sources to tie + + dist_ring = ( + abs( + fet_ref_left.ports["tie_W_top_met_W"].center[0] + - fet_ref_left.ports["tie_W_top_met_E"].center[0] + ) + / 2 + ) + + left_tie_source_via = top_level << viam1m2 + left_tie_source_via.move( + (fet_ref_left.ports["tie_W_top_met_E"].center[0], fet_ref_left.ports["multiplier_0_source_W"].center[1]) + ).movex(-dist_ring) + + + top_level << straight_route(pdk, fet_ref_left.ports["multiplier_0_source_W"], left_tie_source_via.ports["top_met_E"], glayer1="met2", glayer2="met2") + + right_tie_source_via = top_level << viam1m2 + right_tie_source_via.move( + (fet_ref_right.ports["tie_W_top_met_E"].center[0], fet_ref_right.ports["multiplier_0_source_W"].center[1]) + ).movex(-dist_ring) + + top_level << straight_route(pdk, fet_ref_right.ports["multiplier_0_source_W"], right_tie_source_via.ports["top_met_E"], glayer1="met2", glayer2="met2") + + # Connect fets ties to tie for VDD + top_level << straight_route(pdk, fet_ref_left.ports["tie_E_top_met_E"], fet_ref_right.ports["tie_W_top_met_W"], glayer1="met1", glayer2="met1", width=6) + + # Connect base left and right well ties for VDD + + top_level, rc_h = c_route_welltie_south(top_level, pdk, left_key="base_left", right_key="base_right", width = 10, drop=10.0, layer_name="met1") + + + top_level = component_snap_to_grid(rename_ports_by_orientation(top_level)) + + top_level.info["netlist"] = generate_bias_netlist( + pdk=pdk, + prefix="BIAS", + in_net="VIN", # Input drain connected to IREF + en_net="EN", # Auxiliary node + out_net="VOUT", + show_netlist=show_netlist, + ) + + if add_labels: + return add_cm_labels(top_level, pdk) + else: + if "VDD_port" not in top_level.ports: + top_level.add_port( + name="VDD_port", + port=Port( + name="VDD_port", + center=rc_h.center, + width=rc_h.width, + orientation=rc_h.orientation, + layer=rc_h.layer, # tuple + ), + ) + return top_level + + +def c_route_welltie_south( + top_level, + pdk, + left_key: str, # e.g. "base_left" + right_key: str, # e.g. "base_right" + width: float = 4.0, + drop: float = 6.0, + layer_name: str = "met1", # STRING for straight_route glayers +): + # Resolve real S-facing well-tie ports + pL_real = top_level.ports[f"{left_key}_welltie_S_top_met_S"] + pR_real = top_level.ports[f"{right_key}_welltie_S_top_met_S"] + + gl_tuple = pdk.get_glayer(layer_name) # tuple for Port.layer + gl_name = layer_name # string for straight_route arg + + # Snap coords + xL = pdk.snap_to_2xgrid(pL_real.center[0]) + xR = pdk.snap_to_2xgrid(pR_real.center[0]) + yL = pdk.snap_to_2xgrid(pL_real.center[1]) + yR = pdk.snap_to_2xgrid(pR_real.center[1]) + y_jog = pdk.snap_to_2xgrid(min(yL, yR) - abs(drop)) + + # Shadow endpoints (tuple-layer) + pL = Port("shadow_pL", center=(xL, yL), width=width, orientation=pL_real.orientation, layer=gl_tuple) + pR = Port("shadow_pR", center=(xR, yR), width=width, orientation=pR_real.orientation, layer=gl_tuple) + + # Vertical–corner ports at the jog (centered on verticals) + lc_v = Port("lc_v", center=(xL, y_jog), width=width, orientation=90, layer=gl_tuple) # faces north + rc_v = Port("rc_v", center=(xR, y_jog), width=width, orientation=270, layer=gl_tuple) # faces south + + # >>> Edge-aligned horizontal corners <<< + # horizontal start at *left edge* of left vertical: x_left_edge = xL - width/2 + lc_h = Port("lc_h", center=(pdk.snap_to_2xgrid(xL - width/2), y_jog), + width=width, orientation=0, layer=gl_tuple) # faces east + # horizontal end at *right edge* of right vertical: x_right_edge = xR + width/2 + rc_h = Port("rc_h", center=(pdk.snap_to_2xgrid(xR + width/2), y_jog), + width=width, orientation=180, layer=gl_tuple) # faces west + + top_level.add_port(name="VDD_port", port=rc_h) + + # Routes (all on layer_name) + top_level << straight_route(pdk, pL, lc_v, glayer2=gl_name, width=width) # left vertical + top_level << straight_route(pdk, lc_h, rc_h, glayer2=gl_name, width=width) # horizontal, edge-aligned + top_level << straight_route(pdk, rc_v, pR, glayer2=gl_name, width=width) # right vertical + + return top_level, rc_h + + +def add_cm_labels(cm_in: Component, pdk: MappedPDK) -> Component: + cm_in.unlock() + + psize = (0.35, 0.35) + move_info = [] + + # VIN + vinlabel = rectangle(layer=pdk.get_glayer("met2_pin"), size=psize, centered=True).copy() + vinlabel.add_label(text="VIN", layer=pdk.get_glayer("met2_label")) + move_info.append((vinlabel, cm_in.ports["base_left_IN_top_met_N"], None)) + + # EN + venlabel = rectangle(layer=pdk.get_glayer("met2_pin"), size=psize, centered=True).copy() + venlabel.add_label(text="EN", layer=pdk.get_glayer("met2_label")) + move_info.append((venlabel, cm_in.ports["fet_left_multiplier_0_gate_N"], None)) + + # VOUT + voutlabel = rectangle(layer=pdk.get_glayer("met2_pin"), size=psize, centered=True).copy() + voutlabel.add_label(text="VOUT", layer=pdk.get_glayer("met2_label")) + move_info.append((voutlabel, cm_in.ports["base_right_OUT_top_met_N"], None)) + + # VDD (well tie) + vddlabel = rectangle(layer=pdk.get_glayer("met1_pin"), size=psize, centered=True).copy() + vddlabel.add_label(text="VDD", layer=pdk.get_glayer("met1_label")) + move_info.append((vddlabel, cm_in.ports["fet_left_tie_N_top_met_N"], None)) + + # VSS (well tie) + vsslabel = rectangle(layer=pdk.get_glayer("met1_pin"), size=psize, centered=True).copy() + vsslabel.add_label(text="VSS", layer=pdk.get_glayer("met1_label")) + move_info.append((vsslabel, cm_in.ports["base_bottom_welltie_S_top_met_S"], None)) + + for comp, prt, alignment in move_info: + alignment = ("c", "b") if alignment is None else alignment + compref = align_comp_to_port(comp, prt, alignment=alignment) + cm_in.add(compref) + + return cm_in.flatten() + + +if __name__ == "__main__": + selected_pdk = gf180 + comp = bias_stage( + selected_pdk, num_cols=1, Width=10, Length=2, with_substrate_tap=False, show_netlist=False, add_labels=True + ) + + comp.name = "BIAS_STAGE" + comp.show() + # Write the current mirror layout to a GDS file + comp.write_gds("GDS/bias_stage.gds") + + # Generate the netlist for the current mirror + # print(comp.info["netlist"].generate_netlist()) + + # DRC Checks + drc_result = selected_pdk.drc_magic(comp, comp.name, output_file=Path("DRC/")) + + # LVS Checks + netgen_lvs_result = selected_pdk.lvs_netgen( + comp, comp.name, output_file_path=Path("LVS/"), copy_intermediate_files=True + ) + \ No newline at end of file diff --git a/blocks/composite/regulated_cascoded_cmirror/bias_base.py b/blocks/composite/regulated_cascoded_cmirror/bias_base.py new file mode 100644 index 00000000..dfb09947 --- /dev/null +++ b/blocks/composite/regulated_cascoded_cmirror/bias_base.py @@ -0,0 +1,634 @@ +from glayout import MappedPDK, gf180 +from glayout import nmos, pmos, tapring,via_stack, multiplier +from n_fets_fingers import n_transistor_clustered + +from glayout.spice.netlist import Netlist +from glayout.routing import c_route,L_route,straight_route + +from gdsfactory.cell import cell +from gdsfactory.component import Component, copy +from gdsfactory.components.rectangle import rectangle +from gdsfactory.routing.route_quad import route_quad +from gdsfactory.routing.route_sharp import route_sharp + +from gdsfactory.component import Component +from gdsfactory.component_reference import ComponentReference +from gdsfactory.cell import cell +from gdsfactory import Component +from gdsfactory.components import text_freetype, rectangle + +from glayout.util.comp_utils import evaluate_bbox, prec_center, align_comp_to_port, prec_ref_center,movex,movey +from glayout.util.snap_to_grid import component_snap_to_grid +from glayout.util.port_utils import set_port_orientation, rename_ports_by_orientation, create_private_ports, add_ports_perimeter, get_orientation +from itertools import product + +###### Only Required for IIC-OSIC Docker +import os +import subprocess +from pathlib import Path +# Run a shell, source .bashrc, then printenv +cmd = 'bash -c "source ~/.bashrc && printenv"' +result = subprocess.run(cmd, shell=True, text=True, capture_output=True) +env_vars = {} +for line in result.stdout.splitlines(): + if '=' in line: + key, value = line.split('=', 1) + env_vars[key] = value + +# Now, update os.environ with these +os.environ.update(env_vars) +############################################################################### +from typing import Optional, Union +import time + +def generate_biased_base_netlist( + pdk: MappedPDK, + prefix : str, + CM_size: tuple[float, float, int, int], # (width, length, multipliers, fingers) + drain_net_in: str, + drain_net_out: str, + transistor_type: str = "nfet", + bulk_net: str = None, + dummy: bool = True, + subckt_only: bool = False, + show_netlist: bool = False, + **kwargs, +) -> Netlist: + """Generate a netlist for a current mirror.""" + + if bulk_net is None: + bulk_net = "VDD" if transistor_type.lower() == "pfet" else "VSS" + + width = CM_size[0] + length = CM_size[1] + multipliers = CM_size[2] + fingers = CM_size[3] # Number of fingers of the interdigitized fets + mtop = fingers if subckt_only else 1 + # mtop = multipliers * 2 if dummy else multipliers # Double the multiplier to account for the dummies + + model_name = pdk.models[transistor_type.lower()] + + circuit_name = prefix + # Take only unique NET names + nodes = [drain_net_in, drain_net_out, bulk_net] + + source_netlist = f".subckt {circuit_name} {' '.join(nodes)}\n" + + # Proposed ground connection (commented) + # source_netlist += f"V{proposed_ground}1 ({proposed_ground} {bulk_net}) 0\n" + + # Generating four transistors (one on each side): + top_bottomleft_net = "VTBL" + top_bottomright_net = "VTBR" + + source_netlist += ( + f"X{prefix}_A {drain_net_in} {drain_net_in} {top_bottomleft_net} {bulk_net} " + f"{model_name} l={length} w={width} m={mtop}\n" + ) + source_netlist += ( + f"X{prefix}_B {top_bottomleft_net} {top_bottomleft_net} {bulk_net} {bulk_net} " + f"{model_name} l={length} w={width} m={mtop}\n" + ) + source_netlist += ( + f"X{prefix}_C {drain_net_out} {drain_net_in} {top_bottomright_net} {bulk_net} " + f"{model_name} l={length} w={width} m={1}\n" + ) + source_netlist += ( + f"X{prefix}_D {top_bottomright_net} {top_bottomleft_net} {bulk_net} {bulk_net} " + f"{model_name} l={length} w={width} m={1}\n" + ) + + if dummy: + source_netlist += ( + f"X{prefix}_DUMMY {bulk_net} {bulk_net} {bulk_net} {bulk_net} " + f"{model_name} l={length} w={width} m={4}\n" + ) + + source_netlist += ".ends " + circuit_name + + instance_format = "X{name} {nodes} {circuit_name} l={length} w={width} m={mult}" + + topnet = Netlist( + circuit_name=circuit_name, + nodes=nodes, + source_netlist=source_netlist, + instance_format=instance_format, + parameters={ + "model": model_name, + "width": width, + "length": length, + "mult": multipliers, + }, + ) + + if show_netlist: + generated_netlist_for_lvs = topnet.generate_netlist() + print("Generated netlist :\n", generated_netlist_for_lvs) + + file_path_local_storage = "./gen_netlist.txt" + try: + with open(file_path_local_storage, "w") as file: + file.write(generated_netlist_for_lvs) + except Exception: + print( + "Verify the file availability and type: ", + generated_netlist_for_lvs, + type(generated_netlist_for_lvs), + ) + + return topnet + +# @cell +def biased_base( + pdk: MappedPDK, + width: tuple[float,float] = (1,1), + length: Optional[float] = None, + fingers: tuple[int,int] = (2,2), + multipliers: tuple[int,int] = (1,1), + device: Optional[str] = 'nfet', + plus_minus_seperation: float = 0, + with_substrate_tap: Optional[bool] = False, + with_tie: Optional[bool] = True, + with_dummy: Union[bool, tuple[bool, bool]] = True, + tie_layers: tuple[str,str]=("met2","met1"), + show_netlist: Optional[bool] = False, + add_labels: Optional[bool] = False, + **kwargs + ) -> Component: + """An instantiable self biased casoded current mirror that returns a Component object.""" + + pdk.activate() + maxmet_sep = pdk.util_max_metal_seperation() + psize=(0.35,0.35) + + # Create the current mirror component + top_level = Component(name="Biased Base") + length = length if length is not None else pdk.get_grule('poly')['min_width'] + top_ref = prec_ref_center(top_level) + + if multipliers[1] > multipliers[0]: + multipliers = (multipliers[1],multipliers[0]) + + # Create the interdigitized fets + if device.lower() == "pfet" or device.lower() == "pmos": + currm1 = n_transistor_clustered( + pdk, + device="pfet", + numcols=fingers[0], + n_devices=1, + width=width[0], + # gate_route_extension=0, + length=length, + fingers=1, + dummy=(True, 0), + with_substrate_tap=False, + with_tie=False, + ) + currm2 = n_transistor_clustered( + pdk, + device="pfet", + numcols=fingers[1], + n_devices=1, + width=width[0], + # gate_route_extension=0, + length=length, + fingers=1, + dummy=(0, True), + with_substrate_tap=False, + with_tie=False, + ) + well, sdglayer = "nwell", "n+s/d" + elif device.lower() == "nfet" or device.lower() == "nmos": + currm1 = n_transistor_clustered( + pdk, + device="nfet", + numcols=fingers[0], + n_devices=1, + width=width[0], + # gate_route_extension=0, + length=length, + fingers=1, + dummy=(True, 0), + with_substrate_tap=False, + with_tie=False, + ) + currm2 = n_transistor_clustered( + pdk, + device="nfet", + numcols=fingers[1], + n_devices=1, + width=width[0], + # gate_route_extension=0, + length=length, + fingers=1, + dummy=(0, True), + with_substrate_tap=False, + with_tie=False, + ) + well, sdglayer = "pwell", "p+s/d" + else: + raise ValueError("type must be either nfet or pfet") + + # ------------------------------------------------------------------------- + # BOTTOM CURRENT MIRRORS + # ------------------------------------------------------------------------- + viam1m2 = via_stack(pdk, glayer1="met1", glayer2="met2", centered=True) + viam2m3 = via_stack(pdk, glayer1="met2", glayer2="met3", centered=True) + + core1 = currm1.copy().flatten() # so we don't mutate while measuring + + xmin1, xmax1 = core1.xmin, core1.xmax + ymin1, ymax1 = core1.ymin, core1.ymax + + core2 = currm2.copy().flatten() # so we don't mutate while measuring + + xmin2, xmax2 = core2.xmin, core2.xmax + ymin2, ymax2 = core2.ymin, core2.ymax + + sep = pdk.get_grule(sdglayer)["min_separation"] + + a_botl = prec_ref_center(currm1) + top_level.add(a_botl) + a_botl.move(top_ref.center) + top_level.add_ports(a_botl.get_ports_list(), prefix="bottom_left_") + + b_botr = prec_ref_center(currm2) + top_level.add(b_botr) + # b_botr.move(top_ref.center).movex(evaluate_bbox(a_botl)[0]+maxmet_sep) + b_botr.move(a_botl.center).movex((xmax1 - xmin1)/2 + (xmax2 - xmin2)/2 + 2*maxmet_sep + 2*sep) + top_level.add_ports(b_botr.get_ports_list(), prefix="bottom_right_") + + # Connect gates of the two bottom blocks + top_level << straight_route(pdk, top_level.ports["bottom_left_A_gate_E"], top_level.ports["bottom_right_A_gate_W"], glayer1="met2", glayer2="met2") + + dist_DS = ( + abs( + top_level.ports[f"bottom_left_A_0_drain_E"].center[0] + - top_level.ports[f"bottom_left_A_0_drain_W"].center[0] + ) + / 2 + ) + + dist_GS = ( + abs( + top_level.ports[f"bottom_left_A_0_gate_E"].center[0] + - top_level.ports[f"bottom_left_A_0_gate_W"].center[0] + ) + / 2 + ) + + # ------------------------------------------------------------------------- + # TOP CURRENT MIRRORS + # ------------------------------------------------------------------------- + + a_topl = prec_ref_center(currm1) + top_level.add(a_topl) + a_topl.move(a_botl.center).movey((ymax1 - ymin1) + 2*maxmet_sep + 2*sep) + top_level.add_ports(a_topl.get_ports_list(), prefix="top_left_") + + b_topr = prec_ref_center(currm2) + top_level.add(b_topr) + b_topr.move(a_topl.center).movex((xmax1 - xmin1)/2 + (xmax2 - xmin2)/2 + 2*maxmet_sep + 2*sep) + top_level.add_ports(b_topr.get_ports_list(), prefix="top_right_") + + # Connect gates of the two top blocks + top_level << straight_route(pdk, top_level.ports["top_left_A_gate_E"], top_level.ports["top_right_A_gate_W"], glayer1="met2", glayer2="met2") + + # ------------------------------------------------------------------------- + # CONNECT BOTTOM AND TOP BLOCKS + # ------------------------------------------------------------------------- + + dist_SS = ( + abs( + top_level.ports[f"top_left_A_{0}_drain_W"].center[0] + - top_level.ports[f"top_left_A_{1}_source_E"].center[0] + ) + ) + + if device == "nfet": + for idx in range(fingers[0]): + topS = top_level << viam2m3 + topS.move(top_level.ports[f"top_left_A_{idx}_source_W"].center).movex(dist_DS) + + bottomD = top_level << viam2m3 + bottomD.move(top_level.ports[f"bottom_left_A_{idx}_drain_W"].center).movex(dist_DS) + + # Connect drain and gate of the left blocks + if idx != fingers[0]-1: # Skip last finger to avoid shorting the gate to drain + top_drain_to_gate = top_level << viam2m3 + top_drain_to_gate.move(top_level.ports[f"top_left_A_{idx}_drain_W"].center).movex(dist_SS/2) + + top_gate = top_level << viam2m3 + top_gate.move((top_drain_to_gate.center[0], top_level.ports[f"top_left_A_{idx}_gate_W"].center[1])) + + top_level << straight_route(pdk, top_drain_to_gate.ports["top_met_S"], top_gate.ports["top_met_N"], glayer1="met3", glayer2="met3") + + bottom_drain_to_gate = top_level << viam2m3 + bottom_drain_to_gate.move(top_level.ports[f"bottom_left_A_{idx}_gate_W"].center).movex(dist_GS) + + top_level << straight_route(pdk, topS.ports["top_met_S"], bottom_drain_to_gate.ports["top_met_N"], glayer1="met3", glayer2="met3") + + for idx in range(fingers[1]): + topS = top_level << viam2m3 + topS.move(top_level.ports[f"top_right_A_{idx}_source_W"].center).movex(dist_DS) + + bottomD = top_level << viam2m3 + bottomD.move(top_level.ports[f"bottom_right_A_{idx}_drain_W"].center).movex(dist_DS) + top_level << straight_route(pdk, topS.ports["top_met_S"], bottomD.ports["top_met_N"], glayer1="met3", glayer2="met3") + elif device == "pfet": + + for idx in range(fingers[0]): + topD = top_level << viam2m3 + topD.move(top_level.ports[f"top_left_A_{idx}_drain_W"].center).movex(dist_DS) + + bottomS = top_level << viam2m3 + bottomS.move(top_level.ports[f"bottom_left_A_{idx}_source_W"].center).movex(dist_DS) + top_level << straight_route(pdk, topD.ports["top_met_S"], bottomS.ports["top_met_N"], glayer1="met3", glayer2="met3") + + # Connect drain and gate of the left blocks + if idx != fingers[0]-1: # Skip last finger to avoid shorting the gate to drain + top_drain_to_gate = top_level << viam2m3 + top_drain_to_gate.move(top_level.ports[f"bottom_left_A_{idx}_drain_W"].center).movex(dist_SS/2) + + top_gate = top_level << viam2m3 + top_gate.move((top_drain_to_gate.center[0], top_level.ports[f"bottom_left_A_{idx}_gate_W"].center[1])) + + top_level << straight_route(pdk, top_drain_to_gate.ports["top_met_S"], top_gate.ports["top_met_N"], glayer1="met3", glayer2="met3") + + bottom_drain_to_gate = top_level << viam2m3 + bottom_drain_to_gate.move(top_level.ports[f"top_left_A_{idx}_gate_W"].center).movex(dist_GS) + + if idx == 0: + top_level.add_ports(bottom_drain_to_gate.get_ports_list(), prefix=f"GATE_CONN_") + + for idx in range(fingers[1]): + topD = top_level << viam2m3 + topD.move(top_level.ports[f"top_right_A_{idx}_drain_W"].center).movex(dist_DS) + + bottomS = top_level << viam2m3 + bottomS.move(top_level.ports[f"bottom_right_A_{idx}_source_W"].center).movex(dist_DS) + top_level << straight_route(pdk, topD.ports["top_met_S"], bottomS.ports["top_met_N"], glayer1="met3", glayer2="met3") + + # ------------------------------------------------------------------------------------------------------------------------------------------------------------ + # TAP RING + # ------------------------------------------------------------------------------------------------------------------------------------------------------------ + + snap = pdk.snap_to_2xgrid + + core = top_level.copy() # so we don't mutate while measuring + core_flat = core.flatten() # include all placed children + + xmin, xmax = core_flat.xmin, core_flat.xmax + ymin, ymax = core_flat.ymin, core_flat.ymax + + core_w = xmax - xmin + core_h = ymax - ymin + + cx = snap((xmin + xmax) / 2) + cy = snap((ymin + ymax) / 2) + + # Adding tapring + if with_tie: + tap_separation = max( + maxmet_sep, pdk.get_grule("active_diff", "active_tap")["min_separation"] + ) + tap_separation += pdk.get_grule(sdglayer, "active_tap")["min_enclosure"] + tap_encloses = ( + (snap(4 * tap_separation + core_w)), + (snap(4 * tap_separation + core_h)), + ) + tie_ref = top_level << tapring( + pdk, + enclosed_rectangle=tap_encloses, + sdlayer=sdglayer, + horizontal_glayer=tie_layers[0], + vertical_glayer=tie_layers[1], + ) + tie_ref.move((cx, cy)) + top_level.add_ports(tie_ref.get_ports_list(), prefix="welltie_") + + # add pwell + top_level.add_padding( + default=pdk.get_grule(well, "active_tap")["min_enclosure"], + layers=[pdk.get_glayer(well)], + ) + top_level = add_ports_perimeter(top_level, layer=pdk.get_glayer(well), prefix="well_") + + # add the substrate tap if specified + if with_substrate_tap: + substrate_tap_separation = pdk.get_grule("dnwell", "active_tap")[ + "min_separation" + ] + substrate_tap_enclosure = ( + (snap(4 * substrate_tap_separation + core_w)), + (snap(4 * substrate_tap_separation + core_h)), + ) + ringtoadd = tapring( + pdk, + enclosed_rectangle=substrate_tap_enclosure, + sdlayer=sdglayer, + horizontal_glayer=tie_layers[0], + vertical_glayer=tie_layers[1], + ) + substrate_tap_ring_ref = top_level << ringtoadd + substrate_tap_ring_ref.move((cx, cy)) + top_level.add_ports( + substrate_tap_ring_ref.get_ports_list(), prefix="substrate_tap_" + ) + + # Connect well ties to well + try: + top_level << straight_route( + pdk, + top_level.ports["top_left_A_0_dummy_L_gsdcon_top_met_W"], + top_level.ports["welltie_W_top_met_W"], + glayer2="met1", + ) + + top_level << straight_route( + pdk, + top_level.ports[ + f"top_right_A_0_dummy_R_gsdcon_top_met_E" + ], + top_level.ports["welltie_E_top_met_E"], + glayer2="met1", + ) + + top_level << straight_route( + pdk, + top_level.ports["bottom_left_A_0_dummy_L_gsdcon_top_met_W"], + top_level.ports["welltie_W_top_met_W"], + glayer2="met1", + ) + + top_level << straight_route( + pdk, + top_level.ports[ + f"bottom_right_A_0_dummy_R_gsdcon_top_met_E" + ], + top_level.ports["welltie_E_top_met_E"], + glayer2="met1", + ) + + except KeyError: + pass + + # ------------------------------------------------------------------------- + # CONNECT SOURCES TO TIE RING + # ------------------------------------------------------------------------- + + dist_ring = ( + abs( + top_level.ports["welltie_W_top_met_W"].center[0] + - top_level.ports["welltie_W_top_met_E"].center[0] + ) + / 2 + ) + + if device == "nfet": + bottomA_source_via = top_level << viam1m2 + bottomA_source_via.move( + (top_level.ports["welltie_W_top_met_E"].center[0], top_level.ports["bottom_left_A_0_source_W"].center[1]) + ).movex(-dist_ring) + + top_level << straight_route( + pdk, + top_level.ports["bottom_left_A_0_source_W"], + bottomA_source_via.ports["top_met_W"], + glayer2="met2", + ) + + bottomA_source_via = top_level << viam1m2 + bottomA_source_via.move( + (top_level.ports["welltie_E_top_met_E"].center[0], top_level.ports["bottom_right_A_0_source_E"].center[1]) + ).movex(-dist_ring) + + top_level << straight_route( + pdk, + top_level.ports["bottom_right_A_0_source_E"], + bottomA_source_via.ports["top_met_W"], + glayer2="met2", + ) + elif device == "pfet": + bottomA_source_via = top_level << viam1m2 + bottomA_source_via.move( + (top_level.ports["welltie_W_top_met_E"].center[0], top_level.ports["top_left_A_0_source_W"].center[1]) + ).movex(-dist_ring) + + top_level << straight_route( + pdk, + top_level.ports["top_left_A_0_source_W"], + bottomA_source_via.ports["top_met_W"], + glayer2="met2", + ) + + bottomA_source_via = top_level << viam1m2 + bottomA_source_via.move( + (top_level.ports["welltie_E_top_met_E"].center[0], top_level.ports["top_right_A_0_source_E"].center[1]) + ).movex(-dist_ring) + + top_level << straight_route( + pdk, + top_level.ports["top_right_A_0_source_E"], + bottomA_source_via.ports["top_met_W"], + glayer2="met2", + ) + + # ------------------------------------------------------------------------------------------------------------------------------------------------------------ + # CONNECT DRAINS TO OTHER STAGES + # ------------------------------------------------------------------------------------------------------------------------------------------------------------ + + if device == "nfet": + in_via = top_level << viam1m2 + in_via.move((top_level.ports["welltie_W_top_met_W"].center[0], top_level.ports["top_left_A_0_drain_W"].center[1])).movex(-dist_DS) + top_level.add_ports(in_via.get_ports_list(), prefix=f"IN_") + + out_via = top_level << viam1m2 + out_via.move((top_level.ports["welltie_E_top_met_E"].center[0], top_level.ports["top_right_A_0_drain_E"].center[1])).movex(dist_DS) + top_level.add_ports(out_via.get_ports_list(), prefix=f"OUT_") + + top_level << straight_route(pdk, top_level.ports["IN_top_met_E"], top_level.ports["top_left_A_0_drain_W"], glayer1="met2", glayer2="met2") + top_level << straight_route(pdk, top_level.ports["OUT_top_met_W"], top_level.ports["top_right_A_0_drain_E"], glayer1="met2", glayer2="met2") + + else: # pfet + in_via = top_level << viam1m2 + in_via.move((top_level.ports["welltie_W_top_met_W"].center[0], top_level.ports["bottom_left_A_0_drain_W"].center[1])).movex(-dist_DS) + top_level.add_ports(in_via.get_ports_list(), prefix=f"IN_") + + out_via = top_level << viam1m2 + out_via.move((top_level.ports["welltie_E_top_met_E"].center[0], top_level.ports["bottom_right_A_0_drain_E"].center[1])).movex(dist_DS) + top_level.add_ports(out_via.get_ports_list(), prefix=f"OUT_") + + top_level << straight_route(pdk, top_level.ports["IN_top_met_E"], top_level.ports["bottom_left_A_0_drain_W"], glayer1="met2", glayer2="met2") + top_level << straight_route(pdk, top_level.ports["OUT_top_met_W"], top_level.ports["bottom_right_A_0_drain_E"], glayer1="met2", glayer2="met2") + + # ------------------------------------------------------------------------- + # ADD IN/OUT PORTS + # ------------------------------------------------------------------------- + + + top_level = component_snap_to_grid(rename_ports_by_orientation(top_level)) + + top_level.info["netlist"] = generate_biased_base_netlist( + pdk=pdk, + prefix="BIASED_BASE", + CM_size=(width[0], length, 1, fingers[0]), # (width, length, multipliers, fingers) + transistor_type=device, + drain_net_in="VIN", # Input drain connected to IREF + drain_net_out="VOUT", + bulk_net="VSS" if device.lower() == "nfet" else "VDD", + subckt_only=True, + show_netlist=show_netlist, + ) + + if add_labels: + return add_cm_labels(top_level, pdk, bulk="VDD" if device.lower() == "pfet" else "VSS") + else: + return top_level + + +def add_cm_labels(cm_in: Component, pdk: MappedPDK, bulk: str) -> Component: + cm_in.unlock() + + psize = (0.35, 0.35) + move_info = [] + + # VIN + vinlabel = rectangle(layer=pdk.get_glayer("met2_pin"), size=psize, centered=True).copy() + vinlabel.add_label(text="VIN", layer=pdk.get_glayer("met2_label")) + move_info.append((vinlabel, cm_in.ports["IN_top_met_N"], None)) + + # VOUT + voutlabel = rectangle(layer=pdk.get_glayer("met2_pin"), size=psize, centered=True).copy() + voutlabel.add_label(text="VOUT", layer=pdk.get_glayer("met2_label")) + move_info.append((voutlabel, cm_in.ports["OUT_top_met_N"], None)) + + # BULK (well tie) + vddlabel = rectangle(layer=pdk.get_glayer("met1_pin"), size=psize, centered=True).copy() + vddlabel.add_label(text=bulk, layer=pdk.get_glayer("met1_label")) + move_info.append((vddlabel, cm_in.ports["welltie_N_top_met_N"], None)) + + for comp, prt, alignment in move_info: + alignment = ("c", "b") if alignment is None else alignment + compref = align_comp_to_port(comp, prt, alignment=alignment) + cm_in.add(compref) + + return cm_in.flatten() + +if __name__ == "__main__": + selected_pdk = gf180 + + comp =biased_base(selected_pdk,width=(8,8), length=1, multipliers=(1,1),fingers=(10,1), device="pfet", with_tie=True, add_labels=True, show_netlist=True) + # comp.pprint_ports() + # comp =add_lvcm_labels(comp,selected_pdk) + comp.name = "BB" + comp.show() + + comp.write_gds("./BB.gds") + + drc_result = selected_pdk.drc_magic(comp, comp.name, output_file=Path("DRC/")) + + + netgen_lvs_result = selected_pdk.lvs_netgen( + comp, comp.name, output_file_path=Path("LVS/"), copy_intermediate_files=True + ) diff --git a/blocks/composite/regulated_cascoded_cmirror/chip_lvs.py b/blocks/composite/regulated_cascoded_cmirror/chip_lvs.py new file mode 100644 index 00000000..95fa50a9 --- /dev/null +++ b/blocks/composite/regulated_cascoded_cmirror/chip_lvs.py @@ -0,0 +1,30 @@ +from pathlib import Path +from typing import Optional, Union +import os +import re +import subprocess + + +from glayout import MappedPDK, sky130, gf180 + + +###### Only Required for IIC-OSIC Docker +# Run a shell, source .bashrc, then printenv +cmd = 'bash -c "source ~/.bashrc && printenv"' +result = subprocess.run(cmd, shell=True, text=True, capture_output=True) +env_vars = {} +for line in result.stdout.splitlines(): + if "=" in line: + key, value = line.split("=", 1) + env_vars[key] = value +os.environ.update(env_vars) + +selected_pdk = gf180 + +# DRC +drc_result = selected_pdk.drc_magic("gds/top_new.gds", "TOP", output_file=Path("DRC/")) + +# LVS +netgen_lvs_result = selected_pdk.lvs_netgen( + "gds/top_new.gds", "TOP", netlist="gds/top_new.spice", output_file_path=Path("LVS/"), copy_intermediate_files=True +) \ No newline at end of file diff --git a/blocks/composite/regulated_cascoded_cmirror/cm_gl_prim.py b/blocks/composite/regulated_cascoded_cmirror/cm_gl_prim.py new file mode 100644 index 00000000..0983d543 --- /dev/null +++ b/blocks/composite/regulated_cascoded_cmirror/cm_gl_prim.py @@ -0,0 +1,53 @@ +from glayout import MappedPDK, sky130,gf180 +from glayout import nmos, pmos, tapring,via_stack + +from glayout.placement.two_transistor_interdigitized import two_nfet_interdigitized, two_pfet_interdigitized +from gdsfactory import cell +from gdsfactory.component import Component +from gdsfactory.components import text_freetype, rectangle + +from glayout.routing import c_route,L_route,straight_route +from glayout.spice.netlist import Netlist + +from glayout.util.port_utils import add_ports_perimeter,rename_ports_by_orientation +from glayout.util.comp_utils import evaluate_bbox, prec_center, prec_ref_center, align_comp_to_port +from glayout.util.snap_to_grid import component_snap_to_grid +from typing import Optional, Union + +###### Only Required for IIC-OSIC Docker +import os +import subprocess +from typing import ClassVar, Optional, Any, Union, Literal, Iterable, TypedDict +from pathlib import Path +# Run a shell, source .bashrc, then printenv +cmd = 'bash -c "source ~/.bashrc && printenv"' +result = subprocess.run(cmd, shell=True, text=True, capture_output=True) +env_vars = {} +for line in result.stdout.splitlines(): + if '=' in line: + key, value = line.split('=', 1) + env_vars[key] = value + +# Now, update os.environ with these +os.environ.update(env_vars) + +import sys +sys.path.append('../../elementary/current_mirror/') + +from current_mirror import current_mirror,add_cm_labels + +comp = current_mirror(gf180) +# comp.pprint_ports() +comp = add_cm_labels(comp,gf180) +comp.name = "CM" +comp.show() +#print(comp.info['netlist'].generate_netlist()) +print("...Running DRC...") +drc_result = gf180.drc_magic(comp, "CM") +## Klayout DRC +#drc_result = sky130.drc(comp)\n + + + +print("...Running LVS...") +lvs_res=gf180.lvs_netgen(comp, "CM") \ No newline at end of file diff --git a/blocks/composite/regulated_cascoded_cmirror/cm_rc.py b/blocks/composite/regulated_cascoded_cmirror/cm_rc.py new file mode 100644 index 00000000..3936c5f7 --- /dev/null +++ b/blocks/composite/regulated_cascoded_cmirror/cm_rc.py @@ -0,0 +1,612 @@ +from pathlib import Path +from typing import Optional, Union + +import os +import subprocess + +from glayout import MappedPDK, sky130, gf180 +from glayout import nmos, pmos, tapring, via_stack +from glayout.placement.two_transistor_interdigitized import ( + two_nfet_interdigitized, + two_pfet_interdigitized, +) +from n_fets_interdigitized import n_transistor_interdigitized +from gdsfactory import cell +from gdsfactory.component import Component +from gdsfactory.components import text_freetype, rectangle +from glayout.routing import c_route, L_route, straight_route +from glayout.spice.netlist import Netlist +from glayout.util.port_utils import add_ports_perimeter, rename_ports_by_orientation +from glayout.util.comp_utils import ( + evaluate_bbox, + prec_center, + prec_ref_center, + align_comp_to_port, +) +from glayout.util.snap_to_grid import component_snap_to_grid + +###### Only Required for IIC-OSIC Docker +# Run a shell, source .bashrc, then printenv +cmd = 'bash -c "source ~/.bashrc && printenv"' +result = subprocess.run(cmd, shell=True, text=True, capture_output=True) +env_vars = {} +for line in result.stdout.splitlines(): + if "=" in line: + key, value = line.split("=", 1) + env_vars[key] = value + +# Now, update os.environ with these +os.environ.update(env_vars) + + +# @validate_arguments +def generate_regulated_current_mirror_netlist( + pdk: MappedPDK, + prefix: str, + instance_name: str, + CM_size: tuple[float, float, int], # (width, length, multipliers) + drain_net_in: str, + drain_net_aux: str, + drain_net_out: str, + source_net_in: str, + source_net_out: str, + gate_net: str, + transistor_type: str = "nfet", + bulk_net: str = None, + proposed_ground: str = None, # Proposed ground net + dummy: bool = True, + subckt_only: bool = False, + show_netlist: bool = False, + **kwargs, +) -> Netlist: + """Generate a netlist for a regulated cascode current mirror.""" + + if bulk_net is None: + bulk_net = "VDD" if transistor_type.lower() == "pfet" else "VSS" + + width = CM_size[0] + length = CM_size[1] + multipliers = CM_size[2] + fingers = CM_size[3] # Number of fingers of the interdigitized fets + mtop = multipliers * fingers if subckt_only else 1 + # mtop = multipliers * 2 if dummy else multipliers # Double the multiplier to account for the dummies + + model_name = pdk.models[transistor_type.lower()] + + circuit_name = prefix + # Take only unique NET names + nodes = [drain_net_in, drain_net_aux, drain_net_out, bulk_net] + + source_netlist = f".subckt {circuit_name} {' '.join(nodes)}\n" + + # Proposed ground connection (commented) + # source_netlist += f"V{proposed_ground}1 ({proposed_ground} {bulk_net}) 0\n" + + # Generating six transistors: + B_source_C_drain_net = "VBC" + E_source_D_drain_net = "VED" + + source_netlist += ( + f"X{prefix}_A {drain_net_aux} {B_source_C_drain_net} {bulk_net} {bulk_net} " + f"{model_name} l={length} w={width} m={mtop}\n" + ) + source_netlist += ( + f"X{prefix}_B {drain_net_in} {drain_net_aux} {B_source_C_drain_net} {bulk_net} " + f"{model_name} l={length} w={width} m={mtop}\n" + ) + source_netlist += ( + f"X{prefix}_C {B_source_C_drain_net} {drain_net_in} {bulk_net} {bulk_net} " + f"{model_name} l={length} w={width} m={mtop}\n" + ) + source_netlist += ( + f"X{prefix}_D {E_source_D_drain_net} {drain_net_in} {bulk_net} {bulk_net} " + f"{model_name} l={length} w={width} m={mtop}\n" + ) + source_netlist += ( + f"X{prefix}_E {drain_net_out} {drain_net_aux} {E_source_D_drain_net} {bulk_net} " + f"{model_name} l={length} w={width} m={mtop}\n" + ) + source_netlist += ( + f"X{prefix}_F {drain_net_aux} {E_source_D_drain_net} {bulk_net} {bulk_net} " + f"{model_name} l={length} w={width} m={mtop}\n" + ) + + if dummy: + source_netlist += ( + f"X{prefix}_DUMMY {bulk_net} {bulk_net} {bulk_net} {bulk_net} " + f"{model_name} l={length} w={width} m={6}\n" + ) + + source_netlist += ".ends " + circuit_name + + instance_format = "X{name} {nodes} {circuit_name} l={length} w={width} m={mult}" + + topnet = Netlist( + circuit_name=circuit_name, + nodes=nodes, + source_netlist=source_netlist, + instance_format=instance_format, + parameters={ + "model": model_name, + "width": width, + "length": length, + "mult": multipliers, + }, + ) + + if show_netlist: + generated_netlist_for_lvs = topnet.generate_netlist() + print("Generated netlist :\n", generated_netlist_for_lvs) + + file_path_local_storage = "./gen_netlist.txt" + try: + with open(file_path_local_storage, "w") as file: + file.write(generated_netlist_for_lvs) + except Exception: + print( + "Verify the file availability and type: ", + generated_netlist_for_lvs, + type(generated_netlist_for_lvs), + ) + + return topnet + + +# @validate_arguments +def regulated_cascode_current_mirror( + pdk: MappedPDK, + Width: float = 1, + Length: Optional[float] = None, + num_cols: int = 2, + fingers: int = 1, + type: Optional[str] = "nfet", + with_substrate_tap: Optional[bool] = False, + with_tie: Optional[bool] = True, + with_dummy: Optional[bool] = True, + tie_layers: tuple[str, str] = ("met2", "met1"), + show_netlist: Optional[bool] = False, + add_labels = True, + **kwargs, +) -> Component: + """An instantiable self-biased cascoded current mirror that returns a Component.""" + + pdk.activate() + maxmet_sep = pdk.util_max_metal_seperation() + psize = (0.35, 0.35) + + # Create the current mirror component + top_level = Component(name="RCurrentMirror") + Length = Length if Length is not None else pdk.get_grule("poly")["min_width"] + top_ref = prec_ref_center(top_level) + + # Create the interdigitized FETs + if type.lower() == "pfet" or type.lower() == "pmos": + currm = n_transistor_interdigitized( + pdk, + device="pfet", + numcols=num_cols, + n_devices=2, + width=Width, + length=Length, + fingers=fingers, + with_substrate_tap=False, + with_tie=False, + ) + well, sdglayer = "nwell", "n+s/d" + elif type.lower() == "nfet" or type.lower() == "nmos": + currm = n_transistor_interdigitized( + pdk, + device="nfet", + numcols=num_cols, + n_devices=2, + width=Width, + length=Length, + fingers=fingers, + with_substrate_tap=False, + with_tie=False, + ) + well, sdglayer = "pwell", "p+s/d" + else: + raise ValueError("type must be either nfet or pfet") + + # Add the interdigitized FETs to the current mirror top component + bottom_currm_ref = prec_ref_center(currm) + mid_currm_ref = prec_ref_center(currm) + top_currm_ref = prec_ref_center(currm) + + # ------------------------------------------------------------------------- + # BOTTOM CURRENT MIRRORS + # ------------------------------------------------------------------------- + top_level.add(bottom_currm_ref) + bottom_currm_ref.move(top_ref.center) + top_level.add_ports(bottom_currm_ref.get_ports_list(), prefix="currm_bottom_") + + dist_DS = ( + abs( + top_level.ports["currm_bottom_A_0_drain_E"].center[0] + - top_level.ports["currm_bottom_A_0_drain_W"].center[0] + ) + / 2 + ) + dist_GS = ( + abs( + top_level.ports["currm_bottom_A_0_gate_E"].center[0] + - top_level.ports["currm_bottom_A_0_gate_W"].center[0] + ) + / 2 + ) + + viam2m3 = via_stack(pdk, "met2", "met3", centered=True) + viam1m2 = via_stack(pdk, "met1", "met2", centered=True) + + bottomBdrain_via = top_level << viam2m3 + bottomBdrain_via.move(top_level.ports["currm_bottom_B_1_drain_E"].center).movex(-dist_DS) + + bottomA_gate_via = top_level << viam2m3 + bottomA_gate_via.move( + (bottomBdrain_via.center[0], top_level.ports["currm_bottom_A_0_gate_W"].center[1]) + ) + + top_level << straight_route( + pdk, bottomBdrain_via.ports["bottom_met_N"], bottomA_gate_via.ports["bottom_met_S"], glayer1="met3", glayer2="met3" + ) + + # ------------------------------------------------------------------------- + # MIDDLE CURRENT MIRRORS + # ------------------------------------------------------------------------- + top_level.add(mid_currm_ref) + mid_currm_ref.move(top_ref.center).movey(evaluate_bbox(bottom_currm_ref)[1] + maxmet_sep) + top_level.add_ports(mid_currm_ref.get_ports_list(), prefix="currm_middle_") + + # ------------------------------------------------------------------------- + # TOP CURRENT MIRRORS + # ------------------------------------------------------------------------- + top_level.add(top_currm_ref) + top_currm_ref.move(mid_currm_ref.center).movey(evaluate_bbox(mid_currm_ref)[1] + maxmet_sep) + top_level.add_ports(top_currm_ref.get_ports_list(), prefix="currm_top_") + + topAdrain_via = top_level << viam2m3 + topAdrain_via.move(top_level.ports["currm_top_A_0_drain_W"].center).movex(dist_DS) + + topB_gate_via = top_level << viam2m3 + topB_gate_via.move((topAdrain_via.center[0], top_level.ports["currm_top_B_0_gate_W"].center[1])) + + top_level << straight_route( + pdk, topAdrain_via.ports["top_met_N"], topB_gate_via.ports["top_met_S"], glayer2="met3" + ) + + # ------------------------------------------------------------------------- + # INTERCONNECTIONS + # ------------------------------------------------------------------------- + bottomB_gate_via = top_level << viam2m3 + bottomB_gate_via.move((top_level.ports["currm_bottom_B_0_gate_W"].center)).movex(dist_GS) + + middleB_drain_via = top_level << viam2m3 + middleB_drain_via.move(top_level.ports["currm_middle_B_0_drain_E"].center).movex(-dist_DS) + + bottomA_source_via = top_level << viam2m3 + bottomA_source_via.move((middleB_drain_via.center[0], top_level.ports["currm_bottom_A_0_source_E"].center[1])) + + top_level << straight_route( + pdk, bottomB_gate_via.ports["top_met_S"], middleB_drain_via.ports["top_met_N"], glayer2="met3" + ) + + topA_gate_via = top_level << viam2m3 + topA_gate_via.move((top_level.ports["currm_top_A_1_gate_W"].center)).movex(dist_GS) + + middleA_drain_via = top_level << viam2m3 + middleA_drain_via.move(top_level.ports["currm_middle_A_1_drain_E"].center).movex(-dist_DS) + + topB_source_via = top_level << viam2m3 + topB_source_via.move((middleA_drain_via.center[0], top_level.ports["currm_top_B_0_source_E"].center[1])) + + top_level << straight_route( + pdk, topB_source_via.ports["top_met_N"], middleA_drain_via.ports["top_met_S"], glayer2="met3" + ) + + topB_drain_via = top_level << viam2m3 + topB_drain_via.move(top_level.ports["currm_top_B_1_drain_E"].center).movex(-dist_DS) + + middleB_gate_via = top_level << viam2m3 + middleB_gate_via.move(top_level.ports["currm_middle_B_1_gate_E"].center).movex(-dist_GS) + + middleA_gate_via = top_level << viam2m3 + middleA_gate_via.move((middleB_gate_via.center[0], top_level.ports["currm_middle_A_1_gate_E"].center[1])) + + top_level << straight_route( + pdk, middleB_gate_via.ports["top_met_S"], topB_drain_via.ports["top_met_N"], glayer2="met3" + ) + top_level << straight_route( + pdk, middleA_gate_via.ports["top_met_S"], middleB_gate_via.ports["top_met_N"], glayer2="met3" + ) + + # ------------------------------------------------------------------------- + # TAP RING + # ------------------------------------------------------------------------- + snap = pdk.snap_to_2xgrid + + core = top_level.copy() # so we don't mutate while measuring + core_flat = core.flatten() # include all placed children + + xmin, xmax = core_flat.xmin, core_flat.xmax + ymin, ymax = core_flat.ymin, core_flat.ymax + + core_w = xmax - xmin + core_h = ymax - ymin + + # cx = snap((xmin + xmax) / 2) + # cy = snap((ymin + ymax) / 2) + cx = (xmin + xmax) / 2 + cy = (ymin + ymax) / 2 + + # Adding tapring + if with_tie: + well, sdglayer = "pwell", "p+s/d" + tap_separation = max(maxmet_sep, pdk.get_grule("active_diff", "active_tap")["min_separation"]) + tap_separation += pdk.get_grule(sdglayer, "active_tap")["min_enclosure"] + tap_encloses = ( + # (snap(4 * tap_separation + core_w)), + # (snap(4 * tap_separation + core_h)), + (4 * tap_separation + core_w), + (4 * tap_separation + core_h), + ) + tie_ref = top_level << tapring( + pdk, + enclosed_rectangle=tap_encloses, + sdlayer=sdglayer, + horizontal_glayer=tie_layers[0], + vertical_glayer=tie_layers[1], + ) + tie_ref.move((cx, cy)) + top_level.add_ports(tie_ref.get_ports_list(), prefix="welltie_") + + # add pwell + top_level.add_padding( + default=pdk.get_grule(well, "active_tap")["min_enclosure"], + layers=[pdk.get_glayer(well)], + ) + top_level = add_ports_perimeter(top_level, layer=pdk.get_glayer(well), prefix="well_") + + # add the substrate tap if specified + if with_substrate_tap: + substrate_tap_separation = pdk.get_grule("dnwell", "active_tap")["min_separation"] + substrate_tap_enclosure = ( + # (snap(4 * substrate_tap_separation + core_w)), + # (snap(4 * substrate_tap_separation + core_h)), + (4 * substrate_tap_separation + core_w), + (4 * substrate_tap_separation + core_h), + ) + ringtoadd = tapring( + pdk, + enclosed_rectangle=substrate_tap_enclosure, + sdlayer="p+s/d", + horizontal_glayer=tie_layers[0], + vertical_glayer=tie_layers[1], + ) + substrate_tap_ring_ref = top_level << ringtoadd + substrate_tap_ring_ref.move((cx, cy)) + top_level.add_ports(substrate_tap_ring_ref.get_ports_list(), prefix="substrate_tap_") + + # Connect well ties to well + try: + top_level << straight_route( + pdk, + top_level.ports["currm_bottom_A_0_dummy_L_gsdcon_top_met_W"], + top_level.ports["welltie_W_top_met_W"], + glayer2="met1", + ) + top_level << straight_route( + pdk, + top_level.ports["currm_bottom_B_1_dummy_R_gsdcon_top_met_E"], + top_level.ports["welltie_E_top_met_E"], + glayer2="met1", + ) + top_level << straight_route( + pdk, + top_level.ports["currm_middle_A_0_dummy_L_gsdcon_top_met_W"], + top_level.ports["welltie_W_top_met_W"], + glayer2="met1", + ) + top_level << straight_route( + pdk, + top_level.ports["currm_middle_B_1_dummy_R_gsdcon_top_met_E"], + top_level.ports["welltie_E_top_met_E"], + glayer2="met1", + ) + top_level << straight_route( + pdk, + top_level.ports["currm_top_A_0_dummy_L_gsdcon_top_met_W"], + top_level.ports["welltie_W_top_met_W"], + glayer2="met1", + ) + top_level << straight_route( + pdk, + top_level.ports["currm_top_B_1_dummy_R_gsdcon_top_met_E"], + top_level.ports["welltie_E_top_met_E"], + glayer2="met1", + ) + except KeyError: + pass + + # ------------------------------------------------------------------------- + # CONNECT DRAINS TO OTHER STAGES + # ------------------------------------------------------------------------- + dist_ring = ( + abs( + top_level.ports["welltie_W_top_met_W"].center[0] + - top_level.ports["welltie_W_top_met_E"].center[0] + ) + / 2 + ) + + topA_drain_aux_via = top_level << viam1m2 + topA_drain_aux_via.move( + (top_level.ports["welltie_W_top_met_E"].center[0], top_level.ports["currm_top_A_0_drain_E"].center[1]) + ).movex(-dist_ring - 2 * dist_DS) + top_level.add_ports(topA_drain_aux_via.get_ports_list(), prefix="AUX_A_") + + top_level << straight_route( + pdk, top_level.ports["currm_top_A_0_drain_W"], topA_drain_aux_via.ports["top_met_W"], glayer2="met2" + ) + + topB_drain_in_via = top_level << viam1m2 + topB_drain_in_via.move( + (top_level.ports["welltie_W_top_met_E"].center[0], top_level.ports["currm_top_B_0_drain_E"].center[1]) + ).movex(-dist_ring - 2 * dist_DS) + top_level.add_ports(topB_drain_in_via.get_ports_list(), prefix="IN_") + + top_level << straight_route( + pdk, top_level.ports["currm_top_B_0_drain_W"], topB_drain_in_via.ports["top_met_W"], glayer2="met2" + ) + + bottomB_drain_aux_via = top_level << viam1m2 + bottomB_drain_aux_via.move( + (top_level.ports["welltie_W_top_met_E"].center[0], top_level.ports["currm_bottom_B_0_drain_W"].center[1]) + ).movex(-dist_ring - 2 * dist_DS) + top_level.add_ports(bottomB_drain_aux_via.get_ports_list(), prefix="AUX_B_") + + top_level << straight_route( + pdk, top_level.ports["currm_bottom_B_0_drain_W"], bottomB_drain_aux_via.ports["top_met_W"], glayer2="met2" + ) + + bottomA_drain_out_via = top_level << viam1m2 + bottomA_drain_out_via.move( + (top_level.ports["welltie_E_top_met_W"].center[0], top_level.ports["currm_bottom_A_0_drain_E"].center[1]) + ).movex(dist_ring + 2 * dist_DS) + top_level.add_ports(bottomA_drain_out_via.get_ports_list(), prefix="OUT_") + + top_level << straight_route( + pdk, top_level.ports["currm_bottom_A_0_drain_E"], bottomA_drain_out_via.ports["top_met_E"], glayer2="met2" + ) + + top_level << straight_route( + pdk, topA_drain_aux_via.ports["top_met_S"], bottomB_drain_aux_via.ports["top_met_N"], glayer2="met1" + ) + + # ------------------------------------------------------------------------- + # CONNECT SOURCES TO GND + # ------------------------------------------------------------------------- + topA_source_via = top_level << viam1m2 + topA_source_via.move( + (top_level.ports["welltie_W_top_met_E"].center[0], top_level.ports["currm_top_A_0_source_W"].center[1]) + ).movex(-dist_ring) + + top_level << straight_route( + pdk, top_level.ports["currm_top_A_0_source_W"], topA_source_via.ports["top_met_W"], glayer2="met2" + ) + + middleA_source_via = top_level << viam1m2 + middleA_source_via.move( + (top_level.ports["welltie_W_top_met_E"].center[0], top_level.ports["currm_middle_A_0_source_W"].center[1]) + ).movex(-dist_ring) + + top_level << straight_route( + pdk, top_level.ports["currm_middle_A_0_source_W"], middleA_source_via.ports["top_met_W"], glayer2="met2" + ) + + middleB_source_via = top_level << viam1m2 + middleB_source_via.move( + (top_level.ports["welltie_E_top_met_E"].center[0], top_level.ports["currm_middle_B_0_source_W"].center[1]) + ).movex(-dist_ring) + + top_level << straight_route( + pdk, top_level.ports["currm_middle_B_0_source_W"], middleB_source_via.ports["top_met_W"], glayer2="met2" + ) + + bottomB_source_via = top_level << viam1m2 + bottomB_source_via.move( + (top_level.ports["welltie_E_top_met_W"].center[0], top_level.ports["currm_bottom_B_0_source_W"].center[1]) + ).movex(dist_ring) + + top_level << straight_route( + pdk, top_level.ports["currm_bottom_B_0_source_W"], bottomB_source_via.ports["top_met_E"], glayer2="met2" + ) + + top_level = component_snap_to_grid(rename_ports_by_orientation(top_level)) + + top_level.info["netlist"] = generate_regulated_current_mirror_netlist( + pdk=pdk, + prefix="RCCM", + instance_name=top_level.name, + CM_size=(Width, Length, num_cols, fingers), # (width, length, multipliers, fingers) + transistor_type=type, + drain_net_in="VIN", # Input drain connected to IREF + drain_net_aux="VAUX", # Auxiliary node + drain_net_out="VOUT", # Output drain connected to ICOPY + gate_net="VIN", # Gate connected to VREF + source_net_in="VSS" if type.lower() == "nfet" else "VDD", + source_net_out="VSS" if type.lower() == "nfet" else "VDD", + bulk_net="VSS" if type.lower() == "nfet" else "VDD", + subckt_only=True, + show_netlist=show_netlist, + ) + + if add_labels: + return add_cm_labels(top_level, pdk) + else: + return top_level + + +def add_cm_labels(cm_in: Component, pdk: MappedPDK) -> Component: + cm_in.unlock() + + psize = (0.35, 0.35) + move_info = [] + + # VIN + vinlabel = rectangle(layer=pdk.get_glayer("met2_pin"), size=psize, centered=True).copy() + vinlabel.add_label(text="VIN", layer=pdk.get_glayer("met2_label")) + move_info.append((vinlabel, cm_in.ports["IN_top_met_N"], None)) + + # VOUT + voutlabel = rectangle(layer=pdk.get_glayer("met2_pin"), size=psize, centered=True).copy() + voutlabel.add_label(text="VOUT", layer=pdk.get_glayer("met2_label")) + move_info.append((voutlabel, cm_in.ports["OUT_top_met_N"], None)) + + # VAUX + vauxlabel = rectangle(layer=pdk.get_glayer("met2_pin"), size=psize, centered=True).copy() + vauxlabel.add_label(text="VAUX", layer=pdk.get_glayer("met2_label")) + move_info.append((vauxlabel, cm_in.ports["AUX_A_top_met_N"], None)) + + # VSS (well tie) + vsslabel = rectangle(layer=pdk.get_glayer("met1_pin"), size=psize, centered=True).copy() + vsslabel.add_label(text="VSS", layer=pdk.get_glayer("met1_label")) + move_info.append((vsslabel, cm_in.ports["welltie_N_top_met_N"], None)) + + for comp, prt, alignment in move_info: + alignment = ("c", "b") if alignment is None else alignment + compref = align_comp_to_port(comp, prt, alignment=alignment) + cm_in.add(compref) + + return cm_in.flatten() + + +## To Test their primitives +# from current_mirror import current_mirror, current_mirror_netlist + +if __name__ == "__main__": + # Main function to generate the current mirror layout + # mappedpdk, Width, Length, num_cols, fingers, transistor type + selected_pdk = gf180 + comp = regulated_cascode_current_mirror( + selected_pdk, num_cols=2, Width=4, Length=1, device="nfet", show_netlist=False, with_substrate_tap=False + ) + # comp.pprint_ports() + # comp = add_cm_labels(comp, pdk=selected_pdk) + + comp.name = "RCM" + comp.show() + + # Write the current mirror layout to a GDS file + comp.write_gds("./RCM.gds") + + # Generate the netlist + print(comp.info["netlist"].generate_netlist()) + + # DRC Checks + drc_result = selected_pdk.drc_magic(comp, comp.name, output_file=Path("DRC/")) + + # LVS Checks + netgen_lvs_result = selected_pdk.lvs_netgen( + comp, comp.name, output_file_path=Path("LVS/"), copy_intermediate_files=True + ) \ No newline at end of file diff --git a/blocks/composite/regulated_cascoded_cmirror/cm_regc.py b/blocks/composite/regulated_cascoded_cmirror/cm_regc.py new file mode 100644 index 00000000..62dd9262 --- /dev/null +++ b/blocks/composite/regulated_cascoded_cmirror/cm_regc.py @@ -0,0 +1,366 @@ +#!/headless/conda-env/miniconda3/envs/GLdev/bin/python3 +from glayout import MappedPDK, sky130,gf180 +from glayout import nmos, pmos, tapring,via_stack + +from glayout.placement.two_transistor_interdigitized import two_nfet_interdigitized, two_pfet_interdigitized +from gdsfactory import cell +from gdsfactory.component import Component +from gdsfactory.components import text_freetype, rectangle + +#from glayout.routing import c_route,L_route,straight_route +from glayout.routing.c_route import c_route +from glayout.routing.L_route import L_route +from glayout.routing.straight_route import straight_route +from glayout.spice.netlist import Netlist + +from glayout.util.port_utils import add_ports_perimeter,rename_ports_by_orientation +from glayout.util.comp_utils import evaluate_bbox, prec_center, prec_ref_center, align_comp_to_port +from glayout.util.snap_to_grid import component_snap_to_grid +from typing import Optional, Union + +###### Only Required for IIC-OSIC Docker +import os +import subprocess +from pathlib import Path +import contextlib + +# Run a shell, source .bashrc, then printenv +cmd = 'bash -c "source ~/.bashrc && printenv"' +result = subprocess.run(cmd, shell=True, text=True, capture_output=True) +env_vars = {} +for line in result.stdout.splitlines(): + if '=' in line: + key, value = line.split('=', 1) + env_vars[key] = value + +# Now, update os.environ with these +os.environ.update(env_vars) + + +def display_component(component,path,scale = 3): + # Save to a GDS file + with hide: + component.write_gds(os.path.join(path,'out.gds')) + display_gds(os.path.join(path,'out.gds'),path,scale) + +def regulated_cascode_current_mirror( + pdk: MappedPDK, + Width: float = 1, + Length: Optional[float] = None, + num_cols: int = 2, + fingers: int = 1, + type: Optional[str] = 'nfet', + with_substrate_tap: Optional[bool] = False, + with_tie: Optional[bool] = True, + with_dummy: Optional[bool] = True, + tie_layers: tuple[str,str]=("met2","met1"), + show_netlist: Optional[bool] = False, + **kwargs + ) -> Component: + """An instantiable regulated cascode current mirror that returns a Component object.""" + + pdk.activate() + maxmet_sep = pdk.util_max_metal_seperation() + psize=(0.35,0.35) + + # Create the regulated cascoded current mirror component + RegulatedCM = Component(name="RegulatedCM") + Length = Length if Length is not None else pdk.get_grule('poly')['min_width'] + + # Define transistor parameters + # Add the NMOS devices + nmos_width = 4 + nmos_length = 1 + nmos_mult = 1 + XMB10 = nmos(pdk, + width=nmos_width, + fingers=2, + multipliers=nmos_mult, + with_dummy=False, + with_substrate_tap=True, + length=nmos_length, + with_tie=True, + sd_route_topmet="met2", + gate_route_topmet="met2") + # with_tie=True) + + XMB11 = nmos(pdk, + width=nmos_width, + fingers=2*1, + multipliers=1*nmos_mult, + with_dummy=False, + with_substrate_tap=True, + length=nmos_length) + + XMB8 = nmos(pdk, + width=nmos_width, + fingers=2, + multipliers=nmos_mult, + with_dummy=False, + with_substrate_tap=True, + length=nmos_length, + with_tie=True, + sd_route_topmet="met2", + gate_route_topmet="met2") + + XMB13 = nmos(pdk, + width=nmos_width, + fingers=2, + multipliers=nmos_mult, + with_dummy=False, + with_substrate_tap=True, + length=nmos_length, + with_tie=True, + sd_route_topmet="met2", + gate_route_topmet="met2") + + XMB14 = nmos(pdk, + width=nmos_width, + fingers=2, + multipliers=nmos_mult, + with_dummy=False, + with_substrate_tap=True, + length=nmos_length, + with_tie=True, + sd_route_topmet="met2", + gate_route_topmet="met2") + + XM12 = nmos(pdk, + width=nmos_width, + fingers=2, + multipliers=nmos_mult, + with_dummy=False, + with_substrate_tap=True, + length=nmos_length, + with_tie=True, + sd_route_topmet="met2", + gate_route_topmet="met2") + + # Adding the references of the transistors to the top component + fet_XMB10_ref = RegulatedCM << XMB10 + fet_XMB11_ref = RegulatedCM << XMB11 + fet_XMB8_ref = RegulatedCM << XMB8 + fet_XMB13_ref = RegulatedCM << XMB13 + fet_XMB14_ref = RegulatedCM << XMB14 + fet_XM12_ref = RegulatedCM << XM12 + + + # Naming each transistor reference + fet_XMB10_ref.name = "XMB10" + fet_XMB11_ref.name = "XMB11" + fet_XMB8_ref.name = "XMB8" + fet_XMB13_ref.name = "XMB13" + fet_XMB14_ref.name = "XMB14" + fet_XM12_ref.name = "XM12" + + + # Add reference of each transistor to the top component + RegulatedCM.add(fet_XMB10_ref) + RegulatedCM.add(fet_XMB11_ref) + RegulatedCM.add(fet_XMB8_ref) + RegulatedCM.add(fet_XMB13_ref) + RegulatedCM.add(fet_XMB14_ref) + RegulatedCM.add(fet_XM12_ref) + + # Add ports of each transistor to the top component with prefixes + RegulatedCM.add_ports(fet_XMB10_ref.get_ports_list(),prefix="rcm_XMB10_") + RegulatedCM.add_ports(fet_XMB11_ref.get_ports_list(),prefix="rcm_XMB11_") + RegulatedCM.add_ports(fet_XMB8_ref.get_ports_list(),prefix="rcm_XMB8_") + RegulatedCM.add_ports(fet_XMB13_ref.get_ports_list(),prefix="rcm_XMB13_") + RegulatedCM.add_ports(fet_XMB14_ref.get_ports_list(),prefix="rcm_XMB14_") + RegulatedCM.add_ports(fet_XM12_ref.get_ports_list(),prefix="rcm_XM12_") + + # Get the dimensions of the transistors for placement + fet_XMB10_dim = evaluate_bbox(fet_XMB10_ref) + fet_XMB11_dim = evaluate_bbox(fet_XMB11_ref) + fet_XMB8_dim = evaluate_bbox(fet_XMB8_ref) + fet_XMB13_dim = evaluate_bbox(fet_XMB13_ref) + fet_XMB14_dim = evaluate_bbox(fet_XMB14_ref) + fet_XM12_dim = evaluate_bbox(fet_XM12_ref) + + # Place each transistor in the top component + fet_XMB11_ref.movey(0.5*(fet_XMB10_dim[1]/2 -maxmet_sep - fet_XMB11_dim[1]/2)) + fet_XMB11_ref.movex(fet_XMB10_dim[0]/2 + maxmet_sep + fet_XMB11_dim[0]/2) + + fet_XMB8_ref.movey((fet_XMB10_dim[1]/2 + maxmet_sep + fet_XMB8_dim[1]/2)) + fet_XMB8_ref.movex(fet_XMB10_dim[0]/2 + maxmet_sep + fet_XMB8_dim[0]/2) + + fet_XMB13_ref.movex(fet_XMB10_dim[0]/2 + fet_XMB11_dim[0] + 4*maxmet_sep + fet_XMB13_dim[0]/2) + + fet_XMB14_ref.movex(fet_XMB10_dim[0]/2 + fet_XMB11_dim[0] + 4*maxmet_sep + fet_XMB14_dim[0]/2) + fet_XMB14_ref.movey((fet_XMB11_dim[1]/2 + maxmet_sep + fet_XMB14_dim[1]/2)) + + fet_XM12_ref.movex(fet_XMB10_dim[0]/2 + fet_XMB11_dim[0] + 6*maxmet_sep + fet_XMB14_dim[0] + fet_XM12_dim[0]/2) + + # Routing between the transistors + viam2m3 = via_stack(pdk, "met2", "met3", centered=True) + viam3m4 = via_stack(pdk, "met3", "met4", centered=True) + viam4m5 = via_stack(pdk, "met4", "met5", centered=True) + + # Position the vias to respective ports centre + drain_XMB10_via = RegulatedCM << viam2m3 + drain_XMB10_via.move(RegulatedCM.ports["rcm_XMB10_multiplier_0_drain_W"].center)#.movey(-0.8*maxmet_sep) #.movex(1*maxmet_sep) + source_XMB10_via = RegulatedCM << viam2m3 + source_XMB10_via.move(RegulatedCM.ports["rcm_XMB10_multiplier_0_source_E"].center)#.movey(0.8*maxmet_sep) + gate_XMB10_via = RegulatedCM << viam2m3 + gate_XMB10_via.move(RegulatedCM.ports["rcm_XMB10_multiplier_0_gate_S"].center)#.movey(-0.8*maxmet_sep) + + XMB10_D_XMB8_G_via = RegulatedCM << viam2m3 + XMB10_D_XMB8_G_via.movex((fet_XMB10_ref.ports["drain_E"].center[0] + fet_XMB8_ref.ports["gate_W"].center[0] - 16*maxmet_sep)/2) + XMB10_D_XMB8_G_via.movey((fet_XMB10_ref.ports["drain_N"].center[1] + fet_XMB8_ref.ports["gate_S"].center[1] + 8*maxmet_sep)/2) + # XMB10_D_XMB8_G_via.movey(fet_XMB10_ref.ports["drain_E"].center.y + fet_XMB8_ref.ports["gate_W"].center.y)/2 + # (prec_ref_center(fet_XMB10_ref.ports["drain_E"], fet_XMB8_ref.ports["gate_W"]))#.movey(-0.8*maxmet_sep) + + XM12_G_XM14_S_via = RegulatedCM << viam2m3 + XM12_G_XM14_S_via.movex((fet_XM12_ref.ports["gate_E"].center[0] + fet_XMB14_ref.ports["source_W"].center[0] + 16*maxmet_sep)/2) + XM12_G_XM14_S_via.movey((fet_XM12_ref.ports["gate_N"].center[1] + fet_XMB14_ref.ports["source_S"].center[1] + 12*maxmet_sep)/2) + # XM12_G_XM14_S_via + + drain_XMB11_via = RegulatedCM << viam2m3 + # drain_XMB11_via.move(RegulatedCM.ports["rcm_XMB11_multiplier_0_drain_W"].center)#.movey(-0.8*maxmet_sep) #.movex(1*maxmet_sep) + # drain_XMB11_via.move(RegulatedCM.ports["rcm_XMB11_drain_W"].center) + drain_XMB11_via.move(fet_XMB11_ref.ports["drain_W"].center) + source_XMB11_via = RegulatedCM << viam2m3 + # source_XMB11_via.move(RegulatedCM.ports["rcm_XMB11_multiplier_0_source_E"].center)#.movey(0.8*maxmet_sep) + source_XMB11_via.move(fet_XMB11_ref.ports["source_W"].center) + gate_XMB11_via = RegulatedCM << viam2m3 + # gate_XMB11_via.move(RegulatedCM.ports["rcm_XMB11_multiplier_0_gate_S"].center)#.movey(-0.8*maxmet_sep) + gate_XMB11_via.move(fet_XMB11_ref.ports["gate_W"].center) + + drain_XMB8_via = RegulatedCM << viam2m3 + # drain_XMB8_via.move(RegulatedCM.ports["rcm_XMB8_multiplier_0_drain_W"].center)#.movey(-0.8*maxmet_sep) #.movex(1*maxmet_sep) + drain_XMB8_via.move(fet_XMB8_ref.ports["drain_W"].center) + source_XMB8_via = RegulatedCM << viam2m3 + # source_XMB8_via.move(RegulatedCM.ports["rcm_XMB8_multiplier_0_source_E"].center)#.movey(0.8*maxmet_sep) + source_XMB8_via.move(fet_XMB8_ref.ports["source_W"].center) + gate_XMB8_via = RegulatedCM << viam2m3 + # gate_XMB8_via.move(RegulatedCM.ports["rcm_XMB8_multiplier_0_gate_S"].center)#.movey(-0.8*maxmet_sep) + gate_XMB8_via.move(fet_XMB8_ref.ports["gate_W"].center) + + drain_XMB13_via = RegulatedCM << viam2m3 + drain_XMB13_via.move(fet_XMB13_ref.ports["drain_W"].center) + source_XMB13_via = RegulatedCM << viam2m3 + source_XMB13_via.move(fet_XMB13_ref.ports["source_W"].center) + gate_XMB13_via = RegulatedCM << viam2m3 + gate_XMB13_via.move(fet_XMB13_ref.ports["gate_W"].center) + + drain_XMB14_via = RegulatedCM << viam2m3 + drain_XMB14_via.move(fet_XMB14_ref.ports["drain_W"].center) + source_XMB14_via = RegulatedCM << viam2m3 + source_XMB14_via.move(fet_XMB14_ref.ports["source_W"].center) + gate_XMB14_via = RegulatedCM << viam2m3 + gate_XMB14_via.move(fet_XMB14_ref.ports["gate_W"].center) + + drain_XM12_via = RegulatedCM << viam2m3 + drain_XM12_via.move(fet_XM12_ref.ports["drain_W"].center) + source_XM12_via = RegulatedCM << viam2m3 + source_XM12_via.move(fet_XM12_ref.ports["source_W"].center) + gate_XM12_via = RegulatedCM << viam2m3 + gate_XM12_via.move(fet_XM12_ref.ports["gate_W"].center) + + + + + # with open("ports_RegulatedCM.csv" , "w") as f: + # with contextlib.redirect_stdout(f): + # RegulatedCM.pprint_ports() + # fet_XMB10_ref.pprint_ports() + # RegulatedCM.pprint_ports() + # XMB10_D_XMB8_G_via.pprint_ports() + + #Routing + ## XMB10 Gate to XMB11 Drain; XMB10 Source to XMB11 Source; XMB10 source to V_AUX; + RegulatedCM << straight_route(pdk, RegulatedCM.ports["rcm_XMB10_source_E"], fet_XMB11_ref.ports["source_W"]) + RegulatedCM << L_route(pdk, fet_XMB10_ref.ports["gate_E"], fet_XMB11_ref.ports["drain_S"]) + ## XMB8 Source to XMB11 Drain + RegulatedCM << c_route(pdk, fet_XMB8_ref.ports["source_E"], fet_XMB11_ref.ports["drain_E"], extension = 10*maxmet_sep) + ## XMB8 Gate to XMB10 Drain + # RegulatedCM << L_route(pdk, fet_XMB8_ref.ports["gate_W"], fet_XMB10_ref.ports["drain_N"]) + RegulatedCM << L_route(pdk, fet_XMB8_ref.ports["gate_W"], XMB10_D_XMB8_G_via.ports["bottom_met_N"]) + RegulatedCM << L_route(pdk, XMB10_D_XMB8_G_via.ports["bottom_met_S"], fet_XMB10_ref.ports["drain_E"]) + ## XMB8 Drain to XMB11 Gate + RegulatedCM << c_route(pdk, fet_XMB8_ref.ports["drain_E"], fet_XMB11_ref.ports["gate_E"],extension = 15*maxmet_sep) + ## XM13 Source to XM11 Source + RegulatedCM << straight_route(pdk, fet_XMB13_ref.ports["source_W"], fet_XMB11_ref.ports["source_W"]) + ## XMB13 Gate to XMB11 Gate + RegulatedCM << straight_route(pdk, fet_XMB13_ref.ports["gate_W"], fet_XMB11_ref.ports["gate_E"]) + ## XM13 Drain to XM14 Source + RegulatedCM << c_route(pdk, fet_XMB13_ref.ports["drain_W"], fet_XMB14_ref.ports["source_W"], extension = 10*maxmet_sep) + ## XM12 Source to XM13 Source + RegulatedCM << straight_route(pdk, fet_XM12_ref.ports["source_W"], fet_XMB13_ref.ports["source_W"]) + ## XM12 Gate to XM13 Drain/XM14 Source + RegulatedCM << L_route(pdk, fet_XM12_ref.ports["gate_W"], XM12_G_XM14_S_via.ports["bottom_met_S"]) + RegulatedCM << L_route(pdk, XM12_G_XM14_S_via.ports["bottom_met_N"], fet_XMB14_ref.ports["source_E"]) + ## XM12 Drain to XM14 Gate + RegulatedCM << c_route(pdk, fet_XM12_ref.ports["drain_E"], fet_XMB14_ref.ports["gate_E"], extension = 10*maxmet_sep) + + ##xm12 drain to v_aux + RegulatedCM << c_route(pdk, fet_XM12_ref.ports["drain_N"], fet_XMB10_ref.ports["drain_N"], extension = 10*maxmet_sep) + + + + #Add Pins + psize = (0.5,0.5) + move_info = list() + vaux_label = rectangle(layer = pdk.get_glayer("met3_pin"), size=psize, centered=True).copy() + vaux_label.add_label(text="v_aux", layer=pdk.get_glayer("met3_label")) + # move_info.append((iref_label, RegulatedCM.ports["rcm_XMB5_drain_N"], None)) + move_info.append((vaux_label, fet_XMB10_ref.ports["drain_W"], None)) + + vss_label = rectangle(layer = pdk.get_glayer("met3_pin"), size=psize, centered=True).copy() + vss_label.add_label(text="vss", layer=pdk.get_glayer("met3_label")) + # move_info.append((vss_label, RegulatedCM.ports["rcm_XMB10_source_S"], None)) + move_info.append((vss_label, fet_XMB10_ref.ports["source_W"], None)) + + v_in_label = rectangle(layer = pdk.get_glayer("met3_pin"), size=psize, centered=True).copy() + v_in_label.add_label(text="v_in", layer=pdk.get_glayer("met3_label")) + # move_info.append((v_in_label, RegulatedCM.ports["rcm_XMB8_gate_N"], None)) + move_info.append((v_in_label, fet_XMB8_ref.ports["drain_W"], None)) + + v_out_label = rectangle(layer = pdk.get_glayer("met3_pin"), size=psize, centered=True).copy() + v_out_label.add_label(text="v_out", layer=pdk.get_glayer("met3_label")) + # move_info.append((v_out_label, RegulatedCM.ports["rcm_XMB11_drain_S"], None)) + move_info.append((v_out_label, fet_XMB14_ref.ports["drain_E"], None)) + + for comp, prt, alignment in move_info: + alignment = ('c', 'b') if alignment is None else alignment + aligned_comp = align_comp_to_port(comp, prt, alignment=alignment) + RegulatedCM.add(aligned_comp) + # component = RegulatedCM.flatten() + + #let's take a look at our current state of layout + ## To see in Klayout via Klive + # RegulatedCM.show() + + return RegulatedCM.flatten() + +if __name__ == "__main__": + # Main function to generate the current mirror layout + # mappedpdk, Width, Length, num_cols, fingers, transistor type + #comp = self_biased_cascode_current_mirror(gf180, num_cols=2, Width=3, device='nfet',show_netlist=False) + selected_pdk = gf180 + comp = regulated_cascode_current_mirror(pdk=gf180) + + + comp.name = "CM_RegC" + comp.show() + ##Write the current mirror layout to a GDS file + comp.write_gds("./CM_RegC.gds") + + # # #Generate the netlist for the current mirror + # print("\n...Generating Netlist...") + #print(comp.info["netlist"].generate_netlist()) + # # #DRC Checks + try: + drc_result = selected_pdk.drc_magic(comp, comp.name, output_file=Path("DRC/")) + except: + drc_result = selected_pdk.drc_magic(comp, comp.name) + print("\n...DRC Result: ", drc_result) + # # #LVS Checks + # #print("\n...Running LVS...") + #netgen_lvs_result = selected_pdk.lvs_netgen(comp, comp.name,output_file_path=Path("LVS/"),copy_intermediate_files=True) + + + + + # /headless/conda-env/miniconda3/envs/GLdev/bin/python3 cm_regc.py \ No newline at end of file diff --git a/blocks/composite/regulated_cascoded_cmirror/cm_sb.py b/blocks/composite/regulated_cascoded_cmirror/cm_sb.py new file mode 100644 index 00000000..8c49dea0 --- /dev/null +++ b/blocks/composite/regulated_cascoded_cmirror/cm_sb.py @@ -0,0 +1,621 @@ +from pathlib import Path +from typing import Optional, Union, ClassVar, Any, Literal, Iterable, TypedDict + +import os +import subprocess + +from glayout import MappedPDK, sky130, gf180 +from glayout import nmos, pmos, tapring, via_stack +from glayout.placement.two_transistor_interdigitized import ( + two_nfet_interdigitized, + two_pfet_interdigitized, +) +from n_fets_interdigitized import n_transistor_interdigitized +from gdsfactory import cell +from gdsfactory.component import Component +from gdsfactory.components import text_freetype, rectangle +from glayout.routing import c_route, L_route, straight_route +from glayout.spice.netlist import Netlist +from glayout.util.port_utils import add_ports_perimeter, rename_ports_by_orientation +from glayout.util.comp_utils import ( + evaluate_bbox, + prec_center, + prec_ref_center, + align_comp_to_port, +) +from glayout.util.snap_to_grid import component_snap_to_grid + +###### Only Required for IIC-OSIC Docker +# Run a shell, source .bashrc, then printenv +cmd = 'bash -c "source ~/.bashrc && printenv"' +result = subprocess.run(cmd, shell=True, text=True, capture_output=True) +env_vars = {} +for line in result.stdout.splitlines(): + if "=" in line: + key, value = line.split("=", 1) + env_vars[key] = value + +# Now, update os.environ with these +os.environ.update(env_vars) + + +# @validate_arguments +def generate_self_biased_current_mirror_netlist( + pdk: MappedPDK, + prefix : str, + instance_name: str, + CM_size: tuple[float, float, int], # (width, length, multipliers) + drain_net_in: str, + drain_net_out: str, + source_net_in: str, + source_net_out: str, + gate_net: str, + transistor_type: str = "nfet", + bulk_net: str = None, + proposed_ground: str = None, # Proposed ground net + dummy: bool = True, + subckt_only: bool = False, + show_netlist: bool = False, + **kwargs, +) -> Netlist: + """Generate a netlist for a current mirror.""" + + if bulk_net is None: + bulk_net = "VDD" if transistor_type.lower() == "pfet" else "VSS" + + width = CM_size[0] + length = CM_size[1] + multipliers = CM_size[2] + fingers = CM_size[3] # Number of fingers of the interdigitized fets + mtop = multipliers * fingers if subckt_only else 1 + # mtop = multipliers * 2 if dummy else multipliers # Double the multiplier to account for the dummies + + model_name = pdk.models[transistor_type.lower()] + + circuit_name = prefix + # Take only unique NET names + nodes = [drain_net_in, drain_net_out, bulk_net] + + source_netlist = f".subckt {circuit_name} {' '.join(nodes)}\n" + + # Proposed ground connection (commented) + # source_netlist += f"V{proposed_ground}1 ({proposed_ground} {bulk_net}) 0\n" + + # Generating four transistors (one on each side): + A_source_C_drain_net = "VAC" + B_source_D_drain_net = "VBD" + + source_netlist += ( + f"X{prefix}_A {drain_net_in} {gate_net} {A_source_C_drain_net} {bulk_net} " + f"{model_name} l={length} w={width} m={mtop}\n" + ) + source_netlist += ( + f"X{prefix}_B {drain_net_out} {gate_net} {B_source_D_drain_net} {bulk_net} " + f"{model_name} l={length} w={width} m={mtop}\n" + ) + source_netlist += ( + f"X{prefix}_C {A_source_C_drain_net} {A_source_C_drain_net} {bulk_net} {bulk_net} " + f"{model_name} l={length} w={width} m={mtop}\n" + ) + source_netlist += ( + f"X{prefix}_D {B_source_D_drain_net} {A_source_C_drain_net} {bulk_net} {bulk_net} " + f"{model_name} l={length} w={width} m={mtop}\n" + ) + + if dummy: + source_netlist += ( + f"X{prefix}_DUMMY {bulk_net} {bulk_net} {bulk_net} {bulk_net} " + f"{model_name} l={length} w={width} m={4}\n" + ) + + source_netlist += ".ends " + circuit_name + + instance_format = "X{name} {nodes} {circuit_name} l={length} w={width} m={mult}" + + topnet = Netlist( + circuit_name=circuit_name, + nodes=nodes, + source_netlist=source_netlist, + instance_format=instance_format, + parameters={ + "model": model_name, + "width": width, + "length": length, + "mult": multipliers, + }, + ) + + if show_netlist: + generated_netlist_for_lvs = topnet.generate_netlist() + print("Generated netlist :\n", generated_netlist_for_lvs) + + file_path_local_storage = "./gen_netlist.txt" + try: + with open(file_path_local_storage, "w") as file: + file.write(generated_netlist_for_lvs) + except Exception: + print( + "Verify the file availability and type: ", + generated_netlist_for_lvs, + type(generated_netlist_for_lvs), + ) + + return topnet + + +# @validate_arguments +def self_biased_cascode_current_mirror( + pdk: MappedPDK, + Width: float = 1, + Length: Optional[float] = None, + num_cols: int = 2, + fingers: int = 1, + type: Optional[str] = "nfet", + with_substrate_tap: Optional[bool] = False, + with_tie: Optional[bool] = True, + tie_layers: tuple[str, str] = ("met2", "met1"), + with_dummy: Optional[bool] = True, + show_netlist: Optional[bool] = False, + add_labels = True, + **kwargs +) -> Component: + """ + An instantiable current mirror that returns a Component object. + The current mirror could be a two transistor interdigitized structure with a shorted source and gate. + It can be instantiated with either nmos or pmos devices. It can also be instantiated with a dummy device, + a substrate tap, and a tie layer, and is centered at the origin. + Transistor A acts as the reference and Transistor B acts as the mirror fet + This current mirror is used to generate a exact copy of the reference current. + [TODO] Needs to be checked for both pfet and nfet configurations. + [TODO] It will be updated with multi-leg or stackked length parametrization in future. + [TODO] There will also be a Regulated Cascoded block added to it. + + Args: + pdk (MappedPDK): the process design kit to use + Width (float): width of the interdigitized fets (same for both reference and mirror) + Length (float): length of the interdigitized fets (same for both reference and mirror) + As Default, Set to None to use the minimum length of the technology + numcols (int): number of columns of the interdigitized fets + fingers: Number of fingers of interdigitized fets (same for both reference and mirror) + device (str): nfet or pfet (can only interdigitize one at a time with this option) + with_dummy (bool): True places dummies on either side of the interdigitized fets + with_substrate_tap (bool): boolean to decide whether to place a substrate tapring + with_tie (bool): boolean to decide whether to place a tapring for tielayer + tie_layers (tuple[str,str], optional): the layers to use for the tie. Defaults to ("met2","met1"). + **kwargs: The keyword arguments are passed to the interdigitized functions + Returns: + Component: a current mirror component object + """ + pdk.activate() + maxmet_sep = pdk.util_max_metal_seperation() + + # Create the current mirror component + top_level = Component(name="SBCurrentMirror") + Length = Length if Length is not None else pdk.get_grule("poly")["min_width"] + top_ref = prec_ref_center(top_level) + + # Create the interdigitized fets + if type.lower() == "pfet" or type.lower() == "pmos": + currm = n_transistor_interdigitized( + pdk, + device="pfet", + numcols=num_cols, + n_devices=2, + width=Width, + length=Length, + fingers=fingers, + with_substrate_tap=False, + with_tie=False, + ) + well, sdglayer = "nwell", "n+s/d" + elif type.lower() == "nfet" or type.lower() == "nmos": + currm = n_transistor_interdigitized( + pdk, + device="nfet", + numcols=num_cols, + n_devices=2, + width=Width, + length=Length, + fingers=fingers, + with_substrate_tap=False, + with_tie=False, + ) + well, sdglayer = "pwell", "p+s/d" + else: + raise ValueError("type must be either nfet or pfet") + + # ------------------------------------------------------------------------- + # BOTTOM CURRENT MIRRORS + # ------------------------------------------------------------------------- + bottom_currm_ref = prec_ref_center(currm) + top_level.add(bottom_currm_ref) + bottom_currm_ref.move(top_ref.center) + top_level.add_ports(bottom_currm_ref.get_ports_list(), prefix="currm_bottom_") + + viam2m3 = via_stack(pdk, "met2", "met3", centered=True) + viam1m2 = via_stack(pdk, "met1", "met2", centered=True) + + dist_DS = ( + abs( + top_level.ports["currm_bottom_A_0_drain_E"].center[0] + - top_level.ports["currm_bottom_A_0_drain_W"].center[0] + ) + / 2 + ) + dist_GS = ( + abs( + top_level.ports["currm_bottom_A_0_gate_E"].center[0] + - top_level.ports["currm_bottom_A_0_gate_W"].center[0] + ) + / 2 + ) + + bottomA_drain_via = top_level << viam2m3 + bottomA_drain_via.move(top_level.ports["currm_bottom_A_0_drain_W"].center).movex(dist_DS) + + bottomA_gate_via = top_level << viam2m3 + bottomA_gate_via.move(top_level.ports["currm_bottom_A_0_gate_W"].center).movex(dist_GS) + + bottomB_gate_via = top_level << viam2m3 + bottomB_gate_via.move( + (bottomA_gate_via.center[0], top_level.ports["currm_bottom_B_0_gate_W"].center[1]) + ) + + top_level << straight_route( + pdk, + bottomA_drain_via.ports["top_met_N"], + bottomA_gate_via.ports["top_met_S"], + glayer1="met3", + glayer2="met3", + ) + top_level << straight_route( + pdk, + bottomA_gate_via.ports["top_met_N"], + bottomB_gate_via.ports["top_met_S"], + glayer1="met3", + glayer2="met3", + ) + + # ------------------------------------------------------------------------- + # TOP CURRENT MIRRORS + # ------------------------------------------------------------------------- + top_currm_ref = prec_ref_center(currm) + top_level.add(top_currm_ref) + top_currm_ref.move(top_ref.center).movey(evaluate_bbox(bottom_currm_ref)[1] + maxmet_sep) + top_level.add_ports(top_currm_ref.get_ports_list(), prefix="currm_top_") + + dist_DS = ( + abs( + top_level.ports["currm_top_A_0_drain_E"].center[0] + - top_level.ports["currm_top_A_0_drain_W"].center[0] + ) + / 2 + ) + dist_GS = ( + abs( + top_level.ports["currm_top_A_0_gate_E"].center[0] + - top_level.ports["currm_top_A_0_gate_W"].center[0] + ) + / 2 + ) + + bottomA_drain_via = top_level << viam2m3 + bottomA_drain_via.move(top_level.ports["currm_top_A_0_drain_W"].center).movex(dist_DS) + + bottomA_gate_via = top_level << viam2m3 + bottomA_gate_via.move(top_level.ports["currm_top_A_0_gate_W"].center).movex(dist_GS) + + bottomB_gate_via = top_level << viam2m3 + bottomB_gate_via.move( + (bottomA_gate_via.center[0], top_level.ports["currm_top_B_0_gate_W"].center[1]) + ) + + top_level << straight_route( + pdk, + bottomA_drain_via.ports["top_met_N"], + bottomA_gate_via.ports["top_met_S"], + glayer1="met3", + glayer2="met3", + ) + top_level << straight_route( + pdk, + bottomA_gate_via.ports["top_met_N"], + bottomB_gate_via.ports["top_met_S"], + glayer1="met3", + glayer2="met3", + ) + + # ------------------------------------------------------------------------- + # INTERCONNECTIONS + # ------------------------------------------------------------------------- + bottomA_drain_via = top_level << viam2m3 + bottomA_drain_via.move(top_level.ports["currm_bottom_A_0_drain_W"].center).movex(-dist_DS) + + top_level << straight_route( + pdk, + bottomA_drain_via.ports["top_met_W"], + top_level.ports["currm_bottom_A_0_drain_E"], + glayer1="met2", + glayer2="met2", + ) + + topA_source_via = top_level << viam2m3 + topA_source_via.move(top_level.ports["currm_top_A_0_source_W"].center).movex(-dist_DS) + + top_level << straight_route( + pdk, + topA_source_via.ports["top_met_W"], + top_level.ports["currm_top_A_0_drain_E"], + glayer1="met2", + glayer2="met2", + ) + top_level << straight_route( + pdk, + topA_source_via.ports["top_met_N"], + bottomA_drain_via.ports["top_met_S"], + glayer1="met3", + glayer2="met3", + ) + + bottomB_drain_via = top_level << viam2m3 + bottomB_drain_via.move(top_level.ports["currm_bottom_B_0_drain_E"].center).movex(dist_DS) + + top_level << straight_route( + pdk, + bottomB_drain_via.ports["top_met_E"], + top_level.ports["currm_bottom_B_0_drain_W"], + glayer1="met2", + glayer2="met2", + ) + + topB_source_via = top_level << viam2m3 + topB_source_via.move(top_level.ports["currm_top_B_0_source_E"].center).movex(dist_DS) + + top_level << straight_route( + pdk, + topB_source_via.ports["top_met_E"], + top_level.ports["currm_top_B_0_drain_W"], + glayer1="met2", + glayer2="met2", + ) + top_level << straight_route( + pdk, + topB_source_via.ports["top_met_N"], + bottomB_drain_via.ports["top_met_S"], + glayer1="met3", + glayer2="met3", + ) + + # ------------------------------------------------------------------------- + # TAP RING + # ------------------------------------------------------------------------- + snap = pdk.snap_to_2xgrid + + core = top_level.copy() # so we don't mutate while measuring + core_flat = core.flatten() # include all placed children + + xmin, xmax = core_flat.xmin, core_flat.xmax + ymin, ymax = core_flat.ymin, core_flat.ymax + + core_w = xmax - xmin + core_h = ymax - ymin + + cx = snap((xmin + xmax) / 2) + cy = snap((ymin + ymax) / 2) + + # Adding tapring + if with_tie: + well, sdglayer = "pwell", "p+s/d" + tap_separation = max( + maxmet_sep, pdk.get_grule("active_diff", "active_tap")["min_separation"] + ) + tap_separation += pdk.get_grule(sdglayer, "active_tap")["min_enclosure"] + tap_encloses = ( + snap(4 * tap_separation + core_w), + snap(4 * tap_separation + core_h), + ) + tie_ref = top_level << tapring( + pdk, + enclosed_rectangle=tap_encloses, + sdlayer=sdglayer, + horizontal_glayer=tie_layers[0], + vertical_glayer=tie_layers[1], + ) + tie_ref.move((cx, cy)) + top_level.add_ports(tie_ref.get_ports_list(), prefix="welltie_") + + # add pwell + top_level.add_padding( + default=pdk.get_grule(well, "active_tap")["min_enclosure"], + layers=[pdk.get_glayer(well)], + ) + top_level = add_ports_perimeter(top_level, layer=pdk.get_glayer(well), prefix="well_") + + # add the substrate tap if specified + if with_substrate_tap: + substrate_tap_separation = pdk.get_grule("dnwell", "active_tap")["min_separation"] + substrate_tap_enclosure = ( + snap(4 * substrate_tap_separation + core_w), + snap(4 * substrate_tap_separation + core_h), + ) + ringtoadd = tapring( + pdk, + enclosed_rectangle=substrate_tap_enclosure, + sdlayer="p+s/d", + horizontal_glayer=tie_layers[0], + vertical_glayer=tie_layers[1], + ) + substrate_tap_ring_ref = top_level << ringtoadd + substrate_tap_ring_ref.move((cx, cy)) + top_level.add_ports(substrate_tap_ring_ref.get_ports_list(), prefix="substrate_tap_") + + # Connect well ties to well + try: + pass + top_level << straight_route( + pdk, + top_level.ports["currm_bottom_A_0_dummy_L_gsdcon_top_met_W"], + top_level.ports["welltie_W_top_met_W"], + glayer2="met1", + ) + top_level << straight_route( + pdk, + top_level.ports["currm_bottom_B_0_dummy_R_gsdcon_top_met_E"], + top_level.ports["welltie_E_top_met_E"], + glayer2="met1", + ) + top_level << straight_route( + pdk, + top_level.ports["currm_top_A_0_dummy_L_gsdcon_top_met_W"], + top_level.ports["welltie_W_top_met_W"], + glayer2="met1", + ) + top_level << straight_route( + pdk, + top_level.ports["currm_top_B_0_dummy_R_gsdcon_top_met_E"], + top_level.ports["welltie_E_top_met_E"], + glayer2="met1", + ) + except KeyError: + pass + + # ------------------------------------------------------------------------- + # CONNECT TOP DRAINS TO OTHER STAGES + # ------------------------------------------------------------------------- + dist_ring = ( + abs( + top_level.ports["welltie_W_top_met_W"].center[0] + - top_level.ports["welltie_W_top_met_E"].center[0] + ) + / 2 + ) + + topA_drain_via = top_level << viam1m2 + topA_drain_via.move( + (top_level.ports["welltie_W_top_met_W"].center[0], top_level.ports["currm_top_A_0_drain_W"].center[1]) + ).movex(-dist_ring - 2 * dist_DS) + top_level.add_ports(topA_drain_via.get_ports_list(), prefix="IN_") + + top_level << straight_route( + pdk, + top_level.ports["currm_top_A_0_drain_W"], + topA_drain_via.ports["top_met_W"], + glayer2="met2", + ) + + topB_drain_via = top_level << viam1m2 + topB_drain_via.move( + (top_level.ports["welltie_E_top_met_E"].center[0], top_level.ports["currm_top_B_0_drain_E"].center[1]) + ).movex(-dist_ring + 2 * dist_DS) + top_level.add_ports(topB_drain_via.get_ports_list(), prefix="OUT_") + + top_level << straight_route( + pdk, + top_level.ports["currm_top_B_0_drain_E"], + topB_drain_via.ports["top_met_E"], + glayer2="met2", + ) + + # ------------------------------------------------------------------------- + # CONNECT SOURCES TO GND + # ------------------------------------------------------------------------- + bottomA_source_via = top_level << viam1m2 + bottomA_source_via.move( + (top_level.ports["welltie_W_top_met_E"].center[0], top_level.ports["currm_bottom_A_0_source_W"].center[1]) + ).movex(-dist_ring) + + top_level << straight_route( + pdk, + top_level.ports["currm_bottom_A_0_source_W"], + bottomA_source_via.ports["top_met_W"], + glayer2="met2", + ) + + bottomB_source_via = top_level << viam1m2 + bottomB_source_via.move( + (top_level.ports["welltie_E_top_met_E"].center[0], top_level.ports["currm_bottom_B_0_source_W"].center[1]) + ).movex(-dist_ring) + + top_level << straight_route( + pdk, + top_level.ports["currm_bottom_B_0_source_W"], + bottomB_source_via.ports["top_met_W"], + glayer2="met2", + ) + + top_level = component_snap_to_grid(rename_ports_by_orientation(top_level)) + + top_level.info["netlist"] = generate_self_biased_current_mirror_netlist( + pdk=pdk, + prefix="SBCM", + instance_name=top_level.name, + CM_size=(Width, Length, num_cols, fingers), # (width, length, multipliers, fingers) + transistor_type=type, + drain_net_in="VIN", # Input drain connected to IREF + drain_net_out="VOUT", # Output drain connected to ICOPY + gate_net="VIN", # Gate connected to VREF + source_net_in="VSS" if type.lower() == "nfet" else "VDD", + source_net_out="VSS" if type.lower() == "nfet" else "VDD", + bulk_net="VSS" if type.lower() == "nfet" else "VDD", + subckt_only=True, + show_netlist=show_netlist, + ) + + if add_labels: + return add_cm_labels(top_level, pdk) + else: + return top_level + + +def add_cm_labels(cm_in: Component, pdk: MappedPDK) -> Component: + cm_in.unlock() + + psize = (0.35, 0.35) + move_info = [] + + # VIN + vinlabel = rectangle(layer=pdk.get_glayer("met2_pin"), size=psize, centered=True).copy() + vinlabel.add_label(text="VIN", layer=pdk.get_glayer("met2_label")) + move_info.append((vinlabel, cm_in.ports["IN_top_met_N"], None)) + + # VOUT + voutlabel = rectangle(layer=pdk.get_glayer("met2_pin"), size=psize, centered=True).copy() + voutlabel.add_label(text="VOUT", layer=pdk.get_glayer("met2_label")) + move_info.append((voutlabel, cm_in.ports["OUT_top_met_N"], None)) + + # VSS (well tie) + vsslabel = rectangle(layer=pdk.get_glayer("met1_pin"), size=psize, centered=True).copy() + vsslabel.add_label(text="VSS", layer=pdk.get_glayer("met1_label")) + move_info.append((vsslabel, cm_in.ports["welltie_N_top_met_N"], None)) + + for comp, prt, alignment in move_info: + alignment = ("c", "b") if alignment is None else alignment + compref = align_comp_to_port(comp, prt, alignment=alignment) + cm_in.add(compref) + + return cm_in.flatten() + + +if __name__ == "__main__": + selected_pdk = gf180 + comp = self_biased_cascode_current_mirror( + selected_pdk, num_cols=1, Length=1, Width=4, device="nfet", show_netlist=False + ) + # comp.pprint_ports() + comp.name = "SCM" + comp.show() + + # Write the current mirror layout to a GDS file + comp.write_gds("./SCM.gds") + + # Generate & print the netlist + print(comp.info["netlist"].generate_netlist()) + + # DRC Checks + drc_result = selected_pdk.drc_magic(comp, comp.name, output_file=Path("DRC/")) + + # LVS Checks + netgen_lvs_result = selected_pdk.lvs_netgen( + comp, comp.name, output_file_path=Path("LVS/"), copy_intermediate_files=True + ) +# \ No newline at end of file diff --git a/blocks/composite/regulated_cascoded_cmirror/cm_v.py b/blocks/composite/regulated_cascoded_cmirror/cm_v.py new file mode 100644 index 00000000..145ab374 --- /dev/null +++ b/blocks/composite/regulated_cascoded_cmirror/cm_v.py @@ -0,0 +1,441 @@ +from pathlib import Path +from typing import Optional, Union, ClassVar, Any, Literal, Iterable, TypedDict + +import os +import subprocess + +from glayout import MappedPDK, sky130, gf180 +from glayout import nmos, pmos, tapring, via_stack +from glayout.placement.two_transistor_interdigitized import ( + two_nfet_interdigitized, + two_pfet_interdigitized, +) +from n_fets_interdigitized import n_transistor_interdigitized +from gdsfactory import cell +from gdsfactory.component import Component +from gdsfactory.components import text_freetype, rectangle +from glayout.routing import c_route, L_route, straight_route +from glayout.spice.netlist import Netlist +from glayout.util.port_utils import add_ports_perimeter, rename_ports_by_orientation +from glayout.util.comp_utils import ( + evaluate_bbox, + prec_center, + prec_ref_center, + align_comp_to_port, +) +from glayout.util.snap_to_grid import component_snap_to_grid + +# ------ Only Required for IIC-OSIC Docker ------ +# Run a shell, source .bashrc, then printenv +cmd = 'bash -c "source ~/.bashrc && printenv"' +result = subprocess.run(cmd, shell=True, text=True, capture_output=True) +env_vars = {} +for line in result.stdout.splitlines(): + if "=" in line: + key, value = line.split("=", 1) + env_vars[key] = value + +# Now, update os.environ with these +os.environ.update(env_vars) + + +# @validate_arguments +def generate_current_mirror_netlist( + pdk: MappedPDK, + prefix : str, + instance_name: str, + CM_size: tuple[float, float, int], # (width, length, multipliers) + drain_net_in: str, + drain_net_out: str, + source_net_in: str, + source_net_out: str, + gate_net: str, + transistor_type: str = "nfet", + bulk_net: str = None, + proposed_ground: str = None, # Proposed ground net + dummy: bool = True, + subckt_only: bool = False, + show_netlist: bool = False, + **kwargs, +) -> Netlist: + """Generate a netlist for a current mirror.""" + + if bulk_net is None: + bulk_net = "VDD" if transistor_type.lower() == "pfet" else "VSS" + + width = CM_size[0] + length = CM_size[1] + multipliers = CM_size[2] + fingers = CM_size[3] # Number of fingers of the interdigitized fets + mtop = multipliers * fingers if subckt_only else 1 + # mtop = multipliers * 2 if dummy else multipliers # Double the multiplier to account for the dummies + + model_name = pdk.models[transistor_type.lower()] + + circuit_name = prefix + # Take only unique NET names + nodes = [drain_net_in, drain_net_out, bulk_net] + + source_netlist = f".subckt {circuit_name} {' '.join(nodes)}\n" + + # Proposed ground connection (commented) + # source_netlist += f"V{proposed_ground}1 ({proposed_ground} {bulk_net}) 0\n" + + # Generating only two transistors (one on each side): + source_netlist += ( + f"X{prefix}_A {drain_net_in} {gate_net} {bulk_net} {bulk_net} " + f"{model_name} l={length} w={width} m={mtop}\n" + ) + source_netlist += ( + f"X{prefix}_B {drain_net_out} {gate_net} {bulk_net} {bulk_net} " + f"{model_name} l={length} w={width} m={mtop}\n" + ) + + if dummy: + source_netlist += ( + f"X{prefix}_DUMMY {bulk_net} {bulk_net} {bulk_net} {bulk_net} " + f"{model_name} l={length} w={width} m={2}\n" + ) + + source_netlist += ".ends " + circuit_name + + instance_format = "X{name} {nodes} {circuit_name} l={length} w={width} m={mult}" + + topnet = Netlist( + circuit_name=circuit_name, + nodes=nodes, + source_netlist=source_netlist, + instance_format=instance_format, + parameters={ + "model": model_name, + "width": width, + "length": length, + "mult": multipliers, + }, + ) + + if show_netlist: + generated_netlist_for_lvs = topnet.generate_netlist() + print("Generated netlist :\n", generated_netlist_for_lvs) + + file_path_local_storage = "./gen_netlist.txt" + try: + with open(file_path_local_storage, "w") as file: + file.write(generated_netlist_for_lvs) + except Exception: + print( + "Verify the file availability and type: ", + generated_netlist_for_lvs, + type(generated_netlist_for_lvs), + ) + + return topnet + + +# @validate_arguments +def current_mirror_base( + pdk: MappedPDK, + Width: float = 1, + Length: Optional[float] = None, + num_cols: int = 2, + fingers: int = 1, + type: Optional[str] = "nfet", + with_substrate_tap: Optional[bool] = False, + with_tie: Optional[bool] = True, + tie_layers: tuple[str, str] = ("met2", "met1"), + with_dummy: Optional[bool] = True, + show_netlist: Optional[bool] = False, + add_labels = True, + **kwargs, +) -> Component: + """ + An instantiable current mirror that returns a Component object. + The current mirror could be a two transistor interdigitized structure with a shorted source and gate. + It can be instantiated with either nmos or pmos devices. It can also be instantiated with a dummy device, + a substrate tap, and a tie layer, and is centered at the origin. + Transistor A acts as the reference and Transistor B acts as the mirror fet. + This current mirror is used to generate an exact copy of the reference current. + [TODO] Needs to be checked for both pfet and nfet configurations. + [TODO] It will be updated with multi-leg or stacked length parametrization in future. + [TODO] There will also be a Regulated Cascoded block added to it. + + Args: + pdk (MappedPDK): the process design kit to use + Width (float): width of the interdigitized fets (same for both reference and mirror) + Length (float): length of the interdigitized fets (same for both reference and mirror) + Set to None to use the minimum length of the technology + numcols (int): number of columns of the interdigitized fets + fingers (int): number of fingers of interdigitized fets + type (str): nfet or pfet + with_dummy (bool): True places dummies on either side of the interdigitized fets + with_substrate_tap (bool): place a substrate tapring + with_tie (bool): place a tapring for tie layer + tie_layers (tuple[str, str]): layers to use for the tie. Defaults to ("met2","met1"). + **kwargs: forwarded to the interdigitized builders + Returns: + Component: a current mirror component object + """ + pdk.activate() + maxmet_sep = pdk.util_max_metal_seperation() + + # Create the current mirror component + top_level = Component(name="CurrentMirror") + Length = Length if Length is not None else pdk.get_grule("poly")["min_width"] + + # Create the interdigitized fets + if type.lower() in ("pfet", "pmos"): + currm = n_transistor_interdigitized( + pdk, + device="pfet", + numcols=num_cols, + n_devices=2, + width=Width, + length=Length, + fingers=fingers, + with_substrate_tap=False, + with_tie=False, + ) + well, sdglayer = "nwell", "n+s/d" + elif type.lower() in ("nfet", "nmos"): + currm = n_transistor_interdigitized( + pdk, + device="nfet", + numcols=num_cols, + n_devices=2, + width=Width, + length=Length, + fingers=fingers, + with_substrate_tap=False, + with_tie=False, + ) + well, sdglayer = "pwell", "p+s/d" + else: + raise ValueError("type must be either nfet or pfet") + + # Add the interdigitized fets to the current mirror top component + currm_ref = prec_ref_center(currm) + top_level.add(currm_ref) + top_level.add_ports(currm_ref.get_ports_list(), prefix="currm_") + + viam2m3 = via_stack(pdk, "met2", "met3", centered=True) + viam1m2 = via_stack(pdk, "met1", "met2", centered=True) + + dist_DS = abs( + top_level.ports["currm_A_0_drain_E"].center[0] + - top_level.ports["currm_A_0_drain_W"].center[0] + ) / 2 + + dist_GS = abs( + top_level.ports["currm_A_0_gate_E"].center[0] + - top_level.ports["currm_A_0_gate_W"].center[0] + ) / 2 + + bottomA_drain_via = top_level << viam2m3 + bottomA_drain_via.move(top_level.ports["currm_A_0_drain_W"].center).movex(dist_DS) + + bottomA_gate_via = top_level << viam2m3 + bottomA_gate_via.move(top_level.ports["currm_A_0_gate_W"].center).movex(dist_GS) + + bottomB_gate_via = top_level << viam2m3 + bottomB_gate_via.move( + (bottomA_gate_via.center[0], top_level.ports["currm_B_0_gate_W"].center[1]) + ) + + top_level << straight_route( + pdk, bottomA_drain_via.ports["top_met_N"], bottomA_gate_via.ports["top_met_S"], glayer1="met3", glayer2="met3" + ) + top_level << straight_route( + pdk, bottomA_gate_via.ports["top_met_N"], bottomB_gate_via.ports["top_met_S"], glayer1="met3", glayer2="met3" + ) + + # ------------------------------------------------------------------------- + # TAP RING + # ------------------------------------------------------------------------- + snap = pdk.snap_to_2xgrid + + core = top_level.copy() # so we don't mutate while measuring + core_flat = core.flatten() # include all placed children + + xmin, xmax = core_flat.xmin, core_flat.xmax + ymin, ymax = core_flat.ymin, core_flat.ymax + + core_w = xmax - xmin + core_h = ymax - ymin + + cx = snap((xmin + xmax) / 2) + cy = snap((ymin + ymax) / 2) + + # Adding tapring + if with_tie: + well, sdglayer = "pwell", "p+s/d" + tap_separation = max( + maxmet_sep, pdk.get_grule("active_diff", "active_tap")["min_separation"] + ) + tap_separation += pdk.get_grule(sdglayer, "active_tap")["min_enclosure"] + tap_encloses = (snap(4 * tap_separation + core_w), snap(4 * tap_separation + core_h)) + tie_ref = top_level << tapring( + pdk, + enclosed_rectangle=tap_encloses, + sdlayer=sdglayer, + horizontal_glayer=tie_layers[0], + vertical_glayer=tie_layers[1], + ) + tie_ref.move((cx, cy)) + top_level.add_ports(tie_ref.get_ports_list(), prefix="welltie_") + + # add well padding + perimeter ports + top_level.add_padding( + default=pdk.get_grule(well, "active_tap")["min_enclosure"], + layers=[pdk.get_glayer(well)], + ) + top_level = add_ports_perimeter(top_level, layer=pdk.get_glayer(well), prefix="well_") + + # add the substrate tap if specified + if with_substrate_tap: + substrate_tap_separation = pdk.get_grule("dnwell", "active_tap")["min_separation"] + substrate_tap_enclosure = ( + snap(4 * substrate_tap_separation + core_w), + snap(4 * substrate_tap_separation + core_h), + ) + ringtoadd = tapring( + pdk, + enclosed_rectangle=substrate_tap_enclosure, + sdlayer="p+s/d", + horizontal_glayer=tie_layers[0], + vertical_glayer=tie_layers[1], + ) + substrate_tap_ring_ref = top_level << ringtoadd + substrate_tap_ring_ref.move((cx, cy)) + top_level.add_ports(substrate_tap_ring_ref.get_ports_list(), prefix="substrate_tap_") + + # Connect well ties to well + try: + pass + top_level << straight_route( + pdk, top_level.ports["currm_A_0_dummy_L_gsdcon_top_met_W"], top_level.ports["welltie_W_top_met_W"], glayer2="met1" + ) + top_level << straight_route( + pdk, top_level.ports["currm_B_0_dummy_R_gsdcon_top_met_E"], top_level.ports["welltie_E_top_met_E"], glayer2="met1" + ) + except KeyError: + pass + + # ------------------------------------------------------------------------- + # CONNECT BOTTOM DRAINS TO OTHER STAGES + # ------------------------------------------------------------------------- + dist_ring = abs( + top_level.ports["welltie_W_top_met_W"].center[0] + - top_level.ports["welltie_W_top_met_E"].center[0] + ) / 2 + + bottomA_drain_via = top_level << viam1m2 + bottomA_drain_via.move( + (top_level.ports["welltie_W_top_met_W"].center[0], top_level.ports["currm_A_0_drain_W"].center[1]) + ).movex(-dist_ring - 2 * dist_DS) + top_level.add_ports(bottomA_drain_via.get_ports_list(), prefix="IN_") + + top_level << straight_route( + pdk, top_level.ports["currm_A_0_drain_W"], bottomA_drain_via.ports["top_met_W"], glayer2="met2" + ) + + bottomB_drain_via = top_level << viam1m2 + bottomB_drain_via.move( + (top_level.ports["welltie_E_top_met_E"].center[0], top_level.ports["currm_B_0_drain_E"].center[1]) + ).movex(-dist_ring + 2 * dist_DS) + top_level.add_ports(bottomB_drain_via.get_ports_list(), prefix="OUT_") + + top_level << straight_route( + pdk, top_level.ports["currm_B_0_drain_E"], bottomB_drain_via.ports["top_met_E"], glayer2="met2" + ) + + # ------------------------------------------------------------------------- + # CONNECT SOURCES TO GND + # ------------------------------------------------------------------------- + bottomA_source_via = top_level << viam1m2 + bottomA_source_via.move( + (top_level.ports["welltie_W_top_met_E"].center[0], top_level.ports["currm_A_0_source_W"].center[1]) + ).movex(-dist_ring) + + top_level << straight_route( + pdk, top_level.ports["currm_A_0_source_W"], bottomA_source_via.ports["top_met_W"], glayer2="met2" + ) + + bottomB_source_via = top_level << viam1m2 + bottomB_source_via.move( + (top_level.ports["welltie_E_top_met_E"].center[0], top_level.ports["currm_B_0_source_W"].center[1]) + ).movex(-dist_ring) + + top_level << straight_route( + pdk, top_level.ports["currm_B_0_source_W"], bottomB_source_via.ports["top_met_W"], glayer2="met2" + ) + + top_level = component_snap_to_grid(rename_ports_by_orientation(top_level)) + + top_level.info["netlist"] = generate_current_mirror_netlist( + pdk=pdk, + prefix="VCM", + instance_name=top_level.name, + CM_size=(Width, Length, num_cols, fingers), # (width, length, multipliers, fingers) + transistor_type=type, + drain_net_in="VIN", # Input drain connected to IREF + drain_net_out="VOUT", # Output drain connected to ICOPY + gate_net="VIN", # Gate connected to VREF + source_net_in="VSS" if type.lower() == "nfet" else "VDD", # Source + source_net_out="VSS" if type.lower() == "nfet" else "VDD", # Source + bulk_net="VSS" if type.lower() == "nfet" else "VDD", + subckt_only=True, + show_netlist=show_netlist, + ) + + if add_labels: + return add_cm_labels(top_level, pdk) + else: + return top_level + + +def add_cm_labels(cm_in: Component, pdk: MappedPDK) -> Component: + cm_in.unlock() + + psize = (0.35, 0.35) + move_info = [] + + # VIN + vinlabel = rectangle(layer=pdk.get_glayer("met2_pin"), size=psize, centered=True).copy() + vinlabel.add_label(text="VIN", layer=pdk.get_glayer("met2_label")) + move_info.append((vinlabel, cm_in.ports["IN_top_met_N"], None)) + + # VOUT + voutlabel = rectangle(layer=pdk.get_glayer("met2_pin"), size=psize, centered=True).copy() + voutlabel.add_label(text="VOUT", layer=pdk.get_glayer("met2_label")) + move_info.append((voutlabel, cm_in.ports["OUT_top_met_N"], None)) + + # VSS (well tie) + vsslabel = rectangle(layer=pdk.get_glayer("met1_pin"), size=psize, centered=True).copy() + vsslabel.add_label(text="VSS", layer=pdk.get_glayer("met1_label")) + move_info.append((vsslabel, cm_in.ports["welltie_N_top_met_N"], None)) + + for comp, prt, alignment in move_info: + alignment = ("c", "b") if alignment is None else alignment + compref = align_comp_to_port(comp, prt, alignment=alignment) + cm_in.add(compref) + + return cm_in.flatten() + + +if __name__ == "__main__": + selected_pdk = gf180 + comp = current_mirror_base(selected_pdk, num_cols=1, Length=1, Width=4, device="nfet", show_netlist=False) + # comp = add_cm_labels(comp, pdk=selected_pdk) + comp.name = "CM" + comp.show() + + # Print the generated netlist + print(comp.info["netlist"].generate_netlist()) + + # Run DRC + drc_result = selected_pdk.drc_magic(comp, comp.name, output_file=Path("DRC/")) + + # Run LVS + netgen_lvs_result = selected_pdk.lvs_netgen( + comp, comp.name, output_file_path=Path("LVS/"), copy_intermediate_files=True + ) \ No newline at end of file diff --git a/blocks/composite/regulated_cascoded_cmirror/cm_wl.py b/blocks/composite/regulated_cascoded_cmirror/cm_wl.py new file mode 100644 index 00000000..be7fc7a8 --- /dev/null +++ b/blocks/composite/regulated_cascoded_cmirror/cm_wl.py @@ -0,0 +1,200 @@ +from glayout import MappedPDK, sky130,gf180 +from glayout import nmos, pmos, tapring,via_stack + +from glayout.spice.netlist import Netlist +from glayout.routing import c_route,L_route,straight_route + +from gdsfactory.component import Component +from gdsfactory.component_reference import ComponentReference +from gdsfactory.cell import cell +from gdsfactory import Component +from gdsfactory.components import text_freetype, rectangle + +from glayout.util.comp_utils import evaluate_bbox, prec_center, align_comp_to_port, prec_ref_center +from glayout.util.snap_to_grid import component_snap_to_grid +from glayout.util.port_utils import rename_ports_by_orientation +from glayout.util.port_utils import add_ports_perimeter + +###### Only Required for IIC-OSIC Docker +import os +import subprocess +from pathlib import Path +# Run a shell, source .bashrc, then printenv +cmd = 'bash -c "source ~/.bashrc && printenv"' +result = subprocess.run(cmd, shell=True, text=True, capture_output=True) +env_vars = {} +for line in result.stdout.splitlines(): + if '=' in line: + key, value = line.split('=', 1) + env_vars[key] = value + +# Now, update os.environ with these +os.environ.update(env_vars) +############################################################################### +from typing import Optional +import time + +def add_lvcm_labels(lvcm_in: Component, + pdk: MappedPDK + ) -> Component: + + lvcm_in.unlock() + # list that will contain all port/comp info + move_info = list() + # create labels and append to info list + # gnd + gndlabel = rectangle(layer=pdk.get_glayer("met2_pin"),size=(0.5,0.5),centered=True).copy() + gndlabel.add_label(text="GND",layer=pdk.get_glayer("met2_label")) + move_info.append((gndlabel,lvcm_in.ports["M_1_B_tie_N_top_met_N"],None)) + + #currentbias + ibias1label = rectangle(layer=pdk.get_glayer("met3_pin"),size=(0.5,0.5),centered=True).copy() + ibias1label.add_label(text="IBIAS1",layer=pdk.get_glayer("met3_label")) + move_info.append((ibias1label,lvcm_in.ports["M_1_A_drain_bottom_met_N"],None)) + + ibias2label = rectangle(layer=pdk.get_glayer("met3_pin"),size=(0.5,0.5),centered=True).copy() + ibias2label.add_label(text="IBIAS2",layer=pdk.get_glayer("met3_label")) + move_info.append((ibias2label,lvcm_in.ports["M_2_A_drain_bottom_met_N"],None)) + + # output + output1label = rectangle(layer=pdk.get_glayer("met2_pin"),size=(0.27,0.27),centered=True).copy() + output1label.add_label(text="IOUT1",layer=pdk.get_glayer("met2_label")) + move_info.append((output1label,lvcm_in.ports["M_3_A_multiplier_0_drain_N"],None)) + + output2label = rectangle(layer=pdk.get_glayer("met2_pin"),size=(0.27,0.27),centered=True).copy() + output2label.add_label(text="IOUT2",layer=pdk.get_glayer("met2_label")) + move_info.append((output2label,lvcm_in.ports["M_4_A_multiplier_0_drain_N"],None)) + + # move everything to position + for comp, prt, alignment in move_info: + alignment = ('c','b') if alignment is None else alignment + compref = align_comp_to_port(comp, prt, alignment=alignment) + lvcm_in.add(compref) + return lvcm_in.flatten() + +def low_voltage_cmirr_netlist(bias_fvf: Component, cascode_fvf: Component, fet_1_ref: ComponentReference, fet_2_ref: ComponentReference, fet_3_ref: ComponentReference, fet_4_ref: ComponentReference) -> Netlist: + + netlist = Netlist(circuit_name='Low_voltage_current_mirror', nodes=['IBIAS1', 'IBIAS2', 'GND', 'IOUT1', 'IOUT2']) + netlist.connect_netlist(bias_fvf.info['netlist'], [('VIN','IBIAS1'),('VBULK','GND'),('Ib','IBIAS1'),('VOUT','local_net_1')]) + netlist.connect_netlist(cascode_fvf.info['netlist'], [('VIN','IBIAS1'),('VBULK','GND'),('Ib', 'IBIAS2'),('VOUT','local_net_2')]) + fet_1A_ref=netlist.connect_netlist(fet_2_ref.info['netlist'], [('D', 'IOUT1'),('G','IBIAS1'),('B','GND')]) + fet_2A_ref=netlist.connect_netlist(fet_4_ref.info['netlist'], [('D', 'IOUT2'),('G','IBIAS1'),('B','GND')]) + fet_1B_ref=netlist.connect_netlist(fet_1_ref.info['netlist'], [('G','IBIAS2'),('S', 'GND'),('B','GND')]) + fet_2B_ref=netlist.connect_netlist(fet_3_ref.info['netlist'], [('G','IBIAS2'),('S', 'GND'),('B','GND')]) + netlist.connect_subnets( + fet_1A_ref, + fet_1B_ref, + [('S', 'D')] + ) + netlist.connect_subnets( + fet_2A_ref, + fet_2B_ref, + [('S', 'D')] + ) + + return netlist + +# @cell +def current_mirror_WL( + pdk: MappedPDK, + width: float = 4.15, + length: float = 2, + fingers: int = 2, + multipliers: int = 1, + ) -> Component: + """ + A low voltage P type current mirror. It has one input brnaches and three output branches. + """ + #top level component + cmwl = Component("current_mirror_WL") + cmwl_ref = prec_ref_center(cmwl) + + #creating fets for output branches + fet = pmos(pdk, width=width, length=length, fingers=fingers, multipliers=multipliers, with_dummy=True, dnwell=False, with_substrate_tap=False) + fet_1_ref = prec_ref_center(fet) + fet_2_ref = prec_ref_center(fet) + fet_3_ref = prec_ref_center(fet) + fet_4_ref = prec_ref_center(fet) + + fet_1_ref.move(cmwl_ref.center).movex(- (evaluate_bbox(fet)[0]/2) - pdk.util_max_metal_seperation()) + fet_2_ref.move(cmwl_ref.center).movex(- (3*evaluate_bbox(fet)[0]/2) - 2*pdk.util_max_metal_seperation()) + fet_3_ref.move(cmwl_ref.center).movex( (evaluate_bbox(fet)[0]/2) + pdk.util_max_metal_seperation()) + fet_4_ref.move(cmwl_ref.center).movex( (3*evaluate_bbox(fet)[0]/2) + 2*pdk.util_max_metal_seperation()) + + cmwl.add(fet_1_ref) + cmwl.add(fet_2_ref) + cmwl.add(fet_3_ref) + cmwl.add(fet_4_ref) + + # top_level << c_route(pdk, bias_fvf_ref.ports["A_multiplier_0_gate_E"], bias_fvf_ref.ports["B_gate_bottom_met_E"]) + # top_level << c_route(pdk, cascode_fvf_ref.ports["A_multiplier_0_gate_W"], bias_fvf_ref.ports["A_multiplier_0_gate_W"]) + # top_level << straight_route(pdk, cascode_fvf_ref.ports["B_gate_bottom_met_E"], fet_3_ref.ports["multiplier_0_gate_W"]) + + #creating vias for routing + viam2m3 = via_stack(pdk, "met2", "met3", centered=True) + gate_1_via = cmwl << viam2m3 + gate_1_via.move(fet_1_ref.ports["multiplier_0_gate_W"].center).movex(-1) + gate_2_via = cmwl << viam2m3 + gate_2_via.move(fet_2_ref.ports["multiplier_0_gate_W"].center).movex(-1) + gate_3_via = cmwl << viam2m3 + gate_3_via.move(fet_3_ref.ports["multiplier_0_gate_E"].center).movex(1) + gate_4_via = cmwl << viam2m3 + gate_4_via.move(fet_4_ref.ports["multiplier_0_gate_E"].center).movex(1) + + source_2_via = cmwl << viam2m3 + drain_1_via = cmwl << viam2m3 + source_2_via.move(fet_2_ref.ports["multiplier_0_source_E"].center).movex(1.5) + drain_1_via.move(fet_1_ref.ports["multiplier_0_drain_W"].center).movex(-1) + + source_4_via = cmwl << viam2m3 + drain_3_via = cmwl << viam2m3 + source_4_via.move(fet_4_ref.ports["multiplier_0_source_W"].center).movex(-1) + drain_3_via.move(fet_3_ref.ports["multiplier_0_drain_E"].center).movex(1.5) + + #routing + cmwl << straight_route(pdk, fet_2_ref.ports["multiplier_0_source_E"], source_2_via.ports["bottom_met_W"]) + cmwl << straight_route(pdk, fet_1_ref.ports["multiplier_0_drain_W"], drain_1_via.ports["bottom_met_E"]) + cmwl << straight_route(pdk, fet_4_ref.ports["multiplier_0_source_W"], source_4_via.ports["bottom_met_E"]) + cmwl << straight_route(pdk, fet_3_ref.ports["multiplier_0_drain_E"], drain_3_via.ports["bottom_met_W"]) + cmwl << c_route(pdk, source_2_via.ports["top_met_N"], drain_1_via.ports["top_met_N"], extension=0.5*evaluate_bbox(fet)[1], width1=0.32, width2=0.32, cwidth=0.32, e1glayer="met3", e2glayer="met3", cglayer="met2") + cmwl << c_route(pdk, source_4_via.ports["top_met_N"], drain_3_via.ports["top_met_N"], extension=0.5*evaluate_bbox(fet)[1], width1=0.32, width2=0.32, cwidth=0.32, e1glayer="met3", e2glayer="met3", cglayer="met2") + + cmwl << straight_route(pdk, fet_1_ref.ports["multiplier_0_gate_W"], gate_1_via.ports["bottom_met_E"]) + cmwl << straight_route(pdk, fet_2_ref.ports["multiplier_0_gate_W"], gate_2_via.ports["bottom_met_E"]) + cmwl << straight_route(pdk, fet_3_ref.ports["multiplier_0_gate_E"], gate_3_via.ports["bottom_met_W"]) + cmwl << straight_route(pdk, fet_4_ref.ports["multiplier_0_gate_E"], gate_4_via.ports["bottom_met_W"]) + + cmwl << c_route(pdk, gate_1_via.ports["top_met_S"], gate_3_via.ports["top_met_S"], extension=(1.2*width+0.6), cglayer='met2') + cmwl << c_route(pdk, gate_2_via.ports["top_met_S"], gate_4_via.ports["top_met_S"], extension=(1.2*width-0.6), cglayer='met2') + + cmwl << straight_route(pdk, fet_1_ref.ports["multiplier_0_source_W"], fet_1_ref.ports["tie_W_top_met_W"], glayer1='met1', width=0.2) + cmwl << straight_route(pdk, fet_3_ref.ports["multiplier_0_source_W"], fet_3_ref.ports["tie_W_top_met_W"], glayer1='met1', width=0.2) + + cmwl.add_ports(fet_1_ref.get_ports_list(), prefix="M_3_B_") + cmwl.add_ports(fet_2_ref.get_ports_list(), prefix="M_3_A_") + cmwl.add_ports(fet_3_ref.get_ports_list(), prefix="M_4_B_") + cmwl.add_ports(fet_4_ref.get_ports_list(), prefix="M_4_A_") + + component = component_snap_to_grid(rename_ports_by_orientation(cmwl)) + #component.info['netlist'] = low_voltage_cmirr_netlist(bias_fvf, cascode_fvf, fet_1_ref, fet_2_ref, fet_3_ref, fet_4_ref) + + return component + +if __name__ == "__main__": + comp =current_mirror_WL(gf180) + # comp.pprint_ports() + #comp =add_lvcm_labels(comp,sky130) + comp.name = "CMWL" + comp.show() + #print(comp.info['netlist'].generate_netlist()) + #print("...Running DRC...") + #drc_result = sky130.drc_magic(comp, "LVCM") + ## Klayout DRC + #drc_result = sky130.drc(comp) + + #time.sleep(5) + + #print("...Running LVS...") + #lvs_res=sky130.lvs_netgen(comp, "LVCM") + #print("...Saving GDS...") + #comp.write_gds('out_LVCM.gds') diff --git a/blocks/composite/regulated_cascoded_cmirror/deep_nwell.py b/blocks/composite/regulated_cascoded_cmirror/deep_nwell.py new file mode 100644 index 00000000..297c9404 --- /dev/null +++ b/blocks/composite/regulated_cascoded_cmirror/deep_nwell.py @@ -0,0 +1,180 @@ +from glayout import MappedPDK, sky130, gf180 +from glayout import nmos, pmos, tapring, via_stack + +# from glayout.placement.two_transistor_interdigitized import two_nfet_interdigitized, two_pfet_interdigitized +from gdsfactory import cell +from gdsfactory.component import Component +from gdsfactory.components import text_freetype, rectangle +from pathlib import Path + +from glayout.routing import c_route, L_route, straight_route +from glayout.spice.netlist import Netlist + +from glayout.util.port_utils import add_ports_perimeter, rename_ports_by_orientation +from glayout.util.comp_utils import ( + evaluate_bbox, + prec_center, + prec_ref_center, + align_comp_to_port, +) +from glayout.util.snap_to_grid import component_snap_to_grid +from typing import Optional, Union + + +from cm_v import current_mirror_base +from cm_sb import self_biased_cascode_current_mirror +from cm_rc import regulated_cascode_current_mirror +from input import input_stage +from bias import bias_stage + +###### Only Required for IIC-OSIC Docker +import os +import subprocess + +# Run a shell, source .bashrc, then printenv +cmd = 'bash -c "source ~/.bashrc && printenv"' +result = subprocess.run(cmd, shell=True, text=True, capture_output=True) +env_vars = {} +for line in result.stdout.splitlines(): + if "=" in line: + key, value = line.split("=", 1) + env_vars[key] = value + +# Now, update os.environ with these +os.environ.update(env_vars) + + + +# @validate_arguments +def rec_dnwell( + pdk: MappedPDK, + Width: float = 1, + Length: Optional[float] = 1, + with_tie: Optional[bool] = True, + with_dummy: Optional[bool] = True, + tie_layers: tuple[str, str] = ("met2", "met1"), + show_netlist: Optional[bool] = False, + add_labels: bool = True, + **kwargs, +) -> Component: + """An instantiable self biased casoded current mirror that returns a Component object.""" + + pdk.activate() + maxmet_sep = pdk.util_max_metal_seperation() + + # Create the component + top_level = Component(name="rec_nwell") + top_level.name = "rec_nwell" + Length = Length if Length is not None else pdk.get_grule("poly")["min_width"] + top_ref = prec_ref_center(top_level) + + snap = pdk.snap_to_2xgrid + center = top_level.center + + rec=rectangle(layer=pdk.get_glayer("dnwell"), size=(30,115), centered=True) + rec_ref = prec_ref_center(rec) + #rec_ref.move(center).movex(36.56 + 8 * pdk.util_max_metal_seperation()) + top_level.add(rec_ref) + # # ------------------------------------------------------------------------- + # # CREATING THE VANILLA CURRENT MIRROR STAGE + # # ------------------------------------------------------------------------- + # print("Creating Vanilla Current Mirror ...") + + # VCM = current_mirror_base( + # pdk, + # num_cols=1, + # Length=1, + # Width=4, + # device="nfet", + # with_substrate_tap=False, + # add_labels=False, + # ) + # vcm_ref = prec_ref_center(VCM) + # vcm_ref.move(center).movex(36.56 + 4 * pdk.util_max_metal_seperation() + # ).movey(-81.12 / 2) + + # top_level.add(vcm_ref) + # top_level.add_ports(vcm_ref.get_ports_list(), prefix="vcm_") + + # # ------------------------------------------------------------------------- + # # CREATING THE SELF-BIASED CURRENT MIRROR STAGE + # # ------------------------------------------------------------------------- + # print("Creating Self-Biased Current Mirror ...") + + # SBCM = self_biased_cascode_current_mirror( + # pdk, num_cols=1, Length=1, Width=4, device="nfet", add_labels=False + # ) + # sbcm_ref = prec_ref_center(SBCM) + # sbcm_ref.move(center).movex(36.56 + 4 * pdk.util_max_metal_seperation() + # ) + + # top_level.add(sbcm_ref) + # top_level.add_ports(sbcm_ref.get_ports_list(), prefix="sbcm_") + + # # ------------------------------------------------------------------------- + # # CREATING THE REGULATED CASCODE CURRENT MIRROR STAGE + # # ------------------------------------------------------------------------- + # print("Creating Regulated Cascoded Current Mirror ...") + + # RCCM = regulated_cascode_current_mirror( + # pdk, num_cols=2, Length=1, Width=4, device="nfet", show_netlist=False, add_labels=False + # ) + # rccm_ref = prec_ref_center(RCCM) + # rccm_ref.move(center).movex(36.56 + 4 * pdk.util_max_metal_seperation() + # ).movey(+81.12 / 2) + + # top_level.add(rccm_ref) + # top_level.add_ports(rccm_ref.get_ports_list(), prefix="rccm_") + + # top_level.add_padding( + # layers=(pdk.get_glayer("dnwell"),), + # default=pdk.get_grule("pwell", "dnwell")["min_enclosure"], + # ) + + core = top_level.copy() # so we don't mutate while measuring + core_flat = core.flatten() # include all placed children + + xmin, xmax = core_flat.xmin, core_flat.xmax + ymin, ymax = core_flat.ymin, core_flat.ymax + + core_w = xmax - xmin + core_h = ymax - ymin + + cx = snap((xmin + xmax) / 2) + cy = snap((ymin + ymax) / 2) + + tap_separation = pdk.get_grule("dnwell", "active_tap")["min_separation"] + tap_encloses = ( + (snap(4 * tap_separation + core_w)), + (snap(4 * tap_separation + core_h)), + ) + # subtap_enclosure = ( + # 2.5 * (subtap_sep + interdigitized_fets.xmax), + # 2.5 * (subtap_sep + interdigitized_fets.ymax), + # ) + + ringtoadd = top_level << tapring( + pdk, + enclosed_rectangle=tap_encloses, + sdlayer="p+s/d", + horizontal_glayer= "met1", + vertical_glayer = "met1", + ) + ringtoadd.move((cx, cy)) + + top_level = component_snap_to_grid(rename_ports_by_orientation(top_level)) + return top_level + + + +if __name__ == "__main__": + selected_pdk = gf180 + comp = rec_dnwell(selected_pdk) + + comp.name = "DNWell Rect" + comp.show() + # Write the current mirror layout to a GDS file + comp.write_gds("GDS/deep_nwell_rect.gds") + + # DRC Checks + drc_result = selected_pdk.drc_magic(comp, comp.name, output_file=Path("DRC/")) \ No newline at end of file diff --git a/blocks/composite/regulated_cascoded_cmirror/design_proposal/README.md b/blocks/composite/regulated_cascoded_cmirror/design_proposal/README.md new file mode 100644 index 00000000..845b82fa --- /dev/null +++ b/blocks/composite/regulated_cascoded_cmirror/design_proposal/README.md @@ -0,0 +1,95 @@ +## Team Mahowalders Project proposal, Chipathon 2025 +### Project: Towards Precision Current Mirrors + +:point_right: Tapeout Design [Here](https://docs.google.com/presentation/d/1KF9h7LAYK9whPO62wzKPA4DEyUEtzbTsQ4-uteLiDPU/edit?slide=id.p1#slide=id.p1) + +:point_right: progress @ Google Sheets [Here](https://docs.google.com/spreadsheets/d/1k9veHdDh-e81fpdIpsUblsUgEMs8aU_Jj_eBLXmVOYY/edit?usp=sharing) + +:point_right: Proposal @ Google Docs [link](https://docs.google.com/document/d/1FZdyJ7MXu66QQ6_0kkzPwPryskKX2VRuOPmt5tDAb5Y/edit?usp=sharing) + +**Motivation:** With the rise of analog computation for low-power edge intelligence and sensor systems, the demand for robust bias generation circuits has significantly increased. Bias current sources are fundamental to analog and mixed-signal designs, enabling precise control in amplifiers, comparators, sensor front-ends, and a wide range of other analog building blocks. Ideally, current sources deliver a quasi-constant current when transistors operate in the saturation region, where the output current is largely independent of the drain-to-source voltage. Achieving bias current sources that closely approximate this ideal behaviour is essential to ensure proper circuit operation. However, traditional current mirrors, though widely used, exhibit poor output impedance and limited voltage headroom, which can result in unstable biasing under varying conditions. When the output voltage exceeds the linear range, the current mirror output continues to increase linearly in the saturation region instead of reaching a plateau. This non-ideal behaviour makes such mirrors unsuitable for delivering stable bias currents, often leading to degraded performance in circuits that rely on precise biasing. + +**Objective:** This project proposes the automated design and layout of a high-impedance, energy-efficient bias generation block using regulated current mirror architectures. Integrated into the gLayout toolchain (Python2GDS), this design aims to enhance layout portability, stability, and scalability across process corners. + +**Design:** +We compare three bias current mirror architectures: + +* Vanilla Current Mirror (VCM), as a reference +* Self-Biased Common-Source CM (SB-CM), with improved impedance, moderate complexity +* Regulated Cascode CM (RC-CM), with high output impedance, better stability, but requires auxiliary bias + +All three versions will be parametrically instantiated via gLayout, enabling on-demand generation and automated layout. A testbench OTA stage will be used to convert an input voltage into current, allowing characterisation of each mirror’s response and stability under load. + +**Expected Contributions:** + +* gLayout-compatible IP blocks for advanced analog biasing +* On-silicon testing of all three architectures, with a focus on RC-CM +* Performance benchmarking and trade-off analysis (stability, impedance, layout area, and bias dependencies) + +**Applications:** +The proposed IP targets analog designs where stable biasing is critical, such as sensor front-ends, neural interface systems, and low-frequency amplifiers. The RC-CM in particular can significantly improve performance in circuits sensitive to bias drift, without requiring extensive overhead. The regulated cascode current mirror provides a more robust stable current source than vanilla current mirrors that are usually used as is in analog circuits using biasin. By using this improved version, a wide range of analog circuits applications such as bias current generators, op-amps or sensor front-end where stable and accurate biasing is crucial to ensure the expected functioning of the circuit can benefit from the improved current mirror. + +### **Block: Vanilla Current Mirror (VCM)** +![](./_images/1.png) +A classical current mirror consists of two transistors: the first Q20 has its drain and gate connected (forming a diode-connected structure) and receives the input current, while the second transistor Q21 mirrors this current at its output. The output current is ideally a scaled replica of the input, determined by the ratio of the transistors' width-to-length (W/L) dimensions. + +### **Block: Self-biased Common Source Current Mirror** +![](./_images/2.png) +The self-biased common-source current mirror uses a feedback mechanism to improve current stability and output impedance. Q22 receives the reference current through a diode connection, setting the gate voltage shared with Q24, which mirrors the current. Q23 and Q25, connected in a common-source configuration, form a self-biasing loop that regulates the source voltage of the upper transistors. This feedback stabilises the gate-source voltage, reducing output current variation and enhancing performance compared to a basic current mirror. + +### **Block: Regulated Cascoded Current Mirror** +![](./_images/3.png) +The regulated cascode current mirror shown uses an auxiliary biasing loop to significantly boost output impedance and current stability. Q26 and Q27 form a standard current mirror, while Q28 and Q30 act as cascode transistors, shielding the mirroring devices from output voltage swings. Q29 senses the drain voltage of Q28 and regulates it via Q31, creating a feedback loop that stabilizes the cascode node. This regulation ensures minimal variation in output current despite changes in output voltage, making the design ideal for precision analog applications demanding high output resistance and improved bias accuracy. + +### **Diagram: Proposed Top Integration and Pinout:** +![](./_images/finalS.png) +![](./_images/5.png) + +### **Pinlist:** + +| Pin Name | type | Description | Pin Name | type | Description | +| :---: | :---: | :---: | :---: | :---: | :---: | +| Vin\_OTAI | input | Input of reference current source | Vout\_nVCM | output | Output of nFET VCM | +| Vin\_OTAB | input | Input of RC bias current | Vout\_pVCM | output | Output of pFET VCM | +| Vbias\_OTAI | input\* | Bias Input of the reference current source | Vout\_SB\_nCM | output | Output of nFET SBCM | +| Vbias\_OTAB | input\* | Bias Input of RC bias current | Vout\_RC\_nCM | output | Output of nFET RCCM | + +\*Can be potentially merged + +#### Alternative Pin-out if Current Sources aren’t necessary, can be provided directly from the PCB. + +![](./_images/6_1.png) +![](./_images/6_2.png) + +A sense resistor with sense amplifiers and MCU can be used to monitor current output and relative performance of the blocks, spatially, if the same MCU also digitally control the input current generator. + +### Questions/Doubts/Suggestions + +* Applications \-Integration in larger design + * Temperature compensation + * Current Source: external or OTA, or simple PolyRes with fixed reference, Diode-connected FETs + * Mux’ed Output? + * SKY130 to GF180 transition + +### Reference: + +1. Michal, Vratislav. "Regulated Cascode Current Mirror with Improved Voltage Swing." 2022 International Conference on Applied Electronics (AE). IEEE, 2022\. DOI : 10.1109/AE54730.2022.9920096 +2. Garde, M. Pilar, et al. "Wide-Swing Class AB Regulated Cascode Current Mirror." *2020 IEEE International Symposium on Circuits and Systems (ISCAS)*. IEEE, 2020\. +3. Pretl, Harald, and Matthias Eberlein. "Fifty nifty variations of two-transistor circuits: A tribute to the versatility of MOSFETs." *IEEE Solid-State Circuits Magazine* 13.3 (2021): 38-46 and *references therein* +4. GF180 PadFrame Document: [PADFrame \- Chipathon 2023](https://docs.google.com/presentation/d/12w4WBoleFAE4UePdoUf-bxsZR_BttwY3wknBPPJrEHE/edit?usp=sharing) + +### **Team members, Tasks, and Week-by-week schedule** + +| Chipathon Week | Task | Team member | Milestone | +| :---- | :---- | :---- | :---- | +| 29,30 | Xschem Schematic Preparation and Testing | Quentine, Sudhanshu | Uploading xschem block symbols | +| 29,30 | Pre-PEX simulation and sizing optimisation | Quentine | Publication of the first sim results and plots | +| 29,30 | Porting of blocks from Sky130 to GF180 and DRC Cleaning | Sudhanshu | Push of the first DRC clean GDS of blocks | +| 30,31 | LVS Verification | Quentine | Finalising block GDS | +| 32,33 | **Top Integration / Readiness Check (August 16, go/no decision)** | All Members | **Push of the whole Design GDS, pass go/no review** | +| 33,34 | Creating Test-Bench and Post-PEX ngspice simulations | | Publication of the first Post-PEX sim results and plots | +| 35,36 | Layout Optimization | | Iterative update to Design GDS | +| 35,36 | Parding Integration | | Iterative update to Design GDS | +| 36,37,38 | Final testing and Delivery of GDS | | Communicate and submit GDS | +| 36,37,38 | CACE Integration for Characterisation and Verification | | Upload the Characterisation report of CACE | +| 39, 40 | Documentation: Design and Testing Procedure | | Post-mortem, closing Push and acceptance of merge with glayout repo | diff --git a/blocks/composite/regulated_cascoded_cmirror/design_proposal/Team Mahowalders Chipathon 25.pdf b/blocks/composite/regulated_cascoded_cmirror/design_proposal/Team Mahowalders Chipathon 25.pdf new file mode 100644 index 00000000..358980e9 Binary files /dev/null and b/blocks/composite/regulated_cascoded_cmirror/design_proposal/Team Mahowalders Chipathon 25.pdf differ diff --git a/blocks/composite/regulated_cascoded_cmirror/design_proposal/_images/1.png b/blocks/composite/regulated_cascoded_cmirror/design_proposal/_images/1.png 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b/blocks/composite/regulated_cascoded_cmirror/design_proposal/_images/sim.png differ diff --git a/blocks/composite/regulated_cascoded_cmirror/design_proposal/_images/status.png b/blocks/composite/regulated_cascoded_cmirror/design_proposal/_images/status.png new file mode 100644 index 00000000..7beed895 Binary files /dev/null and b/blocks/composite/regulated_cascoded_cmirror/design_proposal/_images/status.png differ diff --git a/blocks/composite/regulated_cascoded_cmirror/design_proposal/_images/tops.png b/blocks/composite/regulated_cascoded_cmirror/design_proposal/_images/tops.png new file mode 100644 index 00000000..afab1162 Binary files /dev/null and b/blocks/composite/regulated_cascoded_cmirror/design_proposal/_images/tops.png differ diff --git a/blocks/composite/regulated_cascoded_cmirror/design_proposal/_images/vcm.png b/blocks/composite/regulated_cascoded_cmirror/design_proposal/_images/vcm.png new file mode 100644 index 00000000..65f3670d Binary files /dev/null and b/blocks/composite/regulated_cascoded_cmirror/design_proposal/_images/vcm.png differ diff --git a/blocks/composite/regulated_cascoded_cmirror/gds/antenna.lyrdb b/blocks/composite/regulated_cascoded_cmirror/gds/antenna.lyrdb new file mode 100644 index 00000000..3232df3f --- /dev/null +++ b/blocks/composite/regulated_cascoded_cmirror/gds/antenna.lyrdb @@ -0,0 +1,151 @@ + + + GF180 ANTENNA DRC Run Report at + /foss/designs/gLayout-mahowalders/blocks/composite/regulated_cascoded_cmirror/gds/top.gds + drc: script='/foss/pdks/gf180mcuD/libs.tech/klayout/macros/gf180mcu_drc.lydrc' + TOP + + + + + ANT.1 + ANT.1: Maximum ratio of Poly2 perimeter area to related gate oxide area: 200 + + + + + ANT.8 + ANT.8: Maximum ratio of contact area to related gate oxide area: 10 + + + + + ANT.16_i_ANT.2 + ANT.16_i_ANT.2: Maximum ratio of Metal1 perimeter + area to related thin gate oxide area: 400 + + + + + ANT.16_ii_ANT.2 + ANT.16_ii_ANT.2: Maximum ratio of Metal1 perimeter + area to related thick gate oxide area: 400 + + + + + ANT.16_i_ANT.9 + ANT.16_i_ANT.9: Maximum ratio of Via1 area to related thin gate oxide area: 20 + + + + + ANT.16_ii_ANT.9 + ANT.16_ii_ANT.9: Maximum ratio of Via1 area to related thick gate oxide area: 20 + + + + + ANT.16_i_ANT.3 + ANT.16_i_ANT.3: Maximum ratio of Metal2 perimeter area to related gate oxide area: 400 + + + + + ANT.16_ii_ANT.3 + ANT.16_ii_ANT.3: Maximum ratio of Metal2 perimeter area to related gate oxide area: 400 + + + + + ANT.16_i_ANT.10 + ANT.16_i_ANT.10: Maximum ratio of Via2 area to related thin gate oxide area: 20 + + + + + ANT.16_ii_ANT.10 + ANT.16_ii_ANT.10: Maximum ratio of Via2 area to related thick gate oxide area: 20 + + + + + ANT.16_i_ANT.4 + ANT.16_i_ANT.4: Maximum ratio of Metal3 perimeter area to related thin gate oxide area: 400 + + + + + ANT.16_ii_ANT.4 + ANT.16_ii_ANT.4: Maximum ratio of Metal3 perimeter area to related thick gate oxide area: 400 + + + + + ANT.16_i_ANT.11 + ANT.16_i_ANT.11: Maximum ratio of Via3 area to related thin gate oxide area: 20 + + + + + ANT.16_ii_ANT.11 + ANT.16_ii_ANT.11: Maximum ratio of Via3 area to related thick gate oxide area: 20 + + + + + ANT.16_i_ANT.5 + ANT.16_i_ANT.5: Maximum ratio of Metal4 perimeter area to related gate oxide area: 400 + + + + + ANT.16_ii_ANT.5 + ANT.16_ii_ANT.5: Maximum ratio of Metal4 perimeter area to related gate oxide area: 400 + + + + + ANT.16_i_ANT.12 + ANT.16_i_ANT.12: Maximum ratio of Via4 area to related thin gate oxide area: 20 + + + + + ANT.16_ii_ANT.12 + ANT.16_ii_ANT.12: Maximum ratio of Via4 area to related thick gate oxide area: 20 + + + + + ANT.16_i_ANT.6 + ANT.16_i_ANT.6: Maximum ratio of Metal5 perimeter area to related thin gate oxide area: 400 + + + + + ANT.16_ii_ANT.6 + ANT.16_ii_ANT.6: Maximum ratio of Metal5 perimeter area to related thick gate oxide area 400 + + + + + ANT.16_iii_ANT.14_MT_MIMB + ANT.16_iii_ANT.14_MT_MIMB: Maximum ratio of each of the Top metal layer perimeter + area to related MIM area is 400 + + + + + + + TOP + + + + + + + + + diff --git a/blocks/composite/regulated_cascoded_cmirror/gds/density.lyrdb b/blocks/composite/regulated_cascoded_cmirror/gds/density.lyrdb new file mode 100644 index 00000000..096929bd --- /dev/null +++ b/blocks/composite/regulated_cascoded_cmirror/gds/density.lyrdb @@ -0,0 +1,15701 @@ + + + GF180 DENSITY DRC Run Report at + /foss/designs/gLayout-mahowalders/blocks/composite/regulated_cascoded_cmirror/gds/top.gds + drc: script='/foss/pdks/gf180mcuD/libs.tech/klayout/macros/gf180mcu_drc.lydrc' + TOP + + + + + PL.8 + PL.8 : Poly2 coverage over the entire die shall be 14%. + Dummy poly2 lines must be added to meet the minimum poly2 density requirement. : 14% + + + + + M1.4 + M1.4 : Metal1 coverage over the entire die shall be >30% + (Refer to section 13.0 for Dummy Metal fill guidelines. + Customer needs to ensure enough dummy metal to satisfy Metal1 coverage) : 30% + + + + + M2.4 + M2.4 : Metal2 coverage over the entire die shall be >30% + (Refer to section 13.0 for Dummy Metal fill guidelines. + Customer needs to ensure enough dummy metal to satisfy Metal2 coverage) : 30% + + + + + M3.4 + M3.4 : metal3 coverage over the entire die shall be >30% + (Refer to section 13.0 for Dummy Metal fill guidelines. + Customer needs to ensure enough dummy metal to satisfy metal3 coverage) : 30% + + + + + M4.4 + M4.4 : metal4 coverage over the entire die shall be >30% + (Refer to section 13.0 for Dummy Metal fill guidelines. + Customer needs to ensure enough dummy metal to satisfy metal4 coverage) : 30% + + + + + M5.4 + M5.4 : metal5 coverage over the entire die shall be >30% + (Refer to section 13.0 for Dummy Metal fill guidelines. + Customer needs to ensure enough dummy metal to satisfy metal5 coverage) : 30% + + + + + MT.3 + MT.3 : MetalTop coverage over the entire die shall be >30% + (Refer to section 10.3 for Dummy Metal-fill guidelines. + Customer needs to ensure enough dummy metal to satisfy Metaln coverage) : 30% + + + + + + + TOP + + + + + + + + + + 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K(ppolyf_u_dw RES3 + E(R 0 0) + E(L 1 0) + E(W 1 0) + ) + K(npolyf_s RES3 + E(R 0 0) + E(L 1 0) + E(W 1 0) + ) + K(npolyf_s_dw RES3 + E(R 0 0) + E(L 1 0) + E(W 1 0) + ) + K(ppolyf_s RES3 + E(R 0 0) + E(L 1 0) + E(W 1 0) + ) + K(ppolyf_s_dw RES3 + E(R 0 0) + E(L 1 0) + E(W 1 0) + ) + K(ppolyf_u_1k RES3 + E(R 0 0) + E(L 1 0) + E(W 1 0) + ) + K(ppolyf_u_1k_dw RES3 + E(R 0 0) + E(L 1 0) + E(W 1 0) + ) + K(ppolyf_u_1k_6p0 RES3 + E(R 0 0) + E(L 1 0) + E(W 1 0) + ) + K(ppolyf_u_1k_6p0_dw RES3 + E(R 0 0) + E(L 1 0) + E(W 1 0) + ) + K(rm1 RES + E(R 0 0) + E(L 1 0) + E(W 1 0) + ) + K(rm2 RES + E(R 0 0) + E(L 1 0) + E(W 1 0) + ) + K(rm3 RES + E(R 0 0) + E(L 1 0) + E(W 1 0) + ) + K(tm9k RES + E(R 0 0) + E(L 1 0) + E(W 1 0) + ) + K(cap_mim_2f0_m4m5_noshield CAP + E(C 0 0) + E(A 1 0) + E(P 1 0) + ) + K(cap_nmos_03v3 CAP + E(C 0 0) + E(A 1 0) + E(P 1 0) + ) + K(cap_nmos_03v3_dn CAP + E(C 0 0) + E(A 1 0) + E(P 1 0) + ) + K(cap_pmos_03v3 CAP + E(C 0 0) + E(A 1 0) + E(P 1 0) + ) + K(cap_pmos_03v3_dn CAP + E(C 0 0) + E(A 1 0) + E(P 1 0) + ) + K(cap_nmos_06v0 CAP + E(C 0 0) + E(A 1 0) + E(P 1 0) + ) + K(cap_nmos_06v0_dn CAP + E(C 0 0) + E(A 1 0) + E(P 1 0) + ) + K(cap_pmos_06v0 CAP + E(C 0 0) + E(A 1 0) + E(P 1 0) + ) + K(cap_pmos_06v0_dn CAP + E(C 0 0) + E(A 1 0) + E(P 1 0) + ) + K(cap_nmos_03v3_b CAP + E(C 0 0) + E(A 1 0) + E(P 1 0) + ) + K(cap_pmos_03v3_b CAP + E(C 0 0) + E(A 1 0) + E(P 1 0) + ) + K(cap_nmos_06v0_b CAP + E(C 0 0) + E(A 1 0) + E(P 1 0) + ) + K(cap_pmos_06v0_b CAP + E(C 0 0) + E(A 1 0) + E(P 1 0) + ) + K(pfet_03v3_dss MOS4) + K(pfet_05v0_dss MOS4) + K(pfet_06v0_dss MOS4) + K(pfet_03v3_dn_dss MOS4) + K(pfet_05v0_dn_dss MOS4) + K(pfet_06v0_dn_dss MOS4) + K(nfet_03v3_dss MOS4) + K(nfet_05v0_dss MOS4) + K(nfet_06v0_dss MOS4) + K(nfet_03v3_dn_dss MOS4) + K(nfet_05v0_dn_dss MOS4) + K(nfet_06v0_dn_dss MOS4) + K(efuse RES) + D(D$pfet_03v3 pfet_03v3 + T(S + R(l10 (-316 -1000) (116 2000)) + ) + T(G + R(l13 (-200 -1000) (400 2000)) + ) + T(D + R(l10 (200 -1000) (116 2000)) + ) + T(B + R(l7 (-200 -1000) (400 2000)) + ) + ) + D(D$pfet_03v3$1 pfet_03v3 + T(S + R(l10 (-320 -1000) (120 2000)) + ) + T(G + R(l13 (-200 -1000) (400 2000)) + ) + T(D + R(l10 (200 -1000) (120 2000)) + ) + T(B + R(l7 (-200 -1000) (400 2000)) + ) + ) + D(D$pfet_05v0 pfet_05v0 + T(S + R(l10 (-138 -90) (88 180)) + ) + T(G + R(l13 (-50 -90) (100 180)) + ) + T(D + R(l10 (50 -90) (88 180)) + ) + T(B + R(l7 (-50 -90) (100 180)) + ) + ) + D(D$nfet_03v3 nfet_03v3 + T(S + R(l12 (-216 -800) (116 1600)) + ) + T(G + R(l13 (-100 -800) (200 1600)) + ) + T(D + R(l12 (100 -800) (116 1600)) + ) + T(B + R(l1 (-100 -800) (200 1600)) + ) + ) + D(D$nfet_03v3$1 nfet_03v3 + T(S + R(l12 (-220 -800) (120 1600)) + ) + T(G + R(l13 (-100 -800) (200 1600)) + ) + T(D + R(l12 (100 -800) (120 1600)) + ) + T(B + R(l1 (-100 -800) (200 1600)) + ) + ) + D(D$nfet_05v0 nfet_05v0 + T(S + R(l12 (-148 -66) (88 132)) + ) + T(G + R(l13 (-60 -66) (120 132)) + ) + T(D + R(l12 (60 -66) (88 132)) + ) + T(B + R(l1 (-60 -66) (120 132)) + ) + ) + D(D$nfet_03v3_dn nfet_03v3_dn + T(S + R(l12 (-216 -400) (116 800)) + ) + T(G + R(l13 (-100 -400) (200 800)) + ) + T(D + R(l12 (100 -400) (116 800)) + ) + T(B + R(l3 (-100 -400) (200 800)) + ) + ) + D(D$nfet_03v3_dn$1 nfet_03v3_dn + T(S + R(l12 (-220 -400) (120 800)) + ) + T(G + R(l13 (-100 -400) (200 800)) + ) + T(D + R(l12 (100 -400) (120 800)) + ) + T(B + R(l3 (-100 -400) (200 800)) + ) + ) + D(D$diode_nd2ps_06v0 diode_nd2ps_06v0 + T(A + R(l3 (-1000 -1000) (2000 2000)) + ) + T(C + R(l72 (-1000 -1000) (2000 2000)) + ) + ) + D(D$diode_pd2nw_06v0 diode_pd2nw_06v0 + T(A + R(l78 (-1000 -1000) (2000 2000)) + ) + T(C + R(l79 (-1000 -1000) (2000 2000)) + ) + ) + D(D$ppolyf_u ppolyf_u + T(A + R(l13 (-1102 -4000) (102 8000)) + ) + T(B + R(l13 (1000 -4000) (102 8000)) + ) + T(W + R(l1 (-1000 -4000) (2000 8000)) + ) + ) + X(TOP + R((344599 139068) (172627 171658)) + N(1 I(VSS) + R(l2 (395682 211617) (51084 240)) + R(l2 (-102167 0) (240 93694)) + R(l2 (101687 -93694) (240 93694)) + R(l2 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+ D(159 D$diode_pd2nw_06v0 + Y(499947 269180) + E(A 100) + E(P 40) + T(A 317) + T(C 7) + ) + D(160 D$diode_pd2nw_06v0 + Y(502163 269180) + E(A 100) + E(P 40) + T(A 317) + T(C 7) + ) + D(161 D$diode_pd2nw_06v0 + Y(504379 269180) + E(A 100) + E(P 40) + T(A 317) + T(C 7) + ) + D(162 D$diode_pd2nw_06v0 + Y(506595 269180) + E(A 100) + E(P 40) + T(A 317) + T(C 7) + ) + D(163 D$ppolyf_u + Y(511003 223559) + E(R 87.5) + E(L 10) + E(W 40) + E(A 400) + E(P 100) + T(A 149) + T(B 200) + T(W 499) + ) + D(164 D$ppolyf_u + Y(511132 243389) + E(R 87.5) + E(L 10) + E(W 40) + E(A 400) + E(P 100) + T(A 222) + T(B 228) + T(W 499) + ) + D(165 D$ppolyf_u + Y(511063 263404) + E(R 87.5) + E(L 10) + E(W 40) + E(A 400) + E(P 100) + T(A 317) + T(B 366) + T(W 499) + ) + ) +) +H( + K(DIODE_PD2NW_06V0 DIODE) + K(DIODE_ND2PS_06V0 DIODE) + X(TOP + N(1 I(EN)) + N(2 I(VDD)) + N(3 I(VSS)) + N(4 I(VIN)) + N(5 I(VBIAS)) + N(6 I(VCM_OUT)) + N(7 I(BCM_OUT)) + N(8 I(CCM_OUT)) + N(9 I(VIN_OUT)) + N(10 I(PU)) + N(11 I(PD)) + N(12 I(ENA)) + N(13 I(VIN_INT)) + N(14 I(VBIAS_INT)) + N(15 I('1.NET1')) + N(16 I('1.NET2')) + N(17 I('1.NET3')) + N(18 I('1.NET7')) + N(19 I('1.NET4')) + N(20 I('1.NET6')) + N(21 I('1.NET5')) + N(22 I('1.NET8')) + N(23 I('1.NET9')) + N(24 I('3.NET1')) + N(25 I('2.NET1')) + N(26 I('1.3.NET1')) + N(27 I('1.3.NET2')) + N(28 I('1.2.NET2')) + N(29 I('1.2.NET1')) + N(30 I('1.4.NET1')) + N(31 I('1.4.NET2')) + N(32 I('1.4.NET3')) + N(33 I('1.4.NET4')) + N(34 I('1.4.NET5')) + N(35 I('1.4.NET6')) + N(36 I('1.4.NET8')) + N(37 I('1.4.NET7')) + P(1 I(EN)) + P(2 I(VDD)) + P(3 I(VSS)) + P(4 I(VIN)) + P(5 I(VBIAS)) + P(6 I(VCM_OUT)) + P(7 I(BCM_OUT)) + P(8 I(CCM_OUT)) + P(9 I(VIN_OUT)) + P(10 I(PU)) + P(11 I(PD)) + D(1 DIODE_PD2NW_06V0 + I(IO8.1) + E(A 0) + E(P 0) + T(A 12) + T(C 2) + ) + D(2 DIODE_ND2PS_06V0 + I(IO8.2) + E(A 0) + E(P 0) + T(A 3) + T(C 12) + ) + D(3 DIODE_PD2NW_06V0 + I(IO1.1) + E(A 0) + E(P 0) + T(A 13) + T(C 2) + ) + D(4 DIODE_ND2PS_06V0 + I(IO1.2) + E(A 0) + E(P 0) + T(A 3) + T(C 13) + ) + D(5 DIODE_PD2NW_06V0 + I(IO2.1) + E(A 0) + E(P 0) + T(A 14) + T(C 2) + ) + D(6 DIODE_ND2PS_06V0 + I(IO2.2) + E(A 0) + E(P 0) + T(A 3) + T(C 14) + ) + ) +) +Z( + X(TOP TOP X + L( + M(E B('Net PD,Z,tieH is not matching any net from reference netlist')) + M(E B('Net VCM_OUT is not matching any net from reference netlist')) + M(E B('Net VIN is not matching any net from reference netlist')) + M(E B('Net EN is not matching any net from reference netlist')) + M(E B('Net VBIAS is not matching any net from reference netlist')) + M(E B('Net VIN_OUT is not matching any net from reference netlist')) + M(E B('Net PU,ZN,tieL is not matching any net from reference netlist')) + M(E B('Net BCM_OUT is not matching any net from reference netlist')) + M(E B('Net CCM_OUT is not matching any net from reference netlist')) + M(E B('Net $348 is not matching any net from reference netlist')) + M(E B('Net $359 is not matching any net from reference netlist')) + M(E B('Net $247 is not matching any net from reference netlist')) + M(E B('Net $355 is not matching any net from reference netlist')) + M(E B('Net $249 is not matching any net from reference netlist')) + M(E B('Net $251 is not matching any net from reference netlist')) + M(E B('Net $253 is not matching any net from reference netlist')) + M(E B('Net $288 is not matching any net from reference netlist')) + M(E B('Net $312 is not matching any net from reference netlist')) + M(E B('Net $268 is not matching any net from reference netlist')) + M(E B('Net $354 is not matching any net from reference netlist')) + M(E B('Net $358 is not matching any net from reference netlist')) + M(E B('Net $202 is not matching any net from reference netlist')) + M(E B('Net $208 is not matching any net from reference netlist')) + M(E B('Net $368 is not matching any net from reference netlist')) + M(E B('Net $357 is not matching any net from reference netlist')) + M(E B('Net $248 is not matching any net from reference netlist')) + M(E B('Net $252 is not matching any net from reference netlist')) + M(E B('Net $149 is not matching any net from reference netlist')) + M(E B('Net $356 is not matching any net from reference netlist')) + M(E B('Net $314 is not matching any net from reference netlist')) + M(E B('Net $250 is not matching any net from reference netlist')) + M(E B('Net $347 is not matching any net from reference netlist')) + M(E B('Net $222 is not matching any net from reference netlist')) + M(E B('Net $265 is not matching any net from reference netlist')) + M(E B('Net $317 is not matching any net from reference netlist')) + M(E B('Net gf180mcu_gnd is not matching any net from reference netlist')) + M(E B('Net VSS is not matching any net from reference netlist')) + M(E B('Net VDD is not matching any net from reference netlist')) + ) + Z( + N(() 7 0) + N(() 8 0) + N(() 1 0) + N(() 12 0) + N(() 11 0) + N(() 10 0) + N(() 5 0) + N(() 14 0) + N(() 6 0) + N(() 2 0) + N(() 4 0) + N(() 13 0) + N(() 9 0) + N(() 3 0) + N(149 () 0) + N(202 () 0) + N(208 () 0) + N(222 () 0) + N(247 () 0) + N(248 () 0) + N(249 () 0) + N(250 () 0) + N(251 () 0) + N(252 () 0) + N(253 () 0) + N(265 () 0) + N(268 () 0) + N(288 () 0) + N(312 () 0) + N(314 () 0) + N(317 () 0) + N(347 () 0) + N(348 () 0) + N(354 () 0) + N(355 () 0) + N(356 () 0) + N(357 () 0) + N(358 () 0) + N(359 () 0) + N(368 () 0) + N(289 () 0) + N(313 () 0) + N(200 () 0) + N(167 () 0) + N(201 () 0) + N(228 () 0) + N(233 () 0) + N(7 () 0) + N(366 () 0) + N(254 () 0) + N(1 () 0) + N(499 () 0) + P(() 6 1) + P(() 7 1) + P(() 0 1) + P(() 10 1) + P(() 9 1) + P(() 4 1) + P(() 5 1) + P(() 1 1) + P(() 3 1) + P(() 8 1) + P(() 2 1) + P(8 () 1) + P(9 () 1) + P(3 () 1) + P(2 () 1) + P(4 () 1) + P(5 () 1) + P(6 () 1) + P(1 () 1) + P(10 () 1) + P(7 () 1) + P(0 () 1) + P(11 () 1) + D(() 2 0) + D(() 4 0) + D(() 6 0) + D(() 1 0) + D(() 3 0) + D(() 5 0) + D(145 () 0) + D(150 () 0) + D(149 () 0) + D(148 () 0) + D(147 () 0) + D(146 () 0) + D(143 () 0) + D(142 () 0) + D(141 () 0) + D(140 () 0) + D(139 () 0) + D(144 () 0) + D(155 () 0) + D(162 () 0) + D(161 () 0) + D(160 () 0) + D(159 () 0) + D(158 () 0) + D(157 () 0) + D(156 () 0) + D(154 () 0) + D(153 () 0) + D(152 () 0) + D(151 () 0) + D(95 () 0) + D(96 () 0) + D(97 () 0) + D(98 () 0) + D(99 () 0) + D(100 () 0) + D(101 () 0) + D(102 () 0) + D(103 () 0) + D(104 () 0) + D(83 () 0) + D(105 () 0) + D(106 () 0) + D(82 () 0) + D(94 () 0) + D(81 () 0) + D(84 () 0) + D(85 () 0) + D(86 () 0) + D(87 () 0) + D(88 () 0) + D(89 () 0) + D(90 () 0) + D(91 () 0) + D(92 () 0) + D(93 () 0) + D(124 () 0) + D(130 () 0) + D(125 () 0) + D(126 () 0) + D(127 () 0) + D(128 () 0) + D(129 () 0) + D(131 () 0) + D(132 () 0) + D(133 () 0) + D(134 () 0) + D(135 () 0) + D(136 () 0) + D(137 () 0) + D(138 () 0) + D(113 () 0) + D(123 () 0) + D(109 () 0) + D(110 () 0) + D(111 () 0) + D(112 () 0) + D(114 () 0) + D(115 () 0) + D(116 () 0) + D(117 () 0) + D(118 () 0) + D(119 () 0) + D(120 () 0) + D(121 () 0) + D(122 () 0) + D(107 () 0) + D(108 () 0) + D(50 () 0) + D(59 () 0) + D(58 () 0) + D(57 () 0) + D(56 () 0) + D(55 () 0) + D(54 () 0) + D(53 () 0) + D(52 () 0) + D(51 () 0) + D(60 () 0) + D(49 () 0) + D(48 () 0) + D(47 () 0) + D(46 () 0) + D(45 () 0) + D(44 () 0) + D(43 () 0) + D(42 () 0) + D(41 () 0) + D(70 () 0) + D(1 () 0) + D(78 () 0) + D(77 () 0) + D(76 () 0) + D(75 () 0) + D(74 () 0) + D(73 () 0) + D(72 () 0) + D(71 () 0) + D(2 () 0) + D(69 () 0) + D(68 () 0) + D(67 () 0) + D(66 () 0) + D(65 () 0) + D(64 () 0) + D(63 () 0) + D(62 () 0) + D(61 () 0) + D(11 () 0) + D(20 () 0) + D(19 () 0) + D(18 () 0) + D(17 () 0) + D(16 () 0) + D(15 () 0) + D(14 () 0) + D(13 () 0) + D(12 () 0) + D(39 () 0) + D(10 () 0) + D(9 () 0) + D(8 () 0) + D(7 () 0) + D(6 () 0) + D(5 () 0) + D(4 () 0) + D(3 () 0) + D(22 () 0) + D(40 () 0) + D(38 () 0) + D(37 () 0) + D(36 () 0) + D(35 () 0) + D(34 () 0) + D(33 () 0) + D(32 () 0) + D(31 () 0) + D(29 () 0) + D(30 () 0) + D(21 () 0) + D(23 () 0) + D(24 () 0) + D(25 () 0) + D(26 () 0) + D(27 () 0) + D(28 () 0) + D(79 () 0) + D(80 () 0) + D(163 () 0) + D(164 () 0) + D(165 () 0) + ) + ) +) diff --git a/blocks/composite/regulated_cascoded_cmirror/gds/top.gds b/blocks/composite/regulated_cascoded_cmirror/gds/top.gds new file mode 100644 index 00000000..42de3c92 Binary files /dev/null and b/blocks/composite/regulated_cascoded_cmirror/gds/top.gds differ diff --git a/blocks/composite/regulated_cascoded_cmirror/gds/top_new.spice b/blocks/composite/regulated_cascoded_cmirror/gds/top_new.spice new file mode 100644 index 00000000..3f435c5a --- /dev/null +++ b/blocks/composite/regulated_cascoded_cmirror/gds/top_new.spice @@ -0,0 +1,220 @@ +** sch_path: /foss/designs/gLayout-mahowalders/blocks/composite/regulated_cascoded_cmirror/xschem/int_top_lvs.sch +.SUBCKT TOP EN VDD VSS VIN VBIAS VCM_OUT BCM_OUT CCM_OUT VIN_OUT PU PD +*.ipin EN +*.iopin VDD +*.iopin VSS +*.ipin VIN +*.ipin VBIAS +*.opin VCM_OUT +*.opin BCM_OUT +*.opin CCM_OUT +*.opin VIN_OUT +*.ipin PU +*.ipin PD +x2 PD VDD VSS tieH +x3 VDD PU VSS tieL +XIO8 VDD ENA EN VSS io_secondary_5p0 +x1 VDD ENA VIN_INT VCM_OUT BCM_OUT CCM_OUT VBIAS_INT VSS VIN_OUT top_level +XIO1 VDD VIN_INT VIN VSS io_secondary_5p0 +XIO2 VDD VBIAS_INT VBIAS VSS io_secondary_5p0 +**.ends + +* expanding symbol: Chipathon2025_pads/xschem/tieH.sym # of pins=3 +** sym_path: /foss/designs/gLayout-mahowalders/blocks/composite/regulated_cascoded_cmirror/xschem/Chipathon2025_pads/xschem/tieH.sym +** sch_path: /foss/designs/gLayout-mahowalders/blocks/composite/regulated_cascoded_cmirror/xschem/Chipathon2025_pads/xschem/tieH.sch +.subckt tieH TIEH VDD VSS +*.iopin VSS +*.iopin VDD +*.iopin TIEH +XM1 TIEH net1 VDD VDD pfet_05v0 L=0.55u W=2u nf=1 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=1 +XM2 net1 net1 VSS VSS nfet_05v0 L=0.70u W=1u nf=1 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=1 +.ends + + +* expanding symbol: Chipathon2025_pads/xschem/tieL.sym # of pins=3 +** sym_path: /foss/designs/gLayout-mahowalders/blocks/composite/regulated_cascoded_cmirror/xschem/Chipathon2025_pads/xschem/tieL.sym +** sch_path: /foss/designs/gLayout-mahowalders/blocks/composite/regulated_cascoded_cmirror/xschem/Chipathon2025_pads/xschem/tieL.sch +.subckt tieL VDD TIEL VSS +*.iopin VSS +*.iopin VDD +*.iopin TIEL +XM3 net1 net1 VDD VDD pfet_05v0 L=0.55u W=2u nf=1 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=1 +XM4 TIEL net1 VSS VSS nfet_05v0 L=0.70u W=1u nf=1 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=1 +.ends + + +* expanding symbol: Chipathon2025_pads/xschem/symbols/io_secondary_5p0/io_secondary_5p0.sym # of pins=4 +** sym_path: /foss/designs/gLayout-mahowalders/blocks/composite/regulated_cascoded_cmirror/xschem/Chipathon2025_pads/xschem/symbols/io_secondary_5p0/io_secondary_5p0.sym +** sch_path: /foss/designs/gLayout-mahowalders/blocks/composite/regulated_cascoded_cmirror/xschem/Chipathon2025_pads/xschem/symbols/io_secondary_5p0/io_secondary_5p0.sch +.subckt io_secondary_5p0 VDD to_gate ASIG5V VSS + + +*.iopin VSS +*.iopin VDD +*.iopin to_gate +*.iopin ASIG5V +D1 to_gate VDD diode_pd2nw_06v0 area='10u * 10u ' pj='2*10u + 2*10u ' m=4 +XR1 to_gate ASIG5V VDD ppolyf_u r_width=16e-6 r_length=4e-6 m=1 +D2 VSS to_gate diode_nd2ps_06v0 area='10u * 10u ' pj='2*10u + 2*10u ' m=4 +.ends + + +* expanding symbol: top_level.sym # of pins=9 +** sym_path: /foss/designs/gLayout-mahowalders/blocks/composite/regulated_cascoded_cmirror/xschem/top_level.sym +** sch_path: /foss/designs/gLayout-mahowalders/blocks/composite/regulated_cascoded_cmirror/xschem/top_level.sch +.subckt top_level VDD EN V_IN V_OUT_VCM V_OUT_BCM V_OUT_CCM V_AUX_CCM VSS V_OUT_VIN +*.iopin VSS +*.ipin V_AUX_CCM +*.iopin VDD +*.opin V_OUT_VCM +*.opin V_OUT_BCM +*.opin V_OUT_CCM +*.ipin V_IN +*.ipin EN +*.opin V_OUT_VIN +XM1 net1 net1 VDD VDD pfet_03v3 L=2.0u W=10.0u nf=1 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=1 +XM2 V_IN V_IN net1 VDD pfet_03v3 L=2.0u W=10.0u nf=1 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=1 +XM3 net2 net1 VDD VDD pfet_03v3 L=2.0u W=10.0u nf=1 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=1 +XM4 net3 V_IN net2 VDD pfet_03v3 L=2.0u W=10.0u nf=1 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=1 +XM5 net7 net1 VDD VDD pfet_03v3 L=2.0u W=10.0u nf=1 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=1 +XM6 net4 V_IN net7 VDD pfet_03v3 L=2.0u W=10.0u nf=1 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=1 +XM7 net6 net1 VDD VDD pfet_03v3 L=2.0u W=10.0u nf=1 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=1 +XM8 net5 V_IN net6 VDD pfet_03v3 L=2.0u W=10.0u nf=1 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=1 +XM14 net1 EN VDD VDD pfet_03v3 L=2.0u W=10.0u nf=1 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=1 +XM18 net1 EN VDD VDD pfet_03v3 L=2.0u W=10.0u nf=1 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=1 +XM15 net1 EN VDD VDD pfet_03v3 L=2.0u W=10.0u nf=1 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=1 +x1 net3 V_OUT_VCM VSS vanilla_cm +x2 V_OUT_BCM net4 VSS biased_cm +x3 V_OUT_CCM net8 net5 VSS cascode_cm +x4 VDD EN V_AUX_CCM net8 VSS bias +XM9 net9 net1 VDD VDD pfet_03v3 L=2.0u W=10.0u nf=1 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=1 +XM10 V_OUT_VIN V_IN net9 VDD pfet_03v3 L=2.0u W=10.0u nf=1 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=1 +XM11 net1 EN VDD VDD pfet_03v3 L=2.0u W=10.0u nf=1 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=1 +XM12 VDD VDD VDD VDD pfet_03v3 L=2.0u W=10.0u nf=1 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=6 +.ends + + +* expanding symbol: vanilla_cm.sym # of pins=3 +** sym_path: /foss/designs/gLayout-mahowalders/blocks/composite/regulated_cascoded_cmirror/xschem/vanilla_cm.sym +** sch_path: /foss/designs/gLayout-mahowalders/blocks/composite/regulated_cascoded_cmirror/xschem/vanilla_cm.sch +.subckt vanilla_cm v_in v_out vss +*.ipin v_in +*.iopin vss +*.opin v_out +XM1 v_out v_in vss vss nfet_03v3 L=1u W=4u nf=1 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=1 +XM2 v_in v_in vss vss nfet_03v3 L=1u W=4u nf=1 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=1 +XM3 vss vss vss vss nfet_03v3 L=1u W=4u nf=1 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=2 +.ends + + +* expanding symbol: biased_cm.sym # of pins=3 +** sym_path: /foss/designs/gLayout-mahowalders/blocks/composite/regulated_cascoded_cmirror/xschem/biased_cm.sym +** sch_path: /foss/designs/gLayout-mahowalders/blocks/composite/regulated_cascoded_cmirror/xschem/biased_cm.sch +.subckt biased_cm v_out v_in vss +*.ipin v_in +*.iopin vss +*.opin v_out +XM3 net2 net1 vss vss nfet_03v3 L=1u W=4u nf=1 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=1 +XM4 net1 net1 vss vss nfet_03v3 L=1u W=4u nf=1 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=1 +XM5 v_out v_in net2 vss nfet_03v3 L=1u W=4u nf=1 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=1 +XM6 v_in v_in net1 vss nfet_03v3 L=1u W=4u nf=1 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=1 +XM1 vss vss vss vss nfet_03v3 L=1u W=4u nf=1 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=4 +.ends + + +* expanding symbol: cascode_cm.sym # of pins=4 +** sym_path: /foss/designs/gLayout-mahowalders/blocks/composite/regulated_cascoded_cmirror/xschem/cascode_cm.sym +** sch_path: /foss/designs/gLayout-mahowalders/blocks/composite/regulated_cascoded_cmirror/xschem/cascode_cm.sch +.subckt cascode_cm v_out v_aux v_in vss +*.ipin v_in +*.iopin vss +*.ipin v_aux +*.opin v_out +XM10 v_aux net1 vss vss nfet_03v3 L=1u W=8u nf=2 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=1 +XM8 v_in v_aux net1 vss nfet_03v3 L=1u W=8u nf=2 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=1 +XM11 net1 v_in vss vss nfet_03v3 L=1u W=8u nf=2 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=1 +XM12 v_aux net2 vss vss nfet_03v3 L=1u W=8u nf=2 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=1 +XM13 net2 v_in vss vss nfet_03v3 L=1u W=8u nf=2 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=1 +XM14 v_out v_aux net2 vss nfet_03v3 L=1u W=8u nf=2 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=1 +XM1 vss vss vss vss nfet_03v3 L=1u W=4u nf=1 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=6 +.ends + + +* expanding symbol: bias.sym # of pins=5 +** sym_path: /foss/designs/gLayout-mahowalders/blocks/composite/regulated_cascoded_cmirror/xschem/bias.sym +** sch_path: /foss/designs/gLayout-mahowalders/blocks/composite/regulated_cascoded_cmirror/xschem/bias.sch +.subckt bias VDD ENA bias_in bias_out vss +*.iopin vss +*.iopin VDD +*.ipin ENA +*.ipin bias_in +*.opin bias_out +XM11 net1 net1 VDD VDD pfet_03v3 L=2.0u W=100.0u nf=10 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=1 +XM12 bias_in bias_in net1 VDD pfet_03v3 L=2.0u W=100.0u nf=10 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=1 +XM16 net1 ENA VDD VDD pfet_03v3 L=2.0u W=10.0u nf=1 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=1 +XM17 net2 net1 VDD VDD pfet_03v3 L=2.0u W=10.0u nf=1 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=1 +XM19 net3 bias_in net2 VDD pfet_03v3 L=2.0u W=10.0u nf=1 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=1 +XM9 net4 net4 VDD VDD pfet_03v3 L=2.0u W=100.0u nf=10 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=1 +XM10 net5 net5 net4 VDD pfet_03v3 L=2.0u W=100.0u nf=10 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=1 +XM13 net4 ENA VDD VDD pfet_03v3 L=2.0u W=10.0u nf=1 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=1 +XM20 net6 net4 VDD VDD pfet_03v3 L=2.0u W=10.0u nf=1 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=1 +XM21 bias_out net5 net6 VDD pfet_03v3 L=2.0u W=10.0u nf=10 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=1 +XM22 net8 net7 vss vss nfet_03v3 L=1u W=8u nf=1 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=1 +XM23 net7 net7 vss vss nfet_03v3 L=1u W=80u nf=10 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=1 +XM24 net5 net3 net8 vss nfet_03v3 L=1u W=8u nf=1 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=1 +XM25 net3 net3 net7 vss nfet_03v3 L=1u W=80u nf=10 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=1 +XM1 VDD VDD VDD VDD pfet_03v3 L=2.0u W=10.0u nf=1 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=12 +XM2 vss vss vss vss nfet_03v3 L=1u W=8u nf=1 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=4 +.ends + +.end diff --git a/blocks/composite/regulated_cascoded_cmirror/input.py b/blocks/composite/regulated_cascoded_cmirror/input.py new file mode 100644 index 00000000..ce4788db --- /dev/null +++ b/blocks/composite/regulated_cascoded_cmirror/input.py @@ -0,0 +1,873 @@ +from glayout import MappedPDK, sky130, gf180 +from glayout import nmos, pmos, tapring, via_stack + +# from glayout.placement.two_transistor_interdigitized import two_nfet_interdigitized, two_pfet_interdigitized +from n_fets_interdigitized import n_transistor_interdigitized +from gdsfactory import cell +from gdsfactory.component import Component +from gdsfactory.components import text_freetype, rectangle +from pathlib import Path + +from glayout.routing import c_route, L_route, straight_route +from glayout.spice.netlist import Netlist + +from glayout.util.port_utils import add_ports_perimeter, rename_ports_by_orientation +from glayout.util.comp_utils import ( + evaluate_bbox, + prec_center, + prec_ref_center, + align_comp_to_port, +) +from glayout.util.snap_to_grid import component_snap_to_grid +from gdsfactory.port import Port +from typing import Optional, Union + +###### Only Required for IIC-OSIC Docker +import os +import subprocess + +# Run a shell, source .bashrc, then printenv +cmd = 'bash -c "source ~/.bashrc && printenv"' +result = subprocess.run(cmd, shell=True, text=True, capture_output=True) +env_vars = {} +for line in result.stdout.splitlines(): + if "=" in line: + key, value = line.split("=", 1) + env_vars[key] = value + +# Now, update os.environ with these +os.environ.update(env_vars) + + +# @validate_arguments +def generate_input_stage_netlist( + pdk: MappedPDK, + prefix: str, + instance_name: str, + CM_size: tuple[float, float, int], # (width, length, multipliers) + source_net_in: str, + gate_net_en: str, # Auxiliary node + drain_net_out_vin: str, + drain_net_out_vcm: str, + drain_net_out_bcm: str, + drain_net_out_ccm: str, + transistor_type: str = "nfet", + bulk_net: str = None, + proposed_ground: str = None, # Proposed ground net + dummy: bool = True, + subckt_only: bool = False, + show_netlist: bool = False, + **kwargs, +) -> Netlist: + """Generate a netlist for a regulated cascode current mirror.""" + + if bulk_net is None: + bulk_net = "VDD" if transistor_type.lower() == "pfet" else "VSS" + + width = CM_size[0] + length = CM_size[1] + multipliers = CM_size[2] + fingers = CM_size[3] # Number of fingers of the interdigitized fets + mtop = multipliers * fingers if subckt_only else 1 + # mtop = multipliers * 2 if dummy else multipliers # Double the multiplier to account for the dummies + + model_name = pdk.models[transistor_type.lower()] + + circuit_name = prefix + # Take only unique NET names + nodes =[ + source_net_in, + gate_net_en, + drain_net_out_vin, + drain_net_out_vcm, + drain_net_out_bcm, + drain_net_out_ccm, + bulk_net, + ] + source_netlist = f".subckt {circuit_name} {' '.join(nodes)}\n" + + # Proposed ground connection (commented) + # source_netlist += f"V{proposed_ground}1 ({proposed_ground} {bulk_net}) 0\n" + + # Generating six transistors: + middle_gate = "VMG" + middleB_bottomB = "VMBB" + middleC_bottomC = "VMBC" + middleD_bottomD = "VMBD" + middleE_bottomE = "VMBE" + + source_netlist += ( + f"X{prefix}_TA {middle_gate} {gate_net_en} {bulk_net} {bulk_net} " + f"{model_name} l={length} w={width} m={mtop}\n" + ) + + source_netlist += ( + f"X{prefix}_TB {middle_gate} {gate_net_en} {bulk_net} {bulk_net} " + f"{model_name} l={length} w={width} m={mtop}\n" + ) + + source_netlist += ( + f"X{prefix}_TC {middle_gate} {gate_net_en} {bulk_net} {bulk_net} " + f"{model_name} l={length} w={width} m={mtop}\n" + ) + + source_netlist += ( + f"X{prefix}_TD {middle_gate} {gate_net_en} {bulk_net} {bulk_net} " + f"{model_name} l={length} w={width} m={mtop}\n" + ) + + source_netlist += ( + f"X{prefix}_MA {middle_gate} {middle_gate} {bulk_net} {bulk_net} " + f"{model_name} l={length} w={width} m={mtop}\n" + ) + + source_netlist += ( + f"X{prefix}_MB {middleB_bottomB} {middle_gate} {bulk_net} {bulk_net} " + f"{model_name} l={length} w={width} m={mtop}\n" + ) + + source_netlist += ( + f"X{prefix}_MC {middleC_bottomC} {middle_gate} {bulk_net} {bulk_net} " + f"{model_name} l={length} w={width} m={mtop}\n" + ) + + source_netlist += ( + f"X{prefix}_MD {middleD_bottomD} {middle_gate} {bulk_net} {bulk_net} " + f"{model_name} l={length} w={width} m={mtop}\n" + ) + + source_netlist += ( + f"X{prefix}_ME {middleE_bottomE} {middle_gate} {bulk_net} {bulk_net} " + f"{model_name} l={length} w={width} m={mtop}\n" + ) + + source_netlist += ( + f"X{prefix}_BA {source_net_in} {source_net_in} {middle_gate} {bulk_net} " + f"{model_name} l={length} w={width} m={mtop}\n" + ) + + source_netlist += ( + f"X{prefix}_BB {drain_net_out_vcm} {source_net_in} {middleB_bottomB} {bulk_net} " + f"{model_name} l={length} w={width} m={mtop}\n" + ) + + source_netlist += ( + f"X{prefix}_BC {drain_net_out_bcm} {source_net_in} {middleC_bottomC} {bulk_net} " + f"{model_name} l={length} w={width} m={mtop}\n" + ) + + source_netlist += ( + f"X{prefix}_BD {drain_net_out_ccm} {source_net_in} {middleD_bottomD} {bulk_net} " + f"{model_name} l={length} w={width} m={mtop}\n" + ) + + source_netlist += ( + f"X{prefix}_BE {drain_net_out_vin} {source_net_in} {middleE_bottomE} {bulk_net} " + f"{model_name} l={length} w={width} m={mtop}\n" + ) + + if dummy: + source_netlist += ( + f"X{prefix}_DUMMY {bulk_net} {bulk_net} {bulk_net} {bulk_net} " + f"{model_name} l={length} w={width} m={6}\n" + ) + + source_netlist += ".ends " + circuit_name + + instance_format = "X{name} {nodes} {circuit_name} l={length} w={width} m={mult}" + + topnet = Netlist( + circuit_name=circuit_name, + nodes=nodes, + source_netlist=source_netlist, + instance_format=instance_format, + parameters={ + "model": model_name, + "width": width, + "length": length, + "mult": multipliers, + }, + ) + + if show_netlist: + generated_netlist_for_lvs = topnet.generate_netlist() + print("Generated netlist :\n", generated_netlist_for_lvs) + + file_path_local_storage = "./gen_netlist.txt" + try: + with open(file_path_local_storage, "w") as file: + file.write(generated_netlist_for_lvs) + except Exception: + print( + "Verify the file availability and type: ", + generated_netlist_for_lvs, + type(generated_netlist_for_lvs), + ) + + return topnet + + +# @validate_arguments +def input_stage( + pdk: MappedPDK, + Width: float = 1, + Length: Optional[float] = 1, + num_cols: int = 1, + fingers: int = 1, + multipliers: int = 1, + type: Optional[str] = "pfet", + with_substrate_tap: Optional[bool] = False, + with_tie: Optional[bool] = True, + with_dummy: Optional[bool] = False, + tie_layers: tuple[str, str] = ("met2", "met1"), + show_netlist: Optional[bool] = False, + add_labels = True, + **kwargs, +) -> Component: + """An instantiable self biased casoded current mirror that returns a Component object.""" + + pdk.activate() + maxmet_sep = pdk.util_max_metal_seperation() + n_well_sep = maxmet_sep + psize = (0.35, 0.35) + + # Create the current mirror component + top_level = Component(name="input_stage") + top_level.name = "input_stage" + Length = Length if Length is not None else pdk.get_grule("poly")["min_width"] + top_ref = prec_ref_center(top_level) + + # ------------------------------------------------------------------------------------------------------------------------------------------------------------ + # BOTTOM CURRENT MIRRORS + # ------------------------------------------------------------------------------------------------------------------------------------------------------------ + + currm_bottom = n_transistor_interdigitized( + pdk, + device="pfet", + numcols=1, + n_devices=5, + with_substrate_tap=False, + with_tie=False, + width=Width, + length=Length, + ) + + currm_bottom = top_level << currm_bottom + currm_bottom.name = "currm_bottom" + + currm_bottom_ref = prec_ref_center(currm_bottom) + currm_bottom_ref.move(top_ref.center) + top_level.add(currm_bottom_ref) + + top_level.add_ports(currm_bottom_ref.get_ports_list(), prefix="currm_bottom_") + + dist_DS = ( + abs( + top_level.ports[f"currm_bottom_A_0_drain_E"].center[0] + - top_level.ports[f"currm_bottom_A_0_drain_W"].center[0] + ) + / 2 + ) + + dist_GS = ( + abs( + top_level.ports[f"currm_bottom_A_0_gate_E"].center[0] + - top_level.ports[f"currm_bottom_A_0_gate_W"].center[0] + ) + / 2 + ) + + viam2m3 = via_stack(pdk, "met2", "met3", centered=True) + viam1m2 = via_stack(pdk, "met1", "met2", centered=True) + + bottomA_drain_via = top_level << viam2m3 + bottomA_drain_via.move(top_level.ports[f"currm_bottom_A_0_drain_W"].center).movex( + dist_DS + ) + + bottomA_gate_via = top_level << viam2m3 + bottomA_gate_via.move(top_level.ports[f"currm_bottom_A_0_gate_W"].center).movex( + dist_GS + ) + + top_level << straight_route( + pdk, + bottomA_drain_via.ports["top_met_N"], + bottomA_gate_via.ports["top_met_S"], + glayer1="met3", + glayer2="met3", + ) + + poly_to_met2_via = via_stack(pdk, glayer1="poly", glayer2="met2", centered=True) + + # ------------------------------------------------------------------------------------------------------------------------------------------------------------ + # MIDDLE CURRENT MIRRORS + # ------------------------------------------------------------------------------------------------------------------------------------------------------------ + + currm_middle = n_transistor_interdigitized( + pdk, + device="pfet", + numcols=1, + n_devices=5, + with_substrate_tap=False, + with_tie=False, + width=Width, + length=Length, + ) + + currm_middle = top_level << currm_middle + currm_middle.name = "currm_middle" + + currm_middle_ref = prec_ref_center(currm_middle) + currm_middle_ref.move(top_ref.center).movey( + evaluate_bbox(currm_bottom_ref)[1] + 2 * n_well_sep + ) + top_level.add(currm_middle_ref) + + top_level.add_ports(currm_middle_ref.get_ports_list(), prefix="currm_middle_") + + # ------------------------------------------------------------------------------------------------------------------------------------------------------------ + # TOP CURRENT MIRRORS + # ------------------------------------------------------------------------------------------------------------------------------------------------------------ + + currm_top = n_transistor_interdigitized( + pdk, + device="pfet", + numcols=1, + n_devices=4, + with_substrate_tap=False, + with_tie=False, + width=Width, + length=Length, + ) + + currm_top = top_level << currm_top + currm_top.name = "currm_top" + + currm_top_ref = prec_ref_center(currm_top) + currm_top_ref.move(currm_middle.center).movey( + evaluate_bbox(currm_middle_ref)[1] + 2 * n_well_sep + ) + top_level.add(currm_top_ref) + + top_level.add_ports(currm_top_ref.get_ports_list(), prefix="currm_top_") + + # ------------------------------------------------------------------------------------------------------------------------------------------------------------ + # INTERCONNECTIONS + # ------------------------------------------------------------------------------------------------------------------------------------------------------------ + + bottomA_source_via = top_level << viam2m3 + bottomA_source_via.move( + top_level.ports[f"currm_bottom_A_0_source_W"].center + ).movex(-dist_DS) + + top_level << straight_route( + pdk, + bottomA_source_via.ports["top_met_W"], + top_level.ports[f"currm_bottom_A_0_source_E"], + glayer1="met2", + glayer2="met2", + ) + + middleA_drain_via = top_level << viam2m3 + middleA_drain_via.move( + top_level.ports[f"currm_middle_A_0_drain_W"].center + ).movex(-dist_DS) + + top_level << straight_route( + pdk, + middleA_drain_via.ports["top_met_W"], + top_level.ports[f"currm_middle_A_0_drain_E"], + glayer1="met2", + glayer2="met2", + ) + + bottom_middle_route = straight_route( + pdk, + bottomA_source_via.ports["top_met_S"], + middleA_drain_via.ports["top_met_N"], + glayer1="met3", + glayer2="met3", + ) + + bottom_middle_ref = top_level << bottom_middle_route + bottom_middle_route.name = "bottomAsource_to_middleAdrain" + + middleA_gate_via = top_level << viam2m3 + middleA_gate_via.move( + (bottom_middle_ref.center[0], top_level.ports[f"currm_middle_A_0_gate_W"].center[1]) + ) + + top_level << straight_route( + pdk, + middleA_gate_via.ports["top_met_W"], + top_level.ports[f"currm_middle_A_0_gate_W"], + glayer1="met2", + glayer2="met2", + ) + + letters = ["B", "C", "D", "E"] + for letter in letters: + bottomL_source_via = top_level << viam2m3 + bottomL_source_via.move( + top_level.ports[f"currm_bottom_{letter}_0_source_W"].center + ).movex(dist_DS) + + middleL_drain_via = top_level << viam2m3 + middleL_drain_via.move( + top_level.ports[f"currm_middle_{letter}_0_drain_W"].center + ).movex(dist_DS) + + top_level << straight_route( + pdk, + bottomL_source_via.ports["top_met_S"], + middleL_drain_via.ports["top_met_N"], + glayer1="met3", + glayer2="met3", + ) + + middleE_gate_via = top_level << viam2m3 + middleE_gate_via.move( + top_level.ports[f"currm_middle_E_0_gate_W"].center + ).movex(dist_GS + 1.5 * dist_DS) + + top_level << straight_route( + pdk, + middleE_gate_via.ports["top_met_E"], + top_level.ports[f"currm_middle_E_0_gate_W"], + glayer1="met2", + glayer2="met2", + ) + + topD_drain_via = top_level << viam2m3 + topD_drain_via.move( + (middleE_gate_via.center[0], top_level.ports[f"currm_top_D_0_drain_W"].center[1]) + ) + + top_level << straight_route( + pdk, + topD_drain_via.ports["top_met_E"], + top_level.ports[f"currm_top_D_0_drain_W"], + glayer1="met2", + glayer2="met2", + ) + + middle_top_route = straight_route( + pdk, + middleE_gate_via.ports["top_met_S"], + topD_drain_via.ports["top_met_N"], + glayer1="met3", + glayer2="met3", + ) + + middle_top_ref = top_level << middle_top_route + middle_top_route.name = "middleEgate_to_topdrains" + + topA_drain_via = top_level << viam2m3 + topA_drain_via.move( + (middle_top_ref.center[0], top_level.ports[f"currm_top_A_0_drain_W"].center[1]) + ) + + topB_drain_via = top_level << viam2m3 + topB_drain_via.move( + (middle_top_ref.center[0], top_level.ports[f"currm_top_B_0_drain_W"].center[1]) + ) + + topC_drain_via = top_level << viam2m3 + topC_drain_via.move( + (middle_top_ref.center[0], top_level.ports[f"currm_top_C_0_drain_W"].center[1]) + ) + + top_level << straight_route( + pdk, + top_level.ports[f"currm_top_A_0_drain_E"], + topA_drain_via.ports["top_met_E"], + glayer2="met2", + ) + + top_level << straight_route( + pdk, + top_level.ports[f"currm_top_B_0_drain_E"], + topB_drain_via.ports["top_met_E"], + glayer2="met2", + ) + + top_level << straight_route( + pdk, + top_level.ports[f"currm_top_C_0_drain_E"], + topC_drain_via.ports["top_met_E"], + glayer2="met2", + ) + + # ------------------------------------------------------------------------------------------------------------------------------------------------------------ + # TAP RING + # ------------------------------------------------------------------------------------------------------------------------------------------------------------ + + snap = pdk.snap_to_2xgrid + + core = top_level.copy() # so we don't mutate while measuring + core_flat = core.flatten() # include all placed children + + xmin, xmax = core_flat.xmin, core_flat.xmax + ymin, ymax = core_flat.ymin, core_flat.ymax + + core_w = xmax - xmin + core_h = ymax - ymin + + cx = snap((xmin + xmax) / 2) + cy = snap((ymin + ymax) / 2) + + # Adding tapring + if with_tie: + well, sdglayer = "nwell", "n+s/d" + tap_separation = max( + maxmet_sep, pdk.get_grule("active_diff", "active_tap")["min_separation"] + ) + tap_separation += pdk.get_grule(sdglayer, "active_tap")["min_enclosure"] + tap_encloses = ( + (snap(4 * tap_separation + core_w)), + (snap(4 * tap_separation + core_h)), + ) + tie_ref = top_level << tapring( + pdk, + enclosed_rectangle=tap_encloses, + sdlayer=sdglayer, + horizontal_glayer=tie_layers[0], + vertical_glayer=tie_layers[1], + ) + tie_ref.move((cx, cy)) + top_level.add_ports(tie_ref.get_ports_list(), prefix="welltie_") + + # add pwell + top_level.add_padding( + default=pdk.get_grule(well, "active_tap")["min_enclosure"], + layers=[pdk.get_glayer(well)], + ) + top_level = add_ports_perimeter(top_level, layer=pdk.get_glayer(well), prefix="well_") + + # add the substrate tap if specified + if with_substrate_tap: + substrate_tap_separation = pdk.get_grule("dnwell", "active_tap")[ + "min_separation" + ] + substrate_tap_enclosure = ( + (snap(4 * substrate_tap_separation + core_w)), + (snap(4 * substrate_tap_separation + core_h)), + ) + ringtoadd = tapring( + pdk, + enclosed_rectangle=substrate_tap_enclosure, + sdlayer="p+s/d", + horizontal_glayer=tie_layers[0], + vertical_glayer=tie_layers[1], + ) + substrate_tap_ring_ref = top_level << ringtoadd + substrate_tap_ring_ref.move((cx, cy)) + top_level.add_ports( + substrate_tap_ring_ref.get_ports_list(), prefix="substrate_tap_" + ) + + # Connect well ties to well + try: + top_level << straight_route( + pdk, + top_level.ports["currm_bottom_A_0_dummy_L_gsdcon_top_met_W"], + top_level.ports["welltie_W_top_met_W"], + glayer2="met1", + ) + + top_level << straight_route( + pdk, + top_level.ports[ + f"currm_bottom_E_{num_cols - 1}_dummy_R_gsdcon_top_met_E" + ], + top_level.ports["welltie_E_top_met_E"], + glayer2="met1", + ) + + top_level << straight_route( + pdk, + top_level.ports["currm_middle_A_0_dummy_L_gsdcon_top_met_W"], + top_level.ports["welltie_W_top_met_W"], + glayer2="met1", + ) + + top_level << straight_route( + pdk, + top_level.ports[ + f"currm_middle_E_{num_cols - 1}_dummy_R_gsdcon_top_met_E" + ], + top_level.ports["welltie_E_top_met_E"], + glayer2="met1", + ) + + top_level << straight_route( + pdk, + top_level.ports["currm_top_A_0_dummy_L_gsdcon_top_met_W"], + top_level.ports["welltie_W_top_met_W"], + glayer2="met1", + ) + + top_level << straight_route( + pdk, + top_level.ports[ + f"currm_top_D_{num_cols - 1}_dummy_R_gsdcon_top_met_E" + ], + top_level.ports["welltie_E_top_met_E"], + glayer2="met1", + ) + + except KeyError: + pass + + # ------------------------------------------------------------------------------------------------------------------------------------------------------------ + # CONNECT SOURCES TO VDD + # ------------------------------------------------------------------------------------------------------------------------------------------------------------ + + dist_ring = abs( + top_level.ports["welltie_W_top_met_W"].center[0] + - top_level.ports["welltie_W_top_met_E"].center[0] + ) / 2 + + letters = ["A", "B", "C", "D", "E"] + for letter in letters: + middleL_source_via = top_level << viam1m2 + middleL_source_via.move( + ( + top_level.ports["welltie_W_top_met_W"].center[0], + top_level.ports[f"currm_middle_{letter}_0_source_W"].center[1], + ) + ).movex(dist_ring) + + top_level << straight_route( + pdk, + top_level.ports[f"currm_middle_{letter}_0_source_W"], + middleL_source_via.ports["top_met_W"], + glayer2="met2", + ) + + if letter != "E": + topL_source_via = top_level << viam1m2 + topL_source_via.move( + ( + top_level.ports["welltie_W_top_met_W"].center[0], + top_level.ports[f"currm_top_{letter}_0_source_W"].center[1], + ) + ).movex(dist_ring) + + top_level << straight_route( + pdk, + top_level.ports[f"currm_top_{letter}_0_source_W"], + topL_source_via.ports["top_met_W"], + glayer2="met2", + ) + + # ------------------------------------------------------------------------------------------------------------------------------------------------------------ + # CONNECT GATES TO ENABLE AND INPUT + # ------------------------------------------------------------------------------------------------------------------------------------------------------------ + + letters = ["A", "B", "C", "D", "E"] + for letter in letters: + bottomL_gate_input_via = top_level << viam1m2 + bottomL_gate_input_via.move( + ( + top_level.ports["welltie_W_top_met_W"].center[0], + top_level.ports[f"currm_bottom_{letter}_0_gate_W"].center[1], + ) + ).movex(dist_ring - 2 * dist_DS) + top_level.add_ports(bottomL_gate_input_via.get_ports_list(), prefix=f"IN_{letter}_") + + top_level << straight_route( + pdk, + top_level.ports[f"currm_bottom_{letter}_0_gate_W"], + bottomL_gate_input_via.ports["top_met_W"], + glayer2="met2", + ) + + if letter != "E": + topL_gate_enable_via = top_level << viam1m2 + topL_gate_enable_via.move( + ( + top_level.ports["welltie_W_top_met_W"].center[0], + top_level.ports[f"currm_top_{letter}_0_gate_W"].center[1], + ) + ).movex(dist_ring - 2 * dist_DS) + top_level.add_ports(topL_gate_enable_via.get_ports_list(), prefix=f"EN_{letter}_") + + top_level << straight_route( + pdk, + top_level.ports[f"currm_top_{letter}_0_gate_W"], + topL_gate_enable_via.ports["top_met_W"], + glayer2="met2", + ) + + # ------------------------------------------------------------------------------------------------------------------------------------------------------------ + # CONNECT BOTTOM DRAINS TO OTHER STAGES + # ------------------------------------------------------------------------------------------------------------------------------------------------------------ + + for letter in letters: + if letter != "A": + bottomL_drain_via = top_level << viam1m2 + bottomL_drain_via.move( + ( + top_level.ports["welltie_E_top_met_E"].center[0], + top_level.ports[f"currm_bottom_{letter}_0_drain_E"].center[1], + ) + ).movex(-dist_ring + 2 * dist_DS) + top_level.add_ports(bottomL_drain_via.get_ports_list(), prefix=f"OUT_{letter}_") + + top_level << straight_route( + pdk, + top_level.ports[f"currm_bottom_{letter}_0_drain_E"], + bottomL_drain_via.ports["top_met_W"], + glayer2="met2", + ) + + # ------------------------------------------------------------------------------------------------------------------------------------------------------------ + # CONNECTING INPUTS AND EN + # ------------------------------------------------------------------------------------------------------------------------------------------------------------ + + top_level << straight_route( + pdk, top_level.ports[f"IN_A_top_met_N"], top_level.ports["IN_B_top_met_S"], glayer2="met1" + ) + top_level << straight_route( + pdk, top_level.ports[f"IN_B_top_met_N"], top_level.ports[f"IN_C_top_met_S"], glayer2="met1" + ) + top_level << straight_route( + pdk, top_level.ports[f"IN_C_top_met_N"], top_level.ports[f"IN_D_top_met_S"], glayer2="met1" + ) + top_level << straight_route( + pdk, top_level.ports[f"IN_D_top_met_N"], top_level.ports[f"IN_E_top_met_S"], glayer2="met1" + ) + + top_level << straight_route( + pdk, top_level.ports[f"EN_A_top_met_N"], top_level.ports[f"EN_B_top_met_S"], glayer2="met1" + ) + top_level << straight_route( + pdk, top_level.ports[f"EN_B_top_met_N"], top_level.ports[f"EN_C_top_met_S"], glayer2="met1" + ) + top_level << straight_route( + pdk, top_level.ports[f"EN_C_top_met_N"], top_level.ports[f"EN_D_top_met_S"], glayer2="met1" + ) + + + stages = ["bottom", "middle"] + letters = ["A", "B", "C", "D", "E"] + + for stage in stages: + for letter in letters: + default_gate_via_x = ( + top_level.ports[f"currm_{stage}_{letter}_0_gate_W"].center[0] + dist_GS + ) + for let in [l for l in letters if l != letter]: + gate_via = top_level << poly_to_met2_via + gate_via.move( + (default_gate_via_x, top_level.ports[f"currm_{stage}_{let}_0_gate_W"].center[1]) + ) + + for letter in letters[:-1]: + default_gate_via_x = ( + top_level.ports[f"currm_top_{letter}_0_gate_W"].center[0] + dist_GS + ) + for let in [l for l in letters[:-1] if l != letter]: + gate_via = top_level << poly_to_met2_via + gate_via.move( + (default_gate_via_x, top_level.ports[f"currm_top_{let}_0_gate_W"].center[1]) + ) + + top_level = component_snap_to_grid(rename_ports_by_orientation(top_level)) + + top_level.info["netlist"] = generate_input_stage_netlist( + pdk=pdk, + prefix="INPUT", + instance_name=top_level.name, + CM_size=(Width, Length, num_cols, fingers), # (width, length, multipliers, fingers) + transistor_type=type, + source_net_in="VIN", # Input drain connected to IREF + gate_net_en="EN", # Auxiliary node + drain_net_out_vin="VOUT_VIN", + drain_net_out_vcm="VOUT_VCM", + drain_net_out_bcm="VOUT_BCM", + drain_net_out_ccm="VOUT_CCM", + bulk_net="VSS" if type.lower() == "nfet" else "VDD", + subckt_only=True, + show_netlist=show_netlist, + ) + + if add_labels: + return add_cm_labels(top_level, pdk) + else: + return top_level + + +def add_cm_labels(cm_in: Component, pdk: MappedPDK) -> Component: + cm_in.unlock() + + psize = (0.35, 0.35) + move_info = [] + + # VIN + vinlabel = rectangle(layer=pdk.get_glayer("met2_pin"), size=psize, centered=True).copy() + vinlabel.add_label(text="VIN", layer=pdk.get_glayer("met2_label")) + move_info.append((vinlabel, cm_in.ports["IN_A_top_met_N"], None)) + + # EN + venlabel = rectangle(layer=pdk.get_glayer("met2_pin"), size=psize, centered=True).copy() + venlabel.add_label(text="EN", layer=pdk.get_glayer("met2_label")) + move_info.append((venlabel, cm_in.ports["EN_A_top_met_N"], None)) + + # VOUT VCM + voutvcmlabel = rectangle(layer=pdk.get_glayer("met2_pin"), size=psize, centered=True).copy() + voutvcmlabel.add_label(text="VOUT_VCM", layer=pdk.get_glayer("met2_label")) + move_info.append((voutvcmlabel, cm_in.ports["OUT_B_top_met_N"], None)) + + # VOUT BCM + voutbcmlabel = rectangle(layer=pdk.get_glayer("met2_pin"), size=psize, centered=True).copy() + voutbcmlabel.add_label(text="VOUT_BCM", layer=pdk.get_glayer("met2_label")) + move_info.append((voutbcmlabel, cm_in.ports["OUT_C_top_met_N"], None)) + + # VOUT CCM + voutccmlabel = rectangle(layer=pdk.get_glayer("met2_pin"), size=psize, centered=True).copy() + voutccmlabel.add_label(text="VOUT_CCM", layer=pdk.get_glayer("met2_label")) + move_info.append((voutccmlabel, cm_in.ports["OUT_D_top_met_N"], None)) + + # VOUT VIN + voutvinlabel = rectangle(layer=pdk.get_glayer("met2_pin"), size=psize, centered=True).copy() + voutvinlabel.add_label(text="VOUT_VIN", layer=pdk.get_glayer("met2_label")) + move_info.append((voutvinlabel, cm_in.ports["OUT_E_top_met_N"], None)) + + # VDD (well tie) + vddlabel = rectangle(layer=pdk.get_glayer("met1_pin"), size=psize, centered=True).copy() + vddlabel.add_label(text="VDD", layer=pdk.get_glayer("met1_label")) + move_info.append((vddlabel, cm_in.ports["welltie_N_top_met_N"], None)) + + for comp, prt, alignment in move_info: + alignment = ("c", "b") if alignment is None else alignment + compref = align_comp_to_port(comp, prt, alignment=alignment) + cm_in.add(compref) + + return cm_in.flatten() + + + +if __name__ == "__main__": + selected_pdk = gf180 + comp = input_stage( + selected_pdk, num_cols=1, Width=10, Length=2, with_substrate_tap=False, show_netlist=False + ) + + comp.name = "INPUT_STAGE" + comp.show() + # Write the current mirror layout to a GDS file + comp.write_gds("GDS/input_stage.gds") + + # Generate the netlist for the current mirror + print(comp.info["netlist"].generate_netlist()) + + # DRC Checks + drc_result = selected_pdk.drc_magic(comp, comp.name, output_file=Path("DRC/")) + + # LVS Checks + netgen_lvs_result = selected_pdk.lvs_netgen( + comp, comp.name, output_file_path=Path("LVS/"), copy_intermediate_files=True + ) \ No newline at end of file diff --git a/blocks/composite/regulated_cascoded_cmirror/lvs_test.py b/blocks/composite/regulated_cascoded_cmirror/lvs_test.py new file mode 100644 index 00000000..4d15f218 --- /dev/null +++ b/blocks/composite/regulated_cascoded_cmirror/lvs_test.py @@ -0,0 +1,850 @@ +from pathlib import Path +from typing import Optional, Union +import os +import re +import subprocess + +from gdsfactory import cell +from gdsfactory.component import Component +from gdsfactory.components import rectangle, text_freetype + +from glayout import MappedPDK, sky130, gf180, nmos, pmos, tapring, via_stack +from glayout.placement.two_transistor_interdigitized import ( + two_nfet_interdigitized, + two_pfet_interdigitized, +) +from glayout.routing import L_route, c_route, straight_route +from glayout.spice.netlist import Netlist +from glayout.util.comp_utils import ( + align_comp_to_port, + evaluate_bbox, + prec_center, + prec_ref_center, +) +from glayout.util.port_utils import add_ports_perimeter, rename_ports_by_orientation +from glayout.util.snap_to_grid import component_snap_to_grid + +from cm_v import current_mirror_base +from cm_sb import self_biased_cascode_current_mirror +from cm_rc import regulated_cascode_current_mirror +from input import input_stage +from bias import bias_stage + +###### Only Required for IIC-OSIC Docker +# Run a shell, source .bashrc, then printenv +cmd = 'bash -c "source ~/.bashrc && printenv"' +result = subprocess.run(cmd, shell=True, text=True, capture_output=True) +env_vars = {} +for line in result.stdout.splitlines(): + if "=" in line: + key, value = line.split("=", 1) + env_vars[key] = value +os.environ.update(env_vars) + +# ---- helpers ---- +_HEADER_RE = re.compile( + r"^\s*\.subckt\s+(\S+)\s+(.*)\s*$", re.IGNORECASE | re.MULTILINE +) + + +def _parse_subckt_header(source: str): + m = _HEADER_RE.search(source) + if not m: + raise ValueError("Could not find .subckt header in child netlist") + name = m.group(1) + pins = [t for t in m.group(2).split() if t.strip()] + return name, pins + + +def _instance_line( + inst_name: str, + subckt_name: str, + ordered_child_pins: list[str], + pinmap: dict[str, str], +): + try: + nodes_in_order = [pinmap[p] for p in ordered_child_pins] + except KeyError as e: + missing = str(e).strip("'") + raise ValueError( + f"Missing mapping for child pin '{missing}' when instantiating {subckt_name}" + ) + return f"X{inst_name} " + " ".join(nodes_in_order) + f" {subckt_name}\n" + + +def generate_top_netlist( + prefix: str, + in_net: str, + aux_net: str, + en_net: str, + out_vcm_net: str, + out_sbcm_net: str, + out_rccm_net: str, + out_vin_net: str, + nl_input: Netlist, + nl_bias: Netlist, + nl_vcm: Netlist, + nl_sbcm: Netlist, + nl_rccm: Netlist, + show_netlist: bool = False, +) -> Netlist: + """ + Build top-level .subckt that instantiates child subckts and wires them to top nets. + TOP pin order must match layout header: + .subckt TOP VIN VSS VDD VOUT_RCCM VOUT_SBCM VOUT_VCM VAUX EN + """ + top_pins = [ + in_net, + "VSS", + "VDD", + out_vin_net, + out_rccm_net, + out_sbcm_net, + out_vcm_net, + aux_net, + en_net, + ] + + # Render children and parse headers + child_texts = { + "INPUT": nl_input.generate_netlist(), + "BIAS": nl_bias.generate_netlist(), + "VCM": nl_vcm.generate_netlist(), + "SBCM": nl_sbcm.generate_netlist(), + "RCCM": nl_rccm.generate_netlist(), + } + parsed = {} + for key, text in child_texts.items(): + subckt_name, pins = _parse_subckt_header(text) + parsed[key] = {"name": subckt_name, "pins": pins, "text": text} + + # Internal nets + in_vcm_int = "IN_VCM" + in_sbcm_int = "IN_SBCM" + in_rccm_int = "IN_RCCM" + + bias_rccm_int = "BIAS_RCCM" + + # Pin maps matching the child headers + # INPUT: .subckt INPUT VIN EN VOUT_VCM VOUT_BCM VOUT_CCM VDD + pinmap_input = { + "VIN": in_net, + "EN": en_net, + "VOUT_VCM": in_vcm_int, + "VOUT_BCM": in_sbcm_int, + "VOUT_CCM": in_rccm_int, + "VOUT_VIN": out_vin_net, + "VDD": "VDD", + } + # BIAS: .subckt BIAS IN_RCCM VAUX EN VDD + pinmap_bias = { + "VOUT": bias_rccm_int, + "VIN": aux_net, + "EN": en_net, + "VDD": "VDD", + "VSS": "VSS", + } + # VCM: .subckt VCM VIN VOUT VSS + pinmap_vcm = {"VIN": in_vcm_int, "VOUT": out_vcm_net, "VSS": "VSS"} + # SBCM: .subckt SBCM VIN VOUT VSS + pinmap_sbcm = {"VIN": in_sbcm_int, "VOUT": out_sbcm_net, "VSS": "VSS"} + # RCCM: .subckt RCCM VIN VAUX VOUT VSS + pinmap_rccm = { + "VIN": in_rccm_int, + "VAUX": bias_rccm_int, + "VOUT": out_rccm_net, + "VSS": "VSS", + } + + # Build instance lines using parsed child pin order + x_lines = [ + _instance_line( + f"{prefix}IN", + parsed["INPUT"]["name"], + parsed["INPUT"]["pins"], + pinmap_input, + ), + _instance_line( + f"{prefix}BIAS", + parsed["BIAS"]["name"], + parsed["BIAS"]["pins"], + pinmap_bias, + ), + _instance_line( + f"{prefix}VCM", + parsed["VCM"]["name"], + parsed["VCM"]["pins"], + pinmap_vcm, + ), + _instance_line( + f"{prefix}SBCM", + parsed["SBCM"]["name"], + parsed["SBCM"]["pins"], + pinmap_sbcm, + ), + _instance_line( + f"{prefix}RCCM", + parsed["RCCM"]["name"], + parsed["RCCM"]["pins"], + pinmap_rccm, + ), + ] + + # Write children FIRST, then TOP + src = [] + for key in ("INPUT", "BIAS", "VCM", "SBCM", "RCCM"): + src.append(parsed[key]["text"].rstrip()) + src.append("") + + src.append(f".subckt {prefix} " + " ".join(top_pins)) + src.extend(x_lines) + src.append(".ends " + prefix) + src.append("") + + source_netlist = "\n".join(src) + + topnet = Netlist( + circuit_name=prefix, + nodes=top_pins, + source_netlist=source_netlist, + instance_format="X{name} {nodes} {circuit_name}", + parameters={}, + ) + + if show_netlist: + print("Generated top-level netlist:\n") + print(topnet.generate_netlist()) + + return topnet + +# def generate_top_netlist( +# prefix: str, +# in_net: str, +# aux_net: str, +# en_net: str, +# out_vcm_net: str, +# out_sbcm_net: str, +# out_rccm_net: str, +# nl_input: Netlist, +# nl_vcm: Netlist, +# nl_sbcm: Netlist, +# nl_rccm: Netlist, +# show_netlist: bool = False, +# ) -> Netlist: +# """ +# Build top-level .subckt that instantiates child subckts and wires them to top nets. +# TOP pin order must match layout header: +# .subckt TOP VIN VSS VDD VOUT_RCCM VOUT_SBCM VOUT_VCM VAUX EN +# """ +# top_pins = [ +# in_net, +# "VSS", +# "VDD", +# out_rccm_net, +# out_sbcm_net, +# out_vcm_net, +# aux_net, +# en_net, +# ] + +# netlist = Netlist( +# circuit_name=prefix, +# nodes=top_pins, +# ) + + +# in_comp = netlist.connect_netlist(nl_input, [('VIN',in_net),('EN',en_net), ('VDD','VDD')]) +# vcm_comp = netlist.connect_netlist(nl_vcm, [('VOUT',out_vcm_net),('VSS','VSS')]) +# sbcm_comp = netlist.connect_netlist(nl_sbcm, [('VOUT',out_sbcm_net),('VSS','VSS')]) +# rccm_comp = netlist.connect_netlist(nl_rccm, [('VAUX',aux_net),('VOUT',out_rccm_net),('VSS','VSS')]) + +# netlist.connect_subnets(in_comp, vcm_comp, [('VOUT_VCM','VIN')]) +# netlist.connect_subnets(in_comp, sbcm_comp, [('VOUT_BCM','VIN')]) +# netlist.connect_subnets(in_comp, rccm_comp, [('VOUT_CCM','VIN')]) + +# if show_netlist: +# print("Generated top-level netlist:\n") +# print(netlist.generate_netlist()) + +# return netlist + + +# @validate_arguments +def top( + pdk: MappedPDK, + with_tie: Optional[bool] = True, + with_dummy: Optional[bool] = True, + tie_layers: tuple[str, str] = ("met2", "met1"), + show_netlist: Optional[bool] = False, + add_labels: bool = True, + **kwargs, +) -> Component: + """An instantiable self biased cascoded current mirror that returns a Component.""" + pdk.activate() + + # Create the current mirror component + top_level = Component(name="top_design") + top_ref = prec_ref_center(top_level) + + viam1m2 = via_stack(pdk, "met1", "met2", centered=True) + viam2m3 = via_stack(pdk, "met2", "met3", centered=True) + viam1m3 = via_stack(pdk, "met1", "met3", centered=True) + + # ------------------------------------------------------------------------- + # CREATING THE INPUT STAGE + # ------------------------------------------------------------------------- + print("Creating Input Stage ...") + + input_stage_comp = input_stage( + pdk, + num_cols=1, + Length=2, + Width=10, + device="pfet", + with_substrate_tap=False, + with_tie=with_tie, + with_dummy=with_dummy, + tie_layers=tie_layers, + add_labels=False, + ) + input_stage_ref = prec_ref_center(input_stage_comp) + input_stage_ref.move(top_ref.center) + top_level.add(input_stage_ref) + top_level.add_ports(input_stage_ref.get_ports_list(), prefix="input_") + + center = top_level.center + + # ------------------------------------------------------------------------- + # CREATING THE VANILLA CURRENT MIRROR STAGE + # ------------------------------------------------------------------------- + print("Creating Vanilla Current Mirror ...") + + VCM = current_mirror_base( + pdk, + num_cols=1, + Length=1, + Width=4, + device="nfet", + with_substrate_tap=False, + add_labels=False, + ) + vcm_ref = prec_ref_center(VCM) + vcm_ref.move(center).movex( + evaluate_bbox(input_stage_ref)[0] + 4 * pdk.util_max_metal_seperation() + ).movey(-evaluate_bbox(input_stage_ref)[1] / 2) + + top_level.add(vcm_ref) + top_level.add_ports(vcm_ref.get_ports_list(), prefix="vcm_") + + top_level << L_route( + pdk, vcm_ref.ports["IN_top_met_N"], input_stage_ref.ports["OUT_B_top_met_E"] + ) + + # ------------------------------------------------------------------------- + # CREATING THE SELF-BIASED CURRENT MIRROR STAGE + # ------------------------------------------------------------------------- + print("Creating Self-Biased Current Mirror ...") + + SBCM = self_biased_cascode_current_mirror( + pdk, num_cols=1, Length=1, Width=4, device="nfet", add_labels=False + ) + sbcm_ref = prec_ref_center(SBCM) + sbcm_ref.move(center).movex( + evaluate_bbox(input_stage_ref)[0] + 4 * pdk.util_max_metal_seperation() + ) + + top_level.add(sbcm_ref) + top_level.add_ports(sbcm_ref.get_ports_list(), prefix="sbcm_") + + top_level << L_route( + pdk, sbcm_ref.ports["IN_top_met_N"], input_stage_ref.ports["OUT_C_top_met_E"] + ) + + # ------------------------------------------------------------------------- + # CREATING THE REGULATED CASCODE CURRENT MIRROR STAGE + # ------------------------------------------------------------------------- + print("Creating Regulated Cascoded Current Mirror ...") + + RCCM = regulated_cascode_current_mirror( + pdk, num_cols=2, Length=1, Width=4, device="nfet", show_netlist=False, add_labels=False + ) + rccm_ref = prec_ref_center(RCCM) + rccm_ref.move(center).movex( + evaluate_bbox(input_stage_ref)[0] + 4 * pdk.util_max_metal_seperation() + ).movey(+evaluate_bbox(input_stage_ref)[1] / 2) + + top_level.add(rccm_ref) + top_level.add_ports(rccm_ref.get_ports_list(), prefix="rccm_") + + dist_via = abs( + rccm_ref.ports["IN_top_met_W"].center[0] + - rccm_ref.ports["IN_top_met_E"].center[0] + ) / 2 + + in_rccm_via = top_level << viam2m3 + in_rccm_via.move((input_stage_ref.ports["OUT_D_top_met_W"].center)).movex(dist_via) + + rccm_in_via = top_level << viam2m3 + rccm_in_via.move((rccm_ref.ports["IN_top_met_W"].center)).movex(dist_via) + + + top_level << L_route( + pdk, in_rccm_via.ports["top_met_N"], rccm_in_via.ports["top_met_W"], hglayer="met3", vglayer="met3", + ) + + # ------------------------------------------------------------------------- + # CREATING THE BIAS STAGE + # ------------------------------------------------------------------------- + print("Creating Bias Stage ...") + + bias_stage_comp = bias_stage( + pdk, + add_labels=False, + ) + bias_stage_ref = prec_ref_center(bias_stage_comp) + + bias_stage_ref.move(center).movex( + -3 * evaluate_bbox(input_stage_ref)[0] - 6 * pdk.util_max_metal_seperation() + ).movey(+evaluate_bbox(input_stage_ref)[1] / 2 + evaluate_bbox(sbcm_ref)[1] / 2 + 6 * pdk.util_max_metal_seperation()) + bias_stage_ref.move(center) + top_level.add(bias_stage_ref) + top_level.add_ports(bias_stage_ref.get_ports_list(), prefix="bias_") + + + # ------------------------------------------------------------------------- + # CONNECTING AUX + # ------------------------------------------------------------------------- + + + top_level << L_route( + pdk, bias_stage_ref.ports["base_right_OUT_top_met_N"], rccm_ref.ports["AUX_A_top_met_W"], hglayer="met1", vglayer="met1", + ) + + en_via = top_level << viam1m2 + en_via.move(bias_stage_ref.ports["fet_right_multiplier_0_gate_E"].center).movex(evaluate_bbox(bias_stage_ref)[0]) + top_level.add_ports(en_via.get_ports_list(), prefix=f"EN_") + + top_level << straight_route( + pdk, + bias_stage_ref.ports["fet_right_multiplier_0_gate_E"], + en_via.ports["top_met_W"], + glayer1="met2", + glayer2="met2", + ) + + en_input_via = top_level << viam2m3 + en_input_via.move((input_stage_ref.ports["EN_A_top_met_N"].center[0], en_via.center[1])) + + en_input_conn_via = top_level << viam2m3 + en_input_conn_via.move(input_stage_ref.ports["EN_A_top_met_N"].center) + + top_level << straight_route( + pdk, + en_input_via.ports["top_met_S"], + en_input_conn_via.ports["top_met_S"], + glayer1="met3", + glayer2="met3", + ) + + aux_via = top_level << viam2m3 + aux_via.move(en_via.center).movey(evaluate_bbox(rccm_ref)[1]) + top_level.add_ports(aux_via.get_ports_list(), prefix=f"VAUX_") + + ##### This one Met 3 + top_level << L_route( + pdk, + bias_stage_ref.ports["base_left_IN_top_met_N"], + aux_via.ports["top_met_W"], + hglayer="met3", vglayer="met2" + ) + + # Outputs + + vcm_via = top_level << viam1m2 + vcm_via.move((en_via.center[0], vcm_ref.ports["OUT_top_met_W"].center[1])) + top_level.add_ports(vcm_via.get_ports_list(), prefix=f"VOUT_VCM_") + + top_level << straight_route( + pdk, + vcm_via.ports["top_met_W"], + vcm_ref.ports["OUT_top_met_E"], + glayer1="met2", + glayer2="met2", + ) + + sbcm_via = top_level << viam1m2 + sbcm_via.move((en_via.center[0], sbcm_ref.ports["OUT_top_met_W"].center[1])) + top_level.add_ports(sbcm_via.get_ports_list(), prefix=f"VOUT_SBCM_") + + top_level << straight_route( + pdk, + sbcm_via.ports["top_met_W"], + sbcm_ref.ports["OUT_top_met_E"], + glayer1="met2", + glayer2="met2", + ) + + rccm_via = top_level << viam1m2 + rccm_via.move((en_via.center[0], rccm_ref.ports["OUT_top_met_W"].center[1])) + top_level.add_ports(rccm_via.get_ports_list(), prefix=f"VOUT_RCCM_") + + top_level << straight_route( + pdk, + rccm_via.ports["top_met_W"], + rccm_ref.ports["OUT_top_met_E"], + glayer1="met2", + glayer2="met2", + ) + + outvin_via = top_level << viam1m2 + outvin_via.move(en_via.center).movey(-evaluate_bbox(vcm_ref)[1] + 6 * pdk.util_max_metal_seperation()) + top_level.add_ports(outvin_via.get_ports_list(), prefix=f"VOUT_VIN_") + + top_level << L_route( + pdk, input_stage_ref.ports["OUT_E_top_met_N"], outvin_via.ports["top_met_W"], hglayer="met2", vglayer="met2", + ) + + # Input + + vin1_via = top_level << viam1m2 + vin1_via.move(input_stage_ref.ports["IN_A_top_met_N"].center).movey(-evaluate_bbox(sbcm_ref)[1]) + + vin2_via = top_level << viam1m2 + vin2_via.move(vin1_via.center).movex(2*evaluate_bbox(input_stage_ref)[0]) + + vin3_via = top_level << viam1m2 + vin3_via.move(aux_via.center).movey(evaluate_bbox(rccm_ref)[1]) + top_level.add_ports(vin3_via.get_ports_list(), prefix=f"VIN_") + + top_level << straight_route( + pdk, + input_stage_ref.ports["IN_A_top_met_S"], + vin1_via.ports["top_met_N"], + glayer1="met1", + glayer2="met1", + ) + + top_level << straight_route( + pdk, + vin1_via.ports["top_met_E"], + vin2_via.ports["top_met_W"], + glayer1="met1", + glayer2="met1", + ) + + top_level << L_route( + pdk, + vin2_via.ports["top_met_N"], + vin3_via.ports["top_met_W"], + hglayer="met1", vglayer="met1", + ) + + # VSS + + vss_via = top_level << viam1m3 + vss_via.move(vin3_via.center).movey(evaluate_bbox(rccm_ref)[1]) + top_level.add_ports(vss_via.get_ports_list(), prefix=f"VSS_") + + top_level << L_route( + pdk, + vss_via.ports["top_met_W"], + rccm_ref.ports["welltie_N_top_met_N"], + hglayer="met1", vglayer="met1", + vwidth=5, hwidth=5 + ) + + ###### DRC_Error + # handles = place_welltie_via_row( + # top_level, pdk, "bias_base_bottom", + # top_layer="met3", + # use_edges=False, offset=5.0, + # fill_mode="auto", + # ) + + # top_level << L_route( + # pdk, + # bias_stage_ref.ports["base_bottom_welltie_N_top_met_N"], + # vss_via.ports["top_met_W"], + # hglayer="met3", vglayer="met3", + # vwidth=12, hwidth=12, + # ) + ####################################################### + + # VDD + vdd_via = top_level << viam1m2 + vdd_via.move(vss_via.center).movey(evaluate_bbox(rccm_ref)[1]) + top_level.add_ports(vdd_via.get_ports_list(), prefix=f"VDD_") + + top_level << L_route( + pdk, + vdd_via.ports["top_met_W"], + bias_stage_ref.ports["fet_left_tie_N_top_met_N"], + hglayer="met1", vglayer="met1", + vwidth=5, hwidth=5 + ) + + + # ------------------------------------------------------------------------- + # CONNECTING VDD TOGETHER + # ------------------------------------------------------------------------- + + top_level << straight_route( + pdk, + bias_stage_ref.ports["VDD_port"], + top_level.ports["input_welltie_W_top_met_W"], + glayer1="met1", + glayer2="met1", + width=10, + ) + + # ------------------------------------------------------------------------- + # CONNECTING VSS TOGETHER + # ------------------------------------------------------------------------- + top_level << straight_route( + pdk, + top_level.ports["vcm_welltie_N_top_met_N"], + top_level.ports["sbcm_welltie_S_top_met_S"], + glayer1="met1", + glayer2="met1", + width=10, + ) + top_level << straight_route( + pdk, + top_level.ports["sbcm_welltie_N_top_met_N"], + top_level.ports["rccm_welltie_S_top_met_S"], + glayer1="met1", + glayer2="met1", + width=10, + ) + + top_level << L_route( + pdk, + bias_stage_ref.ports["base_bottom_welltie_N_top_met_N"], + vss_via.ports["top_met_W"], + hglayer="met2", vglayer="met2", + vwidth=12, hwidth=12, + ) + + top_level = component_snap_to_grid(rename_ports_by_orientation(top_level)) + + top_level.info["netlist"] = generate_top_netlist( + prefix="TOP", + in_net="VIN", + aux_net="VAUX", + en_net="EN", + out_vcm_net="VOUT_VCM", + out_sbcm_net="VOUT_SBCM", + out_rccm_net="VOUT_RCCM", + out_vin_net="VOUT_VIN", + nl_input=input_stage_comp.info["netlist"], + nl_bias=bias_stage_comp.info["netlist"], + nl_vcm=VCM.info["netlist"], + nl_sbcm=SBCM.info["netlist"], + nl_rccm=RCCM.info["netlist"], + show_netlist=show_netlist, + ) + + if add_labels: + return add_cm_labels(top_level, pdk) + return top_level + +def add_cm_labels(cm_in: Component, pdk: MappedPDK) -> Component: + cm_in.unlock() + + psize = (0.35, 0.35) + move_info = [] + + # VIN + vinlabel = rectangle(layer=pdk.get_glayer("met2_pin"), size=psize, centered=True).copy() + vinlabel.add_label(text="VIN", layer=pdk.get_glayer("met2_label")) + move_info.append((vinlabel, cm_in.ports["VIN_top_met_E"], None)) + + # EN + vEnlabel = rectangle(layer=pdk.get_glayer("met2_pin"), size=psize, centered=True).copy() + vEnlabel.add_label(text="EN", layer=pdk.get_glayer("met2_label")) + move_info.append((vEnlabel, cm_in.ports["EN_top_met_E"], None)) + + # VAUX + vauxlabel = rectangle(layer=pdk.get_glayer("met2_pin"), size=psize, centered=True).copy() + vauxlabel.add_label(text="VAUX", layer=pdk.get_glayer("met2_label")) + move_info.append((vauxlabel, cm_in.ports["VAUX_top_met_E"], None)) + + # VOUT VCM + voutvcmlabel = rectangle(layer=pdk.get_glayer("met2_pin"), size=psize, centered=True).copy() + voutvcmlabel.add_label(text="VOUT_VCM", layer=pdk.get_glayer("met2_label")) + move_info.append((voutvcmlabel, cm_in.ports["VOUT_VCM_top_met_E"], None)) + + # VOUT SBCM + voutsbcmlabel = rectangle(layer=pdk.get_glayer("met2_pin"), size=psize, centered=True).copy() + voutsbcmlabel.add_label(text="VOUT_SBCM", layer=pdk.get_glayer("met2_label")) + move_info.append((voutsbcmlabel, cm_in.ports["VOUT_SBCM_top_met_E"], None)) + + # VOUT RCCM + voutrccmlabel = rectangle(layer=pdk.get_glayer("met2_pin"), size=psize, centered=True).copy() + voutrccmlabel.add_label(text="VOUT_RCCM", layer=pdk.get_glayer("met2_label")) + move_info.append((voutrccmlabel, cm_in.ports["VOUT_RCCM_top_met_E"], None)) + + # VOUT VIN + voutvinlabel = rectangle(layer=pdk.get_glayer("met2_pin"), size=psize, centered=True).copy() + voutvinlabel.add_label(text="VOUT_VIN", layer=pdk.get_glayer("met2_label")) + move_info.append((voutvinlabel, cm_in.ports["VOUT_VIN_top_met_E"], None)) + + # VDD (well tie) + vddlabel = rectangle(layer=pdk.get_glayer("met1_pin"), size=psize, centered=True).copy() + vddlabel.add_label(text="VDD", layer=pdk.get_glayer("met1_label")) + move_info.append((vddlabel, cm_in.ports["VDD_top_met_E"], None)) + + # VSS (well tie) + vsslabel = rectangle(layer=pdk.get_glayer("met1_pin"), size=psize, centered=True).copy() + vsslabel.add_label(text="VSS", layer=pdk.get_glayer("met1_label")) + move_info.append((vsslabel, cm_in.ports["VSS_top_met_E"], None)) + + # + + for comp, prt, alignment in move_info: + alignment = ("c", "b") if alignment is None else alignment + compref = align_comp_to_port(comp, prt, alignment=alignment) + cm_in.add(compref) + + return cm_in.flatten() + + +def place_welltie_via_row( + top_level, + pdk, + block_key: str=None, # expects f"{block_key}_welltie_S_top_met_S" + *, + top_layer: str = "met3", # top layer to reach (string, e.g. "met3") + # Where to put the two edge via stacks: + use_edges: bool = True, # True: at ± welltie.width/2; False: at ±offset + offset: float = 5.0, # used when use_edges=False (distance from center) + jog_dy: float = 0.0, # vertical offset for the whole via row center + + # How to fill middle stacks: mode ∈ {"auto","pitch","count"} + fill_mode: str = "auto", + pitch: float | None = None, # used when fill_mode="pitch" + count: int | None = None, # used when fill_mode="count" + edge_margin: float = 0.0, # keep gap from edges for "pitch" mode +): + """ + Returns dict with keys: + left_ref, right_ref: ComponentReference of edge stacks + left_top, right_top: Port on top_layer for each edge stack + mid_refs: list[ComponentReference] for middle stacks + mid_top_ports: list[Port] top ports for middle stacks + """ + # --- 1) resolve the welltie S-facing top-metal port --- + + wt = top_level.ports[f"{block_key}_welltie_N_top_met_N"] # Port (likely on met1 or met2) + + delta_y = abs(top_level.ports[f"{block_key}_welltie_N_top_met_N"].center[1] - top_level.ports[f"{block_key}_welltie_N_top_met_S"].center[1])/2 + x0, y0 = wt.center + + w_wt = wt.width + + # --- 2) utilities: mapping layer tuple<->name and grid snapping --- + def _name_of(gl_tuple): + for nm in ("met1","met2","met3","met4","met5"): + try: + if pdk.get_glayer(nm) == gl_tuple: + return nm + except Exception: + pass + raise ValueError(f"Unknown layer tuple {gl_tuple}") + + snap = pdk.snap_to_2xgrid + bottom_layer = _name_of(wt.layer) # e.g. "met1" or "met2" + bot_gl = pdk.get_glayer(bottom_layer) + top_gl = pdk.get_glayer(top_layer) + + # --- 3) edge stack X positions --- + if use_edges: + xL = snap(x0 - w_wt/2) + xR = snap(x0 + w_wt/2) + else: + xL = snap(x0 - abs(offset)) + xR = snap(x0 + abs(offset)) + yC = snap(y0 - delta_y+ jog_dy) + + # --- 4) create via stack template and place the two edge stacks (as refs) --- + vs_proto = via_stack(pdk, bottom_layer, top_layer) # Component + left_ref = top_level << vs_proto # ComponentReference + right_ref = top_level << vs_proto + left_ref.move((xL, yC)) + right_ref.move((xR, yC)) + + # helper to pick bottom/top ports of a via ref + def _bottom_port(vref): + return next(p for p in vref.ports.values() if p.layer == bot_gl) + def _top_port(vref): + return next(p for p in vref.ports.values() if p.layer == top_gl) + + left_bot = _bottom_port(left_ref) + right_bot = _bottom_port(right_ref) + left_top = _top_port(left_ref) + right_top = _top_port(right_ref) + + + # --- 6) compute middle positions depending on fill_mode --- + mid_refs = [] + mid_top_ports = [] + + xL_center, _ = left_ref.center + xR_center, _ = right_ref.center + + if fill_mode not in {"auto","pitch","count"}: + raise ValueError("fill_mode must be one of {'auto','pitch','count'}") + + if fill_mode == "count": + n = int(count or 0) + if n > 0: + step = (xR_center - xL_center) / (n + 1) + for k in range(1, n+1): + xk = snap(xL_center + k*step) + r = top_level << vs_proto + r.move((xk, yC)) + mid_refs.append(r) + mid_top_ports.append(_top_port(r)) + + else: + # need a pitch value: either provided, or auto-computed + if fill_mode == "pitch": + if pitch is None or pitch <= 0: + raise ValueError("fill_mode='pitch' requires a positive 'pitch' parameter.") + eff_pitch = float(pitch) + else: + # "auto": via width on top layer + min spacing of that layer + # get via *component* width on x from template bbox + vx, _vy = evaluate_bbox(vs_proto) # (w, h) in layout units + min_sp = pdk.get_grule(top_layer)["min_separation"] + eff_pitch = snap(vx + min_sp) + + x_start = snap(xL_center + edge_margin) + x_stop = snap(xR_center - edge_margin) + + x = x_start + eff_pitch + # leave small epsilon to avoid placing on/over the right ref + while x < x_stop - 1e-6: + r = top_level << vs_proto + r.move((snap(x), yC)) + mid_refs.append(r) + mid_top_ports.append(_top_port(r)) + x += eff_pitch + + return { + "left_ref": left_ref, "right_ref": right_ref, + "left_top": left_top, "right_top": right_top, + "mid_refs": mid_refs, "mid_top_ports": mid_top_ports, + } + + +if __name__ == "__main__": + selected_pdk = gf180 + + # DRC + drc_result = selected_pdk.drc_magic("gds/top.gds", "TOP", output_file=Path("DRC/")) + + # LVS + netgen_lvs_result = selected_pdk.lvs_netgen( + "gds/top.gds", "TOP", netlist="gds/top_new.spice", output_file_path=Path("LVS/"), copy_intermediate_files=True + ) diff --git a/blocks/composite/regulated_cascoded_cmirror/n_fets_fingers.py b/blocks/composite/regulated_cascoded_cmirror/n_fets_fingers.py new file mode 100644 index 00000000..f2182a48 --- /dev/null +++ b/blocks/composite/regulated_cascoded_cmirror/n_fets_fingers.py @@ -0,0 +1,596 @@ +from pathlib import Path +from glayout.pdk.mappedpdk import MappedPDK +from pydantic import validate_arguments +from gdsfactory.component import Component +from glayout.primitives.fet import nmos, pmos, multiplier +from glayout.util.comp_utils import evaluate_bbox +from typing import Literal, Union, List, Tuple +from glayout.util.port_utils import rename_ports_by_orientation, rename_ports_by_list, create_private_ports +from glayout.util.comp_utils import prec_ref_center,evaluate_bbox, prec_center, align_comp_to_port +from glayout.routing.straight_route import straight_route +from gdsfactory.functions import transformed +from glayout.primitives.guardring import tapring +from glayout.util.port_utils import add_ports_perimeter +from gdsfactory.cell import clear_cache +from typing import Literal, Optional, Union +from glayout.pdk.sky130_mapped import sky130_mapped_pdk +from glayout.pdk.gf180_mapped import gf180_mapped_pdk +from glayout.spice.netlist import Netlist +from gdsfactory.components import text_freetype, rectangle +from glayout.primitives.via_gen import via_stack +import re + +from glayout import MappedPDK, sky130,gf180 + +from glayout.util.snap_to_grid import component_snap_to_grid +from glayout.placement.two_transistor_interdigitized import two_nfet_interdigitized, two_pfet_interdigitized + +###### Only Required for IIC-OSIC Docker +import os +import subprocess + +# Run a shell, source .bashrc, then printenv +cmd = 'bash -c "source ~/.bashrc && printenv"' +result = subprocess.run(cmd, shell=True, text=True, capture_output=True) +env_vars = {} +for line in result.stdout.splitlines(): + if '=' in line: + key, value = line.split('=', 1) + env_vars[key] = value + +# Now, update os.environ with these +os.environ.update(env_vars) + +#from glayout.placement.two_transistor_interdigitized import two_nfet_interdigitized; from glayout.pdk.sky130_mapped import sky130_mapped_pdk as pdk; biasParams=[6,2,4]; rmult=2 +def add_n_int_labels( + device_int_in: Component, + pdk: MappedPDK, + *, + n_or_p_fet: Literal["nfet", "pfet"] = "nfet", + width: Optional[float] = 3.0, + length: Optional[float] = None, + fingers: int = 1, + multipliers: int = 1, + with_dummy: bool = False, +) -> Component: + """ + - Auto-detects device prefixes (A_, B_, C_, ...) from the component's ports. + - Adds labels VSSi / VDDi / VGi next to source / drain / gate ports. + - Creates and attaches a Netlist with Xi VDDi VGi VSSi VB . + """ + + device_int_in.unlock() + + # -------- 1) Discover device prefixes (A_, B_, C_, ...) -------- + # We detect prefixes by looking for ports named "_source_*", "_drain_*", "_gate_*" + prefixes = set() + src_pat = re.compile(r"^([A-Za-z]+)_source_[A-Z]$") + drn_pat = re.compile(r"^([A-Za-z]+)_drain_[A-Z]$") + gate_pat = re.compile(r"^([A-Za-z]+)_gate_[A-Z]$") + + for pname in device_int_in.ports.keys(): + m = src_pat.match(pname) or drn_pat.match(pname) or gate_pat.match(pname) + if m: + prefixes.add(m.group(1)) + + # Sort prefixes alphabetically so numbering is deterministic: A,B,C,... → 1,2,3,... + prefixes = sorted(prefixes) + if not prefixes: + raise ValueError("Could not detect any device prefixes (e.g., A_, B_, ...) from ports.") + + # Helper to resolve a port robustly for a given prefix and role + def _resolve_port(prefix: str, role: str) -> str: + """ + role ∈ {'source','drain','gate'} + Prefer specific orientations if available, otherwise any matching role. + """ + # Try common orientations first + candidates_ordered = { + "source": [f"{prefix}_source_E", f"{prefix}_source_W", f"{prefix}_source_N", f"{prefix}_source_S"], + "drain": [f"{prefix}_drain_E", f"{prefix}_drain_W", f"{prefix}_drain_N", f"{prefix}_drain_S"], + "gate": [f"{prefix}_gate_S", f"{prefix}_gate_N", f"{prefix}_gate_E", f"{prefix}_gate_W"], + }[role] + for c in candidates_ordered: + if c in device_int_in.ports: + return c + # Fallback: first any port matching the role + for pname in device_int_in.ports.keys(): + if pname.startswith(f"{prefix}_{role}_"): + return pname + raise KeyError(f"No port found for {prefix} {role}") + + # -------- 2) Add labels for each device i -------- + move_info = [] + for i, prefix in enumerate(prefixes, start=1): + # VSSi at source + vss = rectangle(layer=pdk.get_glayer("met2_pin"), size=(0.27, 0.27), centered=True).copy() + vss.add_label(text=f"VSS{i}", layer=pdk.get_glayer("met2_label")) + move_info.append((vss, device_int_in.ports[_resolve_port(prefix, "source")], None)) + + # VDDi at drain + vdd = rectangle(layer=pdk.get_glayer("met2_pin"), size=(0.27, 0.27), centered=True).copy() + vdd.add_label(text=f"VDD{i}", layer=pdk.get_glayer("met2_label")) + move_info.append((vdd, device_int_in.ports[_resolve_port(prefix, "drain")], None)) + + # VGi at gate + vg = rectangle(layer=pdk.get_glayer("met2_pin"), size=(0.27, 0.27), centered=True).copy() + vg.add_label(text=f"VG{i}", layer=pdk.get_glayer("met2_label")) + move_info.append((vg, device_int_in.ports[_resolve_port(prefix, "gate")], None)) + + # Bulk (VB) — try a generic well tie port name; if missing, skip label quietly + try: + vb_rect = rectangle(layer=pdk.get_glayer("met2_pin"), size=(0.5, 0.5), centered=True).copy() + vb_rect.add_label(text="VB", layer=pdk.get_glayer("met2_label")) + move_info.append((vb_rect, device_int_in.ports["welltie_S_top_met_S"], None)) + except KeyError: + # If your well-tie port is named differently, add another try here or ignore + pass + + # Place all labels + for comp, prt, alignment in move_info: + alignment = ('c', 'b') if alignment is None else alignment + compref = align_comp_to_port(comp, prt, alignment=alignment) + device_int_in.add(compref) + + # -------- 3) Generate & attach Netlist with N devices -------- + if length is None: + length = pdk.get_grule("poly")["min_width"] + if width is None: + width = 3.0 + + model = pdk.models[n_or_p_fet] + mtop = fingers * multipliers + N = len(prefixes) + + # Build .subckt body + # Nodes order: VDD1..N, VSS1..N, VG1..N, VB (or any ordering you prefer) + nodes = ( + [f"VDD{i}" for i in range(1, N + 1)] + + [f"VSS{i}" for i in range(1, N + 1)] + + [f"VG{i}" for i in range(1, N + 1)] + + ["VB"] + ) + + lines = [f".subckt {{circuit_name}} {' '.join(nodes)} l={length} w={width} m=1"] + # XAi lines + for i in range(1, N + 1): + lines.append(f"X{i} VDD{i} VG{i} VSS{i} VB {model} l={length} w={width} m={mtop}") + if with_dummy: + lines.append(f"XDUMMY VB VB VB VB {model} l={length} w={width} m=2") + lines.append(".ends {circuit_name}") + source_netlist = "\n".join(lines) + + device_int_in.info["netlist"] = Netlist( + circuit_name=f"{N}_trans_interdigitized", + nodes=nodes, + source_netlist=source_netlist, + instance_format="X{name} {nodes} {circuit_name} l={length} w={width} m=1", + parameters={ + "model": model, + "width": width, + "length": length, + "mult": multipliers, + }, + ) + + return device_int_in.flatten() + + +# === New: CLUSTERED (non-interdigitized) placement === + +def n_tran_clustered_netlist( + pdk: MappedPDK, + width: Optional[float], + length: Optional[float], + fingers: int, + numcols: int, + with_dummy: bool = True, + n_or_p_fet: Literal['nfet','pfet'] = 'nfet', + n_devices: int = 2, +) -> Netlist: + """ + Build a subcircuit with N clustered transistors (no interdigitation). + Each Xi has m = fingers * numcols. + Nodes per device i: VDDi, VGi, VSSi, VB + """ + if length is None: + length = pdk.get_grule('poly')['min_width'] + if width is None: + width = 3.0 + + model = pdk.models[n_or_p_fet] + mtop = fingers * numcols + N = int(n_devices) + + nodes = ( + [f"VDD{i}" for i in range(1, N+1)] + + [f"VSS{i}" for i in range(1, N+1)] + + [f"VG{i}" for i in range(1, N+1)] + + ["VB"] + ) + + lines = [f".subckt {{circuit_name}} {' '.join(nodes)} l={length} w={width} m=1"] + for i in range(1, N+1): + lines.append(f"X{i} VDD{i} VG{i} VSS{i} VB {model} l={length} w={width} m={mtop}") + if with_dummy: + lines.append(f"XDUMMY VB VB VB VB {model} l={length} w={width} m=2") + lines.append(".ends {circuit_name}") + + return Netlist( + circuit_name=f"{N}_trans_clustered", + nodes=nodes, + source_netlist="\n".join(lines), + instance_format="X{name} {nodes} {circuit_name} l={length} w={width} m=1", + parameters={ + 'model': model, + 'width': width, + 'length': length, + 'mult': numcols, + } + ) + +def _letters(n: int) -> List[str]: + """Return ['A','B','C',...] up to n (supports up to 26 cleanly).""" + if n < 1: + raise ValueError("n_devices must be >= 1") + if n > 26: + # Simple guard; extend to AA/AB... if you need more than 26. + raise ValueError("This helper supports at most 26 devices (A..Z).") + import string + return list(string.ascii_uppercase[:n]) + +def _find_port(cref, patterns: list[str]) -> str | None: + """Return first matching port name on cref given a list of regex patterns.""" + for pat in patterns: + rx = re.compile(pat) + for pname in cref.ports.keys(): + if rx.fullmatch(pname): + return pname + return None + + +@validate_arguments +def macro_n_transistor_clustered( + pdk: MappedPDK, + numcols: int, # columns per device block (repeated unit cells) + devices: Literal["nfet", "pfet"], + n_devices: int, # how many device blocks: A, B, C, ... + dummy: Union[bool, tuple[bool, bool]] = True, # left/right edge dummies on the whole row + **kwargs, +) -> Component: + """ + Place N device *blocks* side-by-side. + Each block = numcols repeated 'multiplier(**kwargs)' cells of the SAME device, + shorted to share gate and S/D rails (clustered fingers, not interdigitized). + Exposes ports per device block: e.g., A_source_*, A_drain_*, A_gate_*; then B_*, etc. + """ + if isinstance(dummy, bool): + dummy = (dummy, dummy) + + # Base kwargs + k = dict(kwargs) + k["pdk"] = pdk + k["sdlayer"] = "n+s/d" if devices == "nfet" else "p+s/d" + # Keep consistent routes inside a block + k.setdefault("sd_route_extension", 0) + k.setdefault("gate_route_extension", 0) + k.setdefault("dummy", False) + + letters = _letters(n_devices) + row = Component() + + # Build a single "unit" for this device type (matched extents) + unit = multiplier(**k) + u_bbox = evaluate_bbox(unit) + pitch = pdk.snap_to_2xgrid(u_bbox[0] + pdk.get_grule("active_diff")["min_separation"]) + + blocks = [] # list[(L, [cref0..cref{numcols-1}])] + x = 0.0 + + for bi, L in enumerate(letters): + # For the first and last block, optionally add edge dummies within the block + left_edge = (bi == 0) and dummy[0] + right_edge = (bi == n_devices - 1) and dummy[1] + + # Build the block + refs = [] + + inter_col = numcols + + if dummy[0]: + inter_col -= 1 + if dummy[1]: + inter_col -= 1 + + + # Left dummy (only if requested for the *row* edge) + if left_edge: + kL = dict(k); kL["dummy"] = (True, False) + dL = row << multiplier(**kL) + dL.movex(x); refs.append(dL); x += pitch + + # numcols repeated real devices for this block + kC = dict(k); kC["dummy"] = False + for ci in range(inter_col): + c = row << multiplier(**kC) + c.name = f"{L}_{ci}" + c.movex(x); refs.append(c); x += pitch + + # Right dummy (only if requested for the *row* edge) + if right_edge: + kR = dict(k); kR["dummy"] = (False, True) + dR = row << multiplier(**kR) + dR.movex(x); refs.append(dR); x += pitch + + blocks.append((L, refs)) + + # Add per-instance ports (scoped under letter for clarity) + for idx, r in enumerate(refs): + row.add_ports(r.get_ports_list(), prefix=f"{L}_{idx}_") + + # Add per-instance ports (scoped under letter for clarity) + # for r in refs: + # row.add_ports(r.get_ports_list(), prefix=f"{L}_inst_") + + # Stitch block-internal rails so the block shares S/D and Gate + # Find first/last *real* cell indices inside refs (skip block-edge dummies) + start_idx = 1 if left_edge else 0 + end_idx = (len(refs)-2) if right_edge else (len(refs)-1) + + first = refs[0]; last = refs[-1] + + # Tie S/D top metals across the block + for r in refs[0:-1]: + end_layer = pdk.layer_to_glayer(r.ports["row0_col0_rightsd_top_met_N"].layer) + row << straight_route(pdk, r.ports["row0_col0_rightsd_top_met_N"], last.ports["drain_E"], glayer2=end_layer) + row << straight_route(pdk, r.ports["leftsd_top_met_N"], last.ports["drain_E"], glayer2=end_layer) + + # Tie gate poly across the block + for r in refs[0:-1]: + row << straight_route(pdk, r.ports["row0_col0_gate_N"], last.ports["gate_E"], glayer1="poly", glayer2="poly") + + # Expose one set of ports per device block (A_*, B_*, ...) + # Use the first and last real cells to create block-wide W/E bus ports. + # Source/Drain buses: + try: + # West/East ends + sW = first.ports["source_W"]; sE = last.ports["source_E"] + dW = first.ports["drain_W"]; dE = last.ports["drain_E"] + gW = first.ports["gate_W"]; gE = last.ports["gate_E"] + + # Create stitched routes so we can expose neat block ports + # (no-op if already continuous from the loops above) + row << straight_route(pdk, sW, sE) + row << straight_route(pdk, dW, dE) + row << straight_route(pdk, gW, gE, glayer1="met2", glayer2="met2") + + # Add named block ports + row.add_port(name=f"{L}_source_W", port=sW) + row.add_port(name=f"{L}_source_E", port=sE) + row.add_port(name=f"{L}_drain_W", port=dW) + row.add_port(name=f"{L}_drain_E", port=dE) + row.add_port(name=f"{L}_gate_W", port=gW) + row.add_port(name=f"{L}_gate_E", port=gE) + + # Also expose the “convenience” N/S ports if present on the last cell + for pname in ["gate_S","gate_N","diff_N","diff_S"]: + pp = f"{pname}" + if pp in last.ports: + row.add_port(name=f"{L}_{pp}", port=last.ports[pp]) + except KeyError: + # Layout variants may name ports slightly differently; adapt here if needed. + pass + + # Merge doped region along the full row (optional but helpful for DRC/matching) + first_cell = blocks[0][1][0] + last_cell = blocks[-1][1][-1] + row << straight_route(pdk, first_cell.ports["plusdoped_W"], last_cell.ports["plusdoped_E"]) + + row = transformed(prec_ref_center(row)) + row.unlock() + return row + + +@validate_arguments +def n_nfet_clustered( + pdk: MappedPDK, + numcols: int, + n_devices: int, + dummy: Union[bool, tuple[bool, bool]] = True, + with_substrate_tap: bool = True, + with_tie: bool = True, + tie_layers: tuple[str, str] = ("met2", "met1"), + **kwargs, +) -> Component: + base = macro_n_transistor_clustered( + pdk=pdk, numcols=numcols, devices="nfet", n_devices=n_devices, dummy=dummy, **kwargs + ) + + # Well tie ring + if with_tie: + tap_sep = max( + pdk.util_max_metal_seperation(), + pdk.get_grule("active_diff", "active_tap")["min_separation"], + ) + tap_sep += pdk.get_grule("p+s/d", "active_tap")["min_enclosure"] + encl = (2 * (tap_sep + base.xmax), 2 * (tap_sep + base.ymax)) + tr = base << tapring(pdk, enclosed_rectangle=encl, sdlayer="p+s/d", + horizontal_glayer=tie_layers[0], vertical_glayer=tie_layers[1]) + base.add_ports(tr.get_ports_list(), prefix="welltie_") + + # pwell padding + perimeter ports + base.add_padding(layers=(pdk.get_glayer("pwell"),), + default=pdk.get_grule("pwell", "active_tap")["min_enclosure"]) + base = add_ports_perimeter(base, layer=pdk.get_glayer("pwell"), prefix="well_") + + # Outer substrate tap + if with_substrate_tap: + sep = pdk.get_grule("dnwell", "active_tap")["min_separation"] + encl = (2 * (sep + base.xmax), 2 * (sep + base.ymax)) + tr = base << tapring(pdk, enclosed_rectangle=encl, sdlayer="p+s/d", + horizontal_glayer="met2", vertical_glayer="met1") + base.add_ports(tr.get_ports_list(), prefix="substratetap_") + + base.info["route_genid"] = "n_transistor_clustered" + base.info["netlist"] = n_tran_clustered_netlist( + pdk=pdk, + width=kwargs.get("width", 3), + length=kwargs.get("length", 0.15), + fingers=kwargs.get("fingers", 1), + numcols=numcols, + with_dummy=bool(dummy) if isinstance(dummy, bool) else any(dummy), + n_or_p_fet="nfet", + n_devices=n_devices, + ) + return base + + +@validate_arguments +def n_pfet_clustered( + pdk: MappedPDK, + numcols: int, + n_devices: int, + dummy: Union[bool, tuple[bool, bool]] = True, + with_substrate_tap: bool = True, + with_tie: bool = True, + tie_layers: tuple[str, str] = ("met2", "met1"), + **kwargs, +) -> Component: + base = macro_n_transistor_clustered( + pdk=pdk, numcols=numcols, devices="pfet", n_devices=n_devices, dummy=dummy, **kwargs + ) + + # Well tie ring + if with_tie: + tap_sep = max( + pdk.util_max_metal_seperation(), + pdk.get_grule("active_diff", "active_tap")["min_separation"], + ) + tap_sep += pdk.get_grule("n+s/d", "active_tap")["min_enclosure"] + encl = (2 * (tap_sep + base.xmax), 2 * (tap_sep + base.ymax)) + tr = base << tapring(pdk, enclosed_rectangle=encl, sdlayer="n+s/d", + horizontal_glayer=tie_layers[0], vertical_glayer=tie_layers[1]) + base.add_ports(tr.get_ports_list(), prefix="welltie_") + + # nwell padding + perimeter ports + base.add_padding(layers=(pdk.get_glayer("nwell"),), + default=pdk.get_grule("nwell", "active_tap")["min_enclosure"]) + base = add_ports_perimeter(base, layer=pdk.get_glayer("nwell"), prefix="well_") + + # Outer substrate tap + if with_substrate_tap: + sep = pdk.get_grule("dnwell", "active_tap")["min_separation"] + encl = (2 * (sep + base.xmax), 2 * (sep + base.ymax)) + tr = base << tapring(pdk, enclosed_rectangle=encl, sdlayer="p+s/d", + horizontal_glayer="met2", vertical_glayer="met1") + base.add_ports(tr.get_ports_list(), prefix="substratetap_") + + base.info["route_genid"] = "n_transistor_clustered" + base.info["netlist"] = n_tran_clustered_netlist( + pdk=pdk, + width=kwargs.get("width", 3), + length=kwargs.get("length", 0.15), + fingers=kwargs.get("fingers", 1), + numcols=numcols, + with_dummy=bool(dummy) if isinstance(dummy, bool) else any(dummy), + n_or_p_fet="pfet", + n_devices=n_devices, + ) + return base + + +def n_transistor_clustered( + pdk: MappedPDK, + device: Literal["nfet", "pfet"], + numcols: int, + n_devices: int = 2, + dummy: Union[bool, Tuple[bool, bool]] = True, + with_substrate_tap: bool = True, + with_tie: bool = True, + tie_layers: tuple[str, str] = ("met2", "met1"), + **kwargs, +) -> Component: + """Wrapper for clustered placement (non-interdigitized).""" + if n_devices < 1: + raise ValueError("n_devices must be >= 1") + if device == "nfet": + return n_nfet_clustered(pdk, numcols, n_devices, dummy, with_substrate_tap, with_tie, tie_layers, **kwargs) + else: + return n_pfet_clustered(pdk, numcols, n_devices, dummy, with_substrate_tap, with_tie, tie_layers, **kwargs) + +def input_stage( + pdk: MappedPDK, + Width: float = 1, + Length: Optional[float] = 1, + num_cols: int = 1, + fingers: int = 1, + multipliers: int = 1, + device: Optional[str] = "pfet", + with_substrate_tap: Optional[bool] = False, + with_tie: Optional[bool] = True, + with_dummy: Optional[bool] = False, + tie_layers: tuple[str, str] = ("met2", "met1"), + show_netlist: Optional[bool] = False, + add_labels = True, + **kwargs, +) -> Component: + """An instantiable self biased casoded current mirror that returns a Component object.""" + + pdk.activate() + maxmet_sep = pdk.util_max_metal_seperation() + n_well_sep = maxmet_sep + psize = (0.35, 0.35) + + # Create the current mirror component + top_level = Component(name="input_stage") + top_level.name = "input_stage" + Length = Length if Length is not None else pdk.get_grule("poly")["min_width"] + top_ref = prec_ref_center(top_level) + + # ------------------------------------------------------------------------------------------------------------------------------------------------------------ + # BOTTOM CURRENT MIRRORS + # ------------------------------------------------------------------------------------------------------------------------------------------------------------ + + currm_bottom = n_transistor_clustered( + pdk, + device=device, + numcols=10, + n_devices=1, + with_substrate_tap=False, + with_tie=with_tie, + width=Width, + length=Length, + ) + + currm_bottom = top_level << currm_bottom + currm_bottom.name = "currm_bottom" + + currm_bottom_ref = prec_ref_center(currm_bottom) + currm_bottom_ref.move(top_ref.center) + top_level.add(currm_bottom_ref) + + top_level.add_ports(currm_bottom_ref.get_ports_list(), prefix="currm_bottom_") + + top_level = component_snap_to_grid(rename_ports_by_orientation(top_level)) + + return top_level + +if __name__ == "__main__": + selected_pdk=gf180 + + comp = input_stage( + selected_pdk, num_cols=1, Width=10, Length=2, with_substrate_tap=False, show_netlist=False, with_tie=True, device="pfet" + ) + # comp = input_stage(selected_pdk, num_cols=1, Width=10, Length=2,with_substrate_tap=True,show_netlist=False) + #comp.pprint_ports() + #comp = add_cm_labels(comp, pdk=selected_pdk) + comp.name = "TEST" + comp.show() + ##Write the current mirror layout to a GDS file + comp.write_gds("GDS/test.gds") + + # # #Generate the netlist for the current mirror + # print("\n...Generating Netlist...") + #print(comp.info["netlist"].generate_netlist()) + # # #DRC Checks + drc_result = selected_pdk.drc_magic(comp, comp.name,output_file=Path("DRC/")) \ No newline at end of file diff --git a/blocks/composite/regulated_cascoded_cmirror/n_fets_interdigitized.py b/blocks/composite/regulated_cascoded_cmirror/n_fets_interdigitized.py new file mode 100644 index 00000000..ce26a5cb --- /dev/null +++ b/blocks/composite/regulated_cascoded_cmirror/n_fets_interdigitized.py @@ -0,0 +1,797 @@ +from pathlib import Path +from glayout.pdk.mappedpdk import MappedPDK +from pydantic import validate_arguments +from gdsfactory.component import Component +from glayout.primitives.fet import nmos, pmos, multiplier +from glayout.util.comp_utils import evaluate_bbox +from typing import Literal, Union, List, Tuple +from glayout.util.port_utils import rename_ports_by_orientation, rename_ports_by_list, create_private_ports +from glayout.util.comp_utils import prec_ref_center,evaluate_bbox, prec_center, align_comp_to_port +from glayout.routing.straight_route import straight_route +from gdsfactory.functions import transformed +from glayout.primitives.guardring import tapring +from glayout.util.port_utils import add_ports_perimeter +from gdsfactory.cell import clear_cache +from typing import Literal, Optional, Union +from glayout.pdk.sky130_mapped import sky130_mapped_pdk +from glayout.pdk.gf180_mapped import gf180_mapped_pdk +from glayout.spice.netlist import Netlist +from gdsfactory.components import text_freetype, rectangle +from glayout.primitives.via_gen import via_stack +import re + +from glayout import MappedPDK, sky130,gf180 + +from glayout.util.snap_to_grid import component_snap_to_grid +from glayout.placement.two_transistor_interdigitized import two_nfet_interdigitized, two_pfet_interdigitized + +###### Only Required for IIC-OSIC Docker +import os +import subprocess + +# Run a shell, source .bashrc, then printenv +cmd = 'bash -c "source ~/.bashrc && printenv"' +result = subprocess.run(cmd, shell=True, text=True, capture_output=True) +env_vars = {} +for line in result.stdout.splitlines(): + if '=' in line: + key, value = line.split('=', 1) + env_vars[key] = value + +# Now, update os.environ with these +os.environ.update(env_vars) + +#from glayout.placement.two_transistor_interdigitized import two_nfet_interdigitized; from glayout.pdk.sky130_mapped import sky130_mapped_pdk as pdk; biasParams=[6,2,4]; rmult=2 +def add_n_int_labels( + device_int_in: Component, + pdk: MappedPDK, + *, + n_or_p_fet: Literal["nfet", "pfet"] = "nfet", + width: Optional[float] = 3.0, + length: Optional[float] = None, + fingers: int = 1, + multipliers: int = 1, + with_dummy: bool = False, +) -> Component: + """ + - Auto-detects device prefixes (A_, B_, C_, ...) from the component's ports. + - Adds labels VSSi / VDDi / VGi next to source / drain / gate ports. + - Creates and attaches a Netlist with Xi VDDi VGi VSSi VB . + """ + + device_int_in.unlock() + + # -------- 1) Discover device prefixes (A_, B_, C_, ...) -------- + # We detect prefixes by looking for ports named "_source_*", "_drain_*", "_gate_*" + prefixes = set() + src_pat = re.compile(r"^([A-Za-z]+)_source_[A-Z]$") + drn_pat = re.compile(r"^([A-Za-z]+)_drain_[A-Z]$") + gate_pat = re.compile(r"^([A-Za-z]+)_gate_[A-Z]$") + + for pname in device_int_in.ports.keys(): + m = src_pat.match(pname) or drn_pat.match(pname) or gate_pat.match(pname) + if m: + prefixes.add(m.group(1)) + + # Sort prefixes alphabetically so numbering is deterministic: A,B,C,... → 1,2,3,... + prefixes = sorted(prefixes) + if not prefixes: + raise ValueError("Could not detect any device prefixes (e.g., A_, B_, ...) from ports.") + + # Helper to resolve a port robustly for a given prefix and role + def _resolve_port(prefix: str, role: str) -> str: + """ + role ∈ {'source','drain','gate'} + Prefer specific orientations if available, otherwise any matching role. + """ + # Try common orientations first + candidates_ordered = { + "source": [f"{prefix}_source_E", f"{prefix}_source_W", f"{prefix}_source_N", f"{prefix}_source_S"], + "drain": [f"{prefix}_drain_E", f"{prefix}_drain_W", f"{prefix}_drain_N", f"{prefix}_drain_S"], + "gate": [f"{prefix}_gate_S", f"{prefix}_gate_N", f"{prefix}_gate_E", f"{prefix}_gate_W"], + }[role] + for c in candidates_ordered: + if c in device_int_in.ports: + return c + # Fallback: first any port matching the role + for pname in device_int_in.ports.keys(): + if pname.startswith(f"{prefix}_{role}_"): + return pname + raise KeyError(f"No port found for {prefix} {role}") + + # -------- 2) Add labels for each device i -------- + move_info = [] + for i, prefix in enumerate(prefixes, start=1): + # VSSi at source + vss = rectangle(layer=pdk.get_glayer("met2_pin"), size=(0.27, 0.27), centered=True).copy() + vss.add_label(text=f"VSS{i}", layer=pdk.get_glayer("met2_label")) + move_info.append((vss, device_int_in.ports[_resolve_port(prefix, "source")], None)) + + # VDDi at drain + vdd = rectangle(layer=pdk.get_glayer("met2_pin"), size=(0.27, 0.27), centered=True).copy() + vdd.add_label(text=f"VDD{i}", layer=pdk.get_glayer("met2_label")) + move_info.append((vdd, device_int_in.ports[_resolve_port(prefix, "drain")], None)) + + # VGi at gate + vg = rectangle(layer=pdk.get_glayer("met2_pin"), size=(0.27, 0.27), centered=True).copy() + vg.add_label(text=f"VG{i}", layer=pdk.get_glayer("met2_label")) + move_info.append((vg, device_int_in.ports[_resolve_port(prefix, "gate")], None)) + + # Bulk (VB) — try a generic well tie port name; if missing, skip label quietly + try: + vb_rect = rectangle(layer=pdk.get_glayer("met2_pin"), size=(0.5, 0.5), centered=True).copy() + vb_rect.add_label(text="VB", layer=pdk.get_glayer("met2_label")) + move_info.append((vb_rect, device_int_in.ports["welltie_S_top_met_S"], None)) + except KeyError: + # If your well-tie port is named differently, add another try here or ignore + pass + + # Place all labels + for comp, prt, alignment in move_info: + alignment = ('c', 'b') if alignment is None else alignment + compref = align_comp_to_port(comp, prt, alignment=alignment) + device_int_in.add(compref) + + # -------- 3) Generate & attach Netlist with N devices -------- + if length is None: + length = pdk.get_grule("poly")["min_width"] + if width is None: + width = 3.0 + + model = pdk.models[n_or_p_fet] + mtop = fingers * multipliers + N = len(prefixes) + + # Build .subckt body + # Nodes order: VDD1..N, VSS1..N, VG1..N, VB (or any ordering you prefer) + nodes = ( + [f"VDD{i}" for i in range(1, N + 1)] + + [f"VSS{i}" for i in range(1, N + 1)] + + [f"VG{i}" for i in range(1, N + 1)] + + ["VB"] + ) + + lines = [f".subckt {{circuit_name}} {' '.join(nodes)} l={length} w={width} m=1"] + # XAi lines + for i in range(1, N + 1): + lines.append(f"X{i} VDD{i} VG{i} VSS{i} VB {model} l={length} w={width} m={mtop}") + if with_dummy: + lines.append(f"XDUMMY VB VB VB VB {model} l={length} w={width} m=2") + lines.append(".ends {circuit_name}") + source_netlist = "\n".join(lines) + + device_int_in.info["netlist"] = Netlist( + circuit_name=f"{N}_trans_interdigitized", + nodes=nodes, + source_netlist=source_netlist, + instance_format="X{name} {nodes} {circuit_name} l={length} w={width} m=1", + parameters={ + "model": model, + "width": width, + "length": length, + "mult": multipliers, + }, + ) + + return device_int_in.flatten() + + +def n_tran_interdigitized_netlist( + pdk: MappedPDK, + width: Optional[float], + length: Optional[float], + fingers: int, + multipliers: int, + with_dummy: bool = True, + n_or_p_fet: Literal['nfet','pfet'] = 'nfet', + subckt_only: Optional[bool] = False, # kept for API compatibility + n_devices: int = 2, # NEW: how many transistors to generate +) -> Netlist: + """ + Build a subcircuit with N interdigitized transistors. + Nodes: VDD1..N, VSS1..N, VG1..N, VB + Instances: X1..XN (each m = fingers * multipliers) + """ + + if length is None: + length = pdk.get_grule('poly')['min_width'] + if width is None: + width = 3.0 + + model = pdk.models[n_or_p_fet] + mtop = fingers * multipliers + N = int(n_devices) + + # Node list (order can be adapted if you prefer a different convention) + nodes = ( + [f"VDD{i}" for i in range(1, N+1)] + + [f"VSS{i}" for i in range(1, N+1)] + + [f"VG{i}" for i in range(1, N+1)] + + ["VB"] + ) + + # Subckt header + lines = [f".subckt {{circuit_name}} {' '.join(nodes)} l={length} w={width} m=1"] + + # Instances X1..XN + for i in range(1, N+1): + lines.append(f"X{i} VDD{i} VG{i} VSS{i} VB {model} l={length} w={width} m={mtop}") + + # Optional dummy + if with_dummy: + lines.append(f"XDUMMY VB VB VB VB {model} l={length} w={width} m=2") + + # End subckt + lines.append(".ends {circuit_name}") + source_netlist = "\n".join(lines) + + return Netlist( + circuit_name=f"{N}_trans_interdigitized", + nodes=nodes, + source_netlist=source_netlist, + instance_format="X{name} {nodes} {circuit_name} l={length} w={width} m=1", + parameters={ + 'model': model, + 'width': width, + 'length': length, + 'mult': multipliers + } + ) + +def _letters(n: int) -> List[str]: + """Return ['A','B','C',...] up to n (supports up to 26 cleanly).""" + if n < 1: + raise ValueError("n_devices must be >= 1") + if n > 26: + # Simple guard; extend to AA/AB... if you need more than 26. + raise ValueError("This helper supports at most 26 devices (A..Z).") + import string + return list(string.ascii_uppercase[:n]) + +def _find_port(cref, patterns: list[str]) -> str | None: + """Return first matching port name on cref given a list of regex patterns.""" + for pat in patterns: + rx = re.compile(pat) + for pname in cref.ports.keys(): + if rx.fullmatch(pname): + return pname + return None + + + +@validate_arguments +def macro_n_transistor_interdigitized( + pdk: MappedPDK, + numcols: int, + devices: Literal["nfet", "pfet"], + n_devices: int, # NEW: how many devices per interdigitized row (e.g., 3 → A,B,C) + dummy: Union[bool, tuple[bool, bool]] = True, # left/right edge dummies + **kwargs, +) -> Component: + """ + Place N identical transistors in a single interdigitized row. + Pattern: A B C ... (N devices) repeated horizontally for `numcols` columns. + + - For matching, per-device metal/poly extents are equalized using PDK spacing. + - Creates 3*N global buses across the full row: _source / _drain / _gate + - Exposes ports for all buses, + private ports for internal use (like original). + """ + + if isinstance(dummy, bool): + dummy = (dummy, dummy) + + # ----- common kwargs for all multipliers ----- + kwargs = dict(kwargs) + kwargs["sd_route_extension"] = 0 + kwargs["gate_route_extension"] = 0 + kwargs["sdlayer"] = "n+s/d" if devices == "nfet" else "p+s/d" + kwargs["pdk"] = pdk + + # Device letters: A, B, C, ... + letters = _letters(n_devices) + + # ---- Create a "center" baseline device for reference (letter A) ---- + # leftmost variant (with left dummy if requested) + kwargs["dummy"] = (True, False) if dummy[0] else False + leftmost_A = multiplier(**kwargs) + + # center variant (no dummies, base extents) + kwargs["dummy"] = False + center_A = multiplier(**kwargs) + + + # Compute extensions so other devices align endpoints (parasitic matching). + # We mimic your original "devB extension" logic, generalized: + dev_sd_extension = pdk.util_max_metal_seperation() + abs( + center_A.ports["drain_N"].center[1] - center_A.ports["diff_N"].center[1] + ) + dev_gate_extension = pdk.util_max_metal_seperation() + abs( + center_A.ports["row0_col0_gate_S"].center[1] - center_A.ports["gate_S"].center[1] + ) + kwargs["sd_route_extension"] = pdk.snap_to_2xgrid(dev_sd_extension) + kwargs["gate_route_extension"] = pdk.snap_to_2xgrid(dev_gate_extension) + + # Build "center" variants for all letters (B..Z), using same matched extensions + center_by_letter = {"A": center_A} + for idx, L in enumerate(letters[1:]): + + kwargs["sd_route_extension"] = pdk.snap_to_2xgrid((idx+1)*dev_sd_extension) + kwargs["gate_route_extension"] = pdk.snap_to_2xgrid((idx+1)*dev_gate_extension) + # no dummies in the middle cells + kwargs["dummy"] = False + center_by_letter[L] = multiplier(**kwargs) + + # Rightmost variant for the last placed device if we put a right dummy: + kwargs["dummy"] = (False, True) if dummy[1] else False + rightmost_last = multiplier(**kwargs) # used at the very end only + + # ----- Placement loop ----- + idplace = Component() + # pitch: device width + min diff separation (like original) + dims = evaluate_bbox(center_A) + xdisp = pdk.snap_to_2xgrid( + dims[0] + pdk.get_grule("active_diff")["min_separation"] + ) + + refs = [] # placed ComponentReferences (in sequence) + total_slots = n_devices * numcols # total instances to place horizontally + + for i in range(total_slots): + # The device index cycles 0..n_devices-1 + idx = i % n_devices + L = letters[idx] + + # Which template to use? + if i == 0: + # very first instance uses leftmost_A (if left dummy requested), else center_A + cref = idplace << (leftmost_A if dummy[0] else center_by_letter["A"]) + elif i == (total_slots - 1): + # very last instance: use rightmost_last (if right dummy requested), else center variant + cref = idplace << (rightmost_last if dummy[1] else center_by_letter[L]) + else: + # middle: center variant for that letter + cref = idplace << center_by_letter[L] + + cref.name = f"{L}_{i // n_devices}" + + # Move to its horizontal slot + cref.movex(i * xdisp) + refs.append(cref) + + # Add the placed instance's ports with a per-instance prefix: + # e.g., A_0_, B_0_, C_0_, A_1_, ... + prefix = f"{L}_{i // n_devices}_" + idplace.add_ports(cref.get_ports_list(), prefix=prefix) + + + + # ----- Equalize extents for each placed device (like original) ----- + # For each placed instance, extend its S/D top metal to the last instance's drain_E, + # and (for A-like positions) extend gate poly to the last instance's gate_E. + last = refs[-1] + for i, r in enumerate(refs): + # get the "end" metal layer from an existing port on r + end_layer = pdk.layer_to_glayer(r.ports["row0_col0_rightsd_top_met_N"].layer) + + idplace << straight_route( + pdk, r.ports["row0_col0_rightsd_top_met_N"], last.ports["drain_E"], glayer2=end_layer + ) + idplace << straight_route( + pdk, r.ports["leftsd_top_met_N"], last.ports["drain_E"], glayer2=end_layer + ) + + + for i, r in enumerate(refs): + + gl = "poly" + up = straight_route(pdk, r.ports["row0_col0_gate_N"], refs[-1].ports["gate_E"], glayer1=gl, glayer2=gl) + idplace << up + + + # ----- Merge doped region across the row (like original) ----- + idplace << straight_route(pdk, refs[0].ports["plusdoped_W"], refs[-1].ports["plusdoped_E"]) + + # ----- Build N×3 global buses across the row ----- + + bus_roles = ["source","drain","gate"] # or ["source","drain","gate"] + bus_layer = "met2" # routing layer for these rails + + N = len(refs) + for i, r in enumerate(refs): + for role in bus_roles: + left_name = f"{role}_W" + right_name = f"{role}_E" + + # (1) from this instance to the LAST instance + if left_name in r.ports and right_name in refs[-1].ports: + gl = pdk.layer_to_glayer(r.ports[left_name].layer) # keep on same layer as start + rr = straight_route(pdk, r.ports[left_name], refs[-1].ports[right_name], glayer2=gl or bus_layer) + rr = rename_ports_by_orientation(rename_ports_by_list(rr, [("route_", "_")])) + idplace << rr + + # (2) from this instance back to the FIRST instance + if right_name in r.ports and left_name in refs[0].ports: + gl = pdk.layer_to_glayer(r.ports[right_name].layer) + rr = straight_route(pdk, r.ports[right_name], refs[0].ports[left_name], glayer2=gl or bus_layer) + rr = rename_ports_by_orientation(rename_ports_by_list(rr, [("route_", "_")])) + idplace << rr + + # Center + finalize + idplace = transformed(prec_ref_center(idplace)) + idplace.unlock() + + return idplace + + +@validate_arguments +def n_nfet_interdigitized( + pdk: MappedPDK, + numcols: int, + n_devices: int, # NEW: number of devices per row (A..) + dummy: Union[bool, tuple[bool, bool]] = True, + with_substrate_tap: bool = True, + with_tie: bool = True, + tie_layers: tuple[str, str] = ("met2", "met1"), + **kwargs, +) -> Component: + """ + N-NFET interdigitized row: places N identical NFETs repeated across `numcols`. + - Preserves dummy-at-edges behavior (bool or (left,right) tuple). + - Adds optional well-tie ring (with_tie) and outer substrate ring (with_substrate_tap). + - Exposes perimeter well ports and attaches an N-device netlist. + """ + + base_multiplier = macro_n_transistor_interdigitized( + pdk=pdk, + numcols=numcols, + devices="nfet", + n_devices=n_devices, + dummy=dummy, + **kwargs, + ) + + # ---- Well tie ring (like your 2T flow) ---- + if with_tie: + tap_separation = max( + pdk.util_max_metal_seperation(), + pdk.get_grule("active_diff", "active_tap")["min_separation"], + ) + tap_separation += pdk.get_grule("p+s/d", "active_tap")["min_enclosure"] # PFET tie uses n+ in nwell + + tap_encloses = ( + 2 * (tap_separation + base_multiplier.xmax), + 2 * (tap_separation + base_multiplier.ymax), + ) + tiering_ref = base_multiplier << tapring( + pdk, + enclosed_rectangle=tap_encloses, + sdlayer="p+s/d", # NFET well tie ring + horizontal_glayer=tie_layers[0], + vertical_glayer=tie_layers[1], + ) + base_multiplier.add_ports(tiering_ref.get_ports_list(), prefix="welltie_") + + # Try to hook up left/right dummy gsd contacts to welltie ring if those ports exist. + # We don’t assume only A/B—scan for any *_dummy_L_gsdcon_top_met_W / *_dummy_R_gsdcon_top_met_E. + try: + wtW = base_multiplier.ports["welltie_W_top_met_W"] + except KeyError: + wtW = None + try: + wtE = base_multiplier.ports["welltie_E_top_met_E"] + except KeyError: + wtE = None + + if wtW: + # Connect any left dummy contact we can find + left_dummy_keys = [k for k in base_multiplier.ports.keys() if k.endswith("dummy_L_gsdcon_top_met_W")] + for k in left_dummy_keys: + try: + base_multiplier << straight_route(pdk, base_multiplier.ports[k], wtW, glayer2="met1") + break + except Exception: + pass + + if wtE: + # Connect any right dummy contact we can find + right_dummy_keys = [k for k in base_multiplier.ports.keys() if k.endswith(f"dummy_R_gsdcon_top_met_E")] + for k in right_dummy_keys: + try: + base_multiplier << straight_route(pdk, base_multiplier.ports[k], wtE, glayer2="met1") + break + except Exception: + pass + + # ---- Add pwell padding + perimeter ports (same as your 2T PFET) ---- + base_multiplier.add_padding( + layers=(pdk.get_glayer("pwell"),), + default=pdk.get_grule("pwell", "active_tap")["min_enclosure"], + ) + base_multiplier = add_ports_perimeter( + base_multiplier, layer=pdk.get_glayer("pwell"), prefix="well_" + ) + + # ---- Optional outer substrate tap ring ---- + if with_substrate_tap: + substrate_tap_separation = pdk.get_grule("dnwell", "active_tap")["min_separation"] + substrate_tap_encloses = ( + 2 * (substrate_tap_separation + base_multiplier.xmax), + 2 * (substrate_tap_separation + base_multiplier.ymax), + ) + ringtoadd = tapring( + pdk, + enclosed_rectangle=substrate_tap_encloses, + sdlayer="p+s/d", # outer ring using p+ taps + horizontal_glayer="met2", + vertical_glayer="met1", + ) + tapring_ref = base_multiplier << ringtoadd + base_multiplier.add_ports(tapring_ref.get_ports_list(), prefix="substratetap_") + + base_multiplier.info["route_genid"] = "n_transistor_interdigitized" + + # ---- Attach N-device netlist ---- + base_multiplier.info["netlist"] = n_tran_interdigitized_netlist( + pdk=pdk, + width=kwargs.get("width", 3), + length=kwargs.get("length", 0.15), + fingers=kwargs.get("fingers", 1), + multipliers=numcols, + with_dummy=bool(dummy) if isinstance(dummy, bool) else any(dummy), + n_or_p_fet="nfet", + subckt_only=True, + n_devices=n_devices, # NEW: pass N + ) + + return base_multiplier + +@validate_arguments +def n_pfet_interdigitized( + pdk: MappedPDK, + numcols: int, + n_devices: int, # NEW: number of devices per row (A..) + dummy: Union[bool, tuple[bool, bool]] = True, + with_substrate_tap: bool = True, + with_tie: bool = True, + tie_layers: tuple[str, str] = ("met2", "met1"), + **kwargs, +) -> Component: + """ + N-PFET interdigitized row: places N identical PFETs repeated across `numcols`. + - Preserves dummy-at-edges behavior (bool or (left,right) tuple). + - Adds optional well-tie ring (with_tie) and outer substrate ring (with_substrate_tap). + - Exposes perimeter well ports and attaches an N-device netlist. + """ + + base_multiplier = macro_n_transistor_interdigitized( + pdk=pdk, + numcols=numcols, + devices="pfet", + n_devices=n_devices, + dummy=dummy, + **kwargs, + ) + + # ---- Well tie ring (like your 2T flow) ---- + if with_tie: + tap_separation = max( + pdk.util_max_metal_seperation(), + pdk.get_grule("active_diff", "active_tap")["min_separation"], + ) + tap_separation += pdk.get_grule("n+s/d", "active_tap")["min_enclosure"] # PFET tie uses n+ in nwell + + tap_encloses = ( + 2 * (tap_separation + base_multiplier.xmax), + 2 * (tap_separation + base_multiplier.ymax), + ) + tiering_ref = base_multiplier << tapring( + pdk, + enclosed_rectangle=tap_encloses, + sdlayer="n+s/d", # PFET well tie ring + horizontal_glayer=tie_layers[0], + vertical_glayer=tie_layers[1], + ) + base_multiplier.add_ports(tiering_ref.get_ports_list(), prefix="welltie_") + + # Try to hook up left/right dummy gsd contacts to welltie ring if those ports exist. + # We don’t assume only A/B—scan for any *_dummy_L_gsdcon_top_met_W / *_dummy_R_gsdcon_top_met_E. + try: + wtW = base_multiplier.ports["welltie_W_top_met_W"] + except KeyError: + wtW = None + try: + wtE = base_multiplier.ports["welltie_E_top_met_E"] + except KeyError: + wtE = None + + if wtW: + # Connect any left dummy contact we can find + left_dummy_keys = [k for k in base_multiplier.ports.keys() if k.endswith("dummy_L_gsdcon_top_met_W")] + for k in left_dummy_keys: + try: + base_multiplier << straight_route(pdk, base_multiplier.ports[k], wtW, glayer2="met1") + break + except Exception: + pass + + if wtE: + # Connect any right dummy contact we can find + right_dummy_keys = [k for k in base_multiplier.ports.keys() if k.endswith(f"dummy_R_gsdcon_top_met_E")] + for k in right_dummy_keys: + try: + base_multiplier << straight_route(pdk, base_multiplier.ports[k], wtE, glayer2="met1") + break + except Exception: + pass + + # ---- Add nwell padding + perimeter ports (same as your 2T PFET) ---- + base_multiplier.add_padding( + layers=(pdk.get_glayer("nwell"),), + default=pdk.get_grule("nwell", "active_tap")["min_enclosure"], + ) + base_multiplier = add_ports_perimeter( + base_multiplier, layer=pdk.get_glayer("nwell"), prefix="well_" + ) + + # ---- Optional outer substrate tap ring ---- + if with_substrate_tap: + substrate_tap_separation = pdk.get_grule("dnwell", "active_tap")["min_separation"] + substrate_tap_encloses = ( + 2 * (substrate_tap_separation + base_multiplier.xmax), + 2 * (substrate_tap_separation + base_multiplier.ymax), + ) + ringtoadd = tapring( + pdk, + enclosed_rectangle=substrate_tap_encloses, + sdlayer="p+s/d", # outer ring using p+ taps + horizontal_glayer="met2", + vertical_glayer="met1", + ) + tapring_ref = base_multiplier << ringtoadd + base_multiplier.add_ports(tapring_ref.get_ports_list(), prefix="substratetap_") + + base_multiplier.info["route_genid"] = "n_transistor_interdigitized" + + # ---- Attach N-device netlist ---- + base_multiplier.info["netlist"] = n_tran_interdigitized_netlist( + pdk=pdk, + width=kwargs.get("width", 3), + length=kwargs.get("length", 0.15), + fingers=kwargs.get("fingers", 1), + multipliers=numcols, + with_dummy=bool(dummy) if isinstance(dummy, bool) else any(dummy), + n_or_p_fet="pfet", + subckt_only=True, + n_devices=n_devices, # NEW: pass N + ) + + return base_multiplier + + + + + +# @validate_arguments +def n_transistor_interdigitized( + pdk: MappedPDK, + device: Literal["nfet", "pfet"], + numcols: int, + n_devices: int = 2, # NEW: how many devices per row + dummy: Union[bool, Tuple[bool, bool]] = True, + with_substrate_tap: bool = True, + with_tie: bool = True, + tie_layers: tuple[str, str] = ("met2", "met1"), + **kwargs, +) -> Component: + """ + Wrapper that builds an interdigitized row of `n_devices` transistors of type `device`. + + - If n_devices == 2 → calls the original two_*_interdigitized for full backward compatibility. + - If n_devices > 2 → calls the generalized n_*_interdigitized(..., n_devices=n_devices). + + Args mirror the 2-device API; extra kwargs are forwarded to the underlying builders. + """ + if n_devices < 1: + raise ValueError("n_devices must be >= 1") + + if device == "nfet": + return n_nfet_interdigitized( + pdk=pdk, + numcols=numcols, + n_devices=n_devices, + dummy=dummy, + with_substrate_tap=with_substrate_tap, + with_tie=with_tie, + tie_layers=tie_layers, + **kwargs, + ) + else: # pfet + # N-device PFET + return n_pfet_interdigitized( + pdk=pdk, + numcols=numcols, + n_devices=n_devices, + dummy=dummy, + with_substrate_tap=with_substrate_tap, + with_tie=with_tie, + tie_layers=tie_layers, + **kwargs, + ) + + +def input_stage( + pdk: MappedPDK, + Width: float = 1, + Length: Optional[float] = 1, + num_cols: int = 1, + fingers: int = 1, + multipliers: int = 1, + type: Optional[str] = "pfet", + with_substrate_tap: Optional[bool] = False, + with_tie: Optional[bool] = True, + with_dummy: Optional[bool] = False, + tie_layers: tuple[str, str] = ("met2", "met1"), + show_netlist: Optional[bool] = False, + add_labels = True, + **kwargs, +) -> Component: + """An instantiable self biased casoded current mirror that returns a Component object.""" + + pdk.activate() + maxmet_sep = pdk.util_max_metal_seperation() + n_well_sep = maxmet_sep + psize = (0.35, 0.35) + + # Create the current mirror component + top_level = Component(name="input_stage") + top_level.name = "input_stage" + Length = Length if Length is not None else pdk.get_grule("poly")["min_width"] + top_ref = prec_ref_center(top_level) + + # ------------------------------------------------------------------------------------------------------------------------------------------------------------ + # BOTTOM CURRENT MIRRORS + # ------------------------------------------------------------------------------------------------------------------------------------------------------------ + + currm_bottom = n_transistor_interdigitized( + pdk, + device="pfet", + numcols=1, + n_devices=4, + with_substrate_tap=False, + with_tie=with_tie, + width=Width, + length=Length, + ) + + currm_bottom = top_level << currm_bottom + currm_bottom.name = "currm_bottom" + + currm_bottom_ref = prec_ref_center(currm_bottom) + currm_bottom_ref.move(top_ref.center) + top_level.add(currm_bottom_ref) + + top_level.add_ports(currm_bottom_ref.get_ports_list(), prefix="currm_bottom_") + + top_level = component_snap_to_grid(rename_ports_by_orientation(top_level)) + + return top_level + + +if __name__ == "__main__": + selected_pdk=gf180 + + comp = input_stage( + selected_pdk, num_cols=1, Width=10, Length=2, with_substrate_tap=False, show_netlist=False, with_tie=True + ) + #comp.pprint_ports() + #comp = add_cm_labels(comp, pdk=selected_pdk) + comp.name = "TEST2" + comp.show() + ##Write the current mirror layout to a GDS file + comp.write_gds("GDS/test2.gds") + + # # #Generate the netlist for the current mirror + # print("\n...Generating Netlist...") + #print(comp.info["netlist"].generate_netlist()) + # # #DRC Checks + drc_result = selected_pdk.drc_magic(comp, comp.name,output_file=Path("DRC/")) \ No newline at end of file diff --git a/blocks/composite/regulated_cascoded_cmirror/plot.py b/blocks/composite/regulated_cascoded_cmirror/plot.py new file mode 100644 index 00000000..d308ad6a --- /dev/null +++ b/blocks/composite/regulated_cascoded_cmirror/plot.py @@ -0,0 +1,21 @@ +import numpy as np +import matplotlib.pyplot as plt + +path = "xschem/simulation/" + +# Load the saved sweeps +v1, i1 = np.loadtxt(path + '/vanilla.txt', unpack=True) +v2, i2 = np.loadtxt(path + '/biased.txt', unpack=True) +v3, i3 = np.loadtxt(path + '/cascode.txt', unpack=True) + +plt.plot(v1, i1, label="Vanilla") +plt.plot(v2, i2, label="Biased") +plt.plot(v3, i3, label="Cascode") + +plt.xlabel("V_out (V)") +plt.ylabel("I_out (A)") +plt.title("I-V Curves of Different Current Mirrors") +plt.legend() +plt.grid(True) +plt.show() + diff --git a/blocks/composite/regulated_cascoded_cmirror/self-biased_cascode_cm.py b/blocks/composite/regulated_cascoded_cmirror/self-biased_cascode_cm.py new file mode 100644 index 00000000..385e5772 --- /dev/null +++ b/blocks/composite/regulated_cascoded_cmirror/self-biased_cascode_cm.py @@ -0,0 +1,335 @@ +from glayout import MappedPDK, sky130,gf180 +from glayout import nmos, pmos, tapring,via_stack + +from glayout.placement.two_transistor_interdigitized import two_nfet_interdigitized, two_pfet_interdigitized +from gdsfactory import cell +from gdsfactory.component import Component +from gdsfactory.components import text_freetype, rectangle + +from glayout.routing import c_route,L_route,straight_route +from glayout.spice.netlist import Netlist + +from glayout.util.port_utils import add_ports_perimeter,rename_ports_by_orientation +from glayout.util.comp_utils import evaluate_bbox, prec_center, prec_ref_center, align_comp_to_port +from glayout.util.snap_to_grid import component_snap_to_grid +from typing import Optional, Union + +###### Only Required for IIC-OSIC Docker +import os +import subprocess + +# Run a shell, source .bashrc, then printenv +cmd = 'bash -c "source ~/.bashrc && printenv"' +result = subprocess.run(cmd, shell=True, text=True, capture_output=True) +env_vars = {} +for line in result.stdout.splitlines(): + if '=' in line: + key, value = line.split('=', 1) + env_vars[key] = value + +# Now, update os.environ with these +os.environ.update(env_vars) + +####################Import the Base structure####################### +from CM_primitive import current_mirror_base, generate_current_mirror_netlist + +def generate_self_biased_current_mirror_netlist( + names: str = "SelfBiasedCurrentMirror", + regulator: Component = None, + base: Component = None, + show_netlist : Optional[bool] = False, + ) -> Netlist: + """Generate a netlist for a current mirror.""" + + topnet = Netlist( + circuit_name=names, + nodes=['IREF', 'ICOPY', 'VSS'], + ) + + base_ref = topnet.connect_netlist( + base.info['netlist'], + [('VSS', 'VSS') ] + ) + + regulator_ref = topnet.connect_netlist( + regulator.info['netlist'], + [('IREF', 'IREF'), ('ICOPY', 'ICOPY'), ('VSS', 'VSS')] + ) + + topnet.connect_subnets( + base_ref, + regulator_ref, + [('IREF', 'INTA'), (('ICOPY', 'INTB')),('VSS', 'VSS')] + ) + + if show_netlist: + generated_netlist_for_lvs = topnet.generate_netlist() + print(f"Generated netlist :\n", generated_netlist_for_lvs) + + file_path_local_storage = "./gen_netlist.txt" + try: + with open(file_path_local_storage, 'w') as file: + file.write(generated_netlist_for_lvs) + except: + print(f"Verify the file availability and type: ", generated_netlist_for_lvs, type(generated_netlist_for_lvs)) + return topnet + +# @validate_arguments +def self_biased_cascode_current_mirror( + pdk: MappedPDK, + Width: float = 1, + Length: Optional[float] = None, + num_cols: int = 2, + fingers: int = 1, + type: Optional[str] = 'nfet', + with_substrate_tap: Optional[bool] = False, + with_tie: Optional[bool] = True, + with_dummy: Optional[bool] = True, + tie_layers: tuple[str,str]=("met2","met1"), + show_netlist: Optional[bool] = False, + **kwargs + ) -> Component: + """An instantiable self biased casoded current mirror that returns a Component object.""" + + pdk.activate() + maxmet_sep = pdk.util_max_metal_seperation() + psize=(0.35,0.35) + + # Create the current mirror component + SBCurrentMirror = Component(name="SBCurrentMirror") + Length = Length if Length is not None else pdk.get_grule('poly')['min_width'] + + # Create the interdigitized fets + if type.lower() =="pfet" or type.lower() =="pmos": + top_currm=two_pfet_interdigitized(pdk,numcols=num_cols,width=Width,length=Length,fingers=fingers,dummy=with_dummy,with_substrate_tap=False,with_tie=False) + well, sdglayer = "nwell", "p+s/d" + elif type.lower() =="nfet" or type.lower() =="nmos": + top_currm= two_nfet_interdigitized(pdk,numcols=num_cols,width=Width,length=Length,fingers=fingers,dummy=with_dummy,with_substrate_tap=False,with_tie=False) + well, sdglayer = "pwell", "n+s/d" + else: + raise ValueError("type must be either nfet or pfet") + + # Add the interdigitized fets to the current mirror top component + top_currm_ref = prec_ref_center(top_currm) + SBCurrentMirror.add(top_currm_ref) + SBCurrentMirror.add_ports(top_currm_ref.get_ports_list(),prefix="top_currm_") + + #Routing + viam2m3 = via_stack(pdk, "met2", "met3", centered=True) + topA_drain_via = SBCurrentMirror << viam2m3 + topA_drain_via.move(SBCurrentMirror.ports[f"top_currm_A_{num_cols-1:d}_drain_E"].center).movex(0.5*(num_cols)) + topA_source_via = SBCurrentMirror << viam2m3 + topA_source_via.move(SBCurrentMirror.ports[f"top_currm_A_0_source_W"].center).movex(-1) + topA_gate_via = SBCurrentMirror << viam2m3 + topA_gate_via.move(SBCurrentMirror.ports[f"top_currm_A_{num_cols-1:d}_gate_E"].center).movex(-0.5*Length+maxmet_sep+0.5*(num_cols)) + + topB_drain_via = SBCurrentMirror << viam2m3 + topB_drain_via.move(topA_drain_via.center).movex(+0.5*num_cols).movey(+1+maxmet_sep-Length) + topB_source_via = SBCurrentMirror << viam2m3 + topB_source_via.move(topA_source_via.center).movex(-1+Length).movey(+1+maxmet_sep-Length) + topB_gate_via = SBCurrentMirror << viam2m3 + topB_gate_via.move(topA_gate_via.center).movey(-1.0-0.4*maxmet_sep) + ##################### + SBCurrentMirror << straight_route(pdk,top_currm_ref.ports["A_0_drain_E"], topA_drain_via.ports["bottom_met_W"]) + SBCurrentMirror << straight_route(pdk,top_currm_ref.ports["B_0_drain_E"], topB_drain_via.ports["bottom_met_W"]) + ##################### + SBCurrentMirror << straight_route(pdk,top_currm_ref.ports["A_0_source_E"], topA_source_via.ports["bottom_met_W"]) + SBCurrentMirror << straight_route(pdk,top_currm_ref.ports["B_0_source_E"], topB_source_via.ports["bottom_met_W"]) + + #source_short = SBCurrentMirror << straight_route(pdk, topA_source_via.ports["top_met_N"], topB_source_via.ports["top_met_S"]) + #,extension=1.2*max(Width,Width), width1=psize[0], width2=ps, cwidth=0.32, e1glayer="met3", e2glayer="met3", cglayer="met2") + ##################### + SBCurrentMirror << straight_route(pdk,top_currm_ref.ports["A_0_gate_W"], topA_gate_via.ports["bottom_met_W"]) + SBCurrentMirror << straight_route(pdk,top_currm_ref.ports["B_0_gate_W"], topB_gate_via.ports["bottom_met_W"]) + ##################### + gate_short = SBCurrentMirror << straight_route(pdk, topA_gate_via.ports["top_met_S"], topB_gate_via.ports["top_met_N"]) + + # #connecting the Drian of A to gate short + SBCurrentMirror << straight_route(pdk,topA_drain_via.ports["top_met_S"],gate_short.ports["route_N"]) + + # # Connecting dummies to the welltie + # if with_dummy: + # try: + # CurrentMirror << straight_route(pdk, CurrentMirror.ports["A_0_dummy_L_gsdcon_top_met_W"],CurrentMirror.ports["welltie_W_top_met_W"],glayer2="met1") + # except KeyError: + # pass + # try: + # end_col = num_cols - 1 + # port1 = f'B_{end_col}_dummy_R_gdscon_top_met_E' + # CurrentMirror << straight_route(pdk, CurrentMirror.ports[port1], CurrentMirror.ports["welltie_E_top_met_E"], glayer2="met1") + # except KeyError: + # pass + + # # add well + # CurrentMirror.add_padding(default=pdk.get_grule(well, "active_tap")["min_enclosure"],layers=[pdk.get_glayer(well)]) + # CurrentMirror = add_ports_perimeter(CurrentMirror, layer = pdk.get_glayer(well), prefix="well_") + #if well == "nwell": + # CurrentMirror.add_padding(layers=(pdk.get_glayer("nwell"),),default= 1 ) + + + ## Adding the Bottom Current Mirror + BCM=SBCurrentMirror << current_mirror_base(pdk=pdk, Width=Width, Length=Length, num_cols=num_cols, fingers=fingers, type=type, **kwargs) + bottom_cm_ref= prec_ref_center(BCM) + bottom_cm_ref.move(top_currm_ref.center).movey(-evaluate_bbox(top_currm_ref)[1]) + + #bottom_cm_ref.pprint_ports() + + SBCurrentMirror.add(bottom_cm_ref) + SBCurrentMirror.add_ports(bottom_cm_ref.get_ports_list(), prefix="bottom_cm_") + + ############################## + + SBCurrentMirror << straight_route(pdk,topA_source_via.ports["top_met_S"], bottom_cm_ref.ports["refport_N"]) + SBCurrentMirror << straight_route(pdk,topB_source_via.ports["top_met_S"], bottom_cm_ref.ports["copyport_N"]) + src2bulk=SBCurrentMirror << straight_route(pdk, bottom_cm_ref.ports["bulkport_N"],SBCurrentMirror.ports["top_currm_welltie_S_top_met_S"], glayer2="met2") + + ############################## + ########################################################### + Irefpin = SBCurrentMirror << rectangle(size=psize,layer=pdk.get_glayer("met3"),centered=True) + Irefpin.move(topA_drain_via.center).movey(0.2*evaluate_bbox(top_currm_ref)[0]) + SBCurrentMirror << straight_route(pdk, topA_drain_via.ports["top_met_N"],Irefpin.ports["e4"], glayer2="met3") + + Icopypin = SBCurrentMirror << rectangle(size=psize,layer=pdk.get_glayer("met3"),centered=True) + Icopypin.move(topA_drain_via.center).movex(+0.5*num_cols).movey(0.2*evaluate_bbox(top_currm_ref)[0]) + SBCurrentMirror << straight_route(pdk, topB_drain_via.ports["top_met_N"],Icopypin.ports["e4"], glayer2="met3") + + #bulkpin = SBCurrentMirror << rectangle(size=psize,layer=pdk.get_glayer("met3"),centered=True) + #bulkpin.move(src2bulk.center).movey(0.2*evaluate_bbox(top_currm_ref)[0]) + #CurrentMirror << straight_route(pdk, src2bulk["route_N"],bulkpin.ports["e4"], glayer2="met3") + ########################################################### + + + ############################## + # # Adding the Top Current Mirror Netlist + # topcurrm.info["netlist"] = generate_current_mirror_netlist( + # pdk=pdk, + # instance_name="TopCurrentMirror", + # CM_size= (Width, Length, num_cols,fingers), # (width, length, multipliers, fingers) + # transistor_type=type, + # drain_net_ref="IREF", # Input drain connected to VREF + # drain_net_copy="ICOPY", # Output drain connected to VCOPY + # gate_net="IREF", # Gate connected to VREF + # source_net_ref="INTA" , + # source_net_copy="INTB" , + # proposed_ground= "VSS" if type=="nfet" else "VDD", #Proposed ground should also change + # subckt_only=True, + # show_netlist=False, + # ) + + # SBCurrentMirror.info["netlist"] = generate_self_biased_current_mirror_netlist( + # names=SBCurrentMirror.name, + # regulator=topcurrm, + # base=BCM, + # show_netlist=False, + # ) + + return rename_ports_by_orientation(component_snap_to_grid(SBCurrentMirror)) + +def add_self_biased_cascode_cm_labels( + CMS: Component, + transistor_type: str = "nfet", + pdk: MappedPDK =sky130 + ) -> Component: + """Add labels to the current mirror layout for LVS, handling both nfet and pfet.""" + + #Would be adjusted for pdk agonastic later + met2_pin = (69, 16) + met2_label = (69, 5) + met3_pin = (70, 16) + met3_label = (70, 5) + + CMS.unlock() + move_info = [] + psize=(0.35,0.35) + + + # VREF label (for both gate and drain of transistor A, and dummy drains) + Iref_label = rectangle(layer=met2_pin, size=psize, centered=True).copy() + Iref_label.add_label(text="IREF", layer=met2_label) + move_info.append((Iref_label, CMS.ports["refport_N"], None)) # Drain of A + #move_info.append((Iref_label, CMS.ports["gateshortports_con_N"], None)) # Gate of A & B + + # VCOPY label (for drain of transistor B) + Icopy_label = rectangle(layer=met2_pin, size=psize, centered=True).copy() + Icopy_label.add_label(text="ICOPY", layer=met2_label) + move_info.append((Icopy_label, CMS.ports["copyport_N"], None)) # Drain of B + + ################################################################################################################### + # INTA label (for source/drain connection of transistor top/bottom) + INTA_label = rectangle(layer=met2_pin, size=psize, centered=True).copy() + INTA_label.add_label(text="INTA", layer=met2_label) + move_info.append((INTA_label, CMS.ports["INTAport_N"], None)) # Drain of A + + # INTB label (for source/drain connection of transistor top/bottom) + INTB_label = rectangle(layer=met2_pin, size=psize, centered=True).copy() + INTB_label.add_label(text="INTB", layer=met2_label) + move_info.append((INTB_label, CMS.ports["INTBport_N"], None)) # Drain of B + ################################################################################################################### + + + # VSS/VDD label (for sources/bulk connection) + if transistor_type.lower() == "nfet": + bulk_net_name = "VSS" + bulk_pin_layer = met2_pin + bulk_label_layer = met2_label + else: # pfet + bulk_net_name = "VDD" + bulk_pin_layer = met2_pin + bulk_label_layer = met2_label + + ##Need to clarify the bulk and source connection?? + # VB label + vb_label = rectangle(layer=bulk_pin_layer, size=psize, centered=True).copy() + vb_label.add_label(text=bulk_net_name , layer=bulk_label_layer) + move_info.append((vb_label, CMS.ports["purposegndport_S"], None)) + + # Add labels to the component + for label, port, alignment in move_info: + if port: + alignment = ('c', 'b') if alignment is None else alignment + aligned_label = align_comp_to_port(label, port, alignment=alignment) + CMS.add(aligned_label) + + return CMS.flatten() + + + + +## To Test their primitives +# from current_mirror import current_mirror, current_mirror_netlist + +if __name__ == "__main__": + # Main function to generate the current mirror layout + # mappedpdk, Width, Length, num_cols, fingers, transistor type + comp = self_biased_cascode_current_mirror(sky130, num_cols=4, Width=3, device='nfet',show_netlist=False) + #comp.pprint_ports() + #comp = add_self_biased_cascode_cm_labels(comp, transistor_type='nfet', pdk=sky130) + + + + + # # # Write the current mirror layout to a GDS file + #comp.name = "CM" + # # delete_files_in_directory("GDS/") + # # tmpdirname = Path("GDS/").resolve() + # # delete_files_in_directory("GDS/") + # # tmp_gds_path = Path(comp.write_gds(gdsdir=tmpdirname)).resolve() + #comp.write_gds("./CM.gds") + comp.show() + # # # Generate the netlist for the current mirror + # # print("\n...Generating Netlist...") + #print(comp.info["netlist"].generate_netlist()) + # # # DRC Checks + # # #delete_files_in_directory("DRC/") + # print("\n...Running DRC...") + # drc_result = sky130.drc_magic(comp, "CM") + # # #drc_result = sky130.drc_magic(comp, "CM",output_file="DRC/") + # print(drc_result['result_str']) + # # LVS Checks + # #delete_files_in_directory("LVS/") + #print("\n...Running LVS...") + #netgen_lvs_result = sky130.lvs_netgen(comp, "CM") + #netgen_lvs_result = sky130.lvs_netgen(comp, "CM",output_file_path="LVS/") + #print(netgen_lvs_result['result_str']) + + \ No newline at end of file diff --git a/blocks/composite/regulated_cascoded_cmirror/tb/README.md b/blocks/composite/regulated_cascoded_cmirror/tb/README.md new file mode 100644 index 00000000..18485e0a --- /dev/null +++ b/blocks/composite/regulated_cascoded_cmirror/tb/README.md @@ -0,0 +1,4 @@ +## gLayout-mahowalders + +> 🚧 **Under Construction** + diff --git a/blocks/composite/regulated_cascoded_cmirror/top.py b/blocks/composite/regulated_cascoded_cmirror/top.py new file mode 100644 index 00000000..a6329ff3 --- /dev/null +++ b/blocks/composite/regulated_cascoded_cmirror/top.py @@ -0,0 +1,858 @@ +from pathlib import Path +from typing import Optional, Union +import os +import re +import subprocess + +from gdsfactory import cell +from gdsfactory.component import Component +from gdsfactory.components import rectangle, text_freetype + +from glayout import MappedPDK, sky130, gf180, nmos, pmos, tapring, via_stack +from glayout.placement.two_transistor_interdigitized import ( + two_nfet_interdigitized, + two_pfet_interdigitized, +) +from glayout.routing import L_route, c_route, straight_route +from glayout.spice.netlist import Netlist +from glayout.util.comp_utils import ( + align_comp_to_port, + evaluate_bbox, + prec_center, + prec_ref_center, +) +from glayout.util.port_utils import add_ports_perimeter, rename_ports_by_orientation +from glayout.util.snap_to_grid import component_snap_to_grid + +from cm_v import current_mirror_base +from cm_sb import self_biased_cascode_current_mirror +from cm_rc import regulated_cascode_current_mirror +from input import input_stage +from bias import bias_stage + +###### Only Required for IIC-OSIC Docker +# Run a shell, source .bashrc, then printenv +cmd = 'bash -c "source ~/.bashrc && printenv"' +result = subprocess.run(cmd, shell=True, text=True, capture_output=True) +env_vars = {} +for line in result.stdout.splitlines(): + if "=" in line: + key, value = line.split("=", 1) + env_vars[key] = value +os.environ.update(env_vars) + +# ---- helpers ---- +_HEADER_RE = re.compile( + r"^\s*\.subckt\s+(\S+)\s+(.*)\s*$", re.IGNORECASE | re.MULTILINE +) + + +def _parse_subckt_header(source: str): + m = _HEADER_RE.search(source) + if not m: + raise ValueError("Could not find .subckt header in child netlist") + name = m.group(1) + pins = [t for t in m.group(2).split() if t.strip()] + return name, pins + + +def _instance_line( + inst_name: str, + subckt_name: str, + ordered_child_pins: list[str], + pinmap: dict[str, str], +): + try: + nodes_in_order = [pinmap[p] for p in ordered_child_pins] + except KeyError as e: + missing = str(e).strip("'") + raise ValueError( + f"Missing mapping for child pin '{missing}' when instantiating {subckt_name}" + ) + return f"X{inst_name} " + " ".join(nodes_in_order) + f" {subckt_name}\n" + + +def generate_top_netlist( + prefix: str, + in_net: str, + aux_net: str, + en_net: str, + out_vcm_net: str, + out_sbcm_net: str, + out_rccm_net: str, + out_vin_net: str, + nl_input: Netlist, + nl_bias: Netlist, + nl_vcm: Netlist, + nl_sbcm: Netlist, + nl_rccm: Netlist, + show_netlist: bool = False, +) -> Netlist: + """ + Build top-level .subckt that instantiates child subckts and wires them to top nets. + TOP pin order must match layout header: + .subckt TOP VIN VSS VDD VOUT_RCCM VOUT_SBCM VOUT_VCM VAUX EN + """ + top_pins = [ + in_net, + "VSS", + "VDD", + out_vin_net, + out_rccm_net, + out_sbcm_net, + out_vcm_net, + aux_net, + en_net, + ] + + # Render children and parse headers + child_texts = { + "INPUT": nl_input.generate_netlist(), + "BIAS": nl_bias.generate_netlist(), + "VCM": nl_vcm.generate_netlist(), + "SBCM": nl_sbcm.generate_netlist(), + "RCCM": nl_rccm.generate_netlist(), + } + parsed = {} + for key, text in child_texts.items(): + subckt_name, pins = _parse_subckt_header(text) + parsed[key] = {"name": subckt_name, "pins": pins, "text": text} + + # Internal nets + in_vcm_int = "IN_VCM" + in_sbcm_int = "IN_SBCM" + in_rccm_int = "IN_RCCM" + + bias_rccm_int = "BIAS_RCCM" + + # Pin maps matching the child headers + # INPUT: .subckt INPUT VIN EN VOUT_VCM VOUT_BCM VOUT_CCM VDD + pinmap_input = { + "VIN": in_net, + "EN": en_net, + "VOUT_VCM": in_vcm_int, + "VOUT_BCM": in_sbcm_int, + "VOUT_CCM": in_rccm_int, + "VOUT_VIN": out_vin_net, + "VDD": "VDD", + } + # BIAS: .subckt BIAS IN_RCCM VAUX EN VDD + pinmap_bias = { + "VOUT": bias_rccm_int, + "VIN": aux_net, + "EN": en_net, + "VDD": "VDD", + "VSS": "VSS", + } + # VCM: .subckt VCM VIN VOUT VSS + pinmap_vcm = {"VIN": in_vcm_int, "VOUT": out_vcm_net, "VSS": "VSS"} + # SBCM: .subckt SBCM VIN VOUT VSS + pinmap_sbcm = {"VIN": in_sbcm_int, "VOUT": out_sbcm_net, "VSS": "VSS"} + # RCCM: .subckt RCCM VIN VAUX VOUT VSS + pinmap_rccm = { + "VIN": in_rccm_int, + "VAUX": bias_rccm_int, + "VOUT": out_rccm_net, + "VSS": "VSS", + } + + # Build instance lines using parsed child pin order + x_lines = [ + _instance_line( + f"{prefix}IN", + parsed["INPUT"]["name"], + parsed["INPUT"]["pins"], + pinmap_input, + ), + _instance_line( + f"{prefix}BIAS", + parsed["BIAS"]["name"], + parsed["BIAS"]["pins"], + pinmap_bias, + ), + _instance_line( + f"{prefix}VCM", + parsed["VCM"]["name"], + parsed["VCM"]["pins"], + pinmap_vcm, + ), + _instance_line( + f"{prefix}SBCM", + parsed["SBCM"]["name"], + parsed["SBCM"]["pins"], + pinmap_sbcm, + ), + _instance_line( + f"{prefix}RCCM", + parsed["RCCM"]["name"], + parsed["RCCM"]["pins"], + pinmap_rccm, + ), + ] + + # Write children FIRST, then TOP + src = [] + for key in ("INPUT", "BIAS", "VCM", "SBCM", "RCCM"): + src.append(parsed[key]["text"].rstrip()) + src.append("") + + src.append(f".subckt {prefix} " + " ".join(top_pins)) + src.extend(x_lines) + src.append(".ends " + prefix) + src.append("") + + source_netlist = "\n".join(src) + + topnet = Netlist( + circuit_name=prefix, + nodes=top_pins, + source_netlist=source_netlist, + instance_format="X{name} {nodes} {circuit_name}", + parameters={}, + ) + + if show_netlist: + print("Generated top-level netlist:\n") + print(topnet.generate_netlist()) + + return topnet + +# def generate_top_netlist( +# prefix: str, +# in_net: str, +# aux_net: str, +# en_net: str, +# out_vcm_net: str, +# out_sbcm_net: str, +# out_rccm_net: str, +# nl_input: Netlist, +# nl_vcm: Netlist, +# nl_sbcm: Netlist, +# nl_rccm: Netlist, +# show_netlist: bool = False, +# ) -> Netlist: +# """ +# Build top-level .subckt that instantiates child subckts and wires them to top nets. +# TOP pin order must match layout header: +# .subckt TOP VIN VSS VDD VOUT_RCCM VOUT_SBCM VOUT_VCM VAUX EN +# """ +# top_pins = [ +# in_net, +# "VSS", +# "VDD", +# out_rccm_net, +# out_sbcm_net, +# out_vcm_net, +# aux_net, +# en_net, +# ] + +# netlist = Netlist( +# circuit_name=prefix, +# nodes=top_pins, +# ) + + +# in_comp = netlist.connect_netlist(nl_input, [('VIN',in_net),('EN',en_net), ('VDD','VDD')]) +# vcm_comp = netlist.connect_netlist(nl_vcm, [('VOUT',out_vcm_net),('VSS','VSS')]) +# sbcm_comp = netlist.connect_netlist(nl_sbcm, [('VOUT',out_sbcm_net),('VSS','VSS')]) +# rccm_comp = netlist.connect_netlist(nl_rccm, [('VAUX',aux_net),('VOUT',out_rccm_net),('VSS','VSS')]) + +# netlist.connect_subnets(in_comp, vcm_comp, [('VOUT_VCM','VIN')]) +# netlist.connect_subnets(in_comp, sbcm_comp, [('VOUT_BCM','VIN')]) +# netlist.connect_subnets(in_comp, rccm_comp, [('VOUT_CCM','VIN')]) + +# if show_netlist: +# print("Generated top-level netlist:\n") +# print(netlist.generate_netlist()) + +# return netlist + + +# @validate_arguments +def top( + pdk: MappedPDK, + with_tie: Optional[bool] = True, + with_dummy: Optional[bool] = True, + tie_layers: tuple[str, str] = ("met2", "met1"), + show_netlist: Optional[bool] = False, + add_labels: bool = True, + **kwargs, +) -> Component: + """An instantiable self biased cascoded current mirror that returns a Component.""" + pdk.activate() + + # Create the current mirror component + top_level = Component(name="top_design") + top_ref = prec_ref_center(top_level) + + viam1m2 = via_stack(pdk, "met1", "met2", centered=True) + viam2m3 = via_stack(pdk, "met2", "met3", centered=True) + viam1m3 = via_stack(pdk, "met1", "met3", centered=True) + + # ------------------------------------------------------------------------- + # CREATING THE INPUT STAGE + # ------------------------------------------------------------------------- + print("Creating Input Stage ...") + + input_stage_comp = input_stage( + pdk, + num_cols=1, + Length=2, + Width=10, + device="pfet", + with_substrate_tap=False, + with_tie=with_tie, + with_dummy=with_dummy, + tie_layers=tie_layers, + add_labels=False, + ) + input_stage_ref = prec_ref_center(input_stage_comp) + input_stage_ref.move(top_ref.center) + top_level.add(input_stage_ref) + top_level.add_ports(input_stage_ref.get_ports_list(), prefix="input_") + + center = top_level.center + + # ------------------------------------------------------------------------- + # CREATING THE VANILLA CURRENT MIRROR STAGE + # ------------------------------------------------------------------------- + print("Creating Vanilla Current Mirror ...") + + VCM = current_mirror_base( + pdk, + num_cols=1, + Length=1, + Width=4, + device="nfet", + with_substrate_tap=False, + add_labels=False, + ) + vcm_ref = prec_ref_center(VCM) + vcm_ref.move(center).movex( + evaluate_bbox(input_stage_ref)[0] + 4 * pdk.util_max_metal_seperation() + ).movey(-evaluate_bbox(input_stage_ref)[1] / 2) + + top_level.add(vcm_ref) + top_level.add_ports(vcm_ref.get_ports_list(), prefix="vcm_") + + top_level << L_route( + pdk, vcm_ref.ports["IN_top_met_N"], input_stage_ref.ports["OUT_B_top_met_E"] + ) + + # ------------------------------------------------------------------------- + # CREATING THE SELF-BIASED CURRENT MIRROR STAGE + # ------------------------------------------------------------------------- + print("Creating Self-Biased Current Mirror ...") + + SBCM = self_biased_cascode_current_mirror( + pdk, num_cols=1, Length=1, Width=4, device="nfet", add_labels=False + ) + sbcm_ref = prec_ref_center(SBCM) + sbcm_ref.move(center).movex( + evaluate_bbox(input_stage_ref)[0] + 4 * pdk.util_max_metal_seperation() + ) + + top_level.add(sbcm_ref) + top_level.add_ports(sbcm_ref.get_ports_list(), prefix="sbcm_") + + top_level << L_route( + pdk, sbcm_ref.ports["IN_top_met_N"], input_stage_ref.ports["OUT_C_top_met_E"] + ) + + # ------------------------------------------------------------------------- + # CREATING THE REGULATED CASCODE CURRENT MIRROR STAGE + # ------------------------------------------------------------------------- + print("Creating Regulated Cascoded Current Mirror ...") + + RCCM = regulated_cascode_current_mirror( + pdk, num_cols=2, Length=1, Width=4, device="nfet", show_netlist=False, add_labels=False + ) + rccm_ref = prec_ref_center(RCCM) + rccm_ref.move(center).movex( + evaluate_bbox(input_stage_ref)[0] + 4 * pdk.util_max_metal_seperation() + ).movey(+evaluate_bbox(input_stage_ref)[1] / 2) + + top_level.add(rccm_ref) + top_level.add_ports(rccm_ref.get_ports_list(), prefix="rccm_") + + dist_via = abs( + rccm_ref.ports["IN_top_met_W"].center[0] + - rccm_ref.ports["IN_top_met_E"].center[0] + ) / 2 + + in_rccm_via = top_level << viam2m3 + in_rccm_via.move((input_stage_ref.ports["OUT_D_top_met_W"].center)).movex(dist_via) + + rccm_in_via = top_level << viam2m3 + rccm_in_via.move((rccm_ref.ports["IN_top_met_W"].center)).movex(dist_via) + + + top_level << L_route( + pdk, in_rccm_via.ports["top_met_N"], rccm_in_via.ports["top_met_W"], hglayer="met3", vglayer="met3", + ) + + # ------------------------------------------------------------------------- + # CREATING THE BIAS STAGE + # ------------------------------------------------------------------------- + print("Creating Bias Stage ...") + + bias_stage_comp = bias_stage( + pdk, + add_labels=False, + ) + bias_stage_ref = prec_ref_center(bias_stage_comp) + + bias_stage_ref.move(center).movex( + -3 * evaluate_bbox(input_stage_ref)[0] - 6 * pdk.util_max_metal_seperation() + ).movey(+evaluate_bbox(input_stage_ref)[1] / 2 + evaluate_bbox(sbcm_ref)[1] / 2 + 6 * pdk.util_max_metal_seperation()) + bias_stage_ref.move(center) + top_level.add(bias_stage_ref) + top_level.add_ports(bias_stage_ref.get_ports_list(), prefix="bias_") + + + # ------------------------------------------------------------------------- + # CONNECTING AUX + # ------------------------------------------------------------------------- + + + top_level << L_route( + pdk, bias_stage_ref.ports["base_right_OUT_top_met_N"], rccm_ref.ports["AUX_A_top_met_W"], hglayer="met1", vglayer="met1", + ) + + en_via = top_level << viam1m2 + en_via.move(bias_stage_ref.ports["fet_right_multiplier_0_gate_E"].center).movex(evaluate_bbox(bias_stage_ref)[0]) + top_level.add_ports(en_via.get_ports_list(), prefix=f"EN_") + + top_level << straight_route( + pdk, + bias_stage_ref.ports["fet_right_multiplier_0_gate_E"], + en_via.ports["top_met_W"], + glayer1="met2", + glayer2="met2", + ) + + en_input_via = top_level << viam2m3 + en_input_via.move((input_stage_ref.ports["EN_A_top_met_N"].center[0], en_via.center[1])) + + en_input_conn_via = top_level << viam2m3 + en_input_conn_via.move(input_stage_ref.ports["EN_A_top_met_N"].center) + + top_level << straight_route( + pdk, + en_input_via.ports["top_met_S"], + en_input_conn_via.ports["top_met_S"], + glayer1="met3", + glayer2="met3", + ) + + aux_via = top_level << viam2m3 + aux_via.move(en_via.center).movey(evaluate_bbox(rccm_ref)[1]) + top_level.add_ports(aux_via.get_ports_list(), prefix=f"VAUX_") + + ##### This one Met 3 + top_level << L_route( + pdk, + bias_stage_ref.ports["base_left_IN_top_met_N"], + aux_via.ports["top_met_W"], + hglayer="met3", vglayer="met2" + ) + + # Outputs + + vcm_via = top_level << viam1m2 + vcm_via.move((en_via.center[0], vcm_ref.ports["OUT_top_met_W"].center[1])) + top_level.add_ports(vcm_via.get_ports_list(), prefix=f"VOUT_VCM_") + + top_level << straight_route( + pdk, + vcm_via.ports["top_met_W"], + vcm_ref.ports["OUT_top_met_E"], + glayer1="met2", + glayer2="met2", + ) + + sbcm_via = top_level << viam1m2 + sbcm_via.move((en_via.center[0], sbcm_ref.ports["OUT_top_met_W"].center[1])) + top_level.add_ports(sbcm_via.get_ports_list(), prefix=f"VOUT_SBCM_") + + top_level << straight_route( + pdk, + sbcm_via.ports["top_met_W"], + sbcm_ref.ports["OUT_top_met_E"], + glayer1="met2", + glayer2="met2", + ) + + rccm_via = top_level << viam1m2 + rccm_via.move((en_via.center[0], rccm_ref.ports["OUT_top_met_W"].center[1])) + top_level.add_ports(rccm_via.get_ports_list(), prefix=f"VOUT_RCCM_") + + top_level << straight_route( + pdk, + rccm_via.ports["top_met_W"], + rccm_ref.ports["OUT_top_met_E"], + glayer1="met2", + glayer2="met2", + ) + + outvin_via = top_level << viam1m2 + outvin_via.move(en_via.center).movey(-evaluate_bbox(vcm_ref)[1] + 6 * pdk.util_max_metal_seperation()) + top_level.add_ports(outvin_via.get_ports_list(), prefix=f"VOUT_VIN_") + + top_level << L_route( + pdk, input_stage_ref.ports["OUT_E_top_met_N"], outvin_via.ports["top_met_W"], hglayer="met2", vglayer="met2", + ) + + # Input + + vin1_via = top_level << viam1m2 + vin1_via.move(input_stage_ref.ports["IN_A_top_met_N"].center).movey(-evaluate_bbox(sbcm_ref)[1]) + + vin2_via = top_level << viam1m2 + vin2_via.move(vin1_via.center).movex(2*evaluate_bbox(input_stage_ref)[0]) + + vin3_via = top_level << viam1m2 + vin3_via.move(aux_via.center).movey(evaluate_bbox(rccm_ref)[1]) + top_level.add_ports(vin3_via.get_ports_list(), prefix=f"VIN_") + + top_level << straight_route( + pdk, + input_stage_ref.ports["IN_A_top_met_S"], + vin1_via.ports["top_met_N"], + glayer1="met1", + glayer2="met1", + ) + + top_level << straight_route( + pdk, + vin1_via.ports["top_met_E"], + vin2_via.ports["top_met_W"], + glayer1="met1", + glayer2="met1", + ) + + top_level << L_route( + pdk, + vin2_via.ports["top_met_N"], + vin3_via.ports["top_met_W"], + hglayer="met1", vglayer="met1", + ) + + # VSS + + vss_via = top_level << viam1m3 + vss_via.move(vin3_via.center).movey(evaluate_bbox(rccm_ref)[1]) + top_level.add_ports(vss_via.get_ports_list(), prefix=f"VSS_") + + top_level << L_route( + pdk, + vss_via.ports["top_met_W"], + rccm_ref.ports["welltie_N_top_met_N"], + hglayer="met1", vglayer="met1", + vwidth=5, hwidth=5 + ) + + ###### DRC_Error + # handles = place_welltie_via_row( + # top_level, pdk, "bias_base_bottom", + # top_layer="met3", + # use_edges=False, offset=5.0, + # fill_mode="auto", + # ) + + # top_level << L_route( + # pdk, + # bias_stage_ref.ports["base_bottom_welltie_N_top_met_N"], + # vss_via.ports["top_met_W"], + # hglayer="met3", vglayer="met3", + # vwidth=12, hwidth=12, + # ) + ####################################################### + + # VDD + vdd_via = top_level << viam1m2 + vdd_via.move(vss_via.center).movey(evaluate_bbox(rccm_ref)[1]) + top_level.add_ports(vdd_via.get_ports_list(), prefix=f"VDD_") + + top_level << L_route( + pdk, + vdd_via.ports["top_met_W"], + bias_stage_ref.ports["fet_left_tie_N_top_met_N"], + hglayer="met1", vglayer="met1", + vwidth=5, hwidth=5 + ) + + + # ------------------------------------------------------------------------- + # CONNECTING VDD TOGETHER + # ------------------------------------------------------------------------- + + top_level << straight_route( + pdk, + bias_stage_ref.ports["VDD_port"], + top_level.ports["input_welltie_W_top_met_W"], + glayer1="met1", + glayer2="met1", + width=10, + ) + + # ------------------------------------------------------------------------- + # CONNECTING VSS TOGETHER + # ------------------------------------------------------------------------- + top_level << straight_route( + pdk, + top_level.ports["vcm_welltie_N_top_met_N"], + top_level.ports["sbcm_welltie_S_top_met_S"], + glayer1="met1", + glayer2="met1", + width=10, + ) + top_level << straight_route( + pdk, + top_level.ports["sbcm_welltie_N_top_met_N"], + top_level.ports["rccm_welltie_S_top_met_S"], + glayer1="met1", + glayer2="met1", + width=10, + ) + + top_level << L_route( + pdk, + bias_stage_ref.ports["base_bottom_welltie_N_top_met_N"], + vss_via.ports["top_met_W"], + hglayer="met2", vglayer="met2", + vwidth=12, hwidth=12, + ) + + top_level = component_snap_to_grid(rename_ports_by_orientation(top_level)) + + top_level.info["netlist"] = generate_top_netlist( + prefix="TOP", + in_net="VIN", + aux_net="VAUX", + en_net="EN", + out_vcm_net="VOUT_VCM", + out_sbcm_net="VOUT_SBCM", + out_rccm_net="VOUT_RCCM", + out_vin_net="VOUT_VIN", + nl_input=input_stage_comp.info["netlist"], + nl_bias=bias_stage_comp.info["netlist"], + nl_vcm=VCM.info["netlist"], + nl_sbcm=SBCM.info["netlist"], + nl_rccm=RCCM.info["netlist"], + show_netlist=show_netlist, + ) + + if add_labels: + return add_cm_labels(top_level, pdk) + return top_level + +def add_cm_labels(cm_in: Component, pdk: MappedPDK) -> Component: + cm_in.unlock() + + psize = (0.35, 0.35) + move_info = [] + + # VIN + vinlabel = rectangle(layer=pdk.get_glayer("met2_pin"), size=psize, centered=True).copy() + vinlabel.add_label(text="VIN", layer=pdk.get_glayer("met2_label")) + move_info.append((vinlabel, cm_in.ports["VIN_top_met_E"], None)) + + # EN + vEnlabel = rectangle(layer=pdk.get_glayer("met2_pin"), size=psize, centered=True).copy() + vEnlabel.add_label(text="EN", layer=pdk.get_glayer("met2_label")) + move_info.append((vEnlabel, cm_in.ports["EN_top_met_E"], None)) + + # VAUX + vauxlabel = rectangle(layer=pdk.get_glayer("met2_pin"), size=psize, centered=True).copy() + vauxlabel.add_label(text="VAUX", layer=pdk.get_glayer("met2_label")) + move_info.append((vauxlabel, cm_in.ports["VAUX_top_met_E"], None)) + + # VOUT VCM + voutvcmlabel = rectangle(layer=pdk.get_glayer("met2_pin"), size=psize, centered=True).copy() + voutvcmlabel.add_label(text="VOUT_VCM", layer=pdk.get_glayer("met2_label")) + move_info.append((voutvcmlabel, cm_in.ports["VOUT_VCM_top_met_E"], None)) + + # VOUT SBCM + voutsbcmlabel = rectangle(layer=pdk.get_glayer("met2_pin"), size=psize, centered=True).copy() + voutsbcmlabel.add_label(text="VOUT_SBCM", layer=pdk.get_glayer("met2_label")) + move_info.append((voutsbcmlabel, cm_in.ports["VOUT_SBCM_top_met_E"], None)) + + # VOUT RCCM + voutrccmlabel = rectangle(layer=pdk.get_glayer("met2_pin"), size=psize, centered=True).copy() + voutrccmlabel.add_label(text="VOUT_RCCM", layer=pdk.get_glayer("met2_label")) + move_info.append((voutrccmlabel, cm_in.ports["VOUT_RCCM_top_met_E"], None)) + + # VOUT VIN + voutvinlabel = rectangle(layer=pdk.get_glayer("met2_pin"), size=psize, centered=True).copy() + voutvinlabel.add_label(text="VOUT_VIN", layer=pdk.get_glayer("met2_label")) + move_info.append((voutvinlabel, cm_in.ports["VOUT_VIN_top_met_E"], None)) + + # VDD (well tie) + vddlabel = rectangle(layer=pdk.get_glayer("met1_pin"), size=psize, centered=True).copy() + vddlabel.add_label(text="VDD", layer=pdk.get_glayer("met1_label")) + move_info.append((vddlabel, cm_in.ports["VDD_top_met_E"], None)) + + # VSS (well tie) + vsslabel = rectangle(layer=pdk.get_glayer("met1_pin"), size=psize, centered=True).copy() + vsslabel.add_label(text="VSS", layer=pdk.get_glayer("met1_label")) + move_info.append((vsslabel, cm_in.ports["VSS_top_met_E"], None)) + + # + + for comp, prt, alignment in move_info: + alignment = ("c", "b") if alignment is None else alignment + compref = align_comp_to_port(comp, prt, alignment=alignment) + cm_in.add(compref) + + return cm_in.flatten() + + +def place_welltie_via_row( + top_level, + pdk, + block_key: str=None, # expects f"{block_key}_welltie_S_top_met_S" + *, + top_layer: str = "met3", # top layer to reach (string, e.g. "met3") + # Where to put the two edge via stacks: + use_edges: bool = True, # True: at ± welltie.width/2; False: at ±offset + offset: float = 5.0, # used when use_edges=False (distance from center) + jog_dy: float = 0.0, # vertical offset for the whole via row center + + # How to fill middle stacks: mode ∈ {"auto","pitch","count"} + fill_mode: str = "auto", + pitch: float | None = None, # used when fill_mode="pitch" + count: int | None = None, # used when fill_mode="count" + edge_margin: float = 0.0, # keep gap from edges for "pitch" mode +): + """ + Returns dict with keys: + left_ref, right_ref: ComponentReference of edge stacks + left_top, right_top: Port on top_layer for each edge stack + mid_refs: list[ComponentReference] for middle stacks + mid_top_ports: list[Port] top ports for middle stacks + """ + # --- 1) resolve the welltie S-facing top-metal port --- + + wt = top_level.ports[f"{block_key}_welltie_N_top_met_N"] # Port (likely on met1 or met2) + + delta_y = abs(top_level.ports[f"{block_key}_welltie_N_top_met_N"].center[1] - top_level.ports[f"{block_key}_welltie_N_top_met_S"].center[1])/2 + x0, y0 = wt.center + + w_wt = wt.width + + # --- 2) utilities: mapping layer tuple<->name and grid snapping --- + def _name_of(gl_tuple): + for nm in ("met1","met2","met3","met4","met5"): + try: + if pdk.get_glayer(nm) == gl_tuple: + return nm + except Exception: + pass + raise ValueError(f"Unknown layer tuple {gl_tuple}") + + snap = pdk.snap_to_2xgrid + bottom_layer = _name_of(wt.layer) # e.g. "met1" or "met2" + bot_gl = pdk.get_glayer(bottom_layer) + top_gl = pdk.get_glayer(top_layer) + + # --- 3) edge stack X positions --- + if use_edges: + xL = snap(x0 - w_wt/2) + xR = snap(x0 + w_wt/2) + else: + xL = snap(x0 - abs(offset)) + xR = snap(x0 + abs(offset)) + yC = snap(y0 - delta_y+ jog_dy) + + # --- 4) create via stack template and place the two edge stacks (as refs) --- + vs_proto = via_stack(pdk, bottom_layer, top_layer) # Component + left_ref = top_level << vs_proto # ComponentReference + right_ref = top_level << vs_proto + left_ref.move((xL, yC)) + right_ref.move((xR, yC)) + + # helper to pick bottom/top ports of a via ref + def _bottom_port(vref): + return next(p for p in vref.ports.values() if p.layer == bot_gl) + def _top_port(vref): + return next(p for p in vref.ports.values() if p.layer == top_gl) + + left_bot = _bottom_port(left_ref) + right_bot = _bottom_port(right_ref) + left_top = _top_port(left_ref) + right_top = _top_port(right_ref) + + + # --- 6) compute middle positions depending on fill_mode --- + mid_refs = [] + mid_top_ports = [] + + xL_center, _ = left_ref.center + xR_center, _ = right_ref.center + + if fill_mode not in {"auto","pitch","count"}: + raise ValueError("fill_mode must be one of {'auto','pitch','count'}") + + if fill_mode == "count": + n = int(count or 0) + if n > 0: + step = (xR_center - xL_center) / (n + 1) + for k in range(1, n+1): + xk = snap(xL_center + k*step) + r = top_level << vs_proto + r.move((xk, yC)) + mid_refs.append(r) + mid_top_ports.append(_top_port(r)) + + else: + # need a pitch value: either provided, or auto-computed + if fill_mode == "pitch": + if pitch is None or pitch <= 0: + raise ValueError("fill_mode='pitch' requires a positive 'pitch' parameter.") + eff_pitch = float(pitch) + else: + # "auto": via width on top layer + min spacing of that layer + # get via *component* width on x from template bbox + vx, _vy = evaluate_bbox(vs_proto) # (w, h) in layout units + min_sp = pdk.get_grule(top_layer)["min_separation"] + eff_pitch = snap(vx + min_sp) + + x_start = snap(xL_center + edge_margin) + x_stop = snap(xR_center - edge_margin) + + x = x_start + eff_pitch + # leave small epsilon to avoid placing on/over the right ref + while x < x_stop - 1e-6: + r = top_level << vs_proto + r.move((snap(x), yC)) + mid_refs.append(r) + mid_top_ports.append(_top_port(r)) + x += eff_pitch + + return { + "left_ref": left_ref, "right_ref": right_ref, + "left_top": left_top, "right_top": right_top, + "mid_refs": mid_refs, "mid_top_ports": mid_top_ports, + } + + +if __name__ == "__main__": + selected_pdk = gf180 + + comp = top(selected_pdk, show_netlist=False, add_labels=True) + # comp.pprint_ports() + comp.name = "M" + comp.show() + + # Write the layout to GDS + comp.write_gds("GDS/topv6.gds") + + # DRC + drc_result = selected_pdk.drc_magic(comp, comp.name, output_file=Path("DRC/")) + + # LVS + netgen_lvs_result = selected_pdk.lvs_netgen( + comp, comp.name, output_file_path=Path("LVS/"), copy_intermediate_files=True + ) diff --git a/blocks/composite/regulated_cascoded_cmirror/xschem/.gitignore b/blocks/composite/regulated_cascoded_cmirror/xschem/.gitignore new file mode 100644 index 00000000..f807ef9c --- /dev/null +++ b/blocks/composite/regulated_cascoded_cmirror/xschem/.gitignore @@ -0,0 +1,2 @@ +**/*.raw +**/*.txt diff --git a/blocks/composite/regulated_cascoded_cmirror/xschem/Chipathon2025_pads/magic/mag/diode_nd2ps_06v0_MV3SZ3.mag b/blocks/composite/regulated_cascoded_cmirror/xschem/Chipathon2025_pads/magic/mag/diode_nd2ps_06v0_MV3SZ3.mag new file mode 100644 index 00000000..e767866e --- /dev/null +++ b/blocks/composite/regulated_cascoded_cmirror/xschem/Chipathon2025_pads/magic/mag/diode_nd2ps_06v0_MV3SZ3.mag @@ -0,0 +1,113 @@ +magic +tech gf180mcuD +magscale 1 10 +timestamp 1757961865 +<< pwell >> +rect -4524 -1176 4524 1176 +<< mvpsubdiff >> +rect -4500 1139 4500 1152 +rect -4500 1093 -4384 1139 +rect -2312 1093 -2152 1139 +rect -80 1093 80 1139 +rect 2152 1093 2312 1139 +rect 4384 1093 4500 1139 +rect -4500 1080 4500 1093 +rect -4500 1036 -4428 1080 +rect -4500 -1036 -4487 1036 +rect -4441 -1036 -4428 1036 +rect -2268 1036 -2196 1080 +rect -4500 -1080 -4428 -1036 +rect -2268 -1036 -2255 1036 +rect -2209 -1036 -2196 1036 +rect -36 1036 36 1080 +rect -2268 -1080 -2196 -1036 +rect -36 -1036 -23 1036 +rect 23 -1036 36 1036 +rect 2196 1036 2268 1080 +rect -36 -1080 36 -1036 +rect 2196 -1036 2209 1036 +rect 2255 -1036 2268 1036 +rect 4428 1036 4500 1080 +rect 2196 -1080 2268 -1036 +rect 4428 -1036 4441 1036 +rect 4487 -1036 4500 1036 +rect 4428 -1080 4500 -1036 +rect -4500 -1093 4500 -1080 +rect -4500 -1139 -4384 -1093 +rect -2312 -1139 -2152 -1093 +rect -80 -1139 80 -1093 +rect 2152 -1139 2312 -1093 +rect 4384 -1139 4500 -1093 +rect -4500 -1152 4500 -1139 +<< mvpsubdiffcont >> +rect -4384 1093 -2312 1139 +rect -2152 1093 -80 1139 +rect 80 1093 2152 1139 +rect 2312 1093 4384 1139 +rect -4487 -1036 -4441 1036 +rect -2255 -1036 -2209 1036 +rect -23 -1036 23 1036 +rect 2209 -1036 2255 1036 +rect 4441 -1036 4487 1036 +rect -4384 -1139 -2312 -1093 +rect -2152 -1139 -80 -1093 +rect 80 -1139 2152 -1093 +rect 2312 -1139 4384 -1093 +<< mvndiode >> +rect -4348 987 -2348 1000 +rect -4348 -987 -4335 987 +rect -2361 -987 -2348 987 +rect -4348 -1000 -2348 -987 +rect -2116 987 -116 1000 +rect -2116 -987 -2103 987 +rect -129 -987 -116 987 +rect -2116 -1000 -116 -987 +rect 116 987 2116 1000 +rect 116 -987 129 987 +rect 2103 -987 2116 987 +rect 116 -1000 2116 -987 +rect 2348 987 4348 1000 +rect 2348 -987 2361 987 +rect 4335 -987 4348 987 +rect 2348 -1000 4348 -987 +<< mvndiodec >> +rect -4335 -987 -2361 987 +rect -2103 -987 -129 987 +rect 129 -987 2103 987 +rect 2361 -987 4335 987 +<< metal1 >> +rect -4487 1093 -4384 1139 +rect -2312 1093 -2152 1139 +rect -80 1093 80 1139 +rect 2152 1093 2312 1139 +rect 4384 1093 4487 1139 +rect -4487 1036 -4441 1093 +rect -2255 1036 -2209 1093 +rect -4346 -987 -4335 987 +rect -2361 -987 -2350 987 +rect -4487 -1093 -4441 -1036 +rect -23 1036 23 1093 +rect -2114 -987 -2103 987 +rect -129 -987 -118 987 +rect -2255 -1093 -2209 -1036 +rect 2209 1036 2255 1093 +rect 118 -987 129 987 +rect 2103 -987 2114 987 +rect -23 -1093 23 -1036 +rect 4441 1036 4487 1093 +rect 2350 -987 2361 987 +rect 4335 -987 4346 987 +rect 2209 -1093 2255 -1036 +rect 4441 -1093 4487 -1036 +rect -4487 -1139 -4384 -1093 +rect -2312 -1139 -2152 -1093 +rect -80 -1139 80 -1093 +rect 2152 -1139 2312 -1093 +rect 4384 -1139 4487 -1093 +<< properties >> +string diode_nd2ps_06v0_MV3SZ3 parameters +string FIXED_BBOX 2232 -1116 4464 1116 +string gencell diode_nd2ps_06v0 +string library gf180mcu +string parameters w 10 l 10 area 100.0 peri 40.0 nx 4 ny 1 dummy 0 lmin 0.45 wmin 0.45 class diode elc 1 erc 1 etc 1 ebc 1 doverlap 1 full_metal 1 compatible {diode_nd2ps_03v3 diode_nd2ps_06v0} +<< end >> diff --git a/blocks/composite/regulated_cascoded_cmirror/xschem/Chipathon2025_pads/magic/mag/diode_pd2nw_03v3_5DG9GA.mag b/blocks/composite/regulated_cascoded_cmirror/xschem/Chipathon2025_pads/magic/mag/diode_pd2nw_03v3_5DG9GA.mag new file mode 100644 index 00000000..0809aeed --- /dev/null +++ b/blocks/composite/regulated_cascoded_cmirror/xschem/Chipathon2025_pads/magic/mag/diode_pd2nw_03v3_5DG9GA.mag @@ -0,0 +1,148 @@ +magic +tech gf180mcuD +magscale 1 10 +timestamp 1757928106 +<< nwell >> +rect -4460 -1160 4460 1160 +<< pwell >> +rect -4622 1160 4622 1322 +rect -4622 -1160 -4460 1160 +rect 4460 -1160 4622 1160 +rect -4622 -1322 4622 -1160 +<< psubdiff >> +rect -4598 1285 4598 1298 +rect -4598 1239 -4482 1285 +rect 4482 1239 4598 1285 +rect -4598 1226 4598 1239 +rect -4598 1182 -4526 1226 +rect -4598 -1182 -4585 1182 +rect -4539 -1182 -4526 1182 +rect 4526 1182 4598 1226 +rect -4598 -1226 -4526 -1182 +rect 4526 -1182 4539 1182 +rect 4585 -1182 4598 1182 +rect 4526 -1226 4598 -1182 +rect -4598 -1239 4598 -1226 +rect -4598 -1285 -4482 -1239 +rect 4482 -1285 4598 -1239 +rect -4598 -1298 4598 -1285 +<< nsubdiff >> +rect -4436 1123 4436 1136 +rect -4436 1073 -4316 1123 +rect -2284 1073 -2116 1123 +rect -84 1073 84 1123 +rect 2116 1073 2284 1123 +rect 4316 1073 4436 1123 +rect -4436 1060 4436 1073 +rect -4436 1016 -4360 1060 +rect -4436 -1016 -4423 1016 +rect -4373 -1016 -4360 1016 +rect -2240 1016 -2160 1060 +rect -4436 -1060 -4360 -1016 +rect -2240 -1016 -2227 1016 +rect -2173 -1016 -2160 1016 +rect -40 1016 40 1060 +rect -2240 -1060 -2160 -1016 +rect -40 -1016 -27 1016 +rect 27 -1016 40 1016 +rect 2160 1016 2240 1060 +rect -40 -1060 40 -1016 +rect 2160 -1016 2173 1016 +rect 2227 -1016 2240 1016 +rect 4360 1016 4436 1060 +rect 2160 -1060 2240 -1016 +rect 4360 -1016 4373 1016 +rect 4423 -1016 4436 1016 +rect 4360 -1060 4436 -1016 +rect -4436 -1073 4436 -1060 +rect -4436 -1123 -4316 -1073 +rect -2284 -1123 -2116 -1073 +rect -84 -1123 84 -1073 +rect 2116 -1123 2284 -1073 +rect 4316 -1123 4436 -1073 +rect -4436 -1136 4436 -1123 +<< psubdiffcont >> +rect -4482 1239 4482 1285 +rect -4585 -1182 -4539 1182 +rect 4539 -1182 4585 1182 +rect -4482 -1285 4482 -1239 +<< nsubdiffcont >> +rect -4316 1073 -2284 1123 +rect -2116 1073 -84 1123 +rect 84 1073 2116 1123 +rect 2284 1073 4316 1123 +rect -4423 -1016 -4373 1016 +rect -2227 -1016 -2173 1016 +rect -27 -1016 27 1016 +rect 2173 -1016 2227 1016 +rect 4373 -1016 4423 1016 +rect -4316 -1123 -2284 -1073 +rect -2116 -1123 -84 -1073 +rect 84 -1123 2116 -1073 +rect 2284 -1123 4316 -1073 +<< pdiode >> +rect -4300 987 -2300 1000 +rect -4300 -987 -4287 987 +rect -2313 -987 -2300 987 +rect -4300 -1000 -2300 -987 +rect -2100 987 -100 1000 +rect -2100 -987 -2087 987 +rect -113 -987 -100 987 +rect -2100 -1000 -100 -987 +rect 100 987 2100 1000 +rect 100 -987 113 987 +rect 2087 -987 2100 987 +rect 100 -1000 2100 -987 +rect 2300 987 4300 1000 +rect 2300 -987 2313 987 +rect 4287 -987 4300 987 +rect 2300 -1000 4300 -987 +<< pdiodec >> +rect -4287 -987 -2313 987 +rect -2087 -987 -113 987 +rect 113 -987 2087 987 +rect 2313 -987 4287 987 +<< metal1 >> +rect -4585 1239 -4482 1285 +rect 4482 1239 4585 1285 +rect -4585 1182 -4539 1239 +rect 4539 1182 4585 1239 +rect -4423 1073 -4316 1123 +rect -2284 1073 -2116 1123 +rect -84 1073 84 1123 +rect 2116 1073 2284 1123 +rect 4316 1073 4423 1123 +rect -4423 1016 -4373 1073 +rect -2227 1016 -2173 1073 +rect -4298 -987 -4287 987 +rect -2313 -987 -2302 987 +rect -4423 -1073 -4373 -1016 +rect -27 1016 27 1073 +rect -2098 -987 -2087 987 +rect -113 -987 -102 987 +rect -2227 -1073 -2173 -1016 +rect 2173 1016 2227 1073 +rect 102 -987 113 987 +rect 2087 -987 2098 987 +rect -27 -1073 27 -1016 +rect 4373 1016 4423 1073 +rect 2302 -987 2313 987 +rect 4287 -987 4298 987 +rect 2173 -1073 2227 -1016 +rect 4373 -1073 4423 -1016 +rect -4423 -1123 -4316 -1073 +rect -2284 -1123 -2116 -1073 +rect -84 -1123 84 -1073 +rect 2116 -1123 2284 -1073 +rect 4316 -1123 4423 -1073 +rect -4585 -1239 -4539 -1182 +rect 4539 -1239 4585 -1182 +rect -4585 -1285 -4482 -1239 +rect 4482 -1285 4585 -1239 +<< properties >> +string diode_pd2nw_03v3_5DG9GA parameters +string FIXED_BBOX 2202 -1098 4398 1098 +string gencell diode_pd2nw_03v3 +string library gf180mcu +string parameters w 10 l 10 area 100.0 peri 40.0 nx 4 ny 1 dummy 0 lmin 0.45 wmin 0.45 class diode elc 1 erc 1 etc 1 ebc 1 glc 1 grc 1 gtc 1 gbc 1 doverlap 1 full_metal 1 compatible {diode_pd2nw_03v3 diode_pd2nw_06v0} +<< end >> diff --git a/blocks/composite/regulated_cascoded_cmirror/xschem/Chipathon2025_pads/magic/mag/diode_pd2nw_06v0_5DG9HC.mag b/blocks/composite/regulated_cascoded_cmirror/xschem/Chipathon2025_pads/magic/mag/diode_pd2nw_06v0_5DG9HC.mag new file mode 100644 index 00000000..16671d75 --- /dev/null +++ b/blocks/composite/regulated_cascoded_cmirror/xschem/Chipathon2025_pads/magic/mag/diode_pd2nw_06v0_5DG9HC.mag @@ -0,0 +1,138 @@ +magic +tech gf180mcuD +magscale 1 10 +timestamp 1757961865 +<< nwell >> +rect -4500 -1176 4500 1176 +<< pwell >> +rect -4676 1176 4676 1352 +rect -4676 -1176 -4500 1176 +rect 4500 -1176 4676 1176 +rect -4676 -1352 4676 -1176 +<< mvpsubdiff >> +rect -4644 1248 4644 1320 +rect -4644 1204 -4572 1248 +rect -4644 -1204 -4631 1204 +rect -4585 -1204 -4572 1204 +rect 4572 1204 4644 1248 +rect -4644 -1248 -4572 -1204 +rect 4572 -1204 4585 1204 +rect 4631 -1204 4644 1204 +rect 4572 -1248 4644 -1204 +rect -4644 -1320 4644 -1248 +<< mvnsubdiff >> +rect -4468 1131 4468 1144 +rect -4468 1085 -4352 1131 +rect -2296 1085 -2136 1131 +rect -80 1085 80 1131 +rect 2136 1085 2296 1131 +rect 4352 1085 4468 1131 +rect -4468 1072 4468 1085 +rect -4468 1028 -4396 1072 +rect -4468 -1028 -4455 1028 +rect -4409 -1028 -4396 1028 +rect -2252 1028 -2180 1072 +rect -4468 -1072 -4396 -1028 +rect -2252 -1028 -2239 1028 +rect -2193 -1028 -2180 1028 +rect -36 1028 36 1072 +rect -2252 -1072 -2180 -1028 +rect -36 -1028 -23 1028 +rect 23 -1028 36 1028 +rect 2180 1028 2252 1072 +rect -36 -1072 36 -1028 +rect 2180 -1028 2193 1028 +rect 2239 -1028 2252 1028 +rect 4396 1028 4468 1072 +rect 2180 -1072 2252 -1028 +rect 4396 -1028 4409 1028 +rect 4455 -1028 4468 1028 +rect 4396 -1072 4468 -1028 +rect -4468 -1085 4468 -1072 +rect -4468 -1131 -4352 -1085 +rect -2296 -1131 -2136 -1085 +rect -80 -1131 80 -1085 +rect 2136 -1131 2296 -1085 +rect 4352 -1131 4468 -1085 +rect -4468 -1144 4468 -1131 +<< mvpsubdiffcont >> +rect -4631 -1204 -4585 1204 +rect 4585 -1204 4631 1204 +<< mvnsubdiffcont >> +rect -4352 1085 -2296 1131 +rect -2136 1085 -80 1131 +rect 80 1085 2136 1131 +rect 2296 1085 4352 1131 +rect -4455 -1028 -4409 1028 +rect -2239 -1028 -2193 1028 +rect -23 -1028 23 1028 +rect 2193 -1028 2239 1028 +rect 4409 -1028 4455 1028 +rect -4352 -1131 -2296 -1085 +rect -2136 -1131 -80 -1085 +rect 80 -1131 2136 -1085 +rect 2296 -1131 4352 -1085 +<< mvpdiode >> +rect -4324 987 -2324 1000 +rect -4324 -987 -4311 987 +rect -2337 -987 -2324 987 +rect -4324 -1000 -2324 -987 +rect -2108 987 -108 1000 +rect -2108 -987 -2095 987 +rect -121 -987 -108 987 +rect -2108 -1000 -108 -987 +rect 108 987 2108 1000 +rect 108 -987 121 987 +rect 2095 -987 2108 987 +rect 108 -1000 2108 -987 +rect 2324 987 4324 1000 +rect 2324 -987 2337 987 +rect 4311 -987 4324 987 +rect 2324 -1000 4324 -987 +<< mvpdiodec >> +rect -4311 -987 -2337 987 +rect -2095 -987 -121 987 +rect 121 -987 2095 987 +rect 2337 -987 4311 987 +<< metal1 >> +rect -4631 1261 4631 1307 +rect -4631 1204 -4585 1261 +rect 4585 1204 4631 1261 +rect -4455 1085 -4352 1131 +rect -2296 1085 -2136 1131 +rect -80 1085 80 1131 +rect 2136 1085 2296 1131 +rect 4352 1085 4455 1131 +rect -4455 1028 -4409 1085 +rect -2239 1028 -2193 1085 +rect -4322 -987 -4311 987 +rect -2337 -987 -2326 987 +rect -4455 -1085 -4409 -1028 +rect -23 1028 23 1085 +rect -2106 -987 -2095 987 +rect -121 -987 -110 987 +rect -2239 -1085 -2193 -1028 +rect 2193 1028 2239 1085 +rect 110 -987 121 987 +rect 2095 -987 2106 987 +rect -23 -1085 23 -1028 +rect 4409 1028 4455 1085 +rect 2326 -987 2337 987 +rect 4311 -987 4322 987 +rect 2193 -1085 2239 -1028 +rect 4409 -1085 4455 -1028 +rect -4455 -1131 -4352 -1085 +rect -2296 -1131 -2136 -1085 +rect -80 -1131 80 -1085 +rect 2136 -1131 2296 -1085 +rect 4352 -1131 4455 -1085 +rect -4631 -1261 -4585 -1204 +rect 4585 -1261 4631 -1204 +rect -4631 -1307 4631 -1261 +<< properties >> +string diode_pd2nw_06v0_5DG9HC parameters +string FIXED_BBOX 2216 -1108 4432 1108 +string gencell diode_pd2nw_06v0 +string library gf180mcu +string parameters w 10 l 10 area 100.0 peri 40.0 nx 4 ny 1 dummy 0 lmin 0.45 wmin 0.45 class diode elc 1 erc 1 etc 1 ebc 1 glc 1 grc 1 gtc 0 gbc 0 doverlap 1 full_metal 1 compatible {diode_pd2nw_03v3 diode_pd2nw_06v0} +<< end >> diff --git a/blocks/composite/regulated_cascoded_cmirror/xschem/Chipathon2025_pads/magic/mag/io_secondary_5p0.mag b/blocks/composite/regulated_cascoded_cmirror/xschem/Chipathon2025_pads/magic/mag/io_secondary_5p0.mag new file mode 100644 index 00000000..d22ee597 --- /dev/null +++ b/blocks/composite/regulated_cascoded_cmirror/xschem/Chipathon2025_pads/magic/mag/io_secondary_5p0.mag @@ -0,0 +1,141 @@ +magic +tech gf180mcuD +magscale 1 10 +timestamp 1757963017 +<< metal1 >> +rect -7200 12140 7520 12240 +rect -7200 11530 -6410 12140 +rect 2510 11530 7520 12140 +rect -7200 11450 7520 11530 +rect 4140 11448 7520 11450 +rect 4170 10500 7520 11448 +rect -7200 7290 -6510 9850 +rect -6420 9710 -6370 9720 +rect 2490 9710 2540 9720 +rect -6420 9620 -6410 9710 +rect 2507 9620 2540 9710 +rect -6420 9610 -6370 9620 +rect 2490 9610 2540 9620 +rect -5943 7732 -5933 8316 +rect -4592 7732 -4582 8316 +rect -3726 7713 -3716 8297 +rect -2375 7713 -2365 8297 +rect -1501 7709 -1491 8293 +rect -150 7709 -140 8293 +rect 680 7723 690 8307 +rect 2031 7723 2041 8307 +rect 2620 7290 2950 9850 +rect 4160 7410 7520 10500 +rect -7200 -1620 2950 7290 +rect -7200 -1650 -6360 -1620 +rect 2500 -1650 2950 -1620 +rect 4170 6880 7520 7410 +rect 4170 -1340 4630 6880 +rect 4680 6760 4810 6770 +rect 4680 -1230 4690 6760 +rect 4800 -1230 4810 6760 +rect 4680 -1240 4810 -1230 +rect 6880 6760 7010 6770 +rect 6880 -1230 6890 6760 +rect 7000 -1230 7010 6760 +rect 6880 -1240 7010 -1230 +rect 7070 -1340 7520 6880 +rect -7200 -3810 -6358 -1650 +rect -5942 -2413 -5932 -1829 +rect -4591 -2413 -4581 -1829 +rect -3725 -2413 -3715 -1829 +rect -2374 -2413 -2364 -1829 +rect -1500 -2410 -1490 -1826 +rect -149 -2410 -139 -1826 +rect 680 -2410 690 -1826 +rect 2031 -2410 2041 -1826 +rect 2500 -1880 2952 -1650 +rect 2502 -3810 2952 -1880 +rect 4170 -2070 7520 -1340 +rect -7200 -4830 2952 -3810 +<< via1 >> +rect -6410 11530 2510 12140 +rect -6410 9620 2507 9710 +rect -5933 7732 -4592 8316 +rect -3716 7713 -2375 8297 +rect -1491 7709 -150 8293 +rect 690 7723 2031 8307 +rect 4690 -1230 4800 6760 +rect 6890 -1230 7000 6760 +rect -5932 -2413 -4591 -1829 +rect -3715 -2413 -2374 -1829 +rect -1490 -2410 -149 -1826 +rect 690 -2410 2031 -1826 +<< metal2 >> +rect -6440 12140 2540 12190 +rect -6440 11530 -6410 12140 +rect 2510 11530 2540 12140 +rect -6440 11520 2540 11530 +rect -6433 11388 2540 11520 +rect -6431 11120 2540 11388 +rect -6430 9710 2540 11120 +rect -6430 9620 -6410 9710 +rect 2507 9620 2540 9710 +rect -6430 9600 2540 9620 +rect -5950 8316 -4570 8330 +rect -5950 7732 -5933 8316 +rect -4592 7732 -4570 8316 +rect -5950 6760 -4570 7732 +rect -3730 8297 -2350 8330 +rect -3730 7713 -3716 8297 +rect -2375 7713 -2350 8297 +rect -3730 6760 -2350 7713 +rect -1510 8293 -130 8330 +rect -1510 7709 -1491 8293 +rect -150 7709 -130 8293 +rect -1510 6760 -130 7709 +rect 670 8307 2050 8320 +rect 670 7723 690 8307 +rect 2031 7723 2050 8307 +rect 670 6770 2050 7723 +rect 670 6760 4810 6770 +rect -7200 -1230 4690 6760 +rect 4800 -1230 4810 6760 +rect -7200 -1240 4810 -1230 +rect 6880 6760 7930 6770 +rect 6880 -1230 6890 6760 +rect 7000 -1230 7930 6760 +rect 6880 -1240 7930 -1230 +rect -5950 -1829 -4570 -1240 +rect -5950 -2413 -5932 -1829 +rect -4591 -2413 -4570 -1829 +rect -5950 -2420 -4570 -2413 +rect -3730 -1829 -2350 -1240 +rect -3730 -2413 -3715 -1829 +rect -2374 -2413 -2350 -1829 +rect -3730 -2420 -2350 -2413 +rect -1510 -1826 -130 -1240 +rect -1510 -2410 -1490 -1826 +rect -149 -2410 -130 -1826 +rect -1510 -2420 -130 -2410 +rect 670 -1826 2050 -1240 +rect 670 -2410 690 -1826 +rect 2031 -2410 2050 -1826 +rect 670 -2430 2050 -2410 +use diode_nd2ps_06v0_MV3SZ3 diode_nd2ps_06v0_MV3SZ3_0 +timestamp 1757961865 +transform 1 0 -1916 0 1 -2714 +box -4524 -1176 4524 1176 +use diode_pd2nw_06v0_5DG9HC diode_pd2nw_06v0_5DG9HC_0 +timestamp 1757961865 +transform 1 0 -1944 0 1 8542 +box -4676 -1352 4676 1352 +use ppolyf_u_9H3LNU ppolyf_u_9H3LNU_0 +timestamp 1757961865 +transform 0 1 5848 -1 0 2766 +box -4216 -1318 4216 1318 +<< labels >> +rlabel metal1 -6708 -4450 -6708 -4450 1 VSS +port 3 n +rlabel metal2 -6710 3260 -6710 3280 1 to_gate +port 1 n +rlabel metal1 -7168 11918 -7168 11918 1 VDD +port 2 n +rlabel metal2 7697 2976 7697 2976 1 ASIG5V +port 0 n +<< end >> diff --git a/blocks/composite/regulated_cascoded_cmirror/xschem/Chipathon2025_pads/magic/mag/ppolyf_u_4VJXJK.mag b/blocks/composite/regulated_cascoded_cmirror/xschem/Chipathon2025_pads/magic/mag/ppolyf_u_4VJXJK.mag new file mode 100644 index 00000000..1fd4f8e3 --- /dev/null +++ b/blocks/composite/regulated_cascoded_cmirror/xschem/Chipathon2025_pads/magic/mag/ppolyf_u_4VJXJK.mag @@ -0,0 +1,62 @@ +magic +tech gf180mcuD +magscale 1 10 +timestamp 1757960183 +<< nwell >> +rect -1816 -718 1816 718 +<< nsubdiff >> +rect -1792 681 1792 694 +rect -1792 635 -1676 681 +rect 1676 635 1792 681 +rect -1792 622 1792 635 +rect -1792 578 -1720 622 +rect -1792 -578 -1779 578 +rect -1733 -578 -1720 578 +rect 1720 578 1792 622 +rect -1792 -622 -1720 -578 +rect 1720 -578 1733 578 +rect 1779 -578 1792 578 +rect 1720 -622 1792 -578 +rect -1792 -635 1792 -622 +rect -1792 -681 -1676 -635 +rect 1676 -681 1792 -635 +rect -1792 -694 1792 -681 +<< nsubdiffcont >> +rect -1676 635 1676 681 +rect -1779 -578 -1733 578 +rect 1733 -578 1779 578 +rect -1676 -681 1676 -635 +<< polysilicon >> +rect -1600 489 1600 502 +rect -1600 443 -1587 489 +rect 1587 443 1600 489 +rect -1600 400 1600 443 +rect -1600 -443 1600 -400 +rect -1600 -489 -1587 -443 +rect 1587 -489 1600 -443 +rect -1600 -502 1600 -489 +<< polycontact >> +rect -1587 443 1587 489 +rect -1587 -489 1587 -443 +<< ppolyres >> +rect -1600 -400 1600 400 +<< metal1 >> +rect -1779 635 -1676 681 +rect 1676 635 1779 681 +rect -1779 578 -1733 635 +rect 1733 578 1779 635 +rect -1598 443 -1587 489 +rect 1587 443 1598 489 +rect -1598 -489 -1587 -443 +rect 1587 -489 1598 -443 +rect -1779 -635 -1733 -578 +rect 1733 -635 1779 -578 +rect -1779 -681 -1676 -635 +rect 1676 -681 1779 -635 +<< properties >> +string FIXED_BBOX -1756 -658 1756 658 +string gencell ppolyf_u +string library gf180mcu +string parameters w 16 l 4 m 1 nx 1 wmin 0.80 lmin 1.00 class resistor rho 315 val 79.096 dummy 0 dw 0.07 term 0.0 sterm 0.0 caplen 0.4 snake 0 glc 1 grc 1 gtc 1 gbc 1 roverlap 0 endcov 100 full_metal 1 +string ppolyf_u_4VJXJK parameters +<< end >> diff --git a/blocks/composite/regulated_cascoded_cmirror/xschem/Chipathon2025_pads/magic/mag/ppolyf_u_9H3L5V.mag b/blocks/composite/regulated_cascoded_cmirror/xschem/Chipathon2025_pads/magic/mag/ppolyf_u_9H3L5V.mag new file mode 100644 index 00000000..7eb6e44d --- /dev/null +++ b/blocks/composite/regulated_cascoded_cmirror/xschem/Chipathon2025_pads/magic/mag/ppolyf_u_9H3L5V.mag @@ -0,0 +1,52 @@ +magic +tech gf180mcuD +magscale 1 10 +timestamp 1757961865 +<< nwell >> +rect -4216 -1318 4216 1318 +<< nsubdiff >> +rect -4192 1222 4192 1294 +rect -4192 1178 -4120 1222 +rect -4192 -1178 -4179 1178 +rect -4133 -1178 -4120 1178 +rect 4120 1178 4192 1222 +rect -4192 -1222 -4120 -1178 +rect 4120 -1178 4133 1178 +rect 4179 -1178 4192 1178 +rect 4120 -1222 4192 -1178 +rect -4192 -1294 4192 -1222 +<< nsubdiffcont >> +rect -4179 -1178 -4133 1178 +rect 4133 -1178 4179 1178 +<< polysilicon >> +rect -4000 1089 4000 1102 +rect -4000 1043 -3987 1089 +rect 3987 1043 4000 1089 +rect -4000 1000 4000 1043 +rect -4000 -1043 4000 -1000 +rect -4000 -1089 -3987 -1043 +rect 3987 -1089 4000 -1043 +rect -4000 -1102 4000 -1089 +<< polycontact >> +rect -3987 1043 3987 1089 +rect -3987 -1089 3987 -1043 +<< ppolyres >> +rect -4000 -1000 4000 1000 +<< metal1 >> +rect -4179 1235 4179 1281 +rect -4179 1178 -4133 1235 +rect 4133 1178 4179 1235 +rect -3998 1043 -3987 1089 +rect 3987 1043 3998 1089 +rect -3998 -1089 -3987 -1043 +rect 3987 -1089 3998 -1043 +rect -4179 -1235 -4133 -1178 +rect 4133 -1235 4179 -1178 +rect -4179 -1281 4179 -1235 +<< properties >> +string FIXED_BBOX -4156 -1258 4156 1258 +string gencell ppolyf_u +string library gf180mcu +string parameters w 40 l 10 m 1 nx 1 wmin 0.80 lmin 1.00 class resistor rho 315 val 78.888 dummy 0 dw 0.07 term 0.0 sterm 0.0 caplen 0.4 snake 0 glc 1 grc 1 gtc 0 gbc 0 roverlap 0 endcov 100 full_metal 1 +string ppolyf_u_9H3L5V parameters +<< end >> diff --git a/blocks/composite/regulated_cascoded_cmirror/xschem/Chipathon2025_pads/magic/mag/ppolyf_u_9H3LNU.mag b/blocks/composite/regulated_cascoded_cmirror/xschem/Chipathon2025_pads/magic/mag/ppolyf_u_9H3LNU.mag new file mode 100644 index 00000000..f43cabaa --- /dev/null +++ b/blocks/composite/regulated_cascoded_cmirror/xschem/Chipathon2025_pads/magic/mag/ppolyf_u_9H3LNU.mag @@ -0,0 +1,62 @@ +magic +tech gf180mcuD +magscale 1 10 +timestamp 1757961865 +<< nwell >> +rect -4216 -1318 4216 1318 +<< nsubdiff >> +rect -4192 1281 4192 1294 +rect -4192 1235 -4076 1281 +rect 4076 1235 4192 1281 +rect -4192 1222 4192 1235 +rect -4192 1178 -4120 1222 +rect -4192 -1178 -4179 1178 +rect -4133 -1178 -4120 1178 +rect 4120 1178 4192 1222 +rect -4192 -1222 -4120 -1178 +rect 4120 -1178 4133 1178 +rect 4179 -1178 4192 1178 +rect 4120 -1222 4192 -1178 +rect -4192 -1235 4192 -1222 +rect -4192 -1281 -4076 -1235 +rect 4076 -1281 4192 -1235 +rect -4192 -1294 4192 -1281 +<< nsubdiffcont >> +rect -4076 1235 4076 1281 +rect -4179 -1178 -4133 1178 +rect 4133 -1178 4179 1178 +rect -4076 -1281 4076 -1235 +<< polysilicon >> +rect -4000 1089 4000 1102 +rect -4000 1043 -3987 1089 +rect 3987 1043 4000 1089 +rect -4000 1000 4000 1043 +rect -4000 -1043 4000 -1000 +rect -4000 -1089 -3987 -1043 +rect 3987 -1089 4000 -1043 +rect -4000 -1102 4000 -1089 +<< polycontact >> +rect -3987 1043 3987 1089 +rect -3987 -1089 3987 -1043 +<< ppolyres >> +rect -4000 -1000 4000 1000 +<< metal1 >> +rect -4179 1235 -4076 1281 +rect 4076 1235 4179 1281 +rect -4179 1178 -4133 1235 +rect 4133 1178 4179 1235 +rect -3998 1043 -3987 1089 +rect 3987 1043 3998 1089 +rect -3998 -1089 -3987 -1043 +rect 3987 -1089 3998 -1043 +rect -4179 -1235 -4133 -1178 +rect 4133 -1235 4179 -1178 +rect -4179 -1281 -4076 -1235 +rect 4076 -1281 4179 -1235 +<< properties >> +string FIXED_BBOX -4156 -1258 4156 1258 +string gencell ppolyf_u +string library gf180mcu +string parameters w 40 l 10 m 1 nx 1 wmin 0.80 lmin 1.00 class resistor rho 315 val 78.888 dummy 0 dw 0.07 term 0.0 sterm 0.0 caplen 0.4 snake 0 glc 1 grc 1 gtc 1 gbc 1 roverlap 0 endcov 100 full_metal 1 +string ppolyf_u_9H3LNU parameters +<< end >> diff --git a/blocks/composite/regulated_cascoded_cmirror/xschem/Chipathon2025_pads/magic/secondary_ESD.gds b/blocks/composite/regulated_cascoded_cmirror/xschem/Chipathon2025_pads/magic/secondary_ESD.gds new file mode 100644 index 00000000..ed0f3e78 Binary files /dev/null and b/blocks/composite/regulated_cascoded_cmirror/xschem/Chipathon2025_pads/magic/secondary_ESD.gds differ diff --git a/blocks/composite/regulated_cascoded_cmirror/xschem/Chipathon2025_pads/xschem/README.md b/blocks/composite/regulated_cascoded_cmirror/xschem/Chipathon2025_pads/xschem/README.md new file mode 100644 index 00000000..d9453eeb --- /dev/null +++ b/blocks/composite/regulated_cascoded_cmirror/xschem/Chipathon2025_pads/xschem/README.md @@ -0,0 +1,25 @@ +This folder contains different test benches and configurations for analog and digital pads. + +Description of the files: + +## Simulation files of the analog pad (asig_5p0) in the simulations. +1) **asig5V_AC_tb.sch:** AC simulation of the asig_5p0 analog pad. +2) **asig5V_DC_tb.sch:** DC simulation of the ASIG_5P0 analog pad. +3) **asig5V_tran_tb.sch:** Transient simulation of the asig_5p0 analog pad. + +Note that there is no symbol associated with the pad in any of these three simulation files, so the model is included to account for its effect on the simulation. + +Additionally, the model used in all three simulations is the extracted view of the pad by incorporating the model [gf180mcu_fd_io__asig_5p0_extracted.spice](https://github.com/JuanMoya/sscs-chipathon-2025/blob/main/resources/Integration/Chipathon2025_pads/xschem/gf180mcu_fd_io__asig_5p0_extracted.spice), which includes all the extracted parasitic elements. Comparing the previous file with the non-extracted model of the [asig_5p0 pad](https://github.com/JuanMoya/sscs-chipathon-2025/blob/main/resources/Integration/Chipathon2025_pads/xschem/gf180mcu_fd_io.spice) reveals that the extracted view contains an additional pad pin (PAD), as shown in [Figure 4.5](https://gf180mcu-pdk.readthedocs.io/en/latest/IPs/IO/gf180mcu_fd_io/analog.html). This is the main reason why including the extracted view of the asig_5p0 pad is preferable to using the non-extracted view. + +## Simulation files of the digital pad (bi_t) in the simulations. +**bi_t_tran_tb.sch:** Transient simulation of the bi_t digital pad. + +The configuration of the pin is based on the documentation provided by GF in [4.1 Digital I/O Cell Control Pins](https://gf180mcu-pdk.readthedocs.io/en/latest/IPs/IO/gf180mcu_fd_io/digital.html) an in [4.2 Tri-state Programmable Digital I/O Cell](https://gf180mcu-pdk.readthedocs.io/en/latest/IPs/IO/gf180mcu_fd_io/tri_state_1.html). + +In this schematic, it is possible to observe 3 different configurations based on the values of **IE** and **OE** pins: +1) Bidirectional +2) Output Enabled +3) Input Enabled + +## Simulation files of the tiehigh and tielow cells. +**test_tieH_L.sch:** Transient simulation of the tiehigh and tielow cells. diff --git a/blocks/composite/regulated_cascoded_cmirror/xschem/Chipathon2025_pads/xschem/asig5V_AC_tb.sch b/blocks/composite/regulated_cascoded_cmirror/xschem/Chipathon2025_pads/xschem/asig5V_AC_tb.sch new file mode 100644 index 00000000..f4e1d15d --- /dev/null +++ b/blocks/composite/regulated_cascoded_cmirror/xschem/Chipathon2025_pads/xschem/asig5V_AC_tb.sch @@ -0,0 +1,66 @@ +v {xschem version=3.4.7 file_version=1.2} +G {} +K {} +V {} +S {} +E {} +N 60 -100 60 -60 {lab=GND} +N 160 -100 160 -60 {lab=GND} +N 260 -100 260 -60 {lab=GND} +N 360 -100 360 -60 {lab=GND} +N 60 -200 60 -160 {lab=DVDD} +N 160 -200 160 -160 {lab=VDD} +N 260 -200 260 -160 {lab=DVSS} +N 360 -200 360 -160 {lab=VSS} +N 60 -60 360 -60 {lab=GND} +N 210 -60 210 -40 {lab=GND} +N 500 -60 500 -40 { +lab=GND} +N 500 -270 500 -210 { +lab=ASIG} +N 500 -150 500 -120 { +lab=#net1} +C {vsource.sym} 60 -130 0 0 {name=V1 value=5 savecurrent=false} +C {vsource.sym} 160 -130 0 0 {name=V2 value=5 savecurrent=false} +C {vsource.sym} 260 -130 0 0 {name=V3 value=0 savecurrent=false} +C {vsource.sym} 360 -130 0 0 {name=V4 value=0 savecurrent=false} +C {lab_wire.sym} 60 -200 0 0 {name=p1 sig_type=std_logic lab=DVDD} +C {lab_wire.sym} 160 -200 0 0 {name=p2 sig_type=std_logic lab=VDD} +C {gnd.sym} 210 -40 0 0 {name=l1 lab=GND} +C {lab_wire.sym} 260 -200 0 0 {name=p3 sig_type=std_logic lab=DVSS} +C {lab_wire.sym} 360 -200 0 0 {name=p4 sig_type=std_logic lab=VSS} +C {devices/vsource.sym} 500 -90 0 0 {name=V5 value="DC 3 AC 1"} +C {devices/lab_wire.sym} 500 -250 0 0 {name=p5 sig_type=std_logic lab=ASIG} +C {devices/gnd.sym} 500 -40 0 0 {name=l2 lab=GND} +C {devices/res.sym} 500 -180 0 0 {name=R1 +value=1k +footprint=1206 +device=resistor +m=1} +C {devices/code_shown.sym} 10 -500 0 0 {name=DUT only_toplevel=true +format="tcleval( @value )" +value=" +.include "/foss/designs/Chipathon2025_pads/xschem/gf180mcu_fd_io__asig_5p0_extracted.spice" +XDUT DVSS DVDD VSS VDD PAD ASIG gf180mcu_fd_io__asig_5p0_extracted +"} +C {devices/code_shown.sym} 610 -370 0 0 {name=MODELS only_toplevel=true +format="tcleval( @value )" +value=" +.include $::180MCU_MODELS/design.ngspice +.lib $::180MCU_MODELS/sm141064.ngspice typical +.lib $::180MCU_MODELS/sm141064.ngspice diode_typical +.lib $::180MCU_MODELS/sm141064.ngspice res_typical +.lib $::180MCU_MODELS/sm141064.ngspice moscap_typical +"} +C {devices/code_shown.sym} 620 -190 0 0 {name=s1 +only_toplevel=false +value=" +.ac dec 100 1k 100G +.save all +.control +run +display +plot PAD ASIG +plot vdb(asig) vdb(pad) +.endc +"} diff --git a/blocks/composite/regulated_cascoded_cmirror/xschem/Chipathon2025_pads/xschem/asig5V_DC_tb.sch b/blocks/composite/regulated_cascoded_cmirror/xschem/Chipathon2025_pads/xschem/asig5V_DC_tb.sch new file mode 100644 index 00000000..1571bf9a --- /dev/null +++ b/blocks/composite/regulated_cascoded_cmirror/xschem/Chipathon2025_pads/xschem/asig5V_DC_tb.sch @@ -0,0 +1,104 @@ +v {xschem version=3.4.7 file_version=1.2} +G {} +K {} +V {} +S {} +E {} +N 50 -140 50 -100 {lab=GND} +N 150 -140 150 -100 {lab=GND} +N 250 -140 250 -100 {lab=GND} +N 350 -140 350 -100 {lab=GND} +N 50 -240 50 -200 {lab=DVDD} +N 150 -240 150 -200 {lab=VDD} +N 250 -240 250 -200 {lab=DVSS} +N 350 -240 350 -200 {lab=VSS} +N 50 -100 350 -100 {lab=GND} +N 200 -100 200 -80 {lab=GND} +N 770 -120 770 -100 { +lab=VSS} +N 680 -260 730 -260 {lab=Vin} +N 680 -260 680 -150 {lab=Vin} +N 680 -150 730 -150 {lab=Vin} +N 770 -100 770 -80 {lab=VSS} +N 770 -330 770 -290 {lab=VDD} +N 770 -230 770 -180 {lab=ASIG} +N 770 -200 790 -200 {lab=ASIG} +N 660 -200 680 -200 {lab=Vin} +N 770 -260 840 -260 {lab=VDD} +N 840 -330 840 -260 {lab=VDD} +N 770 -330 840 -330 {lab=VDD} +N 770 -350 770 -330 {lab=VDD} +N 770 -80 770 -60 {lab=VSS} +N 770 -150 840 -150 {lab=VSS} +N 840 -150 840 -80 {lab=VSS} +N 770 -80 840 -80 {lab=VSS} +N 450 -140 450 -100 {lab=GND} +N 450 -240 450 -200 {lab=Vin} +N 350 -100 450 -100 {lab=GND} +C {vsource.sym} 50 -170 0 0 {name=V1 value=5 savecurrent=false} +C {vsource.sym} 150 -170 0 0 {name=V2 value=5 savecurrent=false} +C {vsource.sym} 250 -170 0 0 {name=V3 value=0 savecurrent=false} +C {vsource.sym} 350 -170 0 0 {name=V4 value=0 savecurrent=false} +C {lab_wire.sym} 50 -240 0 0 {name=p1 sig_type=std_logic lab=DVDD} +C {lab_wire.sym} 150 -240 0 0 {name=p2 sig_type=std_logic lab=VDD} +C {gnd.sym} 200 -80 0 0 {name=l1 lab=GND} +C {lab_wire.sym} 250 -240 0 0 {name=p3 sig_type=std_logic lab=DVSS} +C {lab_wire.sym} 350 -240 0 0 {name=p4 sig_type=std_logic lab=VSS} +C {devices/lab_wire.sym} 790 -200 0 1 {name=p5 sig_type=std_logic lab=ASIG} +C {devices/code_shown.sym} 0 -540 0 0 {name=DUT only_toplevel=true +format="tcleval( @value )" +value=" +.include "/foss/designs/Chipathon2025_pads/xschem/gf180mcu_fd_io__asig_5p0_extracted.spice" +XDUT DVSS DVDD VSS VDD PAD ASIG gf180mcu_fd_io__asig_5p0_extracted +"} +C {devices/code_shown.sym} 930 -410 0 0 {name=MODELS only_toplevel=true +format="tcleval( @value )" +value=" +.include $::180MCU_MODELS/design.ngspice +.lib $::180MCU_MODELS/sm141064.ngspice typical +.lib $::180MCU_MODELS/sm141064.ngspice diode_typical +.lib $::180MCU_MODELS/sm141064.ngspice res_typical +.lib $::180MCU_MODELS/sm141064.ngspice moscap_typical +"} +C {devices/code_shown.sym} 940 -230 0 0 {name=s1 +only_toplevel=false +value=" + +.control +tran 1n 1u +plot V(Vin)+12 V(ASIG)+6 V(PAD) +.endc +"} +C {lab_wire.sym} 770 -350 0 0 {name=p6 sig_type=std_logic lab=VDD} +C {lab_wire.sym} 770 -60 0 0 {name=p7 sig_type=std_logic lab=VSS} +C {vsource.sym} 450 -170 0 0 {name=V5 value="PWL(0 0 500n 2.5 1u 5)" savecurrent=false} +C {lab_wire.sym} 450 -240 0 0 {name=p8 sig_type=std_logic lab=Vin} +C {lab_wire.sym} 660 -200 0 0 {name=p9 sig_type=std_logic lab=Vin} +C {symbols/pfet_05v0.sym} 750 -260 0 0 {name=M1 +L=0.50u +W=8.0u +nf=1 +m=1 +ad="'int((nf+1)/2) * W/nf * 0.18u'" +pd="'2*int((nf+1)/2) * (W/nf + 0.18u)'" +as="'int((nf+2)/2) * W/nf * 0.18u'" +ps="'2*int((nf+2)/2) * (W/nf + 0.18u)'" +nrd="'0.18u / W'" nrs="'0.18u / W'" +sa=0 sb=0 sd=0 +model=pfet_05v0 +spiceprefix=X +} +C {symbols/nfet_05v0.sym} 750 -150 0 0 {name=M2 +L=0.60u +W=3.0u +nf=1 +m=1 +ad="'int((nf+1)/2) * W/nf * 0.18u'" +pd="'2*int((nf+1)/2) * (W/nf + 0.18u)'" +as="'int((nf+2)/2) * W/nf * 0.18u'" +ps="'2*int((nf+2)/2) * (W/nf + 0.18u)'" +nrd="'0.18u / W'" nrs="'0.18u / W'" +sa=0 sb=0 sd=0 +model=nfet_05v0 +spiceprefix=X +} diff --git a/blocks/composite/regulated_cascoded_cmirror/xschem/Chipathon2025_pads/xschem/asig5V_tran_tb.sch b/blocks/composite/regulated_cascoded_cmirror/xschem/Chipathon2025_pads/xschem/asig5V_tran_tb.sch new file mode 100644 index 00000000..86db9341 --- /dev/null +++ b/blocks/composite/regulated_cascoded_cmirror/xschem/Chipathon2025_pads/xschem/asig5V_tran_tb.sch @@ -0,0 +1,104 @@ +v {xschem version=3.4.7 file_version=1.2} +G {} +K {} +V {} +S {} +E {} +N 80 -140 80 -100 {lab=GND} +N 180 -140 180 -100 {lab=GND} +N 280 -140 280 -100 {lab=GND} +N 380 -140 380 -100 {lab=GND} +N 80 -240 80 -200 {lab=DVDD} +N 180 -240 180 -200 {lab=VDD} +N 280 -240 280 -200 {lab=DVSS} +N 380 -240 380 -200 {lab=VSS} +N 80 -100 380 -100 {lab=GND} +N 230 -100 230 -80 {lab=GND} +N 800 -120 800 -100 { +lab=VSS} +N 710 -260 760 -260 {lab=Vin} +N 710 -260 710 -150 {lab=Vin} +N 710 -150 760 -150 {lab=Vin} +N 800 -100 800 -80 {lab=VSS} +N 800 -330 800 -290 {lab=VDD} +N 800 -230 800 -180 {lab=ASIG} +N 800 -200 820 -200 {lab=ASIG} +N 690 -200 710 -200 {lab=Vin} +N 800 -260 870 -260 {lab=VDD} +N 870 -330 870 -260 {lab=VDD} +N 800 -330 870 -330 {lab=VDD} +N 800 -350 800 -330 {lab=VDD} +N 800 -80 800 -60 {lab=VSS} +N 800 -150 870 -150 {lab=VSS} +N 870 -150 870 -80 {lab=VSS} +N 800 -80 870 -80 {lab=VSS} +N 480 -140 480 -100 {lab=GND} +N 480 -240 480 -200 {lab=Vin} +N 380 -100 480 -100 {lab=GND} +C {vsource.sym} 80 -170 0 0 {name=V1 value=5 savecurrent=false} +C {vsource.sym} 180 -170 0 0 {name=V2 value=5 savecurrent=false} +C {vsource.sym} 280 -170 0 0 {name=V3 value=0 savecurrent=false} +C {vsource.sym} 380 -170 0 0 {name=V4 value=0 savecurrent=false} +C {lab_wire.sym} 80 -240 0 0 {name=p1 sig_type=std_logic lab=DVDD} +C {lab_wire.sym} 180 -240 0 0 {name=p2 sig_type=std_logic lab=VDD} +C {gnd.sym} 230 -80 0 0 {name=l1 lab=GND} +C {lab_wire.sym} 280 -240 0 0 {name=p3 sig_type=std_logic lab=DVSS} +C {lab_wire.sym} 380 -240 0 0 {name=p4 sig_type=std_logic lab=VSS} +C {devices/lab_wire.sym} 820 -200 0 1 {name=p5 sig_type=std_logic lab=ASIG} +C {devices/code_shown.sym} 30 -540 0 0 {name=DUT only_toplevel=true +format="tcleval( @value )" +value=" +.include "/foss/designs/Chipathon2025_pads/xschem/gf180mcu_fd_io__asig_5p0_extracted.spice" +XDUT DVSS DVDD VSS VDD PAD ASIG gf180mcu_fd_io__asig_5p0_extracted +"} +C {devices/code_shown.sym} 960 -410 0 0 {name=MODELS only_toplevel=true +format="tcleval( @value )" +value=" +.include $::180MCU_MODELS/design.ngspice +.lib $::180MCU_MODELS/sm141064.ngspice typical +.lib $::180MCU_MODELS/sm141064.ngspice diode_typical +.lib $::180MCU_MODELS/sm141064.ngspice res_typical +.lib $::180MCU_MODELS/sm141064.ngspice moscap_typical +"} +C {devices/code_shown.sym} 970 -230 0 0 {name=s1 +only_toplevel=false +value=" + +.control +tran 1n 1u +plot V(Vin)+12 V(ASIG)+6 V(PAD) +.endc +"} +C {lab_wire.sym} 800 -350 0 0 {name=p6 sig_type=std_logic lab=VDD} +C {lab_wire.sym} 800 -60 0 0 {name=p7 sig_type=std_logic lab=VSS} +C {vsource.sym} 480 -170 0 0 {name=V5 value="PULSE(0 5 2n 10n 10n 400n 800n)" savecurrent=false} +C {lab_wire.sym} 480 -240 0 0 {name=p8 sig_type=std_logic lab=Vin} +C {lab_wire.sym} 690 -200 0 0 {name=p9 sig_type=std_logic lab=Vin} +C {symbols/pfet_05v0.sym} 780 -260 0 0 {name=M1 +L=0.50u +W=8.0u +nf=1 +m=1 +ad="'int((nf+1)/2) * W/nf * 0.18u'" +pd="'2*int((nf+1)/2) * (W/nf + 0.18u)'" +as="'int((nf+2)/2) * W/nf * 0.18u'" +ps="'2*int((nf+2)/2) * (W/nf + 0.18u)'" +nrd="'0.18u / W'" nrs="'0.18u / W'" +sa=0 sb=0 sd=0 +model=pfet_05v0 +spiceprefix=X +} +C {symbols/nfet_05v0.sym} 780 -150 0 0 {name=M2 +L=0.60u +W=3.0u +nf=1 +m=1 +ad="'int((nf+1)/2) * W/nf * 0.18u'" +pd="'2*int((nf+1)/2) * (W/nf + 0.18u)'" +as="'int((nf+2)/2) * W/nf * 0.18u'" +ps="'2*int((nf+2)/2) * (W/nf + 0.18u)'" +nrd="'0.18u / W'" nrs="'0.18u / W'" +sa=0 sb=0 sd=0 +model=nfet_05v0 +spiceprefix=X +} diff --git a/blocks/composite/regulated_cascoded_cmirror/xschem/Chipathon2025_pads/xschem/bi_t_tran_tb.sch b/blocks/composite/regulated_cascoded_cmirror/xschem/Chipathon2025_pads/xschem/bi_t_tran_tb.sch new file mode 100644 index 00000000..f193966b --- /dev/null +++ b/blocks/composite/regulated_cascoded_cmirror/xschem/Chipathon2025_pads/xschem/bi_t_tran_tb.sch @@ -0,0 +1,188 @@ +v {xschem version=3.4.7 file_version=1.2} +G {} +K {} +V {} +S {} +E {} +T {Bidirectional configuration} 290 -290 0 0 0.4 0.4 {} +T {Output enabled configuration} 760 -290 0 0 0.4 0.4 {} +T {Input enabled configuration} 1210 -290 0 0 0.4 0.4 {} +N 150 -490 150 -470 { +lab=GND} +N 150 -610 150 -550 { +lab=DVDD} +N 210 -490 210 -470 { +lab=GND} +N 210 -610 210 -550 { +lab=VDD} +N 150 -470 210 -470 { +lab=GND} +N 270 -490 270 -470 { +lab=GND} +N 270 -610 270 -550 { +lab=DVSS} +N 330 -490 330 -470 { +lab=GND} +N 330 -610 330 -550 { +lab=VSS} +N 270 -470 330 -470 { +lab=GND} +N 210 -470 270 -470 { +lab=GND} +N 460 -110 460 -90 { +lab=GND} +N 460 -230 460 -170 { +lab=A0} +N 340 -110 340 -90 { +lab=GND} +N 340 -230 340 -170 { +lab=IE_0} +N 400 -110 400 -90 { +lab=GND} +N 340 -90 400 -90 { +lab=GND} +N 400 -230 400 -170 { +lab=OE_0} +N 390 -490 390 -470 { +lab=GND} +N 330 -470 390 -470 { +lab=GND} +N 390 -610 390 -550 { +lab=PU} +N 450 -490 450 -470 { +lab=GND} +N 390 -470 450 -470 { +lab=GND} +N 450 -610 450 -550 { +lab=PD} +N 510 -490 510 -470 { +lab=GND} +N 450 -470 510 -470 { +lab=GND} +N 510 -610 510 -550 { +lab=SL} +N 570 -490 570 -470 { +lab=GND} +N 510 -470 570 -470 { +lab=GND} +N 570 -610 570 -550 { +lab=CS} +N 670 -490 670 -470 { +lab=GND} +N 670 -610 670 -550 { +lab=PDRV0} +N 760 -490 760 -470 { +lab=GND} +N 700 -470 760 -470 { +lab=GND} +N 760 -610 760 -550 { +lab=PDRV1} +N 460 -90 460 -70 {lab=GND} +N 670 -470 700 -470 {lab=GND} +N 570 -470 670 -470 {lab=GND} +N 400 -90 460 -90 {lab=GND} +N 930 -110 930 -90 { +lab=GND} +N 930 -230 930 -170 { +lab=A1} +N 810 -110 810 -90 { +lab=GND} +N 810 -230 810 -170 { +lab=IE_1} +N 870 -110 870 -90 { +lab=GND} +N 810 -90 870 -90 { +lab=GND} +N 870 -230 870 -170 { +lab=OE_1} +N 930 -90 930 -70 {lab=GND} +N 870 -90 930 -90 {lab=GND} +N 1380 -110 1380 -90 { +lab=GND} +N 1380 -230 1380 -170 { +lab=PAD2} +N 1260 -110 1260 -90 { +lab=GND} +N 1260 -230 1260 -170 { +lab=IE_2} +N 1320 -110 1320 -90 { +lab=GND} +N 1260 -90 1320 -90 { +lab=GND} +N 1320 -230 1320 -170 { +lab=OE_2} +N 1380 -90 1380 -70 {lab=GND} +N 1320 -90 1380 -90 {lab=GND} +C {devices/code_shown.sym} 1050 -630 0 0 {name=s1 +only_toplevel=false +value=" +.tran 100p 100n +.save all +.control +run +display +plot A0 PAD0 Y0 +plot A1 PAD1 Y1 +plot A2 PAD2 Y2 +.endc +"} +C {devices/code_shown.sym} 1050 -800 0 0 {name=MODELS only_toplevel=true +format="tcleval( @value )" +value=" +.include $::180MCU_MODELS/design.ngspice +.lib $::180MCU_MODELS/sm141064.ngspice typical +.lib $::180MCU_MODELS/sm141064.ngspice diode_typical +.lib $::180MCU_MODELS/sm141064.ngspice res_typical +.lib $::180MCU_MODELS/sm141064.ngspice mimcap_typical +.lib $::180MCU_MODELS/sm141064.ngspice moscap_typical +"} +C {devices/code_shown.sym} 70 -770 0 0 {name=DUT only_toplevel=true +format="tcleval( @value )" +value=" +.include "/foss/designs/Chipathon2025_pads/xschem/gf180mcu_fd_io.spice" +XDUT0 A0 CS DVDD DVSS IE_0 OE_0 PAD0 PD PDRV0 PDRV1 PU SL VDD VSS Y0 gf180mcu_fd_io__bi_t +XDUT1 A1 CS DVDD DVSS IE_1 OE_1 PAD1 PD PDRV0 PDRV1 PU SL VDD VSS Y1 gf180mcu_fd_io__bi_t +XDUT2 A2 CS DVDD DVSS IE_2 OE_2 PAD2 PD PDRV0 PDRV1 PU SL VDD VSS Y2 gf180mcu_fd_io__bi_t +"} +C {devices/vsource.sym} 150 -520 0 0 {name=V1 value=5} +C {devices/gnd.sym} 150 -470 0 0 {name=l1 lab=GND} +C {devices/lab_wire.sym} 150 -590 0 0 {name=p1 sig_type=std_logic lab=DVDD} +C {devices/vsource.sym} 210 -520 0 0 {name=V2 value=5} +C {devices/lab_wire.sym} 210 -590 0 0 {name=p2 sig_type=std_logic lab=VDD} +C {devices/vsource.sym} 270 -520 0 0 {name=V3 value=0} +C {devices/lab_wire.sym} 270 -590 0 0 {name=p3 sig_type=std_logic lab=DVSS} +C {devices/vsource.sym} 330 -520 0 0 {name=V4 value=0} +C {devices/lab_wire.sym} 330 -590 0 0 {name=p4 sig_type=std_logic lab=VSS} +C {devices/vsource.sym} 460 -140 0 0 {name=V5 value="PULSE(0 5 10n 100p 100p 10n 20n)"} +C {devices/lab_wire.sym} 460 -210 0 0 {name=p5 sig_type=std_logic lab=A0} +C {devices/vsource.sym} 340 -140 0 0 {name=V7 value=5} +C {devices/lab_wire.sym} 340 -210 0 0 {name=p7 sig_type=std_logic lab=IE_0} +C {devices/vsource.sym} 400 -140 0 0 {name=V8 value=5} +C {devices/lab_wire.sym} 400 -210 0 0 {name=p8 sig_type=std_logic lab=OE_0} +C {devices/vsource.sym} 390 -520 0 0 {name=V9 value=0} +C {devices/lab_wire.sym} 390 -590 0 0 {name=p9 sig_type=std_logic lab=PU} +C {devices/vsource.sym} 450 -520 0 0 {name=V10 value=0} +C {devices/lab_wire.sym} 450 -590 0 0 {name=p10 sig_type=std_logic lab=PD} +C {devices/vsource.sym} 510 -520 0 0 {name=V11 value=0} +C {devices/lab_wire.sym} 510 -590 0 0 {name=p11 sig_type=std_logic lab=SL} +C {devices/gnd.sym} 460 -70 0 0 {name=l2 lab=GND} +C {devices/vsource.sym} 570 -520 0 0 {name=V13 value=5} +C {devices/lab_wire.sym} 570 -590 0 0 {name=p13 sig_type=std_logic lab=CS} +C {devices/vsource.sym} 670 -520 0 0 {name=V6 value=0} +C {devices/lab_wire.sym} 670 -590 0 0 {name=p6 sig_type=std_logic lab=PDRV0} +C {devices/vsource.sym} 760 -520 0 0 {name=V12 value=0} +C {devices/lab_wire.sym} 760 -590 0 0 {name=p12 sig_type=std_logic lab=PDRV1} +C {devices/vsource.sym} 930 -140 0 0 {name=V14 value="PULSE(0 5 10n 100p 100p 10n 20n)"} +C {devices/lab_wire.sym} 930 -210 0 0 {name=p14 sig_type=std_logic lab=A1} +C {devices/vsource.sym} 810 -140 0 0 {name=V15 value=0} +C {devices/lab_wire.sym} 810 -210 0 0 {name=p15 sig_type=std_logic lab=IE_1} +C {devices/vsource.sym} 870 -140 0 0 {name=V16 value=5} +C {devices/lab_wire.sym} 870 -210 0 0 {name=p16 sig_type=std_logic lab=OE_1} +C {devices/gnd.sym} 930 -70 0 0 {name=l3 lab=GND} +C {devices/vsource.sym} 1380 -140 0 0 {name=V17 value="PULSE(0 5 10n 100p 100p 10n 20n)"} +C {devices/lab_wire.sym} 1380 -210 0 0 {name=p17 sig_type=std_logic lab=PAD2} +C {devices/vsource.sym} 1260 -140 0 0 {name=V18 value=5} +C {devices/lab_wire.sym} 1260 -210 0 0 {name=p18 sig_type=std_logic lab=IE_2} +C {devices/vsource.sym} 1320 -140 0 0 {name=V19 value=0} +C {devices/lab_wire.sym} 1320 -210 0 0 {name=p19 sig_type=std_logic lab=OE_2} +C {devices/gnd.sym} 1380 -70 0 0 {name=l4 lab=GND} diff --git a/blocks/composite/regulated_cascoded_cmirror/xschem/Chipathon2025_pads/xschem/dvdd_AC_tb.sch b/blocks/composite/regulated_cascoded_cmirror/xschem/Chipathon2025_pads/xschem/dvdd_AC_tb.sch new file mode 100644 index 00000000..7ce101f9 --- /dev/null +++ b/blocks/composite/regulated_cascoded_cmirror/xschem/Chipathon2025_pads/xschem/dvdd_AC_tb.sch @@ -0,0 +1,66 @@ +v {xschem version=3.4.7 file_version=1.2} +G {} +K {} +V {} +S {} +E {} +N 60 -100 60 -60 {lab=GND} +N 160 -100 160 -60 {lab=GND} +N 260 -100 260 -60 {lab=GND} +N 360 -100 360 -60 {lab=GND} +N 60 -200 60 -160 {lab=DVDD} +N 160 -200 160 -160 {lab=VDD} +N 260 -200 260 -160 {lab=DVSS} +N 360 -200 360 -160 {lab=VSS} +N 60 -60 360 -60 {lab=GND} +N 210 -60 210 -40 {lab=GND} +N 500 -60 500 -40 { +lab=GND} +N 500 -270 500 -210 { +lab=ASIG} +N 500 -150 500 -120 { +lab=#net1} +C {vsource.sym} 60 -130 0 0 {name=V1 value=5 savecurrent=false} +C {vsource.sym} 160 -130 0 0 {name=V2 value=5 savecurrent=false} +C {vsource.sym} 260 -130 0 0 {name=V3 value=0 savecurrent=false} +C {vsource.sym} 360 -130 0 0 {name=V4 value=0 savecurrent=false} +C {lab_wire.sym} 60 -200 0 0 {name=p1 sig_type=std_logic lab=DVDD} +C {lab_wire.sym} 160 -200 0 0 {name=p2 sig_type=std_logic lab=VDD} +C {gnd.sym} 210 -40 0 0 {name=l1 lab=GND} +C {lab_wire.sym} 260 -200 0 0 {name=p3 sig_type=std_logic lab=DVSS} +C {lab_wire.sym} 360 -200 0 0 {name=p4 sig_type=std_logic lab=VSS} +C {devices/vsource.sym} 500 -90 0 0 {name=V5 value="DC 3 AC 1"} +C {devices/lab_wire.sym} 500 -250 0 0 {name=p5 sig_type=std_logic lab=ASIG} +C {devices/gnd.sym} 500 -40 0 0 {name=l2 lab=GND} +C {devices/res.sym} 500 -180 0 0 {name=R1 +value=1k +footprint=1206 +device=resistor +m=1} +C {devices/code_shown.sym} 10 -500 0 0 {name=DUT only_toplevel=true +format="tcleval( @value )" +value=" +.include "/foss/designs/Chipathon2025_pads/xschem/gf180mcu_fd_io.spice" +XDUT DVDD DVSS VSS gf180mcu_fd_io__dvdd +"} +C {devices/code_shown.sym} 610 -370 0 0 {name=MODELS only_toplevel=true +format="tcleval( @value )" +value=" +.include $::180MCU_MODELS/design.ngspice +.lib $::180MCU_MODELS/sm141064.ngspice typical +.lib $::180MCU_MODELS/sm141064.ngspice diode_typical +.lib $::180MCU_MODELS/sm141064.ngspice res_typical +.lib $::180MCU_MODELS/sm141064.ngspice moscap_typical +"} +C {devices/code_shown.sym} 620 -190 0 0 {name=s1 +only_toplevel=false +value=" +.ac dec 100 1k 100G +.save all +.control +run +display +plot PAD ASIG +plot vdb(asig) vdb(pad) +.endc +"} diff --git a/blocks/composite/regulated_cascoded_cmirror/xschem/Chipathon2025_pads/xschem/gf180mcu_fd_io.spice b/blocks/composite/regulated_cascoded_cmirror/xschem/Chipathon2025_pads/xschem/gf180mcu_fd_io.spice new file mode 100644 index 00000000..76c3056a --- /dev/null +++ b/blocks/composite/regulated_cascoded_cmirror/xschem/Chipathon2025_pads/xschem/gf180mcu_fd_io.spice @@ -0,0 +1,2669 @@ +************* +* Copied from OpenPDK Release 78b7bc32ddb4b6f14f76883c2e2dc5b5de9d1cbc +************* + +* Copyright 2022 GlobalFoundries PDK Authors +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. + +.SUBCKT gf180mcu_fd_io__asig_5p0 ASIG5V DVDD DVSS VDD VSS +D0 DVSS DVDD diode_nd2ps_06v0 m=4.0 area=40e-12 pj=82e-6 +X1 DVDD DVSS cap_nmos_06v0 m=36.0 c_length=15e-6 c_width=15e-6 +D2 DVSS ASIG5V diode_nd2ps_06v0 m=4.0 area=150e-12 pj=106e-6 +D3 ASIG5V DVDD diode_pd2nw_06v0 m=4.0 area=150e-12 pj=106e-6 +.ENDS + + +******* EOF + +* Copyright 2022 GlobalFoundries PDK Authors +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. + +.SUBCKT gf180mcu_fd_io__bi_24t A CS DVDD DVSS IE OE PAD PD PU SL VDD VSS Y +X0 n9 VDD VDD ppolyf_u r_width=800e-9 r_length=1.6e-6 m=1.0 r=907.859 par=1 +X1 n11 VDD VDD ppolyf_u r_width=800e-9 r_length=1.6e-6 m=1.0 r=907.859 par=1 +X2 DVDD DVSS cap_nmos_06v0 m=4.0 c_length=3e-6 c_width=3e-6 +X3 DVDD DVSS cap_nmos_06v0 m=8.0 c_length=1.5e-6 c_width=5e-6 +X4 n43 n32 DVSS DVSS nfet_06v0 m=1.0 w=3e-6 l=700e-9 nf=2.0 as=1.32e-12 ad=780e-15 ++ ps=7.76e-6 pd=4.04e-6 nrd=86.667e-3 nrs=146.667e-3 sa=440e-9 sb=440e-9 ++ sd=520e-9 dtemp=0.0 par=1 +X5 n56 IE VSS VSS nfet_06v0 m=1.0 w=1.5e-6 l=700e-9 nf=1.0 as=660e-15 ad=660e-15 ++ ps=3.88e-6 pd=3.88e-6 nrd=293.333e-3 nrs=293.333e-3 sa=440e-9 sb=440e-9 ++ sd=0.0 dtemp=0.0 par=1 +X6 n32 n56 DVSS DVSS nfet_06v0 m=1.0 w=3e-6 l=700e-9 nf=2.0 as=1.32e-12 ad=780e-15 ++ ps=7.76e-6 pd=4.04e-6 nrd=86.667e-3 nrs=146.667e-3 sa=440e-9 sb=440e-9 ++ sd=520e-9 dtemp=0.0 par=1 +X7 n43 n32 DVDD DVDD pfet_06v0 m=1.0 w=6e-6 l=700e-9 nf=2.0 as=2.64e-12 ad=1.56e-12 ++ ps=13.76e-6 pd=7.04e-6 nrd=43.333e-3 nrs=73.333e-3 sa=440e-9 sb=440e-9 ++ sd=520e-9 dtemp=0.0 par=1 +X8 n56 IE VDD VDD pfet_06v0 m=1.0 w=3e-6 l=700e-9 nf=1.0 as=1.32e-12 ad=1.32e-12 ++ ps=6.88e-6 pd=6.88e-6 nrd=146.667e-3 nrs=146.667e-3 sa=440e-9 sb=440e-9 ++ sd=0.0 dtemp=0.0 par=1 +X9 n32 n56 DVDD DVDD pfet_06v0 m=1.0 w=6e-6 l=700e-9 nf=2.0 as=2.64e-12 ad=1.56e-12 ++ ps=13.76e-6 pd=7.04e-6 nrd=43.333e-3 nrs=73.333e-3 sa=440e-9 sb=440e-9 ++ sd=520e-9 dtemp=0.0 par=1 +X10 n49 n33 DVSS DVSS nfet_06v0 m=1.0 w=3e-6 l=700e-9 nf=2.0 as=1.32e-12 ad=780e-15 ++ ps=7.76e-6 pd=4.04e-6 nrd=86.667e-3 nrs=146.667e-3 sa=440e-9 sb=440e-9 ++ sd=520e-9 dtemp=0.0 par=1 +X11 n64 CS VSS VSS nfet_06v0 m=1.0 w=1.5e-6 l=700e-9 nf=1.0 as=660e-15 ++ ad=660e-15 ps=3.88e-6 pd=3.88e-6 nrd=293.333e-3 nrs=293.333e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X12 n33 n64 DVSS DVSS nfet_06v0 m=1.0 w=3e-6 l=700e-9 nf=2.0 as=1.32e-12 ad=780e-15 ++ ps=7.76e-6 pd=4.04e-6 nrd=86.667e-3 nrs=146.667e-3 sa=440e-9 sb=440e-9 ++ sd=520e-9 dtemp=0.0 par=1 +X13 n49 n33 DVDD DVDD pfet_06v0 m=1.0 w=6e-6 l=700e-9 nf=2.0 as=2.64e-12 ++ ad=1.56e-12 ps=13.76e-6 pd=7.04e-6 nrd=43.333e-3 nrs=73.333e-3 sa=440e-9 ++ sb=440e-9 sd=520e-9 dtemp=0.0 par=1 +X14 n64 CS VDD VDD pfet_06v0 m=1.0 w=3e-6 l=700e-9 nf=1.0 as=1.32e-12 ++ ad=1.32e-12 ps=6.88e-6 pd=6.88e-6 nrd=146.667e-3 nrs=146.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X15 n33 n64 DVDD DVDD pfet_06v0 m=1.0 w=6e-6 l=700e-9 nf=2.0 as=2.64e-12 ++ ad=1.56e-12 ps=13.76e-6 pd=7.04e-6 nrd=43.333e-3 nrs=73.333e-3 sa=440e-9 ++ sb=440e-9 sd=520e-9 dtemp=0.0 par=1 +X16 n47 n35 DVSS DVSS nfet_06v0 m=1.0 w=3e-6 l=700e-9 nf=2.0 as=1.32e-12 ad=780e-15 ++ ps=7.76e-6 pd=4.04e-6 nrd=86.667e-3 nrs=146.667e-3 sa=440e-9 sb=440e-9 ++ sd=520e-9 dtemp=0.0 par=1 +X17 n72 n36 VSS VSS nfet_06v0 m=1.0 w=1.5e-6 l=700e-9 nf=1.0 as=660e-15 ++ ad=660e-15 ps=3.88e-6 pd=3.88e-6 nrd=293.333e-3 nrs=293.333e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X18 n35 n72 DVSS DVSS nfet_06v0 m=1.0 w=3e-6 l=700e-9 nf=2.0 as=1.32e-12 ad=780e-15 ++ ps=7.76e-6 pd=4.04e-6 nrd=86.667e-3 nrs=146.667e-3 sa=440e-9 sb=440e-9 ++ sd=520e-9 dtemp=0.0 par=1 +X19 n47 n35 DVDD DVDD pfet_06v0 m=1.0 w=6e-6 l=700e-9 nf=2.0 as=2.64e-12 ++ ad=1.56e-12 ps=13.76e-6 pd=7.04e-6 nrd=43.333e-3 nrs=73.333e-3 sa=440e-9 ++ sb=440e-9 sd=520e-9 dtemp=0.0 par=1 +X20 n72 n36 VDD VDD pfet_06v0 m=1.0 w=3e-6 l=700e-9 nf=1.0 as=1.32e-12 ++ ad=1.32e-12 ps=6.88e-6 pd=6.88e-6 nrd=146.667e-3 nrs=146.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X21 n35 n72 DVDD DVDD pfet_06v0 m=1.0 w=6e-6 l=700e-9 nf=2.0 as=2.64e-12 ++ ad=1.56e-12 ps=13.76e-6 pd=7.04e-6 nrd=43.333e-3 nrs=73.333e-3 sa=440e-9 ++ sb=440e-9 sd=520e-9 dtemp=0.0 par=1 +X22 n51 n38 DVSS DVSS nfet_06v0 m=1.0 w=3e-6 l=700e-9 nf=2.0 as=1.32e-12 ad=780e-15 ++ ps=7.76e-6 pd=4.04e-6 nrd=86.667e-3 nrs=146.667e-3 sa=440e-9 sb=440e-9 ++ sd=520e-9 dtemp=0.0 par=1 +X23 n80 n34 VSS VSS nfet_06v0 m=1.0 w=1.5e-6 l=700e-9 nf=1.0 as=660e-15 ++ ad=660e-15 ps=3.88e-6 pd=3.88e-6 nrd=293.333e-3 nrs=293.333e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X24 n38 n80 DVSS DVSS nfet_06v0 m=1.0 w=3e-6 l=700e-9 nf=2.0 as=1.32e-12 ad=780e-15 ++ ps=7.76e-6 pd=4.04e-6 nrd=86.667e-3 nrs=146.667e-3 sa=440e-9 sb=440e-9 ++ sd=520e-9 dtemp=0.0 par=1 +X25 n51 n38 DVDD DVDD pfet_06v0 m=1.0 w=6e-6 l=700e-9 nf=2.0 as=2.64e-12 ++ ad=1.56e-12 ps=13.76e-6 pd=7.04e-6 nrd=43.333e-3 nrs=73.333e-3 sa=440e-9 ++ sb=440e-9 sd=520e-9 dtemp=0.0 par=1 +X26 n80 n34 VDD VDD pfet_06v0 m=1.0 w=3e-6 l=700e-9 nf=1.0 as=1.32e-12 ++ ad=1.32e-12 ps=6.88e-6 pd=6.88e-6 nrd=146.667e-3 nrs=146.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X27 n38 n80 DVDD DVDD pfet_06v0 m=1.0 w=6e-6 l=700e-9 nf=2.0 as=2.64e-12 ++ ad=1.56e-12 ps=13.76e-6 pd=7.04e-6 nrd=43.333e-3 nrs=73.333e-3 sa=440e-9 ++ sb=440e-9 sd=520e-9 dtemp=0.0 par=1 +D28 PD VDD diode_pd2nw_06v0 m=1.0 area=1e-12 pj=4e-6 +D29 IE VDD diode_pd2nw_06v0 m=1.0 area=1e-12 pj=4e-6 +D30 CS VDD diode_pd2nw_06v0 m=1.0 area=1e-12 pj=4e-6 +D31 PU VDD diode_pd2nw_06v0 m=1.0 area=1e-12 pj=4e-6 +X32 n88 n33 DVDD DVDD pfet_06v0 m=1.0 w=8e-6 l=700e-9 nf=1.0 as=3.52e-12 ++ ad=3.52e-12 ps=16.88e-6 pd=16.88e-6 nrd=55e-3 nrs=55e-3 sa=440e-9 sb=440e-9 ++ sd=0.0 dtemp=0.0 par=1 +X33 DVDD n33 n89 DVDD pfet_06v0 m=1.0 w=3e-6 l=700e-9 nf=1.0 as=1.32e-12 ++ ad=1.32e-12 ps=6.88e-6 pd=6.88e-6 nrd=146.667e-3 nrs=146.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X34 n90 n21 DVDD DVDD pfet_06v0 m=1.0 w=3.8e-6 l=700e-9 nf=1.0 as=1.672e-12 ++ ad=1.672e-12 ps=8.48e-6 pd=8.48e-6 nrd=115.789e-3 nrs=115.789e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X35 DVSS n89 n90 DVDD pfet_06v0 m=1.0 w=3.8e-6 l=700e-9 nf=1.0 as=1.672e-12 ++ ad=1.672e-12 ps=8.48e-6 pd=8.48e-6 nrd=115.789e-3 nrs=115.789e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X36 n50 n32 DVDD DVDD pfet_06v0 m=1.0 w=6e-6 l=700e-9 nf=1.0 as=2.64e-12 ++ ad=2.64e-12 ps=12.88e-6 pd=12.88e-6 nrd=73.333e-3 nrs=73.333e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X37 n50 n88 n85 DVDD pfet_06v0 m=1.0 w=2e-6 l=700e-9 nf=1.0 as=880e-15 ad=880e-15 ++ ps=4.88e-6 pd=4.88e-6 nrd=220e-3 nrs=220e-3 sa=440e-9 sb=440e-9 sd=0.0 ++ dtemp=0.0 par=1 +X38 n50 n88 n89 DVDD pfet_06v0 m=1.0 w=2e-6 l=700e-9 nf=1.0 as=880e-15 ad=880e-15 ++ ps=4.88e-6 pd=4.88e-6 nrd=220e-3 nrs=220e-3 sa=440e-9 sb=440e-9 sd=0.0 ++ dtemp=0.0 par=1 +X39 n50 n21 n90 DVDD pfet_06v0 m=1.0 w=4.3e-6 l=700e-9 nf=1.0 as=1.892e-12 ++ ad=1.892e-12 ps=9.48e-6 pd=9.48e-6 nrd=102.326e-3 nrs=102.326e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X40 n95 n32 DVSS DVSS nfet_06v0 m=1.0 w=16e-6 l=700e-9 nf=1.0 as=7.04e-12 ++ ad=7.04e-12 ps=32.88e-6 pd=32.88e-6 nrd=27.5e-3 nrs=27.5e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X41 n87 n21 n95 DVSS nfet_06v0 m=1.0 w=10.6e-6 l=700e-9 nf=1.0 as=4.664e-12 ++ ad=4.664e-12 ps=22.08e-6 pd=22.08e-6 nrd=41.509e-3 nrs=41.509e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X42 n50 n21 n87 DVSS nfet_06v0 m=1.0 w=12e-6 l=700e-9 nf=1.0 as=5.28e-12 ++ ad=5.28e-12 ps=24.88e-6 pd=24.88e-6 nrd=36.667e-3 nrs=36.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X43 n88 n33 DVSS DVSS nfet_06v0 m=1.0 w=4e-6 l=700e-9 nf=1.0 as=1.76e-12 ++ ad=1.76e-12 ps=8.88e-6 pd=8.88e-6 nrd=110e-3 nrs=110e-3 sa=440e-9 sb=440e-9 ++ sd=0.0 dtemp=0.0 par=1 +X44 n50 n33 n85 DVSS nfet_06v0 m=1.0 w=1.5e-6 l=700e-9 nf=1.0 as=660e-15 ++ ad=660e-15 ps=3.88e-6 pd=3.88e-6 nrd=293.333e-3 nrs=293.333e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X45 n50 n33 n89 DVSS nfet_06v0 m=1.0 w=1.5e-6 l=700e-9 nf=1.0 as=660e-15 ++ ad=660e-15 ps=3.88e-6 pd=3.88e-6 nrd=293.333e-3 nrs=293.333e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X46 DVDD n85 n87 DVSS nfet_06v0 m=1.0 w=1.3e-6 l=700e-9 nf=1.0 as=572e-15 ++ ad=572e-15 ps=3.48e-6 pd=3.48e-6 nrd=338.462e-3 nrs=338.462e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X47 DVSS n88 n85 DVSS nfet_06v0 m=1.0 w=1.5e-6 l=700e-9 nf=1.0 as=660e-15 ++ ad=660e-15 ps=3.88e-6 pd=3.88e-6 nrd=293.333e-3 nrs=293.333e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X48 n103 n50 DVDD DVDD pfet_06v0 m=1.0 w=2e-6 l=700e-9 nf=1.0 as=880e-15 ad=880e-15 ++ ps=4.88e-6 pd=4.88e-6 nrd=220e-3 nrs=220e-3 sa=440e-9 sb=440e-9 sd=0.0 ++ dtemp=0.0 par=1 +X49 n100 n103 VDD VDD pfet_06v0 m=1.0 w=10e-6 l=700e-9 nf=1.0 as=4.4e-12 ++ ad=4.4e-12 ps=20.88e-6 pd=20.88e-6 nrd=44e-3 nrs=44e-3 sa=440e-9 sb=440e-9 ++ sd=0.0 dtemp=0.0 par=1 +X50 Y n100 VDD VDD pfet_06v0 m=1.0 w=21e-6 l=700e-9 nf=1.0 as=9.24e-12 ++ ad=9.24e-12 ps=42.88e-6 pd=42.88e-6 nrd=20.952e-3 nrs=20.952e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X51 n103 n50 DVSS DVSS nfet_06v0 m=1.0 w=8e-6 l=700e-9 nf=1.0 as=3.52e-12 ++ ad=3.52e-12 ps=16.88e-6 pd=16.88e-6 nrd=55e-3 nrs=55e-3 sa=440e-9 sb=440e-9 ++ sd=0.0 dtemp=0.0 par=1 +X52 Y n100 VSS VSS nfet_06v0 m=1.0 w=9e-6 l=700e-9 nf=1.0 as=3.96e-12 ++ ad=3.96e-12 ps=18.88e-6 pd=18.88e-6 nrd=48.889e-3 nrs=48.889e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X53 n100 n103 VSS VSS nfet_06v0 m=1.0 w=2.5e-6 l=700e-9 nf=1.0 as=1.1e-12 ++ ad=1.1e-12 ps=5.88e-6 pd=5.88e-6 nrd=176e-3 nrs=176e-3 sa=440e-9 sb=440e-9 ++ sd=0.0 dtemp=0.0 par=1 +X54 n36 n110 VDD VDD pfet_06v0 m=1.0 w=3e-6 l=700e-9 nf=1.0 as=1.32e-12 ++ ad=1.32e-12 ps=6.88e-6 pd=6.88e-6 nrd=146.667e-3 nrs=146.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X55 n36 PU VDD VDD pfet_06v0 m=1.0 w=3e-6 l=700e-9 nf=1.0 as=1.32e-12 ad=1.32e-12 ++ ps=6.88e-6 pd=6.88e-6 nrd=146.667e-3 nrs=146.667e-3 sa=440e-9 sb=440e-9 ++ sd=0.0 dtemp=0.0 par=1 +X56 n111 PU VSS VSS nfet_06v0 m=1.0 w=3e-6 l=700e-9 nf=1.0 as=1.32e-12 ++ ad=1.32e-12 ps=6.88e-6 pd=6.88e-6 nrd=146.667e-3 nrs=146.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X57 n36 n110 n111 VSS nfet_06v0 m=1.0 w=3e-6 l=700e-9 nf=1.0 as=1.32e-12 ++ ad=1.32e-12 ps=6.88e-6 pd=6.88e-6 nrd=146.667e-3 nrs=146.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X58 n34 PD VDD VDD pfet_06v0 m=1.0 w=3e-6 l=700e-9 nf=1.0 as=1.32e-12 ad=1.32e-12 ++ ps=6.88e-6 pd=6.88e-6 nrd=146.667e-3 nrs=146.667e-3 sa=440e-9 sb=440e-9 ++ sd=0.0 dtemp=0.0 par=1 +X59 n34 n110 VDD VDD pfet_06v0 m=1.0 w=3e-6 l=700e-9 nf=1.0 as=1.32e-12 ++ ad=1.32e-12 ps=6.88e-6 pd=6.88e-6 nrd=146.667e-3 nrs=146.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X60 n117 n110 VSS VSS nfet_06v0 m=1.0 w=3e-6 l=700e-9 nf=1.0 as=1.32e-12 ++ ad=1.32e-12 ps=6.88e-6 pd=6.88e-6 nrd=146.667e-3 nrs=146.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X61 n34 PD n117 VSS nfet_06v0 m=1.0 w=3e-6 l=700e-9 nf=1.0 as=1.32e-12 ++ ad=1.32e-12 ps=6.88e-6 pd=6.88e-6 nrd=146.667e-3 nrs=146.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X62 n123 n129 n110 VDD pfet_06v0 m=1.0 w=3e-6 l=700e-9 nf=1.0 as=1.32e-12 ++ ad=1.32e-12 ps=6.88e-6 pd=6.88e-6 nrd=146.667e-3 nrs=146.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X63 PU PD n110 VDD pfet_06v0 m=1.0 w=3e-6 l=700e-9 nf=1.0 as=1.32e-12 ++ ad=1.32e-12 ps=6.88e-6 pd=6.88e-6 nrd=146.667e-3 nrs=146.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X64 n129 PD VDD VDD pfet_06v0 m=1.0 w=3e-6 l=700e-9 nf=1.0 as=1.32e-12 ++ ad=1.32e-12 ps=6.88e-6 pd=6.88e-6 nrd=146.667e-3 nrs=146.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X65 n123 PU VDD VDD pfet_06v0 m=1.0 w=3e-6 l=700e-9 nf=1.0 as=1.32e-12 ++ ad=1.32e-12 ps=6.88e-6 pd=6.88e-6 nrd=146.667e-3 nrs=146.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X66 n123 PD n110 VSS nfet_06v0 m=1.0 w=1.5e-6 l=700e-9 nf=1.0 as=660e-15 ++ ad=660e-15 ps=3.88e-6 pd=3.88e-6 nrd=293.333e-3 nrs=293.333e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X67 PU n129 n110 VSS nfet_06v0 m=1.0 w=1.5e-6 l=700e-9 nf=1.0 as=660e-15 ++ ad=660e-15 ps=3.88e-6 pd=3.88e-6 nrd=293.333e-3 nrs=293.333e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X68 n129 PD VSS VSS nfet_06v0 m=1.0 w=1.5e-6 l=700e-9 nf=1.0 as=660e-15 ++ ad=660e-15 ps=3.88e-6 pd=3.88e-6 nrd=293.333e-3 nrs=293.333e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X69 n123 PU VSS VSS nfet_06v0 m=1.0 w=1.5e-6 l=700e-9 nf=1.0 as=660e-15 ++ ad=660e-15 ps=3.88e-6 pd=3.88e-6 nrd=293.333e-3 nrs=293.333e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X70 n21 n132 DVDD ppolyf_u r_width=800e-9 r_length=23e-6 m=1.0 r=9.94533e3 par=1 +X71 n132 n131 DVDD ppolyf_u r_width=800e-9 r_length=35.7e-6 m=1.0 r=15.3065e3 par=1 +X72 n131 n130 DVDD ppolyf_u r_width=800e-9 r_length=35.7e-6 m=1.0 r=15.3065e3 par=1 +X73 n130 n133 DVDD ppolyf_u r_width=800e-9 r_length=35.7e-6 m=1.0 r=15.3065e3 par=1 +X74 n133 n138 DVDD ppolyf_u r_width=800e-9 r_length=35.7e-6 m=1.0 r=15.3065e3 par=1 +X75 n138 n137 DVDD ppolyf_u r_width=800e-9 r_length=35.7e-6 m=1.0 r=15.3065e3 par=1 +X76 n137 n134 DVDD ppolyf_u r_width=800e-9 r_length=35.7e-6 m=1.0 r=15.3065e3 par=1 +X77 n134 n135 DVDD ppolyf_u r_width=800e-9 r_length=35.7e-6 m=1.0 r=15.3065e3 par=1 +X78 n135 n51 DVSS DVSS nfet_06v0 m=1.0 w=1.5e-6 l=700e-9 nf=1.0 as=660e-15 ++ ad=660e-15 ps=3.88e-6 pd=3.88e-6 nrd=293.333e-3 nrs=293.333e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X79 n135 n35 DVDD DVDD pfet_06v0 m=1.0 w=3e-6 l=700e-9 nf=1.0 as=1.32e-12 ++ ad=1.32e-12 ps=6.88e-6 pd=6.88e-6 nrd=146.667e-3 nrs=146.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +D80 DVSS n21 diode_nd2ps_06v0 m=2.0 area=20e-12 pj=42e-6 +D81 n21 DVDD diode_pd2nw_06v0 m=2.0 area=20e-12 pj=42e-6 +X82 PAD n21 DVDD ppolyf_u r_width=2.5e-6 r_length=2.8e-6 m=1.0 r=432.59 par=1 +X83 PAD n21 DVDD ppolyf_u r_width=2.5e-6 r_length=2.8e-6 m=1.0 r=449.157 par=1 +X84 PAD n21 DVDD ppolyf_u r_width=2.5e-6 r_length=2.8e-6 m=1.0 r=432.59 par=1 +X85 PAD n21 DVDD ppolyf_u r_width=2.5e-6 r_length=2.8e-6 m=1.0 r=449.157 par=1 +X86 n183 n191 DVSS DVSS nfet_06v0 m=1.0 w=3e-6 l=700e-9 nf=1.0 as=1.32e-12 ++ ad=1.32e-12 ps=6.88e-6 pd=6.88e-6 nrd=146.667e-3 nrs=146.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X87 n153 n183 DVSS DVSS nfet_06v0 m=1.0 w=3e-6 l=700e-9 nf=1.0 as=1.32e-12 ++ ad=1.32e-12 ps=6.88e-6 pd=6.88e-6 nrd=146.667e-3 nrs=146.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X88 n188 OE VSS VSS nfet_06v0 m=1.0 w=3e-6 l=700e-9 nf=1.0 as=1.32e-12 ++ ad=1.32e-12 ps=6.88e-6 pd=6.88e-6 nrd=146.667e-3 nrs=146.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X89 n191 A n188 VSS nfet_06v0 m=1.0 w=3e-6 l=700e-9 nf=1.0 as=1.32e-12 ++ ad=1.32e-12 ps=6.88e-6 pd=6.88e-6 nrd=146.667e-3 nrs=146.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X90 n183 n191 DVDD DVDD pfet_06v0 m=1.0 w=6e-6 l=700e-9 nf=1.0 as=2.64e-12 ++ ad=2.64e-12 ps=12.88e-6 pd=12.88e-6 nrd=73.333e-3 nrs=73.333e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X91 n153 n183 DVDD DVDD pfet_06v0 m=1.0 w=6e-6 l=700e-9 nf=1.0 as=2.64e-12 ++ ad=2.64e-12 ps=12.88e-6 pd=12.88e-6 nrd=73.333e-3 nrs=73.333e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X92 n191 OE VDD VDD pfet_06v0 m=1.0 w=3e-6 l=700e-9 nf=1.0 as=1.32e-12 ++ ad=1.32e-12 ps=6.88e-6 pd=6.88e-6 nrd=146.667e-3 nrs=146.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X93 n191 A VDD VDD pfet_06v0 m=1.0 w=3e-6 l=700e-9 nf=1.0 as=1.32e-12 ++ ad=1.32e-12 ps=6.88e-6 pd=6.88e-6 nrd=146.667e-3 nrs=146.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X94 PAD n157 DVDD DVDD pfet_06v0_dss m=1.0 w=120e-6 l=700e-9 nf=2.0 s_sab=280e-9 ++ d_sab=2.78e-6 par=1 dtemp=0.0 +X95 PAD n165 DVDD DVDD pfet_06v0_dss m=1.0 w=60e-6 l=700e-9 nf=1.0 s_sab=280e-9 ++ d_sab=2.78e-6 par=1 dtemp=0.0 +X96 PAD n172 DVSS DVSS nfet_06v0_dss m=1.0 w=37e-6 l=800e-9 nf=1.0 s_sab=280e-9 ++ d_sab=3.78e-6 par=1 dtemp=0.0 +X97 PAD n169 DVSS DVSS nfet_06v0_dss m=1.0 w=37e-6 l=800e-9 nf=1.0 s_sab=280e-9 ++ d_sab=3.78e-6 par=1 dtemp=0.0 +X98 PAD n158 DVDD DVDD pfet_06v0_dss m=1.0 w=120e-6 l=700e-9 nf=2.0 s_sab=280e-9 ++ d_sab=2.78e-6 par=1 dtemp=0.0 +X99 PAD n164 DVDD DVDD pfet_06v0_dss m=1.0 w=60e-6 l=700e-9 nf=1.0 s_sab=280e-9 ++ d_sab=2.78e-6 par=1 dtemp=0.0 +X100 PAD n173 DVSS DVSS nfet_06v0_dss m=1.0 w=37e-6 l=800e-9 nf=1.0 s_sab=280e-9 ++ d_sab=3.78e-6 par=1 dtemp=0.0 +X101 PAD n168 DVSS DVSS nfet_06v0_dss m=1.0 w=37e-6 l=800e-9 nf=1.0 s_sab=280e-9 ++ d_sab=3.78e-6 par=1 dtemp=0.0 +X102 PAD n161 DVDD DVDD pfet_06v0_dss m=1.0 w=120e-6 l=700e-9 nf=2.0 s_sab=280e-9 ++ d_sab=2.78e-6 par=1 dtemp=0.0 +X103 PAD n166 DVDD DVDD pfet_06v0_dss m=1.0 w=60e-6 l=700e-9 nf=1.0 s_sab=280e-9 ++ d_sab=2.78e-6 par=1 dtemp=0.0 +X104 PAD n171 DVSS DVSS nfet_06v0_dss m=1.0 w=37e-6 l=800e-9 nf=1.0 s_sab=280e-9 ++ d_sab=3.78e-6 par=1 dtemp=0.0 +X105 PAD n170 DVSS DVSS nfet_06v0_dss m=1.0 w=37e-6 l=800e-9 nf=1.0 s_sab=280e-9 ++ d_sab=3.78e-6 par=1 dtemp=0.0 +X106 PAD n162 DVDD DVDD pfet_06v0_dss m=1.0 w=120e-6 l=700e-9 nf=2.0 s_sab=280e-9 ++ d_sab=2.78e-6 par=1 dtemp=0.0 +X107 PAD n163 DVDD DVDD pfet_06v0_dss m=1.0 w=60e-6 l=700e-9 nf=1.0 s_sab=280e-9 ++ d_sab=2.78e-6 par=1 dtemp=0.0 +X108 PAD n174 DVSS DVSS nfet_06v0_dss m=1.0 w=37e-6 l=800e-9 nf=1.0 s_sab=280e-9 ++ d_sab=3.78e-6 par=1 dtemp=0.0 +X109 PAD n167 DVSS DVSS nfet_06v0_dss m=1.0 w=37e-6 l=800e-9 nf=1.0 s_sab=280e-9 ++ d_sab=3.78e-6 par=1 dtemp=0.0 +D110 A VDD diode_pd2nw_06v0 m=1.0 area=1e-12 pj=4e-6 +D111 SL VDD diode_pd2nw_06v0 m=1.0 area=1e-12 pj=4e-6 +X112 n159 n160 DVSS DVSS nfet_06v0 m=1.0 w=3e-6 l=700e-9 nf=2.0 as=1.32e-12 ++ ad=780e-15 ps=7.76e-6 pd=4.04e-6 nrd=86.667e-3 nrs=146.667e-3 sa=440e-9 ++ sb=440e-9 sd=520e-9 dtemp=0.0 par=1 +X113 n291 SL VSS VSS nfet_06v0 m=1.0 w=1.5e-6 l=700e-9 nf=1.0 as=660e-15 ++ ad=660e-15 ps=3.88e-6 pd=3.88e-6 nrd=293.333e-3 nrs=293.333e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X114 n160 n291 DVSS DVSS nfet_06v0 m=1.0 w=3e-6 l=700e-9 nf=2.0 as=1.32e-12 ++ ad=780e-15 ps=7.76e-6 pd=4.04e-6 nrd=86.667e-3 nrs=146.667e-3 sa=440e-9 ++ sb=440e-9 sd=520e-9 dtemp=0.0 par=1 +X115 n159 n160 DVDD DVDD pfet_06v0 m=1.0 w=6e-6 l=700e-9 nf=2.0 as=2.64e-12 ++ ad=1.56e-12 ps=13.76e-6 pd=7.04e-6 nrd=43.333e-3 nrs=73.333e-3 sa=440e-9 ++ sb=440e-9 sd=520e-9 dtemp=0.0 par=1 +X116 n291 SL VDD VDD pfet_06v0 m=1.0 w=3e-6 l=700e-9 nf=1.0 as=1.32e-12 ++ ad=1.32e-12 ps=6.88e-6 pd=6.88e-6 nrd=146.667e-3 nrs=146.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X117 n160 n291 DVDD DVDD pfet_06v0 m=1.0 w=6e-6 l=700e-9 nf=2.0 as=2.64e-12 ++ ad=1.56e-12 ps=13.76e-6 pd=7.04e-6 nrd=43.333e-3 nrs=73.333e-3 sa=440e-9 ++ sb=440e-9 sd=520e-9 dtemp=0.0 par=1 +D118 VSS n9 diode_pd2nw_06v0 m=1.0 area=230.4e-15 pj=1.92e-6 +D119 VSS OE diode_pd2nw_06v0 m=1.0 area=230.4e-15 pj=1.92e-6 +X120 n304 n9 VSS VSS nfet_06v0 m=1.0 w=3e-6 l=700e-9 nf=1.0 as=1.32e-12 ++ ad=1.32e-12 ps=6.88e-6 pd=6.88e-6 nrd=146.667e-3 nrs=146.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X121 n295 OE n304 VSS nfet_06v0 m=1.0 w=3e-6 l=700e-9 nf=1.0 as=1.32e-12 ++ ad=1.32e-12 ps=6.88e-6 pd=6.88e-6 nrd=146.667e-3 nrs=146.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X122 n156 n152 DVSS DVSS nfet_06v0 m=1.0 w=3e-6 l=700e-9 nf=1.0 as=1.32e-12 ++ ad=1.32e-12 ps=6.88e-6 pd=6.88e-6 nrd=146.667e-3 nrs=146.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X123 n152 n295 DVSS DVSS nfet_06v0 m=1.0 w=3e-6 l=700e-9 nf=1.0 as=1.32e-12 ++ ad=1.32e-12 ps=6.88e-6 pd=6.88e-6 nrd=146.667e-3 nrs=146.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X124 n295 n9 VDD VDD pfet_06v0 m=1.0 w=3e-6 l=700e-9 nf=1.0 as=1.32e-12 ++ ad=1.32e-12 ps=6.88e-6 pd=6.88e-6 nrd=146.667e-3 nrs=146.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X125 n295 OE VDD VDD pfet_06v0 m=1.0 w=3e-6 l=700e-9 nf=1.0 as=1.32e-12 ++ ad=1.32e-12 ps=6.88e-6 pd=6.88e-6 nrd=146.667e-3 nrs=146.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X126 n156 n152 DVDD DVDD pfet_06v0 m=1.0 w=6e-6 l=700e-9 nf=1.0 as=2.64e-12 ++ ad=2.64e-12 ps=12.88e-6 pd=12.88e-6 nrd=73.333e-3 nrs=73.333e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X127 n152 n295 DVDD DVDD pfet_06v0 m=1.0 w=6e-6 l=700e-9 nf=1.0 as=2.64e-12 ++ ad=2.64e-12 ps=12.88e-6 pd=12.88e-6 nrd=73.333e-3 nrs=73.333e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +D128 VSS n11 diode_pd2nw_06v0 m=1.0 area=230.4e-15 pj=1.92e-6 +D129 VSS OE diode_pd2nw_06v0 m=1.0 area=230.4e-15 pj=1.92e-6 +X130 n314 n11 VSS VSS nfet_06v0 m=1.0 w=3e-6 l=700e-9 nf=1.0 as=1.32e-12 ++ ad=1.32e-12 ps=6.88e-6 pd=6.88e-6 nrd=146.667e-3 nrs=146.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X131 n305 OE n314 VSS nfet_06v0 m=1.0 w=3e-6 l=700e-9 nf=1.0 as=1.32e-12 ++ ad=1.32e-12 ps=6.88e-6 pd=6.88e-6 nrd=146.667e-3 nrs=146.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X132 n151 n150 DVSS DVSS nfet_06v0 m=1.0 w=3e-6 l=700e-9 nf=1.0 as=1.32e-12 ++ ad=1.32e-12 ps=6.88e-6 pd=6.88e-6 nrd=146.667e-3 nrs=146.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X133 n150 n305 DVSS DVSS nfet_06v0 m=1.0 w=3e-6 l=700e-9 nf=1.0 as=1.32e-12 ++ ad=1.32e-12 ps=6.88e-6 pd=6.88e-6 nrd=146.667e-3 nrs=146.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X134 n305 n11 VDD VDD pfet_06v0 m=1.0 w=3e-6 l=700e-9 nf=1.0 as=1.32e-12 ++ ad=1.32e-12 ps=6.88e-6 pd=6.88e-6 nrd=146.667e-3 nrs=146.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X135 n305 OE VDD VDD pfet_06v0 m=1.0 w=3e-6 l=700e-9 nf=1.0 as=1.32e-12 ++ ad=1.32e-12 ps=6.88e-6 pd=6.88e-6 nrd=146.667e-3 nrs=146.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X136 n151 n150 DVDD DVDD pfet_06v0 m=1.0 w=6e-6 l=700e-9 nf=1.0 as=2.64e-12 ++ ad=2.64e-12 ps=12.88e-6 pd=12.88e-6 nrd=73.333e-3 nrs=73.333e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X137 n150 n305 DVDD DVDD pfet_06v0 m=1.0 w=6e-6 l=700e-9 nf=1.0 as=2.64e-12 ++ ad=2.64e-12 ps=12.88e-6 pd=12.88e-6 nrd=73.333e-3 nrs=73.333e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +D138 VSS VDD diode_pd2nw_06v0 m=1.0 area=230.4e-15 pj=1.92e-6 +D139 VSS OE diode_pd2nw_06v0 m=1.0 area=230.4e-15 pj=1.92e-6 +X140 n324 VDD VSS VSS nfet_06v0 m=1.0 w=3e-6 l=700e-9 nf=1.0 as=1.32e-12 ++ ad=1.32e-12 ps=6.88e-6 pd=6.88e-6 nrd=146.667e-3 nrs=146.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X141 n315 OE n324 VSS nfet_06v0 m=1.0 w=3e-6 l=700e-9 nf=1.0 as=1.32e-12 ++ ad=1.32e-12 ps=6.88e-6 pd=6.88e-6 nrd=146.667e-3 nrs=146.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X142 n148 n147 DVSS DVSS nfet_06v0 m=1.0 w=3e-6 l=700e-9 nf=1.0 as=1.32e-12 ++ ad=1.32e-12 ps=6.88e-6 pd=6.88e-6 nrd=146.667e-3 nrs=146.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X143 n147 n315 DVSS DVSS nfet_06v0 m=1.0 w=3e-6 l=700e-9 nf=1.0 as=1.32e-12 ++ ad=1.32e-12 ps=6.88e-6 pd=6.88e-6 nrd=146.667e-3 nrs=146.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X144 n315 VDD VDD VDD pfet_06v0 m=1.0 w=3e-6 l=700e-9 nf=1.0 as=1.32e-12 ++ ad=1.32e-12 ps=6.88e-6 pd=6.88e-6 nrd=146.667e-3 nrs=146.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X145 n315 OE VDD VDD pfet_06v0 m=1.0 w=3e-6 l=700e-9 nf=1.0 as=1.32e-12 ++ ad=1.32e-12 ps=6.88e-6 pd=6.88e-6 nrd=146.667e-3 nrs=146.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X146 n148 n147 DVDD DVDD pfet_06v0 m=1.0 w=6e-6 l=700e-9 nf=1.0 as=2.64e-12 ++ ad=2.64e-12 ps=12.88e-6 pd=12.88e-6 nrd=73.333e-3 nrs=73.333e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X147 n147 n315 DVDD DVDD pfet_06v0 m=1.0 w=6e-6 l=700e-9 nf=1.0 as=2.64e-12 ++ ad=2.64e-12 ps=12.88e-6 pd=12.88e-6 nrd=73.333e-3 nrs=73.333e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X148 n163 n159 n162 DVSS nfet_06v0 m=1.0 w=12e-6 l=700e-9 nf=1.0 as=5.28e-12 ++ ad=5.28e-12 ps=24.88e-6 pd=24.88e-6 nrd=36.667e-3 nrs=36.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X149 n162 DVDD n163 DVSS nfet_06v0 m=1.0 w=1.2e-6 l=700e-9 nf=1.0 as=528e-15 ++ ad=528e-15 ps=3.28e-6 pd=3.28e-6 nrd=366.667e-3 nrs=366.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X150 n167 n325 DVSS DVSS nfet_06v0 m=1.0 w=12e-6 l=700e-9 nf=1.0 as=5.28e-12 ++ ad=5.28e-12 ps=24.88e-6 pd=24.88e-6 nrd=36.667e-3 nrs=36.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X151 n174 n325 DVSS DVSS nfet_06v0 m=1.0 w=12e-6 l=700e-9 nf=1.0 as=5.28e-12 ++ ad=5.28e-12 ps=24.88e-6 pd=24.88e-6 nrd=36.667e-3 nrs=36.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X152 n163 n330 DVSS DVSS nfet_06v0 m=1.0 w=12e-6 l=700e-9 nf=1.0 as=5.28e-12 ++ ad=5.28e-12 ps=24.88e-6 pd=24.88e-6 nrd=36.667e-3 nrs=36.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X153 n330 n153 DVSS DVSS nfet_06v0 m=1.0 w=6e-6 l=700e-9 nf=1.0 as=2.64e-12 ++ ad=2.64e-12 ps=12.88e-6 pd=12.88e-6 nrd=73.333e-3 nrs=73.333e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X154 n330 n156 DVSS DVSS nfet_06v0 m=1.0 w=6e-6 l=700e-9 nf=1.0 as=2.64e-12 ++ ad=2.64e-12 ps=12.88e-6 pd=12.88e-6 nrd=73.333e-3 nrs=73.333e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X155 n325 n152 n330 DVSS nfet_06v0 m=1.0 w=6e-6 l=700e-9 nf=1.0 as=2.64e-12 ++ ad=2.64e-12 ps=12.88e-6 pd=12.88e-6 nrd=73.333e-3 nrs=73.333e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X156 n167 n160 n174 DVDD pfet_06v0 m=1.0 w=24e-6 l=700e-9 nf=1.0 as=10.56e-12 ++ ad=10.56e-12 ps=48.88e-6 pd=48.88e-6 nrd=18.333e-3 nrs=18.333e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X157 n325 n152 DVDD DVDD pfet_06v0 m=1.0 w=12e-6 l=700e-9 nf=1.0 as=5.28e-12 ++ ad=5.28e-12 ps=24.88e-6 pd=24.88e-6 nrd=36.667e-3 nrs=36.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X158 n163 n330 DVDD DVDD pfet_06v0 m=1.0 w=24e-6 l=700e-9 nf=1.0 as=10.56e-12 ++ ad=10.56e-12 ps=48.88e-6 pd=48.88e-6 nrd=18.333e-3 nrs=18.333e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X159 n174 n325 DVDD DVDD pfet_06v0 m=1.0 w=24e-6 l=700e-9 nf=1.0 as=10.56e-12 ++ ad=10.56e-12 ps=48.88e-6 pd=48.88e-6 nrd=18.333e-3 nrs=18.333e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X160 n167 DVSS n174 DVDD pfet_06v0 m=1.0 w=1.2e-6 l=700e-9 nf=1.0 as=528e-15 ++ ad=528e-15 ps=3.28e-6 pd=3.28e-6 nrd=366.667e-3 nrs=366.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X161 n325 n153 DVDD DVDD pfet_06v0 m=1.0 w=12e-6 l=700e-9 nf=1.0 as=5.28e-12 ++ ad=5.28e-12 ps=24.88e-6 pd=24.88e-6 nrd=36.667e-3 nrs=36.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X162 n330 n156 n325 DVDD pfet_06v0 m=1.0 w=12e-6 l=700e-9 nf=1.0 as=5.28e-12 ++ ad=5.28e-12 ps=24.88e-6 pd=24.88e-6 nrd=36.667e-3 nrs=36.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X163 n162 n330 DVDD DVDD pfet_06v0 m=1.0 w=24e-6 l=700e-9 nf=1.0 as=10.56e-12 ++ ad=10.56e-12 ps=48.88e-6 pd=48.88e-6 nrd=18.333e-3 nrs=18.333e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X164 n164 n159 n158 DVSS nfet_06v0 m=1.0 w=12e-6 l=700e-9 nf=1.0 as=5.28e-12 ++ ad=5.28e-12 ps=24.88e-6 pd=24.88e-6 nrd=36.667e-3 nrs=36.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X165 n158 DVDD n164 DVSS nfet_06v0 m=1.0 w=1.2e-6 l=700e-9 nf=1.0 as=528e-15 ++ ad=528e-15 ps=3.28e-6 pd=3.28e-6 nrd=366.667e-3 nrs=366.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X166 n168 n338 DVSS DVSS nfet_06v0 m=1.0 w=12e-6 l=700e-9 nf=1.0 as=5.28e-12 ++ ad=5.28e-12 ps=24.88e-6 pd=24.88e-6 nrd=36.667e-3 nrs=36.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X167 n173 n338 DVSS DVSS nfet_06v0 m=1.0 w=12e-6 l=700e-9 nf=1.0 as=5.28e-12 ++ ad=5.28e-12 ps=24.88e-6 pd=24.88e-6 nrd=36.667e-3 nrs=36.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X168 n164 n343 DVSS DVSS nfet_06v0 m=1.0 w=12e-6 l=700e-9 nf=1.0 as=5.28e-12 ++ ad=5.28e-12 ps=24.88e-6 pd=24.88e-6 nrd=36.667e-3 nrs=36.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X169 n343 n153 DVSS DVSS nfet_06v0 m=1.0 w=6e-6 l=700e-9 nf=1.0 as=2.64e-12 ++ ad=2.64e-12 ps=12.88e-6 pd=12.88e-6 nrd=73.333e-3 nrs=73.333e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X170 n343 n151 DVSS DVSS nfet_06v0 m=1.0 w=6e-6 l=700e-9 nf=1.0 as=2.64e-12 ++ ad=2.64e-12 ps=12.88e-6 pd=12.88e-6 nrd=73.333e-3 nrs=73.333e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X171 n338 n150 n343 DVSS nfet_06v0 m=1.0 w=6e-6 l=700e-9 nf=1.0 as=2.64e-12 ++ ad=2.64e-12 ps=12.88e-6 pd=12.88e-6 nrd=73.333e-3 nrs=73.333e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X172 n168 n160 n173 DVDD pfet_06v0 m=1.0 w=24e-6 l=700e-9 nf=1.0 as=10.56e-12 ++ ad=10.56e-12 ps=48.88e-6 pd=48.88e-6 nrd=18.333e-3 nrs=18.333e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X173 n338 n150 DVDD DVDD pfet_06v0 m=1.0 w=12e-6 l=700e-9 nf=1.0 as=5.28e-12 ++ ad=5.28e-12 ps=24.88e-6 pd=24.88e-6 nrd=36.667e-3 nrs=36.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X174 n164 n343 DVDD DVDD pfet_06v0 m=1.0 w=24e-6 l=700e-9 nf=1.0 as=10.56e-12 ++ ad=10.56e-12 ps=48.88e-6 pd=48.88e-6 nrd=18.333e-3 nrs=18.333e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X175 n173 n338 DVDD DVDD pfet_06v0 m=1.0 w=24e-6 l=700e-9 nf=1.0 as=10.56e-12 ++ ad=10.56e-12 ps=48.88e-6 pd=48.88e-6 nrd=18.333e-3 nrs=18.333e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X176 n168 DVSS n173 DVDD pfet_06v0 m=1.0 w=1.2e-6 l=700e-9 nf=1.0 as=528e-15 ++ ad=528e-15 ps=3.28e-6 pd=3.28e-6 nrd=366.667e-3 nrs=366.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X177 n338 n153 DVDD DVDD pfet_06v0 m=1.0 w=12e-6 l=700e-9 nf=1.0 as=5.28e-12 ++ ad=5.28e-12 ps=24.88e-6 pd=24.88e-6 nrd=36.667e-3 nrs=36.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X178 n343 n151 n338 DVDD pfet_06v0 m=1.0 w=12e-6 l=700e-9 nf=1.0 as=5.28e-12 ++ ad=5.28e-12 ps=24.88e-6 pd=24.88e-6 nrd=36.667e-3 nrs=36.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X179 n158 n343 DVDD DVDD pfet_06v0 m=1.0 w=24e-6 l=700e-9 nf=1.0 as=10.56e-12 ++ ad=10.56e-12 ps=48.88e-6 pd=48.88e-6 nrd=18.333e-3 nrs=18.333e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X180 n165 n159 n157 DVSS nfet_06v0 m=1.0 w=12e-6 l=700e-9 nf=1.0 as=5.28e-12 ++ ad=5.28e-12 ps=24.88e-6 pd=24.88e-6 nrd=36.667e-3 nrs=36.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X181 n157 DVDD n165 DVSS nfet_06v0 m=1.0 w=1.2e-6 l=700e-9 nf=1.0 as=528e-15 ++ ad=528e-15 ps=3.28e-6 pd=3.28e-6 nrd=366.667e-3 nrs=366.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X182 n169 n351 DVSS DVSS nfet_06v0 m=1.0 w=12e-6 l=700e-9 nf=1.0 as=5.28e-12 ++ ad=5.28e-12 ps=24.88e-6 pd=24.88e-6 nrd=36.667e-3 nrs=36.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X183 n172 n351 DVSS DVSS nfet_06v0 m=1.0 w=12e-6 l=700e-9 nf=1.0 as=5.28e-12 ++ ad=5.28e-12 ps=24.88e-6 pd=24.88e-6 nrd=36.667e-3 nrs=36.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X184 n165 n356 DVSS DVSS nfet_06v0 m=1.0 w=12e-6 l=700e-9 nf=1.0 as=5.28e-12 ++ ad=5.28e-12 ps=24.88e-6 pd=24.88e-6 nrd=36.667e-3 nrs=36.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X185 n356 n153 DVSS DVSS nfet_06v0 m=1.0 w=6e-6 l=700e-9 nf=1.0 as=2.64e-12 ++ ad=2.64e-12 ps=12.88e-6 pd=12.88e-6 nrd=73.333e-3 nrs=73.333e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X186 n356 n151 DVSS DVSS nfet_06v0 m=1.0 w=6e-6 l=700e-9 nf=1.0 as=2.64e-12 ++ ad=2.64e-12 ps=12.88e-6 pd=12.88e-6 nrd=73.333e-3 nrs=73.333e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X187 n351 n150 n356 DVSS nfet_06v0 m=1.0 w=6e-6 l=700e-9 nf=1.0 as=2.64e-12 ++ ad=2.64e-12 ps=12.88e-6 pd=12.88e-6 nrd=73.333e-3 nrs=73.333e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X188 n169 n160 n172 DVDD pfet_06v0 m=1.0 w=24e-6 l=700e-9 nf=1.0 as=10.56e-12 ++ ad=10.56e-12 ps=48.88e-6 pd=48.88e-6 nrd=18.333e-3 nrs=18.333e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X189 n351 n150 DVDD DVDD pfet_06v0 m=1.0 w=12e-6 l=700e-9 nf=1.0 as=5.28e-12 ++ ad=5.28e-12 ps=24.88e-6 pd=24.88e-6 nrd=36.667e-3 nrs=36.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X190 n165 n356 DVDD DVDD pfet_06v0 m=1.0 w=24e-6 l=700e-9 nf=1.0 as=10.56e-12 ++ ad=10.56e-12 ps=48.88e-6 pd=48.88e-6 nrd=18.333e-3 nrs=18.333e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X191 n172 n351 DVDD DVDD pfet_06v0 m=1.0 w=24e-6 l=700e-9 nf=1.0 as=10.56e-12 ++ ad=10.56e-12 ps=48.88e-6 pd=48.88e-6 nrd=18.333e-3 nrs=18.333e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X192 n169 DVSS n172 DVDD pfet_06v0 m=1.0 w=1.2e-6 l=700e-9 nf=1.0 as=528e-15 ++ ad=528e-15 ps=3.28e-6 pd=3.28e-6 nrd=366.667e-3 nrs=366.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X193 n351 n153 DVDD DVDD pfet_06v0 m=1.0 w=12e-6 l=700e-9 nf=1.0 as=5.28e-12 ++ ad=5.28e-12 ps=24.88e-6 pd=24.88e-6 nrd=36.667e-3 nrs=36.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X194 n356 n151 n351 DVDD pfet_06v0 m=1.0 w=12e-6 l=700e-9 nf=1.0 as=5.28e-12 ++ ad=5.28e-12 ps=24.88e-6 pd=24.88e-6 nrd=36.667e-3 nrs=36.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X195 n157 n356 DVDD DVDD pfet_06v0 m=1.0 w=24e-6 l=700e-9 nf=1.0 as=10.56e-12 ++ ad=10.56e-12 ps=48.88e-6 pd=48.88e-6 nrd=18.333e-3 nrs=18.333e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X196 n166 n159 n161 DVSS nfet_06v0 m=1.0 w=12e-6 l=700e-9 nf=1.0 as=5.28e-12 ++ ad=5.28e-12 ps=24.88e-6 pd=24.88e-6 nrd=36.667e-3 nrs=36.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X197 n161 DVDD n166 DVSS nfet_06v0 m=1.0 w=1.2e-6 l=700e-9 nf=1.0 as=528e-15 ++ ad=528e-15 ps=3.28e-6 pd=3.28e-6 nrd=366.667e-3 nrs=366.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X198 n170 n364 DVSS DVSS nfet_06v0 m=1.0 w=12e-6 l=700e-9 nf=1.0 as=5.28e-12 ++ ad=5.28e-12 ps=24.88e-6 pd=24.88e-6 nrd=36.667e-3 nrs=36.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X199 n171 n364 DVSS DVSS nfet_06v0 m=1.0 w=12e-6 l=700e-9 nf=1.0 as=5.28e-12 ++ ad=5.28e-12 ps=24.88e-6 pd=24.88e-6 nrd=36.667e-3 nrs=36.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X200 n166 n369 DVSS DVSS nfet_06v0 m=1.0 w=12e-6 l=700e-9 nf=1.0 as=5.28e-12 ++ ad=5.28e-12 ps=24.88e-6 pd=24.88e-6 nrd=36.667e-3 nrs=36.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X201 n369 n153 DVSS DVSS nfet_06v0 m=1.0 w=6e-6 l=700e-9 nf=1.0 as=2.64e-12 ++ ad=2.64e-12 ps=12.88e-6 pd=12.88e-6 nrd=73.333e-3 nrs=73.333e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X202 n369 n148 DVSS DVSS nfet_06v0 m=1.0 w=6e-6 l=700e-9 nf=1.0 as=2.64e-12 ++ ad=2.64e-12 ps=12.88e-6 pd=12.88e-6 nrd=73.333e-3 nrs=73.333e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X203 n364 n147 n369 DVSS nfet_06v0 m=1.0 w=6e-6 l=700e-9 nf=1.0 as=2.64e-12 ++ ad=2.64e-12 ps=12.88e-6 pd=12.88e-6 nrd=73.333e-3 nrs=73.333e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X204 n170 n160 n171 DVDD pfet_06v0 m=1.0 w=24e-6 l=700e-9 nf=1.0 as=10.56e-12 ++ ad=10.56e-12 ps=48.88e-6 pd=48.88e-6 nrd=18.333e-3 nrs=18.333e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X205 n364 n147 DVDD DVDD pfet_06v0 m=1.0 w=12e-6 l=700e-9 nf=1.0 as=5.28e-12 ++ ad=5.28e-12 ps=24.88e-6 pd=24.88e-6 nrd=36.667e-3 nrs=36.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X206 n166 n369 DVDD DVDD pfet_06v0 m=1.0 w=24e-6 l=700e-9 nf=1.0 as=10.56e-12 ++ ad=10.56e-12 ps=48.88e-6 pd=48.88e-6 nrd=18.333e-3 nrs=18.333e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X207 n171 n364 DVDD DVDD pfet_06v0 m=1.0 w=24e-6 l=700e-9 nf=1.0 as=10.56e-12 ++ ad=10.56e-12 ps=48.88e-6 pd=48.88e-6 nrd=18.333e-3 nrs=18.333e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X208 n170 DVSS n171 DVDD pfet_06v0 m=1.0 w=1.2e-6 l=700e-9 nf=1.0 as=528e-15 ++ ad=528e-15 ps=3.28e-6 pd=3.28e-6 nrd=366.667e-3 nrs=366.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X209 n364 n153 DVDD DVDD pfet_06v0 m=1.0 w=12e-6 l=700e-9 nf=1.0 as=5.28e-12 ++ ad=5.28e-12 ps=24.88e-6 pd=24.88e-6 nrd=36.667e-3 nrs=36.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X210 n369 n148 n364 DVDD pfet_06v0 m=1.0 w=12e-6 l=700e-9 nf=1.0 as=5.28e-12 ++ ad=5.28e-12 ps=24.88e-6 pd=24.88e-6 nrd=36.667e-3 nrs=36.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X211 n161 n369 DVDD DVDD pfet_06v0 m=1.0 w=24e-6 l=700e-9 nf=1.0 as=10.56e-12 ++ ad=10.56e-12 ps=48.88e-6 pd=48.88e-6 nrd=18.333e-3 nrs=18.333e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +.ENDS + + +******* EOF + +* Copyright 2022 GlobalFoundries PDK Authors +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. + +.SUBCKT gf180mcu_fd_io__bi_t A CS DVDD DVSS IE OE PAD PD PDRV0 PDRV1 PU SL VDD VSS Y +X0 DVDD DVSS cap_nmos_06v0 m=4.0 c_length=3e-6 c_width=3e-6 +X1 DVDD DVSS cap_nmos_06v0 m=10.0 c_length=1.5e-6 c_width=5e-6 +X2 n67 n75 DVSS DVSS nfet_06v0 m=1.0 w=3e-6 l=700e-9 nf=1.0 as=1.32e-12 ad=1.32e-12 ++ ps=6.88e-6 pd=6.88e-6 nrd=146.667e-3 nrs=146.667e-3 sa=440e-9 sb=440e-9 ++ sd=0.0 dtemp=0.0 par=1 +X3 n37 n67 DVSS DVSS nfet_06v0 m=1.0 w=3e-6 l=700e-9 nf=1.0 as=1.32e-12 ad=1.32e-12 ++ ps=6.88e-6 pd=6.88e-6 nrd=146.667e-3 nrs=146.667e-3 sa=440e-9 sb=440e-9 ++ sd=0.0 dtemp=0.0 par=1 +X4 n72 OE VSS VSS nfet_06v0 m=1.0 w=3e-6 l=700e-9 nf=1.0 as=1.32e-12 ad=1.32e-12 ++ ps=6.88e-6 pd=6.88e-6 nrd=146.667e-3 nrs=146.667e-3 sa=440e-9 sb=440e-9 ++ sd=0.0 dtemp=0.0 par=1 +X5 n75 A n72 VSS nfet_06v0 m=1.0 w=3e-6 l=700e-9 nf=1.0 as=1.32e-12 ++ ad=1.32e-12 ps=6.88e-6 pd=6.88e-6 nrd=146.667e-3 nrs=146.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X6 n67 n75 DVDD DVDD pfet_06v0 m=1.0 w=6e-6 l=700e-9 nf=1.0 as=2.64e-12 ad=2.64e-12 ++ ps=12.88e-6 pd=12.88e-6 nrd=73.333e-3 nrs=73.333e-3 sa=440e-9 sb=440e-9 ++ sd=0.0 dtemp=0.0 par=1 +X7 n37 n67 DVDD DVDD pfet_06v0 m=1.0 w=6e-6 l=700e-9 nf=1.0 as=2.64e-12 ad=2.64e-12 ++ ps=12.88e-6 pd=12.88e-6 nrd=73.333e-3 nrs=73.333e-3 sa=440e-9 sb=440e-9 ++ sd=0.0 dtemp=0.0 par=1 +X8 n75 OE VDD VDD pfet_06v0 m=1.0 w=3e-6 l=700e-9 nf=1.0 as=1.32e-12 ad=1.32e-12 ++ ps=6.88e-6 pd=6.88e-6 nrd=146.667e-3 nrs=146.667e-3 sa=440e-9 sb=440e-9 ++ sd=0.0 dtemp=0.0 par=1 +X9 n75 A VDD VDD pfet_06v0 m=1.0 w=3e-6 l=700e-9 nf=1.0 as=1.32e-12 ad=1.32e-12 ++ ps=6.88e-6 pd=6.88e-6 nrd=146.667e-3 nrs=146.667e-3 sa=440e-9 sb=440e-9 ++ sd=0.0 dtemp=0.0 par=1 +X10 PAD n43 DVDD DVDD pfet_06v0_dss m=1.0 w=80e-6 l=700e-9 nf=2.0 s_sab=280e-9 ++ d_sab=2.78e-6 par=1 dtemp=0.0 +X11 PAD n55 DVSS DVSS nfet_06v0_dss m=1.0 w=38e-6 l=1.15e-6 nf=1.0 s_sab=280e-9 ++ d_sab=3.78e-6 par=1 dtemp=0.0 +X12 PAD n52 DVSS DVSS nfet_06v0_dss m=1.0 w=38e-6 l=1.15e-6 nf=1.0 s_sab=280e-9 ++ d_sab=3.78e-6 par=1 dtemp=0.0 +X13 PAD n48 DVDD DVDD pfet_06v0_dss m=1.0 w=40e-6 l=700e-9 nf=1.0 s_sab=280e-9 ++ d_sab=2.78e-6 par=1 dtemp=0.0 +X14 PAD n42 DVDD DVDD pfet_06v0_dss m=1.0 w=80e-6 l=700e-9 nf=2.0 s_sab=280e-9 ++ d_sab=2.78e-6 par=1 dtemp=0.0 +X15 PAD n56 DVSS DVSS nfet_06v0_dss m=1.0 w=38e-6 l=1.15e-6 nf=1.0 s_sab=280e-9 ++ d_sab=3.78e-6 par=1 dtemp=0.0 +X16 PAD n51 DVSS DVSS nfet_06v0_dss m=1.0 w=38e-6 l=1.15e-6 nf=1.0 s_sab=280e-9 ++ d_sab=3.78e-6 par=1 dtemp=0.0 +X17 PAD n47 DVDD DVDD pfet_06v0_dss m=1.0 w=40e-6 l=700e-9 nf=1.0 s_sab=280e-9 ++ d_sab=2.78e-6 par=1 dtemp=0.0 +X18 PAD n44 DVDD DVDD pfet_06v0_dss m=1.0 w=80e-6 l=700e-9 nf=2.0 s_sab=280e-9 ++ d_sab=2.78e-6 par=1 dtemp=0.0 +X19 PAD n54 DVSS DVSS nfet_06v0_dss m=1.0 w=38e-6 l=1.15e-6 nf=1.0 s_sab=280e-9 ++ d_sab=3.78e-6 par=1 dtemp=0.0 +X20 PAD n53 DVSS DVSS nfet_06v0_dss m=1.0 w=38e-6 l=1.15e-6 nf=1.0 s_sab=280e-9 ++ d_sab=3.78e-6 par=1 dtemp=0.0 +X21 PAD n49 DVDD DVDD pfet_06v0_dss m=1.0 w=40e-6 l=700e-9 nf=1.0 s_sab=280e-9 ++ d_sab=2.78e-6 par=1 dtemp=0.0 +X22 PAD n45 DVDD DVDD pfet_06v0_dss m=1.0 w=80e-6 l=700e-9 nf=2.0 s_sab=280e-9 ++ d_sab=2.78e-6 par=1 dtemp=0.0 +X23 PAD n57 DVSS DVSS nfet_06v0_dss m=1.0 w=38e-6 l=1.15e-6 nf=1.0 s_sab=280e-9 ++ d_sab=3.78e-6 par=1 dtemp=0.0 +X24 PAD n50 DVSS DVSS nfet_06v0_dss m=1.0 w=38e-6 l=1.15e-6 nf=1.0 s_sab=280e-9 ++ d_sab=3.78e-6 par=1 dtemp=0.0 +X25 PAD n46 DVDD DVDD pfet_06v0_dss m=1.0 w=40e-6 l=700e-9 nf=1.0 s_sab=280e-9 ++ d_sab=2.78e-6 par=1 dtemp=0.0 +X26 n58 n41 DVSS DVSS nfet_06v0 m=1.0 w=3e-6 l=700e-9 nf=2.0 as=1.32e-12 ad=780e-15 ++ ps=7.76e-6 pd=4.04e-6 nrd=86.667e-3 nrs=146.667e-3 sa=440e-9 sb=440e-9 ++ sd=520e-9 dtemp=0.0 par=1 +X27 n175 SL VSS VSS nfet_06v0 m=1.0 w=1.5e-6 l=700e-9 nf=1.0 as=660e-15 ++ ad=660e-15 ps=3.88e-6 pd=3.88e-6 nrd=293.333e-3 nrs=293.333e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X28 n41 n175 DVSS DVSS nfet_06v0 m=1.0 w=3e-6 l=700e-9 nf=2.0 as=1.32e-12 ++ ad=780e-15 ps=7.76e-6 pd=4.04e-6 nrd=86.667e-3 nrs=146.667e-3 sa=440e-9 ++ sb=440e-9 sd=520e-9 dtemp=0.0 par=1 +X29 n58 n41 DVDD DVDD pfet_06v0 m=1.0 w=6e-6 l=700e-9 nf=2.0 as=2.64e-12 ++ ad=1.56e-12 ps=13.76e-6 pd=7.04e-6 nrd=43.333e-3 nrs=73.333e-3 sa=440e-9 ++ sb=440e-9 sd=520e-9 dtemp=0.0 par=1 +X30 n175 SL VDD VDD pfet_06v0 m=1.0 w=3e-6 l=700e-9 nf=1.0 as=1.32e-12 ++ ad=1.32e-12 ps=6.88e-6 pd=6.88e-6 nrd=146.667e-3 nrs=146.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X31 n41 n175 DVDD DVDD pfet_06v0 m=1.0 w=6e-6 l=700e-9 nf=2.0 as=2.64e-12 ++ ad=1.56e-12 ps=13.76e-6 pd=7.04e-6 nrd=43.333e-3 nrs=73.333e-3 sa=440e-9 ++ sb=440e-9 sd=520e-9 dtemp=0.0 par=1 +D32 A VDD diode_pd2nw_06v0 m=1.0 area=1e-12 pj=4e-6 +D33 SL VDD diode_pd2nw_06v0 m=1.0 area=1e-12 pj=4e-6 +D34 VSS PDRV0 diode_pd2nw_06v0 m=1.0 area=230.4e-15 pj=1.92e-6 +D35 VSS OE diode_pd2nw_06v0 m=1.0 area=230.4e-15 pj=1.92e-6 +X36 n188 PDRV0 VSS VSS nfet_06v0 m=1.0 w=3e-6 l=700e-9 nf=1.0 as=1.32e-12 ++ ad=1.32e-12 ps=6.88e-6 pd=6.88e-6 nrd=146.667e-3 nrs=146.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X37 n179 OE n188 VSS nfet_06v0 m=1.0 w=3e-6 l=700e-9 nf=1.0 as=1.32e-12 ++ ad=1.32e-12 ps=6.88e-6 pd=6.88e-6 nrd=146.667e-3 nrs=146.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X38 n39 n36 DVSS DVSS nfet_06v0 m=1.0 w=3e-6 l=700e-9 nf=1.0 as=1.32e-12 ++ ad=1.32e-12 ps=6.88e-6 pd=6.88e-6 nrd=146.667e-3 nrs=146.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X39 n36 n179 DVSS DVSS nfet_06v0 m=1.0 w=3e-6 l=700e-9 nf=1.0 as=1.32e-12 ++ ad=1.32e-12 ps=6.88e-6 pd=6.88e-6 nrd=146.667e-3 nrs=146.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X40 n179 PDRV0 VDD VDD pfet_06v0 m=1.0 w=3e-6 l=700e-9 nf=1.0 as=1.32e-12 ++ ad=1.32e-12 ps=6.88e-6 pd=6.88e-6 nrd=146.667e-3 nrs=146.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X41 n179 OE VDD VDD pfet_06v0 m=1.0 w=3e-6 l=700e-9 nf=1.0 as=1.32e-12 ++ ad=1.32e-12 ps=6.88e-6 pd=6.88e-6 nrd=146.667e-3 nrs=146.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X42 n39 n36 DVDD DVDD pfet_06v0 m=1.0 w=6e-6 l=700e-9 nf=1.0 as=2.64e-12 ++ ad=2.64e-12 ps=12.88e-6 pd=12.88e-6 nrd=73.333e-3 nrs=73.333e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X43 n36 n179 DVDD DVDD pfet_06v0 m=1.0 w=6e-6 l=700e-9 nf=1.0 as=2.64e-12 ++ ad=2.64e-12 ps=12.88e-6 pd=12.88e-6 nrd=73.333e-3 nrs=73.333e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +D44 VSS PDRV1 diode_pd2nw_06v0 m=1.0 area=230.4e-15 pj=1.92e-6 +D45 VSS OE diode_pd2nw_06v0 m=1.0 area=230.4e-15 pj=1.92e-6 +X46 n198 PDRV1 VSS VSS nfet_06v0 m=1.0 w=3e-6 l=700e-9 nf=1.0 as=1.32e-12 ++ ad=1.32e-12 ps=6.88e-6 pd=6.88e-6 nrd=146.667e-3 nrs=146.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X47 n189 OE n198 VSS nfet_06v0 m=1.0 w=3e-6 l=700e-9 nf=1.0 as=1.32e-12 ++ ad=1.32e-12 ps=6.88e-6 pd=6.88e-6 nrd=146.667e-3 nrs=146.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X48 n35 n33 DVSS DVSS nfet_06v0 m=1.0 w=3e-6 l=700e-9 nf=1.0 as=1.32e-12 ++ ad=1.32e-12 ps=6.88e-6 pd=6.88e-6 nrd=146.667e-3 nrs=146.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X49 n33 n189 DVSS DVSS nfet_06v0 m=1.0 w=3e-6 l=700e-9 nf=1.0 as=1.32e-12 ++ ad=1.32e-12 ps=6.88e-6 pd=6.88e-6 nrd=146.667e-3 nrs=146.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X50 n189 PDRV1 VDD VDD pfet_06v0 m=1.0 w=3e-6 l=700e-9 nf=1.0 as=1.32e-12 ++ ad=1.32e-12 ps=6.88e-6 pd=6.88e-6 nrd=146.667e-3 nrs=146.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X51 n189 OE VDD VDD pfet_06v0 m=1.0 w=3e-6 l=700e-9 nf=1.0 as=1.32e-12 ++ ad=1.32e-12 ps=6.88e-6 pd=6.88e-6 nrd=146.667e-3 nrs=146.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X52 n35 n33 DVDD DVDD pfet_06v0 m=1.0 w=6e-6 l=700e-9 nf=1.0 as=2.64e-12 ++ ad=2.64e-12 ps=12.88e-6 pd=12.88e-6 nrd=73.333e-3 nrs=73.333e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X53 n33 n189 DVDD DVDD pfet_06v0 m=1.0 w=6e-6 l=700e-9 nf=1.0 as=2.64e-12 ++ ad=2.64e-12 ps=12.88e-6 pd=12.88e-6 nrd=73.333e-3 nrs=73.333e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +D54 VSS VDD diode_pd2nw_06v0 m=1.0 area=230.4e-15 pj=1.92e-6 +D55 VSS OE diode_pd2nw_06v0 m=1.0 area=230.4e-15 pj=1.92e-6 +X56 n208 VDD VSS VSS nfet_06v0 m=1.0 w=3e-6 l=700e-9 nf=1.0 as=1.32e-12 ++ ad=1.32e-12 ps=6.88e-6 pd=6.88e-6 nrd=146.667e-3 nrs=146.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X57 n199 OE n208 VSS nfet_06v0 m=1.0 w=3e-6 l=700e-9 nf=1.0 as=1.32e-12 ++ ad=1.32e-12 ps=6.88e-6 pd=6.88e-6 nrd=146.667e-3 nrs=146.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X58 n32 n31 DVSS DVSS nfet_06v0 m=1.0 w=3e-6 l=700e-9 nf=1.0 as=1.32e-12 ++ ad=1.32e-12 ps=6.88e-6 pd=6.88e-6 nrd=146.667e-3 nrs=146.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X59 n31 n199 DVSS DVSS nfet_06v0 m=1.0 w=3e-6 l=700e-9 nf=1.0 as=1.32e-12 ++ ad=1.32e-12 ps=6.88e-6 pd=6.88e-6 nrd=146.667e-3 nrs=146.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X60 n199 VDD VDD VDD pfet_06v0 m=1.0 w=3e-6 l=700e-9 nf=1.0 as=1.32e-12 ++ ad=1.32e-12 ps=6.88e-6 pd=6.88e-6 nrd=146.667e-3 nrs=146.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X61 n199 OE VDD VDD pfet_06v0 m=1.0 w=3e-6 l=700e-9 nf=1.0 as=1.32e-12 ++ ad=1.32e-12 ps=6.88e-6 pd=6.88e-6 nrd=146.667e-3 nrs=146.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X62 n32 n31 DVDD DVDD pfet_06v0 m=1.0 w=6e-6 l=700e-9 nf=1.0 as=2.64e-12 ++ ad=2.64e-12 ps=12.88e-6 pd=12.88e-6 nrd=73.333e-3 nrs=73.333e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X63 n31 n199 DVDD DVDD pfet_06v0 m=1.0 w=6e-6 l=700e-9 nf=1.0 as=2.64e-12 ++ ad=2.64e-12 ps=12.88e-6 pd=12.88e-6 nrd=73.333e-3 nrs=73.333e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X64 n46 n58 n45 DVSS nfet_06v0 m=1.0 w=12e-6 l=700e-9 nf=1.0 as=5.28e-12 ++ ad=5.28e-12 ps=24.88e-6 pd=24.88e-6 nrd=36.667e-3 nrs=36.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X65 n45 DVDD n46 DVSS nfet_06v0 m=1.0 w=1.2e-6 l=700e-9 nf=1.0 as=528e-15 ++ ad=528e-15 ps=3.28e-6 pd=3.28e-6 nrd=366.667e-3 nrs=366.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X66 n50 n209 DVSS DVSS nfet_06v0 m=1.0 w=12e-6 l=700e-9 nf=1.0 as=5.28e-12 ++ ad=5.28e-12 ps=24.88e-6 pd=24.88e-6 nrd=36.667e-3 nrs=36.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X67 n57 n209 DVSS DVSS nfet_06v0 m=1.0 w=12e-6 l=700e-9 nf=1.0 as=5.28e-12 ++ ad=5.28e-12 ps=24.88e-6 pd=24.88e-6 nrd=36.667e-3 nrs=36.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X68 n46 n214 DVSS DVSS nfet_06v0 m=1.0 w=12e-6 l=700e-9 nf=1.0 as=5.28e-12 ++ ad=5.28e-12 ps=24.88e-6 pd=24.88e-6 nrd=36.667e-3 nrs=36.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X69 n214 n37 DVSS DVSS nfet_06v0 m=1.0 w=6e-6 l=700e-9 nf=1.0 as=2.64e-12 ++ ad=2.64e-12 ps=12.88e-6 pd=12.88e-6 nrd=73.333e-3 nrs=73.333e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X70 n214 n39 DVSS DVSS nfet_06v0 m=1.0 w=6e-6 l=700e-9 nf=1.0 as=2.64e-12 ++ ad=2.64e-12 ps=12.88e-6 pd=12.88e-6 nrd=73.333e-3 nrs=73.333e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X71 n209 n36 n214 DVSS nfet_06v0 m=1.0 w=6e-6 l=700e-9 nf=1.0 as=2.64e-12 ++ ad=2.64e-12 ps=12.88e-6 pd=12.88e-6 nrd=73.333e-3 nrs=73.333e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X72 n50 n41 n57 DVDD pfet_06v0 m=1.0 w=24e-6 l=700e-9 nf=1.0 as=10.56e-12 ++ ad=10.56e-12 ps=48.88e-6 pd=48.88e-6 nrd=18.333e-3 nrs=18.333e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X73 n209 n36 DVDD DVDD pfet_06v0 m=1.0 w=12e-6 l=700e-9 nf=1.0 as=5.28e-12 ++ ad=5.28e-12 ps=24.88e-6 pd=24.88e-6 nrd=36.667e-3 nrs=36.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X74 n46 n214 DVDD DVDD pfet_06v0 m=1.0 w=24e-6 l=700e-9 nf=1.0 as=10.56e-12 ++ ad=10.56e-12 ps=48.88e-6 pd=48.88e-6 nrd=18.333e-3 nrs=18.333e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X75 n57 n209 DVDD DVDD pfet_06v0 m=1.0 w=24e-6 l=700e-9 nf=1.0 as=10.56e-12 ++ ad=10.56e-12 ps=48.88e-6 pd=48.88e-6 nrd=18.333e-3 nrs=18.333e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X76 n50 DVSS n57 DVDD pfet_06v0 m=1.0 w=1.2e-6 l=700e-9 nf=1.0 as=528e-15 ++ ad=528e-15 ps=3.28e-6 pd=3.28e-6 nrd=366.667e-3 nrs=366.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X77 n209 n37 DVDD DVDD pfet_06v0 m=1.0 w=12e-6 l=700e-9 nf=1.0 as=5.28e-12 ++ ad=5.28e-12 ps=24.88e-6 pd=24.88e-6 nrd=36.667e-3 nrs=36.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X78 n214 n39 n209 DVDD pfet_06v0 m=1.0 w=12e-6 l=700e-9 nf=1.0 as=5.28e-12 ++ ad=5.28e-12 ps=24.88e-6 pd=24.88e-6 nrd=36.667e-3 nrs=36.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X79 n45 n214 DVDD DVDD pfet_06v0 m=1.0 w=24e-6 l=700e-9 nf=1.0 as=10.56e-12 ++ ad=10.56e-12 ps=48.88e-6 pd=48.88e-6 nrd=18.333e-3 nrs=18.333e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X80 n47 n58 n42 DVSS nfet_06v0 m=1.0 w=12e-6 l=700e-9 nf=1.0 as=5.28e-12 ++ ad=5.28e-12 ps=24.88e-6 pd=24.88e-6 nrd=36.667e-3 nrs=36.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X81 n42 DVDD n47 DVSS nfet_06v0 m=1.0 w=1.2e-6 l=700e-9 nf=1.0 as=528e-15 ++ ad=528e-15 ps=3.28e-6 pd=3.28e-6 nrd=366.667e-3 nrs=366.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X82 n51 n222 DVSS DVSS nfet_06v0 m=1.0 w=12e-6 l=700e-9 nf=1.0 as=5.28e-12 ++ ad=5.28e-12 ps=24.88e-6 pd=24.88e-6 nrd=36.667e-3 nrs=36.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X83 n56 n222 DVSS DVSS nfet_06v0 m=1.0 w=12e-6 l=700e-9 nf=1.0 as=5.28e-12 ++ ad=5.28e-12 ps=24.88e-6 pd=24.88e-6 nrd=36.667e-3 nrs=36.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X84 n47 n227 DVSS DVSS nfet_06v0 m=1.0 w=12e-6 l=700e-9 nf=1.0 as=5.28e-12 ++ ad=5.28e-12 ps=24.88e-6 pd=24.88e-6 nrd=36.667e-3 nrs=36.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X85 n227 n37 DVSS DVSS nfet_06v0 m=1.0 w=6e-6 l=700e-9 nf=1.0 as=2.64e-12 ++ ad=2.64e-12 ps=12.88e-6 pd=12.88e-6 nrd=73.333e-3 nrs=73.333e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X86 n227 n35 DVSS DVSS nfet_06v0 m=1.0 w=6e-6 l=700e-9 nf=1.0 as=2.64e-12 ++ ad=2.64e-12 ps=12.88e-6 pd=12.88e-6 nrd=73.333e-3 nrs=73.333e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X87 n222 n33 n227 DVSS nfet_06v0 m=1.0 w=6e-6 l=700e-9 nf=1.0 as=2.64e-12 ++ ad=2.64e-12 ps=12.88e-6 pd=12.88e-6 nrd=73.333e-3 nrs=73.333e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X88 n51 n41 n56 DVDD pfet_06v0 m=1.0 w=24e-6 l=700e-9 nf=1.0 as=10.56e-12 ++ ad=10.56e-12 ps=48.88e-6 pd=48.88e-6 nrd=18.333e-3 nrs=18.333e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X89 n222 n33 DVDD DVDD pfet_06v0 m=1.0 w=12e-6 l=700e-9 nf=1.0 as=5.28e-12 ++ ad=5.28e-12 ps=24.88e-6 pd=24.88e-6 nrd=36.667e-3 nrs=36.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X90 n47 n227 DVDD DVDD pfet_06v0 m=1.0 w=24e-6 l=700e-9 nf=1.0 as=10.56e-12 ++ ad=10.56e-12 ps=48.88e-6 pd=48.88e-6 nrd=18.333e-3 nrs=18.333e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X91 n56 n222 DVDD DVDD pfet_06v0 m=1.0 w=24e-6 l=700e-9 nf=1.0 as=10.56e-12 ++ ad=10.56e-12 ps=48.88e-6 pd=48.88e-6 nrd=18.333e-3 nrs=18.333e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X92 n51 DVSS n56 DVDD pfet_06v0 m=1.0 w=1.2e-6 l=700e-9 nf=1.0 as=528e-15 ++ ad=528e-15 ps=3.28e-6 pd=3.28e-6 nrd=366.667e-3 nrs=366.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X93 n222 n37 DVDD DVDD pfet_06v0 m=1.0 w=12e-6 l=700e-9 nf=1.0 as=5.28e-12 ++ ad=5.28e-12 ps=24.88e-6 pd=24.88e-6 nrd=36.667e-3 nrs=36.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X94 n227 n35 n222 DVDD pfet_06v0 m=1.0 w=12e-6 l=700e-9 nf=1.0 as=5.28e-12 ++ ad=5.28e-12 ps=24.88e-6 pd=24.88e-6 nrd=36.667e-3 nrs=36.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X95 n42 n227 DVDD DVDD pfet_06v0 m=1.0 w=24e-6 l=700e-9 nf=1.0 as=10.56e-12 ++ ad=10.56e-12 ps=48.88e-6 pd=48.88e-6 nrd=18.333e-3 nrs=18.333e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X96 n48 n58 n43 DVSS nfet_06v0 m=1.0 w=12e-6 l=700e-9 nf=1.0 as=5.28e-12 ++ ad=5.28e-12 ps=24.88e-6 pd=24.88e-6 nrd=36.667e-3 nrs=36.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X97 n43 DVDD n48 DVSS nfet_06v0 m=1.0 w=1.2e-6 l=700e-9 nf=1.0 as=528e-15 ++ ad=528e-15 ps=3.28e-6 pd=3.28e-6 nrd=366.667e-3 nrs=366.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X98 n52 n235 DVSS DVSS nfet_06v0 m=1.0 w=12e-6 l=700e-9 nf=1.0 as=5.28e-12 ++ ad=5.28e-12 ps=24.88e-6 pd=24.88e-6 nrd=36.667e-3 nrs=36.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X99 n55 n235 DVSS DVSS nfet_06v0 m=1.0 w=12e-6 l=700e-9 nf=1.0 as=5.28e-12 ++ ad=5.28e-12 ps=24.88e-6 pd=24.88e-6 nrd=36.667e-3 nrs=36.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X100 n48 n240 DVSS DVSS nfet_06v0 m=1.0 w=12e-6 l=700e-9 nf=1.0 as=5.28e-12 ++ ad=5.28e-12 ps=24.88e-6 pd=24.88e-6 nrd=36.667e-3 nrs=36.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X101 n240 n37 DVSS DVSS nfet_06v0 m=1.0 w=6e-6 l=700e-9 nf=1.0 as=2.64e-12 ++ ad=2.64e-12 ps=12.88e-6 pd=12.88e-6 nrd=73.333e-3 nrs=73.333e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X102 n240 n35 DVSS DVSS nfet_06v0 m=1.0 w=6e-6 l=700e-9 nf=1.0 as=2.64e-12 ++ ad=2.64e-12 ps=12.88e-6 pd=12.88e-6 nrd=73.333e-3 nrs=73.333e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X103 n235 n33 n240 DVSS nfet_06v0 m=1.0 w=6e-6 l=700e-9 nf=1.0 as=2.64e-12 ++ ad=2.64e-12 ps=12.88e-6 pd=12.88e-6 nrd=73.333e-3 nrs=73.333e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X104 n52 n41 n55 DVDD pfet_06v0 m=1.0 w=24e-6 l=700e-9 nf=1.0 as=10.56e-12 ++ ad=10.56e-12 ps=48.88e-6 pd=48.88e-6 nrd=18.333e-3 nrs=18.333e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X105 n235 n33 DVDD DVDD pfet_06v0 m=1.0 w=12e-6 l=700e-9 nf=1.0 as=5.28e-12 ++ ad=5.28e-12 ps=24.88e-6 pd=24.88e-6 nrd=36.667e-3 nrs=36.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X106 n48 n240 DVDD DVDD pfet_06v0 m=1.0 w=24e-6 l=700e-9 nf=1.0 as=10.56e-12 ++ ad=10.56e-12 ps=48.88e-6 pd=48.88e-6 nrd=18.333e-3 nrs=18.333e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X107 n55 n235 DVDD DVDD pfet_06v0 m=1.0 w=24e-6 l=700e-9 nf=1.0 as=10.56e-12 ++ ad=10.56e-12 ps=48.88e-6 pd=48.88e-6 nrd=18.333e-3 nrs=18.333e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X108 n52 DVSS n55 DVDD pfet_06v0 m=1.0 w=1.2e-6 l=700e-9 nf=1.0 as=528e-15 ++ ad=528e-15 ps=3.28e-6 pd=3.28e-6 nrd=366.667e-3 nrs=366.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X109 n235 n37 DVDD DVDD pfet_06v0 m=1.0 w=12e-6 l=700e-9 nf=1.0 as=5.28e-12 ++ ad=5.28e-12 ps=24.88e-6 pd=24.88e-6 nrd=36.667e-3 nrs=36.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X110 n240 n35 n235 DVDD pfet_06v0 m=1.0 w=12e-6 l=700e-9 nf=1.0 as=5.28e-12 ++ ad=5.28e-12 ps=24.88e-6 pd=24.88e-6 nrd=36.667e-3 nrs=36.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X111 n43 n240 DVDD DVDD pfet_06v0 m=1.0 w=24e-6 l=700e-9 nf=1.0 as=10.56e-12 ++ ad=10.56e-12 ps=48.88e-6 pd=48.88e-6 nrd=18.333e-3 nrs=18.333e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X112 n49 n58 n44 DVSS nfet_06v0 m=1.0 w=12e-6 l=700e-9 nf=1.0 as=5.28e-12 ++ ad=5.28e-12 ps=24.88e-6 pd=24.88e-6 nrd=36.667e-3 nrs=36.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X113 n44 DVDD n49 DVSS nfet_06v0 m=1.0 w=1.2e-6 l=700e-9 nf=1.0 as=528e-15 ++ ad=528e-15 ps=3.28e-6 pd=3.28e-6 nrd=366.667e-3 nrs=366.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X114 n53 n248 DVSS DVSS nfet_06v0 m=1.0 w=12e-6 l=700e-9 nf=1.0 as=5.28e-12 ++ ad=5.28e-12 ps=24.88e-6 pd=24.88e-6 nrd=36.667e-3 nrs=36.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X115 n54 n248 DVSS DVSS nfet_06v0 m=1.0 w=12e-6 l=700e-9 nf=1.0 as=5.28e-12 ++ ad=5.28e-12 ps=24.88e-6 pd=24.88e-6 nrd=36.667e-3 nrs=36.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X116 n49 n253 DVSS DVSS nfet_06v0 m=1.0 w=12e-6 l=700e-9 nf=1.0 as=5.28e-12 ++ ad=5.28e-12 ps=24.88e-6 pd=24.88e-6 nrd=36.667e-3 nrs=36.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X117 n253 n37 DVSS DVSS nfet_06v0 m=1.0 w=6e-6 l=700e-9 nf=1.0 as=2.64e-12 ++ ad=2.64e-12 ps=12.88e-6 pd=12.88e-6 nrd=73.333e-3 nrs=73.333e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X118 n253 n32 DVSS DVSS nfet_06v0 m=1.0 w=6e-6 l=700e-9 nf=1.0 as=2.64e-12 ++ ad=2.64e-12 ps=12.88e-6 pd=12.88e-6 nrd=73.333e-3 nrs=73.333e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X119 n248 n31 n253 DVSS nfet_06v0 m=1.0 w=6e-6 l=700e-9 nf=1.0 as=2.64e-12 ++ ad=2.64e-12 ps=12.88e-6 pd=12.88e-6 nrd=73.333e-3 nrs=73.333e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X120 n53 n41 n54 DVDD pfet_06v0 m=1.0 w=24e-6 l=700e-9 nf=1.0 as=10.56e-12 ++ ad=10.56e-12 ps=48.88e-6 pd=48.88e-6 nrd=18.333e-3 nrs=18.333e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X121 n248 n31 DVDD DVDD pfet_06v0 m=1.0 w=12e-6 l=700e-9 nf=1.0 as=5.28e-12 ++ ad=5.28e-12 ps=24.88e-6 pd=24.88e-6 nrd=36.667e-3 nrs=36.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X122 n49 n253 DVDD DVDD pfet_06v0 m=1.0 w=24e-6 l=700e-9 nf=1.0 as=10.56e-12 ++ ad=10.56e-12 ps=48.88e-6 pd=48.88e-6 nrd=18.333e-3 nrs=18.333e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X123 n54 n248 DVDD DVDD pfet_06v0 m=1.0 w=24e-6 l=700e-9 nf=1.0 as=10.56e-12 ++ ad=10.56e-12 ps=48.88e-6 pd=48.88e-6 nrd=18.333e-3 nrs=18.333e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X124 n53 DVSS n54 DVDD pfet_06v0 m=1.0 w=1.2e-6 l=700e-9 nf=1.0 as=528e-15 ++ ad=528e-15 ps=3.28e-6 pd=3.28e-6 nrd=366.667e-3 nrs=366.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X125 n248 n37 DVDD DVDD pfet_06v0 m=1.0 w=12e-6 l=700e-9 nf=1.0 as=5.28e-12 ++ ad=5.28e-12 ps=24.88e-6 pd=24.88e-6 nrd=36.667e-3 nrs=36.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X126 n253 n32 n248 DVDD pfet_06v0 m=1.0 w=12e-6 l=700e-9 nf=1.0 as=5.28e-12 ++ ad=5.28e-12 ps=24.88e-6 pd=24.88e-6 nrd=36.667e-3 nrs=36.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X127 n44 n253 DVDD DVDD pfet_06v0 m=1.0 w=24e-6 l=700e-9 nf=1.0 as=10.56e-12 ++ ad=10.56e-12 ps=48.88e-6 pd=48.88e-6 nrd=18.333e-3 nrs=18.333e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X128 n273 n262 DVSS DVSS nfet_06v0 m=1.0 w=3e-6 l=700e-9 nf=2.0 as=1.32e-12 ++ ad=780e-15 ps=7.76e-6 pd=4.04e-6 nrd=86.667e-3 nrs=146.667e-3 sa=440e-9 ++ sb=440e-9 sd=520e-9 dtemp=0.0 par=1 +X129 n286 IE VSS VSS nfet_06v0 m=1.0 w=1.5e-6 l=700e-9 nf=1.0 as=660e-15 ++ ad=660e-15 ps=3.88e-6 pd=3.88e-6 nrd=293.333e-3 nrs=293.333e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X130 n262 n286 DVSS DVSS nfet_06v0 m=1.0 w=3e-6 l=700e-9 nf=2.0 as=1.32e-12 ++ ad=780e-15 ps=7.76e-6 pd=4.04e-6 nrd=86.667e-3 nrs=146.667e-3 sa=440e-9 ++ sb=440e-9 sd=520e-9 dtemp=0.0 par=1 +X131 n273 n262 DVDD DVDD pfet_06v0 m=1.0 w=6e-6 l=700e-9 nf=2.0 as=2.64e-12 ++ ad=1.56e-12 ps=13.76e-6 pd=7.04e-6 nrd=43.333e-3 nrs=73.333e-3 sa=440e-9 ++ sb=440e-9 sd=520e-9 dtemp=0.0 par=1 +X132 n286 IE VDD VDD pfet_06v0 m=1.0 w=3e-6 l=700e-9 nf=1.0 as=1.32e-12 ++ ad=1.32e-12 ps=6.88e-6 pd=6.88e-6 nrd=146.667e-3 nrs=146.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X133 n262 n286 DVDD DVDD pfet_06v0 m=1.0 w=6e-6 l=700e-9 nf=2.0 as=2.64e-12 ++ ad=1.56e-12 ps=13.76e-6 pd=7.04e-6 nrd=43.333e-3 nrs=73.333e-3 sa=440e-9 ++ sb=440e-9 sd=520e-9 dtemp=0.0 par=1 +X134 n279 n263 DVSS DVSS nfet_06v0 m=1.0 w=3e-6 l=700e-9 nf=2.0 as=1.32e-12 ++ ad=780e-15 ps=7.76e-6 pd=4.04e-6 nrd=86.667e-3 nrs=146.667e-3 sa=440e-9 ++ sb=440e-9 sd=520e-9 dtemp=0.0 par=1 +X135 n294 CS VSS VSS nfet_06v0 m=1.0 w=1.5e-6 l=700e-9 nf=1.0 as=660e-15 ++ ad=660e-15 ps=3.88e-6 pd=3.88e-6 nrd=293.333e-3 nrs=293.333e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X136 n263 n294 DVSS DVSS nfet_06v0 m=1.0 w=3e-6 l=700e-9 nf=2.0 as=1.32e-12 ++ ad=780e-15 ps=7.76e-6 pd=4.04e-6 nrd=86.667e-3 nrs=146.667e-3 sa=440e-9 ++ sb=440e-9 sd=520e-9 dtemp=0.0 par=1 +X137 n279 n263 DVDD DVDD pfet_06v0 m=1.0 w=6e-6 l=700e-9 nf=2.0 as=2.64e-12 ++ ad=1.56e-12 ps=13.76e-6 pd=7.04e-6 nrd=43.333e-3 nrs=73.333e-3 sa=440e-9 ++ sb=440e-9 sd=520e-9 dtemp=0.0 par=1 +X138 n294 CS VDD VDD pfet_06v0 m=1.0 w=3e-6 l=700e-9 nf=1.0 as=1.32e-12 ++ ad=1.32e-12 ps=6.88e-6 pd=6.88e-6 nrd=146.667e-3 nrs=146.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X139 n263 n294 DVDD DVDD pfet_06v0 m=1.0 w=6e-6 l=700e-9 nf=2.0 as=2.64e-12 ++ ad=1.56e-12 ps=13.76e-6 pd=7.04e-6 nrd=43.333e-3 nrs=73.333e-3 sa=440e-9 ++ sb=440e-9 sd=520e-9 dtemp=0.0 par=1 +X140 n277 n265 DVSS DVSS nfet_06v0 m=1.0 w=3e-6 l=700e-9 nf=2.0 as=1.32e-12 ++ ad=780e-15 ps=7.76e-6 pd=4.04e-6 nrd=86.667e-3 nrs=146.667e-3 sa=440e-9 ++ sb=440e-9 sd=520e-9 dtemp=0.0 par=1 +X141 n302 n266 VSS VSS nfet_06v0 m=1.0 w=1.5e-6 l=700e-9 nf=1.0 as=660e-15 ++ ad=660e-15 ps=3.88e-6 pd=3.88e-6 nrd=293.333e-3 nrs=293.333e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X142 n265 n302 DVSS DVSS nfet_06v0 m=1.0 w=3e-6 l=700e-9 nf=2.0 as=1.32e-12 ++ ad=780e-15 ps=7.76e-6 pd=4.04e-6 nrd=86.667e-3 nrs=146.667e-3 sa=440e-9 ++ sb=440e-9 sd=520e-9 dtemp=0.0 par=1 +X143 n277 n265 DVDD DVDD pfet_06v0 m=1.0 w=6e-6 l=700e-9 nf=2.0 as=2.64e-12 ++ ad=1.56e-12 ps=13.76e-6 pd=7.04e-6 nrd=43.333e-3 nrs=73.333e-3 sa=440e-9 ++ sb=440e-9 sd=520e-9 dtemp=0.0 par=1 +X144 n302 n266 VDD VDD pfet_06v0 m=1.0 w=3e-6 l=700e-9 nf=1.0 as=1.32e-12 ++ ad=1.32e-12 ps=6.88e-6 pd=6.88e-6 nrd=146.667e-3 nrs=146.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X145 n265 n302 DVDD DVDD pfet_06v0 m=1.0 w=6e-6 l=700e-9 nf=2.0 as=2.64e-12 ++ ad=1.56e-12 ps=13.76e-6 pd=7.04e-6 nrd=43.333e-3 nrs=73.333e-3 sa=440e-9 ++ sb=440e-9 sd=520e-9 dtemp=0.0 par=1 +X146 n281 n268 DVSS DVSS nfet_06v0 m=1.0 w=3e-6 l=700e-9 nf=2.0 as=1.32e-12 ++ ad=780e-15 ps=7.76e-6 pd=4.04e-6 nrd=86.667e-3 nrs=146.667e-3 sa=440e-9 ++ sb=440e-9 sd=520e-9 dtemp=0.0 par=1 +X147 n310 n264 VSS VSS nfet_06v0 m=1.0 w=1.5e-6 l=700e-9 nf=1.0 as=660e-15 ++ ad=660e-15 ps=3.88e-6 pd=3.88e-6 nrd=293.333e-3 nrs=293.333e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X148 n268 n310 DVSS DVSS nfet_06v0 m=1.0 w=3e-6 l=700e-9 nf=2.0 as=1.32e-12 ++ ad=780e-15 ps=7.76e-6 pd=4.04e-6 nrd=86.667e-3 nrs=146.667e-3 sa=440e-9 ++ sb=440e-9 sd=520e-9 dtemp=0.0 par=1 +X149 n281 n268 DVDD DVDD pfet_06v0 m=1.0 w=6e-6 l=700e-9 nf=2.0 as=2.64e-12 ++ ad=1.56e-12 ps=13.76e-6 pd=7.04e-6 nrd=43.333e-3 nrs=73.333e-3 sa=440e-9 ++ sb=440e-9 sd=520e-9 dtemp=0.0 par=1 +X150 n310 n264 VDD VDD pfet_06v0 m=1.0 w=3e-6 l=700e-9 nf=1.0 as=1.32e-12 ++ ad=1.32e-12 ps=6.88e-6 pd=6.88e-6 nrd=146.667e-3 nrs=146.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X151 n268 n310 DVDD DVDD pfet_06v0 m=1.0 w=6e-6 l=700e-9 nf=2.0 as=2.64e-12 ++ ad=1.56e-12 ps=13.76e-6 pd=7.04e-6 nrd=43.333e-3 nrs=73.333e-3 sa=440e-9 ++ sb=440e-9 sd=520e-9 dtemp=0.0 par=1 +D152 PD VDD diode_pd2nw_06v0 m=1.0 area=1e-12 pj=4e-6 +D153 IE VDD diode_pd2nw_06v0 m=1.0 area=1e-12 pj=4e-6 +D154 CS VDD diode_pd2nw_06v0 m=1.0 area=1e-12 pj=4e-6 +D155 PU VDD diode_pd2nw_06v0 m=1.0 area=1e-12 pj=4e-6 +X156 n318 n263 DVDD DVDD pfet_06v0 m=1.0 w=8e-6 l=700e-9 nf=1.0 as=3.52e-12 ++ ad=3.52e-12 ps=16.88e-6 pd=16.88e-6 nrd=55e-3 nrs=55e-3 sa=440e-9 sb=440e-9 ++ sd=0.0 dtemp=0.0 par=1 +X157 DVDD n263 n319 DVDD pfet_06v0 m=1.0 w=3e-6 l=700e-9 nf=1.0 as=1.32e-12 ++ ad=1.32e-12 ps=6.88e-6 pd=6.88e-6 nrd=146.667e-3 nrs=146.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X158 n320 n20 DVDD DVDD pfet_06v0 m=1.0 w=3.8e-6 l=700e-9 nf=1.0 as=1.672e-12 ++ ad=1.672e-12 ps=8.48e-6 pd=8.48e-6 nrd=115.789e-3 nrs=115.789e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X159 DVSS n319 n320 DVDD pfet_06v0 m=1.0 w=3.8e-6 l=700e-9 nf=1.0 as=1.672e-12 ++ ad=1.672e-12 ps=8.48e-6 pd=8.48e-6 nrd=115.789e-3 nrs=115.789e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X160 n280 n262 DVDD DVDD pfet_06v0 m=1.0 w=6e-6 l=700e-9 nf=1.0 as=2.64e-12 ++ ad=2.64e-12 ps=12.88e-6 pd=12.88e-6 nrd=73.333e-3 nrs=73.333e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X161 n280 n318 n315 DVDD pfet_06v0 m=1.0 w=2e-6 l=700e-9 nf=1.0 as=880e-15 ++ ad=880e-15 ps=4.88e-6 pd=4.88e-6 nrd=220e-3 nrs=220e-3 sa=440e-9 sb=440e-9 ++ sd=0.0 dtemp=0.0 par=1 +X162 n280 n318 n319 DVDD pfet_06v0 m=1.0 w=2e-6 l=700e-9 nf=1.0 as=880e-15 ++ ad=880e-15 ps=4.88e-6 pd=4.88e-6 nrd=220e-3 nrs=220e-3 sa=440e-9 sb=440e-9 ++ sd=0.0 dtemp=0.0 par=1 +X163 n280 n20 n320 DVDD pfet_06v0 m=1.0 w=4.3e-6 l=700e-9 nf=1.0 as=1.892e-12 ++ ad=1.892e-12 ps=9.48e-6 pd=9.48e-6 nrd=102.326e-3 nrs=102.326e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X164 n325 n262 DVSS DVSS nfet_06v0 m=1.0 w=16e-6 l=700e-9 nf=1.0 as=7.04e-12 ++ ad=7.04e-12 ps=32.88e-6 pd=32.88e-6 nrd=27.5e-3 nrs=27.5e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X165 n317 n20 n325 DVSS nfet_06v0 m=1.0 w=10.6e-6 l=700e-9 nf=1.0 as=4.664e-12 ++ ad=4.664e-12 ps=22.08e-6 pd=22.08e-6 nrd=41.509e-3 nrs=41.509e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X166 n280 n20 n317 DVSS nfet_06v0 m=1.0 w=12e-6 l=700e-9 nf=1.0 as=5.28e-12 ++ ad=5.28e-12 ps=24.88e-6 pd=24.88e-6 nrd=36.667e-3 nrs=36.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X167 n318 n263 DVSS DVSS nfet_06v0 m=1.0 w=4e-6 l=700e-9 nf=1.0 as=1.76e-12 ++ ad=1.76e-12 ps=8.88e-6 pd=8.88e-6 nrd=110e-3 nrs=110e-3 sa=440e-9 sb=440e-9 ++ sd=0.0 dtemp=0.0 par=1 +X168 n280 n263 n315 DVSS nfet_06v0 m=1.0 w=1.5e-6 l=700e-9 nf=1.0 as=660e-15 ++ ad=660e-15 ps=3.88e-6 pd=3.88e-6 nrd=293.333e-3 nrs=293.333e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X169 n280 n263 n319 DVSS nfet_06v0 m=1.0 w=1.5e-6 l=700e-9 nf=1.0 as=660e-15 ++ ad=660e-15 ps=3.88e-6 pd=3.88e-6 nrd=293.333e-3 nrs=293.333e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X170 DVDD n315 n317 DVSS nfet_06v0 m=1.0 w=1.3e-6 l=700e-9 nf=1.0 as=572e-15 ++ ad=572e-15 ps=3.48e-6 pd=3.48e-6 nrd=338.462e-3 nrs=338.462e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X171 DVSS n318 n315 DVSS nfet_06v0 m=1.0 w=1.5e-6 l=700e-9 nf=1.0 as=660e-15 ++ ad=660e-15 ps=3.88e-6 pd=3.88e-6 nrd=293.333e-3 nrs=293.333e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X172 n333 n280 DVDD DVDD pfet_06v0 m=1.0 w=2e-6 l=700e-9 nf=1.0 as=880e-15 ++ ad=880e-15 ps=4.88e-6 pd=4.88e-6 nrd=220e-3 nrs=220e-3 sa=440e-9 sb=440e-9 ++ sd=0.0 dtemp=0.0 par=1 +X173 n330 n333 VDD VDD pfet_06v0 m=1.0 w=10e-6 l=700e-9 nf=1.0 as=4.4e-12 ++ ad=4.4e-12 ps=20.88e-6 pd=20.88e-6 nrd=44e-3 nrs=44e-3 sa=440e-9 sb=440e-9 ++ sd=0.0 dtemp=0.0 par=1 +X174 Y n330 VDD VDD pfet_06v0 m=1.0 w=21e-6 l=700e-9 nf=1.0 as=9.24e-12 ++ ad=9.24e-12 ps=42.88e-6 pd=42.88e-6 nrd=20.952e-3 nrs=20.952e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X175 n333 n280 DVSS DVSS nfet_06v0 m=1.0 w=8e-6 l=700e-9 nf=1.0 as=3.52e-12 ++ ad=3.52e-12 ps=16.88e-6 pd=16.88e-6 nrd=55e-3 nrs=55e-3 sa=440e-9 sb=440e-9 ++ sd=0.0 dtemp=0.0 par=1 +X176 Y n330 VSS VSS nfet_06v0 m=1.0 w=9e-6 l=700e-9 nf=1.0 as=3.96e-12 ++ ad=3.96e-12 ps=18.88e-6 pd=18.88e-6 nrd=48.889e-3 nrs=48.889e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X177 n330 n333 VSS VSS nfet_06v0 m=1.0 w=2.5e-6 l=700e-9 nf=1.0 as=1.1e-12 ++ ad=1.1e-12 ps=5.88e-6 pd=5.88e-6 nrd=176e-3 nrs=176e-3 sa=440e-9 sb=440e-9 ++ sd=0.0 dtemp=0.0 par=1 +X178 n266 n340 VDD VDD pfet_06v0 m=1.0 w=3e-6 l=700e-9 nf=1.0 as=1.32e-12 ++ ad=1.32e-12 ps=6.88e-6 pd=6.88e-6 nrd=146.667e-3 nrs=146.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X179 n266 PU VDD VDD pfet_06v0 m=1.0 w=3e-6 l=700e-9 nf=1.0 as=1.32e-12 ++ ad=1.32e-12 ps=6.88e-6 pd=6.88e-6 nrd=146.667e-3 nrs=146.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X180 n341 PU VSS VSS nfet_06v0 m=1.0 w=3e-6 l=700e-9 nf=1.0 as=1.32e-12 ++ ad=1.32e-12 ps=6.88e-6 pd=6.88e-6 nrd=146.667e-3 nrs=146.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X181 n266 n340 n341 VSS nfet_06v0 m=1.0 w=3e-6 l=700e-9 nf=1.0 as=1.32e-12 ++ ad=1.32e-12 ps=6.88e-6 pd=6.88e-6 nrd=146.667e-3 nrs=146.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X182 n264 PD VDD VDD pfet_06v0 m=1.0 w=3e-6 l=700e-9 nf=1.0 as=1.32e-12 ++ ad=1.32e-12 ps=6.88e-6 pd=6.88e-6 nrd=146.667e-3 nrs=146.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X183 n264 n340 VDD VDD pfet_06v0 m=1.0 w=3e-6 l=700e-9 nf=1.0 as=1.32e-12 ++ ad=1.32e-12 ps=6.88e-6 pd=6.88e-6 nrd=146.667e-3 nrs=146.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X184 n347 n340 VSS VSS nfet_06v0 m=1.0 w=3e-6 l=700e-9 nf=1.0 as=1.32e-12 ++ ad=1.32e-12 ps=6.88e-6 pd=6.88e-6 nrd=146.667e-3 nrs=146.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X185 n264 PD n347 VSS nfet_06v0 m=1.0 w=3e-6 l=700e-9 nf=1.0 as=1.32e-12 ++ ad=1.32e-12 ps=6.88e-6 pd=6.88e-6 nrd=146.667e-3 nrs=146.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X186 n353 n359 n340 VDD pfet_06v0 m=1.0 w=3e-6 l=700e-9 nf=1.0 as=1.32e-12 ++ ad=1.32e-12 ps=6.88e-6 pd=6.88e-6 nrd=146.667e-3 nrs=146.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X187 PU PD n340 VDD pfet_06v0 m=1.0 w=3e-6 l=700e-9 nf=1.0 as=1.32e-12 ++ ad=1.32e-12 ps=6.88e-6 pd=6.88e-6 nrd=146.667e-3 nrs=146.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X188 n359 PD VDD VDD pfet_06v0 m=1.0 w=3e-6 l=700e-9 nf=1.0 as=1.32e-12 ++ ad=1.32e-12 ps=6.88e-6 pd=6.88e-6 nrd=146.667e-3 nrs=146.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X189 n353 PU VDD VDD pfet_06v0 m=1.0 w=3e-6 l=700e-9 nf=1.0 as=1.32e-12 ++ ad=1.32e-12 ps=6.88e-6 pd=6.88e-6 nrd=146.667e-3 nrs=146.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X190 n353 PD n340 VSS nfet_06v0 m=1.0 w=1.5e-6 l=700e-9 nf=1.0 as=660e-15 ++ ad=660e-15 ps=3.88e-6 pd=3.88e-6 nrd=293.333e-3 nrs=293.333e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X191 PU n359 n340 VSS nfet_06v0 m=1.0 w=1.5e-6 l=700e-9 nf=1.0 as=660e-15 ++ ad=660e-15 ps=3.88e-6 pd=3.88e-6 nrd=293.333e-3 nrs=293.333e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X192 n359 PD VSS VSS nfet_06v0 m=1.0 w=1.5e-6 l=700e-9 nf=1.0 as=660e-15 ++ ad=660e-15 ps=3.88e-6 pd=3.88e-6 nrd=293.333e-3 nrs=293.333e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X193 n353 PU VSS VSS nfet_06v0 m=1.0 w=1.5e-6 l=700e-9 nf=1.0 as=660e-15 ++ ad=660e-15 ps=3.88e-6 pd=3.88e-6 nrd=293.333e-3 nrs=293.333e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X194 n20 n362 DVDD ppolyf_u r_width=800e-9 r_length=23e-6 m=1.0 r=9.94533e3 par=1 +X195 n362 n361 DVDD ppolyf_u r_width=800e-9 r_length=35.7e-6 m=1.0 r=15.3065e3 par=1 +X196 n361 n360 DVDD ppolyf_u r_width=800e-9 r_length=35.7e-6 m=1.0 r=15.3065e3 par=1 +X197 n360 n363 DVDD ppolyf_u r_width=800e-9 r_length=35.7e-6 m=1.0 r=15.3065e3 par=1 +X198 n363 n368 DVDD ppolyf_u r_width=800e-9 r_length=35.7e-6 m=1.0 r=15.3065e3 par=1 +X199 n368 n367 DVDD ppolyf_u r_width=800e-9 r_length=35.7e-6 m=1.0 r=15.3065e3 par=1 +X200 n367 n364 DVDD ppolyf_u r_width=800e-9 r_length=35.7e-6 m=1.0 r=15.3065e3 par=1 +X201 n364 n365 DVDD ppolyf_u r_width=800e-9 r_length=35.7e-6 m=1.0 r=15.3065e3 par=1 +X202 n365 n281 DVSS DVSS nfet_06v0 m=1.0 w=1.5e-6 l=700e-9 nf=1.0 as=660e-15 ++ ad=660e-15 ps=3.88e-6 pd=3.88e-6 nrd=293.333e-3 nrs=293.333e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X203 n365 n265 DVDD DVDD pfet_06v0 m=1.0 w=3e-6 l=700e-9 nf=1.0 as=1.32e-12 ++ ad=1.32e-12 ps=6.88e-6 pd=6.88e-6 nrd=146.667e-3 nrs=146.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +D204 DVSS n20 diode_nd2ps_06v0 m=2.0 area=20e-12 pj=42e-6 +D205 n20 DVDD diode_pd2nw_06v0 m=2.0 area=20e-12 pj=42e-6 +X206 PAD n20 DVDD ppolyf_u r_width=2.5e-6 r_length=2.8e-6 m=1.0 r=432.59 par=1 +X207 PAD n20 DVDD ppolyf_u r_width=2.5e-6 r_length=2.8e-6 m=1.0 r=449.157 par=1 +X208 PAD n20 DVDD ppolyf_u r_width=2.5e-6 r_length=2.8e-6 m=1.0 r=432.59 par=1 +X209 PAD n20 DVDD ppolyf_u r_width=2.5e-6 r_length=2.8e-6 m=1.0 r=449.157 par=1 +.ENDS + + +******* EOF + +* Copyright 2022 GlobalFoundries PDK Authors +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. + +.SUBCKT gf180mcu_fd_io__brk2 VSS +.ENDS + + +******* EOF + +* Copyright 2022 GlobalFoundries PDK Authors +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. + +.SUBCKT gf180mcu_fd_io__brk5 VSS +.ENDS + + +******* EOF + +* Copyright 2022 GlobalFoundries PDK Authors +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. + +.SUBCKT gf180mcu_fd_io__cor DVDD DVSS VDD VSS +X0 DVDD DVSS cap_nmos_06v0 m=70.0 c_length=10e-6 c_width=25e-6 +X1 n7 n8 VDD VDD pfet_06v0 m=1.0 w=15e-6 l=700e-9 nf=1.0 as=6.6e-12 ad=6.6e-12 ++ ps=30.88e-6 pd=30.88e-6 nrd=29.333e-3 nrs=29.333e-3 sa=440e-9 sb=440e-9 ++ sd=0.0 dtemp=0.0 par=1 +X2 n8 n9 VDD VDD pfet_06v0 m=1.0 w=20e-6 l=700e-9 nf=1.0 as=8.8e-12 ad=8.8e-12 ++ ps=40.88e-6 pd=40.88e-6 nrd=22e-3 nrs=22e-3 sa=440e-9 sb=440e-9 sd=0.0 ++ dtemp=0.0 par=1 +X3 n5 n7 VDD VDD pfet_06v0 m=1.0 w=120e-6 l=700e-9 nf=2.0 as=52.8e-12 ad=31.2e-12 ++ ps=241.76e-6 pd=121.04e-6 nrd=2.167e-3 nrs=3.667e-3 sa=440e-9 sb=440e-9 ++ sd=520e-9 dtemp=0.0 par=1 +X4 n9 VSS cap_nmos_06v0 m=8.0 c_length=10e-6 c_width=25e-6 +X5 n12 n16 VDD ppolyf_u r_width=800e-9 r_length=63.855e-6 m=1.0 r=29.999e3 par=1 +X6 n11 n12 VDD ppolyf_u r_width=800e-9 r_length=63.855e-6 m=1.0 r=29.999e3 par=1 +X7 n20 n11 VDD ppolyf_u r_width=800e-9 r_length=63.855e-6 m=1.0 r=29.999e3 par=1 +X8 n22 n20 VDD ppolyf_u r_width=800e-9 r_length=63.855e-6 m=1.0 r=29.999e3 par=1 +X9 n18 n22 VDD ppolyf_u r_width=800e-9 r_length=63.855e-6 m=1.0 r=29.999e3 par=1 +X10 n21 n9 VDD ppolyf_u r_width=800e-9 r_length=63.855e-6 m=1.0 r=29.999e3 par=1 +X11 n23 n21 VDD ppolyf_u r_width=800e-9 r_length=63.855e-6 m=1.0 r=29.999e3 par=1 +X12 n19 n23 VDD ppolyf_u r_width=800e-9 r_length=63.855e-6 m=1.0 r=29.999e3 par=1 +X13 n14 n19 VDD ppolyf_u r_width=800e-9 r_length=63.855e-6 m=1.0 r=29.999e3 par=1 +X14 n13 n14 VDD ppolyf_u r_width=800e-9 r_length=63.855e-6 m=1.0 r=29.999e3 par=1 +X15 n16 n13 VDD ppolyf_u r_width=800e-9 r_length=63.855e-6 m=1.0 r=29.999e3 par=1 +X16 VDD n18 VDD ppolyf_u r_width=800e-9 r_length=63.855e-6 m=1.0 r=29.999e3 par=1 +X17 n8 n9 VSS VSS nfet_06v0 m=1.0 w=5e-6 l=700e-9 nf=1.0 as=2.2e-12 ad=2.2e-12 ++ ps=10.88e-6 pd=10.88e-6 nrd=88e-3 nrs=88e-3 sa=440e-9 sb=440e-9 sd=0.0 ++ dtemp=0.0 par=1 +X18 VDD n5 VSS VSS nfet_06v0 m=1.0 w=4e-3 l=700e-9 nf=80.0 as=1.058e-9 ad=1.04e-9 ++ ps=4.14232e-3 pd=4.0416e-3 nrd=65e-6 nrs=66e-6 sa=440e-9 sb=440e-9 sd=520e-9 ++ dtemp=0.0 par=1 +X19 n5 n7 VSS VSS nfet_06v0 m=1.0 w=30e-6 l=700e-9 nf=1.0 as=13.2e-12 ad=13.2e-12 ++ ps=60.88e-6 pd=60.88e-6 nrd=14.667e-3 nrs=14.667e-3 sa=440e-9 sb=440e-9 ++ sd=0.0 dtemp=0.0 par=1 +X20 n7 n8 VSS VSS nfet_06v0 m=1.0 w=30e-6 l=700e-9 nf=1.0 as=13.2e-12 ad=13.2e-12 ++ ps=60.88e-6 pd=60.88e-6 nrd=14.667e-3 nrs=14.667e-3 sa=440e-9 sb=440e-9 ++ sd=0.0 dtemp=0.0 par=1 +X21 n27 n28 DVDD DVDD pfet_06v0 m=1.0 w=15e-6 l=700e-9 nf=1.0 as=6.6e-12 ad=6.6e-12 ++ ps=30.88e-6 pd=30.88e-6 nrd=29.333e-3 nrs=29.333e-3 sa=440e-9 sb=440e-9 ++ sd=0.0 dtemp=0.0 par=1 +X22 n28 n29 DVDD DVDD pfet_06v0 m=1.0 w=20e-6 l=700e-9 nf=1.0 as=8.8e-12 ad=8.8e-12 ++ ps=40.88e-6 pd=40.88e-6 nrd=22e-3 nrs=22e-3 sa=440e-9 sb=440e-9 sd=0.0 ++ dtemp=0.0 par=1 +X23 n25 n27 DVDD DVDD pfet_06v0 m=1.0 w=120e-6 l=700e-9 nf=2.0 as=52.8e-12 ++ ad=31.2e-12 ps=241.76e-6 pd=121.04e-6 nrd=2.167e-3 nrs=3.667e-3 sa=440e-9 ++ sb=440e-9 sd=520e-9 dtemp=0.0 par=1 +X24 n29 DVSS cap_nmos_06v0 m=8.0 c_length=10e-6 c_width=25e-6 +X25 n32 n36 DVDD ppolyf_u r_width=800e-9 r_length=63.855e-6 m=1.0 r=29.999e3 par=1 +X26 n31 n32 DVDD ppolyf_u r_width=800e-9 r_length=63.855e-6 m=1.0 r=29.999e3 par=1 +X27 n40 n31 DVDD ppolyf_u r_width=800e-9 r_length=63.855e-6 m=1.0 r=29.999e3 par=1 +X28 n42 n40 DVDD ppolyf_u r_width=800e-9 r_length=63.855e-6 m=1.0 r=29.999e3 par=1 +X29 n38 n42 DVDD ppolyf_u r_width=800e-9 r_length=63.855e-6 m=1.0 r=29.999e3 par=1 +X30 n41 n29 DVDD ppolyf_u r_width=800e-9 r_length=63.855e-6 m=1.0 r=29.999e3 par=1 +X31 n43 n41 DVDD ppolyf_u r_width=800e-9 r_length=63.855e-6 m=1.0 r=29.999e3 par=1 +X32 n39 n43 DVDD ppolyf_u r_width=800e-9 r_length=63.855e-6 m=1.0 r=29.999e3 par=1 +X33 n34 n39 DVDD ppolyf_u r_width=800e-9 r_length=63.855e-6 m=1.0 r=29.999e3 par=1 +X34 n33 n34 DVDD ppolyf_u r_width=800e-9 r_length=63.855e-6 m=1.0 r=29.999e3 par=1 +X35 n36 n33 DVDD ppolyf_u r_width=800e-9 r_length=63.855e-6 m=1.0 r=29.999e3 par=1 +X36 DVDD n38 DVDD ppolyf_u r_width=800e-9 r_length=63.855e-6 m=1.0 r=29.999e3 par=1 +X37 n28 n29 DVSS DVSS nfet_06v0 m=1.0 w=5e-6 l=700e-9 nf=1.0 as=2.2e-12 ad=2.2e-12 ++ ps=10.88e-6 pd=10.88e-6 nrd=88e-3 nrs=88e-3 sa=440e-9 sb=440e-9 sd=0.0 ++ dtemp=0.0 par=1 +X38 DVDD n25 DVSS DVSS nfet_06v0 m=1.0 w=4e-3 l=700e-9 nf=80.0 as=1.058e-9 ad=1.04e-9 ++ ps=4.14232e-3 pd=4.0416e-3 nrd=65e-6 nrs=66e-6 sa=440e-9 sb=440e-9 sd=520e-9 ++ dtemp=0.0 par=1 +X39 n25 n27 DVSS DVSS nfet_06v0 m=1.0 w=30e-6 l=700e-9 nf=1.0 as=13.2e-12 ++ ad=13.2e-12 ps=60.88e-6 pd=60.88e-6 nrd=14.667e-3 nrs=14.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X40 n27 n28 DVSS DVSS nfet_06v0 m=1.0 w=30e-6 l=700e-9 nf=1.0 as=13.2e-12 ++ ad=13.2e-12 ps=60.88e-6 pd=60.88e-6 nrd=14.667e-3 nrs=14.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +.ENDS + + +******* EOF + +* Copyright 2022 GlobalFoundries PDK Authors +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. + +.SUBCKT gf180mcu_fd_io__dvdd DVDD DVSS VSS +X0 n6 n7 DVDD DVDD pfet_06v0 m=1.0 w=15e-6 l=700e-9 nf=1.0 as=6.6e-12 ad=6.6e-12 ++ ps=30.88e-6 pd=30.88e-6 nrd=29.333e-3 nrs=29.333e-3 sa=440e-9 sb=440e-9 ++ sd=0.0 dtemp=0.0 par=1 +X1 n7 n8 DVDD DVDD pfet_06v0 m=1.0 w=20e-6 l=700e-9 nf=1.0 as=8.8e-12 ad=8.8e-12 ++ ps=40.88e-6 pd=40.88e-6 nrd=22e-3 nrs=22e-3 sa=440e-9 sb=440e-9 sd=0.0 ++ dtemp=0.0 par=1 +X2 n4 n6 DVDD DVDD pfet_06v0 m=1.0 w=120e-6 l=700e-9 nf=2.0 as=52.8e-12 ad=31.2e-12 ++ ps=241.76e-6 pd=121.04e-6 nrd=2.167e-3 nrs=3.667e-3 sa=440e-9 sb=440e-9 ++ sd=520e-9 dtemp=0.0 par=1 +X3 n8 DVSS cap_nmos_06v0 m=8.0 c_length=10e-6 c_width=25e-6 +X4 n11 n15 DVDD ppolyf_u r_width=800e-9 r_length=63.855e-6 m=1.0 r=29.999e3 par=1 +X5 n10 n11 DVDD ppolyf_u r_width=800e-9 r_length=63.855e-6 m=1.0 r=29.999e3 par=1 +X6 n19 n10 DVDD ppolyf_u r_width=800e-9 r_length=63.855e-6 m=1.0 r=29.999e3 par=1 +X7 n21 n19 DVDD ppolyf_u r_width=800e-9 r_length=63.855e-6 m=1.0 r=29.999e3 par=1 +X8 n17 n21 DVDD ppolyf_u r_width=800e-9 r_length=63.855e-6 m=1.0 r=29.999e3 par=1 +X9 n20 n8 DVDD ppolyf_u r_width=800e-9 r_length=63.855e-6 m=1.0 r=29.999e3 par=1 +X10 n22 n20 DVDD ppolyf_u r_width=800e-9 r_length=63.855e-6 m=1.0 r=29.999e3 par=1 +X11 n18 n22 DVDD ppolyf_u r_width=800e-9 r_length=63.855e-6 m=1.0 r=29.999e3 par=1 +X12 n13 n18 DVDD ppolyf_u r_width=800e-9 r_length=63.855e-6 m=1.0 r=29.999e3 par=1 +X13 n12 n13 DVDD ppolyf_u r_width=800e-9 r_length=63.855e-6 m=1.0 r=29.999e3 par=1 +X14 n15 n12 DVDD ppolyf_u r_width=800e-9 r_length=63.855e-6 m=1.0 r=29.999e3 par=1 +X15 DVDD n17 DVDD ppolyf_u r_width=800e-9 r_length=63.855e-6 m=1.0 r=29.999e3 par=1 +X16 n7 n8 DVSS DVSS nfet_06v0 m=1.0 w=5e-6 l=700e-9 nf=1.0 as=2.2e-12 ad=2.2e-12 ++ ps=10.88e-6 pd=10.88e-6 nrd=88e-3 nrs=88e-3 sa=440e-9 sb=440e-9 sd=0.0 ++ dtemp=0.0 par=1 +X17 DVDD n4 DVSS DVSS nfet_06v0 m=1.0 w=4e-3 l=700e-9 nf=80.0 as=1.058e-9 ad=1.04e-9 ++ ps=4.14232e-3 pd=4.0416e-3 nrd=65e-6 nrs=66e-6 sa=440e-9 sb=440e-9 sd=520e-9 ++ dtemp=0.0 par=1 +X18 n4 n6 DVSS DVSS nfet_06v0 m=1.0 w=30e-6 l=700e-9 nf=1.0 as=13.2e-12 ad=13.2e-12 ++ ps=60.88e-6 pd=60.88e-6 nrd=14.667e-3 nrs=14.667e-3 sa=440e-9 sb=440e-9 ++ sd=0.0 dtemp=0.0 par=1 +X19 n6 n7 DVSS DVSS nfet_06v0 m=1.0 w=30e-6 l=700e-9 nf=1.0 as=13.2e-12 ad=13.2e-12 ++ ps=60.88e-6 pd=60.88e-6 nrd=14.667e-3 nrs=14.667e-3 sa=440e-9 sb=440e-9 ++ sd=0.0 dtemp=0.0 par=1 +D20 DVSS DVDD diode_nd2ps_06v0 m=4.0 area=40e-12 pj=82e-6 +X21 DVDD DVSS cap_nmos_06v0 m=4.0 c_length=15e-6 c_width=15e-6 +.ENDS + + +******* EOF + +* Copyright 2022 GlobalFoundries PDK Authors +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. + +.SUBCKT gf180mcu_fd_io__dvss DVDD DVSS VDD +X0 n6 n7 DVDD DVDD pfet_06v0 m=1.0 w=15e-6 l=700e-9 nf=1.0 as=6.6e-12 ad=6.6e-12 ++ ps=30.88e-6 pd=30.88e-6 nrd=29.333e-3 nrs=29.333e-3 sa=440e-9 sb=440e-9 ++ sd=0.0 dtemp=0.0 par=1 +X1 n7 n8 DVDD DVDD pfet_06v0 m=1.0 w=20e-6 l=700e-9 nf=1.0 as=8.8e-12 ad=8.8e-12 ++ ps=40.88e-6 pd=40.88e-6 nrd=22e-3 nrs=22e-3 sa=440e-9 sb=440e-9 sd=0.0 ++ dtemp=0.0 par=1 +X2 n4 n6 DVDD DVDD pfet_06v0 m=1.0 w=120e-6 l=700e-9 nf=2.0 as=52.8e-12 ad=31.2e-12 ++ ps=241.76e-6 pd=121.04e-6 nrd=2.167e-3 nrs=3.667e-3 sa=440e-9 sb=440e-9 ++ sd=520e-9 dtemp=0.0 par=1 +X3 n8 DVSS cap_nmos_06v0 m=8.0 c_length=10e-6 c_width=25e-6 +X4 n11 n15 DVDD ppolyf_u r_width=800e-9 r_length=63.855e-6 m=1.0 r=29.999e3 par=1 +X5 n10 n11 DVDD ppolyf_u r_width=800e-9 r_length=63.855e-6 m=1.0 r=29.999e3 par=1 +X6 n19 n10 DVDD ppolyf_u r_width=800e-9 r_length=63.855e-6 m=1.0 r=29.999e3 par=1 +X7 n21 n19 DVDD ppolyf_u r_width=800e-9 r_length=63.855e-6 m=1.0 r=29.999e3 par=1 +X8 n17 n21 DVDD ppolyf_u r_width=800e-9 r_length=63.855e-6 m=1.0 r=29.999e3 par=1 +X9 n20 n8 DVDD ppolyf_u r_width=800e-9 r_length=63.855e-6 m=1.0 r=29.999e3 par=1 +X10 n22 n20 DVDD ppolyf_u r_width=800e-9 r_length=63.855e-6 m=1.0 r=29.999e3 par=1 +X11 n18 n22 DVDD ppolyf_u r_width=800e-9 r_length=63.855e-6 m=1.0 r=29.999e3 par=1 +X12 n13 n18 DVDD ppolyf_u r_width=800e-9 r_length=63.855e-6 m=1.0 r=29.999e3 par=1 +X13 n12 n13 DVDD ppolyf_u r_width=800e-9 r_length=63.855e-6 m=1.0 r=29.999e3 par=1 +X14 n15 n12 DVDD ppolyf_u r_width=800e-9 r_length=63.855e-6 m=1.0 r=29.999e3 par=1 +X15 DVDD n17 DVDD ppolyf_u r_width=800e-9 r_length=63.855e-6 m=1.0 r=29.999e3 par=1 +X16 n7 n8 DVSS DVSS nfet_06v0 m=1.0 w=5e-6 l=700e-9 nf=1.0 as=2.2e-12 ad=2.2e-12 ++ ps=10.88e-6 pd=10.88e-6 nrd=88e-3 nrs=88e-3 sa=440e-9 sb=440e-9 sd=0.0 ++ dtemp=0.0 par=1 +X17 DVDD n4 DVSS DVSS nfet_06v0 m=1.0 w=4e-3 l=700e-9 nf=80.0 as=1.058e-9 ad=1.04e-9 ++ ps=4.14232e-3 pd=4.0416e-3 nrd=65e-6 nrs=66e-6 sa=440e-9 sb=440e-9 sd=520e-9 ++ dtemp=0.0 par=1 +X18 n4 n6 DVSS DVSS nfet_06v0 m=1.0 w=30e-6 l=700e-9 nf=1.0 as=13.2e-12 ad=13.2e-12 ++ ps=60.88e-6 pd=60.88e-6 nrd=14.667e-3 nrs=14.667e-3 sa=440e-9 sb=440e-9 ++ sd=0.0 dtemp=0.0 par=1 +X19 n6 n7 DVSS DVSS nfet_06v0 m=1.0 w=30e-6 l=700e-9 nf=1.0 as=13.2e-12 ad=13.2e-12 ++ ps=60.88e-6 pd=60.88e-6 nrd=14.667e-3 nrs=14.667e-3 sa=440e-9 sb=440e-9 ++ sd=0.0 dtemp=0.0 par=1 +D20 DVSS DVDD diode_nd2ps_06v0 m=4.0 area=40e-12 pj=82e-6 +X21 DVDD DVSS cap_nmos_06v0 m=4.0 c_length=15e-6 c_width=15e-6 +.ENDS + + +******* EOF + +* Copyright 2022 GlobalFoundries PDK Authors +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. + +.SUBCKT gf180mcu_fd_io__fill1 DVDD DVSS VDD VSS +.ENDS + + +******* EOF + +* Copyright 2022 GlobalFoundries PDK Authors +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. + +.SUBCKT gf180mcu_fd_io__fill5 DVDD DVSS VDD VSS +X0 VDD VSS cap_nmos_06v0 m=70.0 c_length=1.5e-6 c_width=1.5e-6 +.ENDS + + +******* EOF + +* Copyright 2022 GlobalFoundries PDK Authors +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. + +.SUBCKT gf180mcu_fd_io__fill10 DVDD DVSS VDD VSS +X0 VDD VSS cap_nmos_06v0 m=32.0 c_length=6e-6 c_width=7e-6 +.ENDS + + +******* EOF + +* Copyright 2022 GlobalFoundries PDK Authors +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. + +.SUBCKT gf180mcu_fd_io__fillnc DVDD DVSS VDD VSS +.ENDS + + +******* EOF + +* Copyright 2022 GlobalFoundries PDK Authors +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. + +.SUBCKT gf180mcu_fd_io__in_c DVDD DVSS PAD PD PU VDD VSS Y +X0 DVDD DVSS cap_nmos_06v0 m=8.0 c_length=1.5e-6 c_width=5e-6 +X1 DVDD DVSS cap_nmos_06v0 m=4.0 c_length=3e-6 c_width=3e-6 +X2 n0 VSS VDD ppolyf_u r_width=800e-9 r_length=3.9e-6 m=1.0 r=1.88247e3 par=1 +X3 VDD n6 VDD ppolyf_u r_width=800e-9 r_length=3.9e-6 m=1.0 r=1.88247e3 par=1 +X4 n62 n70 DVSS DVSS nfet_06v0 m=1.0 w=3e-6 l=700e-9 nf=1.0 as=1.32e-12 ad=1.32e-12 ++ ps=6.88e-6 pd=6.88e-6 nrd=146.667e-3 nrs=146.667e-3 sa=440e-9 sb=440e-9 ++ sd=0.0 dtemp=0.0 par=1 +X5 n32 n62 DVSS DVSS nfet_06v0 m=1.0 w=3e-6 l=700e-9 nf=1.0 as=1.32e-12 ad=1.32e-12 ++ ps=6.88e-6 pd=6.88e-6 nrd=146.667e-3 nrs=146.667e-3 sa=440e-9 sb=440e-9 ++ sd=0.0 dtemp=0.0 par=1 +X6 n67 n0 VSS VSS nfet_06v0 m=1.0 w=3e-6 l=700e-9 nf=1.0 as=1.32e-12 ad=1.32e-12 ++ ps=6.88e-6 pd=6.88e-6 nrd=146.667e-3 nrs=146.667e-3 sa=440e-9 sb=440e-9 ++ sd=0.0 dtemp=0.0 par=1 +X7 n70 n0 n67 VSS nfet_06v0 m=1.0 w=3e-6 l=700e-9 nf=1.0 as=1.32e-12 ad=1.32e-12 ++ ps=6.88e-6 pd=6.88e-6 nrd=146.667e-3 nrs=146.667e-3 sa=440e-9 sb=440e-9 ++ sd=0.0 dtemp=0.0 par=1 +X8 n62 n70 DVDD DVDD pfet_06v0 m=1.0 w=6e-6 l=700e-9 nf=1.0 as=2.64e-12 ad=2.64e-12 ++ ps=12.88e-6 pd=12.88e-6 nrd=73.333e-3 nrs=73.333e-3 sa=440e-9 sb=440e-9 ++ sd=0.0 dtemp=0.0 par=1 +X9 n32 n62 DVDD DVDD pfet_06v0 m=1.0 w=6e-6 l=700e-9 nf=1.0 as=2.64e-12 ad=2.64e-12 ++ ps=12.88e-6 pd=12.88e-6 nrd=73.333e-3 nrs=73.333e-3 sa=440e-9 sb=440e-9 ++ sd=0.0 dtemp=0.0 par=1 +X10 n70 n0 VDD VDD pfet_06v0 m=1.0 w=3e-6 l=700e-9 nf=1.0 as=1.32e-12 ad=1.32e-12 ++ ps=6.88e-6 pd=6.88e-6 nrd=146.667e-3 nrs=146.667e-3 sa=440e-9 sb=440e-9 ++ sd=0.0 dtemp=0.0 par=1 +X11 n70 n0 VDD VDD pfet_06v0 m=1.0 w=3e-6 l=700e-9 nf=1.0 as=1.32e-12 ad=1.32e-12 ++ ps=6.88e-6 pd=6.88e-6 nrd=146.667e-3 nrs=146.667e-3 sa=440e-9 sb=440e-9 ++ sd=0.0 dtemp=0.0 par=1 +X12 PAD n38 DVDD DVDD pfet_06v0_dss m=1.0 w=80e-6 l=700e-9 nf=2.0 s_sab=280e-9 ++ d_sab=2.78e-6 par=1 dtemp=0.0 +X13 PAD n50 DVSS DVSS nfet_06v0_dss m=1.0 w=38e-6 l=1.15e-6 nf=1.0 s_sab=280e-9 ++ d_sab=3.78e-6 par=1 dtemp=0.0 +X14 PAD n47 DVSS DVSS nfet_06v0_dss m=1.0 w=38e-6 l=1.15e-6 nf=1.0 s_sab=280e-9 ++ d_sab=3.78e-6 par=1 dtemp=0.0 +X15 PAD n43 DVDD DVDD pfet_06v0_dss m=1.0 w=40e-6 l=700e-9 nf=1.0 s_sab=280e-9 ++ d_sab=2.78e-6 par=1 dtemp=0.0 +X16 PAD n37 DVDD DVDD pfet_06v0_dss m=1.0 w=80e-6 l=700e-9 nf=2.0 s_sab=280e-9 ++ d_sab=2.78e-6 par=1 dtemp=0.0 +X17 PAD n51 DVSS DVSS nfet_06v0_dss m=1.0 w=38e-6 l=1.15e-6 nf=1.0 s_sab=280e-9 ++ d_sab=3.78e-6 par=1 dtemp=0.0 +X18 PAD n46 DVSS DVSS nfet_06v0_dss m=1.0 w=38e-6 l=1.15e-6 nf=1.0 s_sab=280e-9 ++ d_sab=3.78e-6 par=1 dtemp=0.0 +X19 PAD n42 DVDD DVDD pfet_06v0_dss m=1.0 w=40e-6 l=700e-9 nf=1.0 s_sab=280e-9 ++ d_sab=2.78e-6 par=1 dtemp=0.0 +X20 PAD n39 DVDD DVDD pfet_06v0_dss m=1.0 w=80e-6 l=700e-9 nf=2.0 s_sab=280e-9 ++ d_sab=2.78e-6 par=1 dtemp=0.0 +X21 PAD n49 DVSS DVSS nfet_06v0_dss m=1.0 w=38e-6 l=1.15e-6 nf=1.0 s_sab=280e-9 ++ d_sab=3.78e-6 par=1 dtemp=0.0 +X22 PAD n48 DVSS DVSS nfet_06v0_dss m=1.0 w=38e-6 l=1.15e-6 nf=1.0 s_sab=280e-9 ++ d_sab=3.78e-6 par=1 dtemp=0.0 +X23 PAD n44 DVDD DVDD pfet_06v0_dss m=1.0 w=40e-6 l=700e-9 nf=1.0 s_sab=280e-9 ++ d_sab=2.78e-6 par=1 dtemp=0.0 +X24 PAD n40 DVDD DVDD pfet_06v0_dss m=1.0 w=80e-6 l=700e-9 nf=2.0 s_sab=280e-9 ++ d_sab=2.78e-6 par=1 dtemp=0.0 +X25 PAD n52 DVSS DVSS nfet_06v0_dss m=1.0 w=38e-6 l=1.15e-6 nf=1.0 s_sab=280e-9 ++ d_sab=3.78e-6 par=1 dtemp=0.0 +X26 PAD n45 DVSS DVSS nfet_06v0_dss m=1.0 w=38e-6 l=1.15e-6 nf=1.0 s_sab=280e-9 ++ d_sab=3.78e-6 par=1 dtemp=0.0 +X27 PAD n41 DVDD DVDD pfet_06v0_dss m=1.0 w=40e-6 l=700e-9 nf=1.0 s_sab=280e-9 ++ d_sab=2.78e-6 par=1 dtemp=0.0 +X28 n53 n36 DVSS DVSS nfet_06v0 m=1.0 w=3e-6 l=700e-9 nf=2.0 as=1.32e-12 ad=780e-15 ++ ps=7.76e-6 pd=4.04e-6 nrd=86.667e-3 nrs=146.667e-3 sa=440e-9 sb=440e-9 ++ sd=520e-9 dtemp=0.0 par=1 +X29 n170 n0 VSS VSS nfet_06v0 m=1.0 w=1.5e-6 l=700e-9 nf=1.0 as=660e-15 ++ ad=660e-15 ps=3.88e-6 pd=3.88e-6 nrd=293.333e-3 nrs=293.333e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X30 n36 n170 DVSS DVSS nfet_06v0 m=1.0 w=3e-6 l=700e-9 nf=2.0 as=1.32e-12 ++ ad=780e-15 ps=7.76e-6 pd=4.04e-6 nrd=86.667e-3 nrs=146.667e-3 sa=440e-9 ++ sb=440e-9 sd=520e-9 dtemp=0.0 par=1 +X31 n53 n36 DVDD DVDD pfet_06v0 m=1.0 w=6e-6 l=700e-9 nf=2.0 as=2.64e-12 ++ ad=1.56e-12 ps=13.76e-6 pd=7.04e-6 nrd=43.333e-3 nrs=73.333e-3 sa=440e-9 ++ sb=440e-9 sd=520e-9 dtemp=0.0 par=1 +X32 n170 n0 VDD VDD pfet_06v0 m=1.0 w=3e-6 l=700e-9 nf=1.0 as=1.32e-12 ++ ad=1.32e-12 ps=6.88e-6 pd=6.88e-6 nrd=146.667e-3 nrs=146.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X33 n36 n170 DVDD DVDD pfet_06v0 m=1.0 w=6e-6 l=700e-9 nf=2.0 as=2.64e-12 ++ ad=1.56e-12 ps=13.76e-6 pd=7.04e-6 nrd=43.333e-3 nrs=73.333e-3 sa=440e-9 ++ sb=440e-9 sd=520e-9 dtemp=0.0 par=1 +D34 n0 VDD diode_pd2nw_06v0 m=1.0 area=1e-12 pj=4e-6 +D35 n0 VDD diode_pd2nw_06v0 m=1.0 area=1e-12 pj=4e-6 +D36 VSS n0 diode_pd2nw_06v0 m=1.0 area=230.4e-15 pj=1.92e-6 +D37 VSS n0 diode_pd2nw_06v0 m=1.0 area=230.4e-15 pj=1.92e-6 +X38 n183 n0 VSS VSS nfet_06v0 m=1.0 w=3e-6 l=700e-9 nf=1.0 as=1.32e-12 ++ ad=1.32e-12 ps=6.88e-6 pd=6.88e-6 nrd=146.667e-3 nrs=146.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X39 n174 n0 n183 VSS nfet_06v0 m=1.0 w=3e-6 l=700e-9 nf=1.0 as=1.32e-12 ++ ad=1.32e-12 ps=6.88e-6 pd=6.88e-6 nrd=146.667e-3 nrs=146.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X40 n34 n31 DVSS DVSS nfet_06v0 m=1.0 w=3e-6 l=700e-9 nf=1.0 as=1.32e-12 ++ ad=1.32e-12 ps=6.88e-6 pd=6.88e-6 nrd=146.667e-3 nrs=146.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X41 n31 n174 DVSS DVSS nfet_06v0 m=1.0 w=3e-6 l=700e-9 nf=1.0 as=1.32e-12 ++ ad=1.32e-12 ps=6.88e-6 pd=6.88e-6 nrd=146.667e-3 nrs=146.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X42 n174 n0 VDD VDD pfet_06v0 m=1.0 w=3e-6 l=700e-9 nf=1.0 as=1.32e-12 ++ ad=1.32e-12 ps=6.88e-6 pd=6.88e-6 nrd=146.667e-3 nrs=146.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X43 n174 n0 VDD VDD pfet_06v0 m=1.0 w=3e-6 l=700e-9 nf=1.0 as=1.32e-12 ++ ad=1.32e-12 ps=6.88e-6 pd=6.88e-6 nrd=146.667e-3 nrs=146.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X44 n34 n31 DVDD DVDD pfet_06v0 m=1.0 w=6e-6 l=700e-9 nf=1.0 as=2.64e-12 ++ ad=2.64e-12 ps=12.88e-6 pd=12.88e-6 nrd=73.333e-3 nrs=73.333e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X45 n31 n174 DVDD DVDD pfet_06v0 m=1.0 w=6e-6 l=700e-9 nf=1.0 as=2.64e-12 ++ ad=2.64e-12 ps=12.88e-6 pd=12.88e-6 nrd=73.333e-3 nrs=73.333e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +D46 VSS n0 diode_pd2nw_06v0 m=1.0 area=230.4e-15 pj=1.92e-6 +D47 VSS n0 diode_pd2nw_06v0 m=1.0 area=230.4e-15 pj=1.92e-6 +X48 n193 n0 VSS VSS nfet_06v0 m=1.0 w=3e-6 l=700e-9 nf=1.0 as=1.32e-12 ++ ad=1.32e-12 ps=6.88e-6 pd=6.88e-6 nrd=146.667e-3 nrs=146.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X49 n184 n0 n193 VSS nfet_06v0 m=1.0 w=3e-6 l=700e-9 nf=1.0 as=1.32e-12 ++ ad=1.32e-12 ps=6.88e-6 pd=6.88e-6 nrd=146.667e-3 nrs=146.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X50 n30 n28 DVSS DVSS nfet_06v0 m=1.0 w=3e-6 l=700e-9 nf=1.0 as=1.32e-12 ++ ad=1.32e-12 ps=6.88e-6 pd=6.88e-6 nrd=146.667e-3 nrs=146.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X51 n28 n184 DVSS DVSS nfet_06v0 m=1.0 w=3e-6 l=700e-9 nf=1.0 as=1.32e-12 ++ ad=1.32e-12 ps=6.88e-6 pd=6.88e-6 nrd=146.667e-3 nrs=146.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X52 n184 n0 VDD VDD pfet_06v0 m=1.0 w=3e-6 l=700e-9 nf=1.0 as=1.32e-12 ++ ad=1.32e-12 ps=6.88e-6 pd=6.88e-6 nrd=146.667e-3 nrs=146.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X53 n184 n0 VDD VDD pfet_06v0 m=1.0 w=3e-6 l=700e-9 nf=1.0 as=1.32e-12 ++ ad=1.32e-12 ps=6.88e-6 pd=6.88e-6 nrd=146.667e-3 nrs=146.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X54 n30 n28 DVDD DVDD pfet_06v0 m=1.0 w=6e-6 l=700e-9 nf=1.0 as=2.64e-12 ++ ad=2.64e-12 ps=12.88e-6 pd=12.88e-6 nrd=73.333e-3 nrs=73.333e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X55 n28 n184 DVDD DVDD pfet_06v0 m=1.0 w=6e-6 l=700e-9 nf=1.0 as=2.64e-12 ++ ad=2.64e-12 ps=12.88e-6 pd=12.88e-6 nrd=73.333e-3 nrs=73.333e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +D56 VSS VDD diode_pd2nw_06v0 m=1.0 area=230.4e-15 pj=1.92e-6 +D57 VSS n0 diode_pd2nw_06v0 m=1.0 area=230.4e-15 pj=1.92e-6 +X58 n203 VDD VSS VSS nfet_06v0 m=1.0 w=3e-6 l=700e-9 nf=1.0 as=1.32e-12 ++ ad=1.32e-12 ps=6.88e-6 pd=6.88e-6 nrd=146.667e-3 nrs=146.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X59 n194 n0 n203 VSS nfet_06v0 m=1.0 w=3e-6 l=700e-9 nf=1.0 as=1.32e-12 ++ ad=1.32e-12 ps=6.88e-6 pd=6.88e-6 nrd=146.667e-3 nrs=146.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X60 n27 n26 DVSS DVSS nfet_06v0 m=1.0 w=3e-6 l=700e-9 nf=1.0 as=1.32e-12 ++ ad=1.32e-12 ps=6.88e-6 pd=6.88e-6 nrd=146.667e-3 nrs=146.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X61 n26 n194 DVSS DVSS nfet_06v0 m=1.0 w=3e-6 l=700e-9 nf=1.0 as=1.32e-12 ++ ad=1.32e-12 ps=6.88e-6 pd=6.88e-6 nrd=146.667e-3 nrs=146.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X62 n194 VDD VDD VDD pfet_06v0 m=1.0 w=3e-6 l=700e-9 nf=1.0 as=1.32e-12 ++ ad=1.32e-12 ps=6.88e-6 pd=6.88e-6 nrd=146.667e-3 nrs=146.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X63 n194 n0 VDD VDD pfet_06v0 m=1.0 w=3e-6 l=700e-9 nf=1.0 as=1.32e-12 ++ ad=1.32e-12 ps=6.88e-6 pd=6.88e-6 nrd=146.667e-3 nrs=146.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X64 n27 n26 DVDD DVDD pfet_06v0 m=1.0 w=6e-6 l=700e-9 nf=1.0 as=2.64e-12 ++ ad=2.64e-12 ps=12.88e-6 pd=12.88e-6 nrd=73.333e-3 nrs=73.333e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X65 n26 n194 DVDD DVDD pfet_06v0 m=1.0 w=6e-6 l=700e-9 nf=1.0 as=2.64e-12 ++ ad=2.64e-12 ps=12.88e-6 pd=12.88e-6 nrd=73.333e-3 nrs=73.333e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X66 n41 n53 n40 DVSS nfet_06v0 m=1.0 w=12e-6 l=700e-9 nf=1.0 as=5.28e-12 ++ ad=5.28e-12 ps=24.88e-6 pd=24.88e-6 nrd=36.667e-3 nrs=36.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X67 n40 DVDD n41 DVSS nfet_06v0 m=1.0 w=1.2e-6 l=700e-9 nf=1.0 as=528e-15 ++ ad=528e-15 ps=3.28e-6 pd=3.28e-6 nrd=366.667e-3 nrs=366.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X68 n45 n204 DVSS DVSS nfet_06v0 m=1.0 w=12e-6 l=700e-9 nf=1.0 as=5.28e-12 ++ ad=5.28e-12 ps=24.88e-6 pd=24.88e-6 nrd=36.667e-3 nrs=36.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X69 n52 n204 DVSS DVSS nfet_06v0 m=1.0 w=12e-6 l=700e-9 nf=1.0 as=5.28e-12 ++ ad=5.28e-12 ps=24.88e-6 pd=24.88e-6 nrd=36.667e-3 nrs=36.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X70 n41 n209 DVSS DVSS nfet_06v0 m=1.0 w=12e-6 l=700e-9 nf=1.0 as=5.28e-12 ++ ad=5.28e-12 ps=24.88e-6 pd=24.88e-6 nrd=36.667e-3 nrs=36.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X71 n209 n32 DVSS DVSS nfet_06v0 m=1.0 w=6e-6 l=700e-9 nf=1.0 as=2.64e-12 ++ ad=2.64e-12 ps=12.88e-6 pd=12.88e-6 nrd=73.333e-3 nrs=73.333e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X72 n209 n34 DVSS DVSS nfet_06v0 m=1.0 w=6e-6 l=700e-9 nf=1.0 as=2.64e-12 ++ ad=2.64e-12 ps=12.88e-6 pd=12.88e-6 nrd=73.333e-3 nrs=73.333e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X73 n204 n31 n209 DVSS nfet_06v0 m=1.0 w=6e-6 l=700e-9 nf=1.0 as=2.64e-12 ++ ad=2.64e-12 ps=12.88e-6 pd=12.88e-6 nrd=73.333e-3 nrs=73.333e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X74 n45 n36 n52 DVDD pfet_06v0 m=1.0 w=24e-6 l=700e-9 nf=1.0 as=10.56e-12 ++ ad=10.56e-12 ps=48.88e-6 pd=48.88e-6 nrd=18.333e-3 nrs=18.333e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X75 n204 n31 DVDD DVDD pfet_06v0 m=1.0 w=12e-6 l=700e-9 nf=1.0 as=5.28e-12 ++ ad=5.28e-12 ps=24.88e-6 pd=24.88e-6 nrd=36.667e-3 nrs=36.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X76 n41 n209 DVDD DVDD pfet_06v0 m=1.0 w=24e-6 l=700e-9 nf=1.0 as=10.56e-12 ++ ad=10.56e-12 ps=48.88e-6 pd=48.88e-6 nrd=18.333e-3 nrs=18.333e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X77 n52 n204 DVDD DVDD pfet_06v0 m=1.0 w=24e-6 l=700e-9 nf=1.0 as=10.56e-12 ++ ad=10.56e-12 ps=48.88e-6 pd=48.88e-6 nrd=18.333e-3 nrs=18.333e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X78 n45 DVSS n52 DVDD pfet_06v0 m=1.0 w=1.2e-6 l=700e-9 nf=1.0 as=528e-15 ++ ad=528e-15 ps=3.28e-6 pd=3.28e-6 nrd=366.667e-3 nrs=366.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X79 n204 n32 DVDD DVDD pfet_06v0 m=1.0 w=12e-6 l=700e-9 nf=1.0 as=5.28e-12 ++ ad=5.28e-12 ps=24.88e-6 pd=24.88e-6 nrd=36.667e-3 nrs=36.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X80 n209 n34 n204 DVDD pfet_06v0 m=1.0 w=12e-6 l=700e-9 nf=1.0 as=5.28e-12 ++ ad=5.28e-12 ps=24.88e-6 pd=24.88e-6 nrd=36.667e-3 nrs=36.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X81 n40 n209 DVDD DVDD pfet_06v0 m=1.0 w=24e-6 l=700e-9 nf=1.0 as=10.56e-12 ++ ad=10.56e-12 ps=48.88e-6 pd=48.88e-6 nrd=18.333e-3 nrs=18.333e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X82 n42 n53 n37 DVSS nfet_06v0 m=1.0 w=12e-6 l=700e-9 nf=1.0 as=5.28e-12 ++ ad=5.28e-12 ps=24.88e-6 pd=24.88e-6 nrd=36.667e-3 nrs=36.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X83 n37 DVDD n42 DVSS nfet_06v0 m=1.0 w=1.2e-6 l=700e-9 nf=1.0 as=528e-15 ++ ad=528e-15 ps=3.28e-6 pd=3.28e-6 nrd=366.667e-3 nrs=366.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X84 n46 n217 DVSS DVSS nfet_06v0 m=1.0 w=12e-6 l=700e-9 nf=1.0 as=5.28e-12 ++ ad=5.28e-12 ps=24.88e-6 pd=24.88e-6 nrd=36.667e-3 nrs=36.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X85 n51 n217 DVSS DVSS nfet_06v0 m=1.0 w=12e-6 l=700e-9 nf=1.0 as=5.28e-12 ++ ad=5.28e-12 ps=24.88e-6 pd=24.88e-6 nrd=36.667e-3 nrs=36.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X86 n42 n222 DVSS DVSS nfet_06v0 m=1.0 w=12e-6 l=700e-9 nf=1.0 as=5.28e-12 ++ ad=5.28e-12 ps=24.88e-6 pd=24.88e-6 nrd=36.667e-3 nrs=36.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X87 n222 n32 DVSS DVSS nfet_06v0 m=1.0 w=6e-6 l=700e-9 nf=1.0 as=2.64e-12 ++ ad=2.64e-12 ps=12.88e-6 pd=12.88e-6 nrd=73.333e-3 nrs=73.333e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X88 n222 n30 DVSS DVSS nfet_06v0 m=1.0 w=6e-6 l=700e-9 nf=1.0 as=2.64e-12 ++ ad=2.64e-12 ps=12.88e-6 pd=12.88e-6 nrd=73.333e-3 nrs=73.333e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X89 n217 n28 n222 DVSS nfet_06v0 m=1.0 w=6e-6 l=700e-9 nf=1.0 as=2.64e-12 ++ ad=2.64e-12 ps=12.88e-6 pd=12.88e-6 nrd=73.333e-3 nrs=73.333e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X90 n46 n36 n51 DVDD pfet_06v0 m=1.0 w=24e-6 l=700e-9 nf=1.0 as=10.56e-12 ++ ad=10.56e-12 ps=48.88e-6 pd=48.88e-6 nrd=18.333e-3 nrs=18.333e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X91 n217 n28 DVDD DVDD pfet_06v0 m=1.0 w=12e-6 l=700e-9 nf=1.0 as=5.28e-12 ++ ad=5.28e-12 ps=24.88e-6 pd=24.88e-6 nrd=36.667e-3 nrs=36.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X92 n42 n222 DVDD DVDD pfet_06v0 m=1.0 w=24e-6 l=700e-9 nf=1.0 as=10.56e-12 ++ ad=10.56e-12 ps=48.88e-6 pd=48.88e-6 nrd=18.333e-3 nrs=18.333e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X93 n51 n217 DVDD DVDD pfet_06v0 m=1.0 w=24e-6 l=700e-9 nf=1.0 as=10.56e-12 ++ ad=10.56e-12 ps=48.88e-6 pd=48.88e-6 nrd=18.333e-3 nrs=18.333e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X94 n46 DVSS n51 DVDD pfet_06v0 m=1.0 w=1.2e-6 l=700e-9 nf=1.0 as=528e-15 ++ ad=528e-15 ps=3.28e-6 pd=3.28e-6 nrd=366.667e-3 nrs=366.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X95 n217 n32 DVDD DVDD pfet_06v0 m=1.0 w=12e-6 l=700e-9 nf=1.0 as=5.28e-12 ++ ad=5.28e-12 ps=24.88e-6 pd=24.88e-6 nrd=36.667e-3 nrs=36.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X96 n222 n30 n217 DVDD pfet_06v0 m=1.0 w=12e-6 l=700e-9 nf=1.0 as=5.28e-12 ++ ad=5.28e-12 ps=24.88e-6 pd=24.88e-6 nrd=36.667e-3 nrs=36.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X97 n37 n222 DVDD DVDD pfet_06v0 m=1.0 w=24e-6 l=700e-9 nf=1.0 as=10.56e-12 ++ ad=10.56e-12 ps=48.88e-6 pd=48.88e-6 nrd=18.333e-3 nrs=18.333e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X98 n43 n53 n38 DVSS nfet_06v0 m=1.0 w=12e-6 l=700e-9 nf=1.0 as=5.28e-12 ++ ad=5.28e-12 ps=24.88e-6 pd=24.88e-6 nrd=36.667e-3 nrs=36.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X99 n38 DVDD n43 DVSS nfet_06v0 m=1.0 w=1.2e-6 l=700e-9 nf=1.0 as=528e-15 ++ ad=528e-15 ps=3.28e-6 pd=3.28e-6 nrd=366.667e-3 nrs=366.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X100 n47 n230 DVSS DVSS nfet_06v0 m=1.0 w=12e-6 l=700e-9 nf=1.0 as=5.28e-12 ++ ad=5.28e-12 ps=24.88e-6 pd=24.88e-6 nrd=36.667e-3 nrs=36.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X101 n50 n230 DVSS DVSS nfet_06v0 m=1.0 w=12e-6 l=700e-9 nf=1.0 as=5.28e-12 ++ ad=5.28e-12 ps=24.88e-6 pd=24.88e-6 nrd=36.667e-3 nrs=36.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X102 n43 n235 DVSS DVSS nfet_06v0 m=1.0 w=12e-6 l=700e-9 nf=1.0 as=5.28e-12 ++ ad=5.28e-12 ps=24.88e-6 pd=24.88e-6 nrd=36.667e-3 nrs=36.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X103 n235 n32 DVSS DVSS nfet_06v0 m=1.0 w=6e-6 l=700e-9 nf=1.0 as=2.64e-12 ++ ad=2.64e-12 ps=12.88e-6 pd=12.88e-6 nrd=73.333e-3 nrs=73.333e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X104 n235 n30 DVSS DVSS nfet_06v0 m=1.0 w=6e-6 l=700e-9 nf=1.0 as=2.64e-12 ++ ad=2.64e-12 ps=12.88e-6 pd=12.88e-6 nrd=73.333e-3 nrs=73.333e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X105 n230 n28 n235 DVSS nfet_06v0 m=1.0 w=6e-6 l=700e-9 nf=1.0 as=2.64e-12 ++ ad=2.64e-12 ps=12.88e-6 pd=12.88e-6 nrd=73.333e-3 nrs=73.333e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X106 n47 n36 n50 DVDD pfet_06v0 m=1.0 w=24e-6 l=700e-9 nf=1.0 as=10.56e-12 ++ ad=10.56e-12 ps=48.88e-6 pd=48.88e-6 nrd=18.333e-3 nrs=18.333e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X107 n230 n28 DVDD DVDD pfet_06v0 m=1.0 w=12e-6 l=700e-9 nf=1.0 as=5.28e-12 ++ ad=5.28e-12 ps=24.88e-6 pd=24.88e-6 nrd=36.667e-3 nrs=36.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X108 n43 n235 DVDD DVDD pfet_06v0 m=1.0 w=24e-6 l=700e-9 nf=1.0 as=10.56e-12 ++ ad=10.56e-12 ps=48.88e-6 pd=48.88e-6 nrd=18.333e-3 nrs=18.333e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X109 n50 n230 DVDD DVDD pfet_06v0 m=1.0 w=24e-6 l=700e-9 nf=1.0 as=10.56e-12 ++ ad=10.56e-12 ps=48.88e-6 pd=48.88e-6 nrd=18.333e-3 nrs=18.333e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X110 n47 DVSS n50 DVDD pfet_06v0 m=1.0 w=1.2e-6 l=700e-9 nf=1.0 as=528e-15 ++ ad=528e-15 ps=3.28e-6 pd=3.28e-6 nrd=366.667e-3 nrs=366.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X111 n230 n32 DVDD DVDD pfet_06v0 m=1.0 w=12e-6 l=700e-9 nf=1.0 as=5.28e-12 ++ ad=5.28e-12 ps=24.88e-6 pd=24.88e-6 nrd=36.667e-3 nrs=36.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X112 n235 n30 n230 DVDD pfet_06v0 m=1.0 w=12e-6 l=700e-9 nf=1.0 as=5.28e-12 ++ ad=5.28e-12 ps=24.88e-6 pd=24.88e-6 nrd=36.667e-3 nrs=36.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X113 n38 n235 DVDD DVDD pfet_06v0 m=1.0 w=24e-6 l=700e-9 nf=1.0 as=10.56e-12 ++ ad=10.56e-12 ps=48.88e-6 pd=48.88e-6 nrd=18.333e-3 nrs=18.333e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X114 n44 n53 n39 DVSS nfet_06v0 m=1.0 w=12e-6 l=700e-9 nf=1.0 as=5.28e-12 ++ ad=5.28e-12 ps=24.88e-6 pd=24.88e-6 nrd=36.667e-3 nrs=36.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X115 n39 DVDD n44 DVSS nfet_06v0 m=1.0 w=1.2e-6 l=700e-9 nf=1.0 as=528e-15 ++ ad=528e-15 ps=3.28e-6 pd=3.28e-6 nrd=366.667e-3 nrs=366.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X116 n48 n243 DVSS DVSS nfet_06v0 m=1.0 w=12e-6 l=700e-9 nf=1.0 as=5.28e-12 ++ ad=5.28e-12 ps=24.88e-6 pd=24.88e-6 nrd=36.667e-3 nrs=36.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X117 n49 n243 DVSS DVSS nfet_06v0 m=1.0 w=12e-6 l=700e-9 nf=1.0 as=5.28e-12 ++ ad=5.28e-12 ps=24.88e-6 pd=24.88e-6 nrd=36.667e-3 nrs=36.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X118 n44 n248 DVSS DVSS nfet_06v0 m=1.0 w=12e-6 l=700e-9 nf=1.0 as=5.28e-12 ++ ad=5.28e-12 ps=24.88e-6 pd=24.88e-6 nrd=36.667e-3 nrs=36.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X119 n248 n32 DVSS DVSS nfet_06v0 m=1.0 w=6e-6 l=700e-9 nf=1.0 as=2.64e-12 ++ ad=2.64e-12 ps=12.88e-6 pd=12.88e-6 nrd=73.333e-3 nrs=73.333e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X120 n248 n27 DVSS DVSS nfet_06v0 m=1.0 w=6e-6 l=700e-9 nf=1.0 as=2.64e-12 ++ ad=2.64e-12 ps=12.88e-6 pd=12.88e-6 nrd=73.333e-3 nrs=73.333e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X121 n243 n26 n248 DVSS nfet_06v0 m=1.0 w=6e-6 l=700e-9 nf=1.0 as=2.64e-12 ++ ad=2.64e-12 ps=12.88e-6 pd=12.88e-6 nrd=73.333e-3 nrs=73.333e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X122 n48 n36 n49 DVDD pfet_06v0 m=1.0 w=24e-6 l=700e-9 nf=1.0 as=10.56e-12 ++ ad=10.56e-12 ps=48.88e-6 pd=48.88e-6 nrd=18.333e-3 nrs=18.333e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X123 n243 n26 DVDD DVDD pfet_06v0 m=1.0 w=12e-6 l=700e-9 nf=1.0 as=5.28e-12 ++ ad=5.28e-12 ps=24.88e-6 pd=24.88e-6 nrd=36.667e-3 nrs=36.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X124 n44 n248 DVDD DVDD pfet_06v0 m=1.0 w=24e-6 l=700e-9 nf=1.0 as=10.56e-12 ++ ad=10.56e-12 ps=48.88e-6 pd=48.88e-6 nrd=18.333e-3 nrs=18.333e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X125 n49 n243 DVDD DVDD pfet_06v0 m=1.0 w=24e-6 l=700e-9 nf=1.0 as=10.56e-12 ++ ad=10.56e-12 ps=48.88e-6 pd=48.88e-6 nrd=18.333e-3 nrs=18.333e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X126 n48 DVSS n49 DVDD pfet_06v0 m=1.0 w=1.2e-6 l=700e-9 nf=1.0 as=528e-15 ++ ad=528e-15 ps=3.28e-6 pd=3.28e-6 nrd=366.667e-3 nrs=366.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X127 n243 n32 DVDD DVDD pfet_06v0 m=1.0 w=12e-6 l=700e-9 nf=1.0 as=5.28e-12 ++ ad=5.28e-12 ps=24.88e-6 pd=24.88e-6 nrd=36.667e-3 nrs=36.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X128 n248 n27 n243 DVDD pfet_06v0 m=1.0 w=12e-6 l=700e-9 nf=1.0 as=5.28e-12 ++ ad=5.28e-12 ps=24.88e-6 pd=24.88e-6 nrd=36.667e-3 nrs=36.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X129 n39 n248 DVDD DVDD pfet_06v0 m=1.0 w=24e-6 l=700e-9 nf=1.0 as=10.56e-12 ++ ad=10.56e-12 ps=48.88e-6 pd=48.88e-6 nrd=18.333e-3 nrs=18.333e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X130 n268 n257 DVSS DVSS nfet_06v0 m=1.0 w=3e-6 l=700e-9 nf=2.0 as=1.32e-12 ++ ad=780e-15 ps=7.76e-6 pd=4.04e-6 nrd=86.667e-3 nrs=146.667e-3 sa=440e-9 ++ sb=440e-9 sd=520e-9 dtemp=0.0 par=1 +X131 n281 n6 VSS VSS nfet_06v0 m=1.0 w=1.5e-6 l=700e-9 nf=1.0 as=660e-15 ++ ad=660e-15 ps=3.88e-6 pd=3.88e-6 nrd=293.333e-3 nrs=293.333e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X132 n257 n281 DVSS DVSS nfet_06v0 m=1.0 w=3e-6 l=700e-9 nf=2.0 as=1.32e-12 ++ ad=780e-15 ps=7.76e-6 pd=4.04e-6 nrd=86.667e-3 nrs=146.667e-3 sa=440e-9 ++ sb=440e-9 sd=520e-9 dtemp=0.0 par=1 +X133 n268 n257 DVDD DVDD pfet_06v0 m=1.0 w=6e-6 l=700e-9 nf=2.0 as=2.64e-12 ++ ad=1.56e-12 ps=13.76e-6 pd=7.04e-6 nrd=43.333e-3 nrs=73.333e-3 sa=440e-9 ++ sb=440e-9 sd=520e-9 dtemp=0.0 par=1 +X134 n281 n6 VDD VDD pfet_06v0 m=1.0 w=3e-6 l=700e-9 nf=1.0 as=1.32e-12 ++ ad=1.32e-12 ps=6.88e-6 pd=6.88e-6 nrd=146.667e-3 nrs=146.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X135 n257 n281 DVDD DVDD pfet_06v0 m=1.0 w=6e-6 l=700e-9 nf=2.0 as=2.64e-12 ++ ad=1.56e-12 ps=13.76e-6 pd=7.04e-6 nrd=43.333e-3 nrs=73.333e-3 sa=440e-9 ++ sb=440e-9 sd=520e-9 dtemp=0.0 par=1 +X136 n274 n258 DVSS DVSS nfet_06v0 m=1.0 w=3e-6 l=700e-9 nf=2.0 as=1.32e-12 ++ ad=780e-15 ps=7.76e-6 pd=4.04e-6 nrd=86.667e-3 nrs=146.667e-3 sa=440e-9 ++ sb=440e-9 sd=520e-9 dtemp=0.0 par=1 +X137 n289 n0 VSS VSS nfet_06v0 m=1.0 w=1.5e-6 l=700e-9 nf=1.0 as=660e-15 ++ ad=660e-15 ps=3.88e-6 pd=3.88e-6 nrd=293.333e-3 nrs=293.333e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X138 n258 n289 DVSS DVSS nfet_06v0 m=1.0 w=3e-6 l=700e-9 nf=2.0 as=1.32e-12 ++ ad=780e-15 ps=7.76e-6 pd=4.04e-6 nrd=86.667e-3 nrs=146.667e-3 sa=440e-9 ++ sb=440e-9 sd=520e-9 dtemp=0.0 par=1 +X139 n274 n258 DVDD DVDD pfet_06v0 m=1.0 w=6e-6 l=700e-9 nf=2.0 as=2.64e-12 ++ ad=1.56e-12 ps=13.76e-6 pd=7.04e-6 nrd=43.333e-3 nrs=73.333e-3 sa=440e-9 ++ sb=440e-9 sd=520e-9 dtemp=0.0 par=1 +X140 n289 n0 VDD VDD pfet_06v0 m=1.0 w=3e-6 l=700e-9 nf=1.0 as=1.32e-12 ++ ad=1.32e-12 ps=6.88e-6 pd=6.88e-6 nrd=146.667e-3 nrs=146.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X141 n258 n289 DVDD DVDD pfet_06v0 m=1.0 w=6e-6 l=700e-9 nf=2.0 as=2.64e-12 ++ ad=1.56e-12 ps=13.76e-6 pd=7.04e-6 nrd=43.333e-3 nrs=73.333e-3 sa=440e-9 ++ sb=440e-9 sd=520e-9 dtemp=0.0 par=1 +X142 n272 n260 DVSS DVSS nfet_06v0 m=1.0 w=3e-6 l=700e-9 nf=2.0 as=1.32e-12 ++ ad=780e-15 ps=7.76e-6 pd=4.04e-6 nrd=86.667e-3 nrs=146.667e-3 sa=440e-9 ++ sb=440e-9 sd=520e-9 dtemp=0.0 par=1 +X143 n297 n261 VSS VSS nfet_06v0 m=1.0 w=1.5e-6 l=700e-9 nf=1.0 as=660e-15 ++ ad=660e-15 ps=3.88e-6 pd=3.88e-6 nrd=293.333e-3 nrs=293.333e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X144 n260 n297 DVSS DVSS nfet_06v0 m=1.0 w=3e-6 l=700e-9 nf=2.0 as=1.32e-12 ++ ad=780e-15 ps=7.76e-6 pd=4.04e-6 nrd=86.667e-3 nrs=146.667e-3 sa=440e-9 ++ sb=440e-9 sd=520e-9 dtemp=0.0 par=1 +X145 n272 n260 DVDD DVDD pfet_06v0 m=1.0 w=6e-6 l=700e-9 nf=2.0 as=2.64e-12 ++ ad=1.56e-12 ps=13.76e-6 pd=7.04e-6 nrd=43.333e-3 nrs=73.333e-3 sa=440e-9 ++ sb=440e-9 sd=520e-9 dtemp=0.0 par=1 +X146 n297 n261 VDD VDD pfet_06v0 m=1.0 w=3e-6 l=700e-9 nf=1.0 as=1.32e-12 ++ ad=1.32e-12 ps=6.88e-6 pd=6.88e-6 nrd=146.667e-3 nrs=146.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X147 n260 n297 DVDD DVDD pfet_06v0 m=1.0 w=6e-6 l=700e-9 nf=2.0 as=2.64e-12 ++ ad=1.56e-12 ps=13.76e-6 pd=7.04e-6 nrd=43.333e-3 nrs=73.333e-3 sa=440e-9 ++ sb=440e-9 sd=520e-9 dtemp=0.0 par=1 +X148 n276 n263 DVSS DVSS nfet_06v0 m=1.0 w=3e-6 l=700e-9 nf=2.0 as=1.32e-12 ++ ad=780e-15 ps=7.76e-6 pd=4.04e-6 nrd=86.667e-3 nrs=146.667e-3 sa=440e-9 ++ sb=440e-9 sd=520e-9 dtemp=0.0 par=1 +X149 n305 n259 VSS VSS nfet_06v0 m=1.0 w=1.5e-6 l=700e-9 nf=1.0 as=660e-15 ++ ad=660e-15 ps=3.88e-6 pd=3.88e-6 nrd=293.333e-3 nrs=293.333e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X150 n263 n305 DVSS DVSS nfet_06v0 m=1.0 w=3e-6 l=700e-9 nf=2.0 as=1.32e-12 ++ ad=780e-15 ps=7.76e-6 pd=4.04e-6 nrd=86.667e-3 nrs=146.667e-3 sa=440e-9 ++ sb=440e-9 sd=520e-9 dtemp=0.0 par=1 +X151 n276 n263 DVDD DVDD pfet_06v0 m=1.0 w=6e-6 l=700e-9 nf=2.0 as=2.64e-12 ++ ad=1.56e-12 ps=13.76e-6 pd=7.04e-6 nrd=43.333e-3 nrs=73.333e-3 sa=440e-9 ++ sb=440e-9 sd=520e-9 dtemp=0.0 par=1 +X152 n305 n259 VDD VDD pfet_06v0 m=1.0 w=3e-6 l=700e-9 nf=1.0 as=1.32e-12 ++ ad=1.32e-12 ps=6.88e-6 pd=6.88e-6 nrd=146.667e-3 nrs=146.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X153 n263 n305 DVDD DVDD pfet_06v0 m=1.0 w=6e-6 l=700e-9 nf=2.0 as=2.64e-12 ++ ad=1.56e-12 ps=13.76e-6 pd=7.04e-6 nrd=43.333e-3 nrs=73.333e-3 sa=440e-9 ++ sb=440e-9 sd=520e-9 dtemp=0.0 par=1 +D154 PD VDD diode_pd2nw_06v0 m=1.0 area=1e-12 pj=4e-6 +D155 n6 VDD diode_pd2nw_06v0 m=1.0 area=1e-12 pj=4e-6 +D156 n0 VDD diode_pd2nw_06v0 m=1.0 area=1e-12 pj=4e-6 +D157 PU VDD diode_pd2nw_06v0 m=1.0 area=1e-12 pj=4e-6 +X158 n313 n258 DVDD DVDD pfet_06v0 m=1.0 w=8e-6 l=700e-9 nf=1.0 as=3.52e-12 ++ ad=3.52e-12 ps=16.88e-6 pd=16.88e-6 nrd=55e-3 nrs=55e-3 sa=440e-9 sb=440e-9 ++ sd=0.0 dtemp=0.0 par=1 +X159 DVDD n258 n314 DVDD pfet_06v0 m=1.0 w=3e-6 l=700e-9 nf=1.0 as=1.32e-12 ++ ad=1.32e-12 ps=6.88e-6 pd=6.88e-6 nrd=146.667e-3 nrs=146.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X160 n315 n15 DVDD DVDD pfet_06v0 m=1.0 w=3.8e-6 l=700e-9 nf=1.0 as=1.672e-12 ++ ad=1.672e-12 ps=8.48e-6 pd=8.48e-6 nrd=115.789e-3 nrs=115.789e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X161 DVSS n314 n315 DVDD pfet_06v0 m=1.0 w=3.8e-6 l=700e-9 nf=1.0 as=1.672e-12 ++ ad=1.672e-12 ps=8.48e-6 pd=8.48e-6 nrd=115.789e-3 nrs=115.789e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X162 n275 n257 DVDD DVDD pfet_06v0 m=1.0 w=6e-6 l=700e-9 nf=1.0 as=2.64e-12 ++ ad=2.64e-12 ps=12.88e-6 pd=12.88e-6 nrd=73.333e-3 nrs=73.333e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X163 n275 n313 n310 DVDD pfet_06v0 m=1.0 w=2e-6 l=700e-9 nf=1.0 as=880e-15 ++ ad=880e-15 ps=4.88e-6 pd=4.88e-6 nrd=220e-3 nrs=220e-3 sa=440e-9 sb=440e-9 ++ sd=0.0 dtemp=0.0 par=1 +X164 n275 n313 n314 DVDD pfet_06v0 m=1.0 w=2e-6 l=700e-9 nf=1.0 as=880e-15 ++ ad=880e-15 ps=4.88e-6 pd=4.88e-6 nrd=220e-3 nrs=220e-3 sa=440e-9 sb=440e-9 ++ sd=0.0 dtemp=0.0 par=1 +X165 n275 n15 n315 DVDD pfet_06v0 m=1.0 w=4.3e-6 l=700e-9 nf=1.0 as=1.892e-12 ++ ad=1.892e-12 ps=9.48e-6 pd=9.48e-6 nrd=102.326e-3 nrs=102.326e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X166 n320 n257 DVSS DVSS nfet_06v0 m=1.0 w=16e-6 l=700e-9 nf=1.0 as=7.04e-12 ++ ad=7.04e-12 ps=32.88e-6 pd=32.88e-6 nrd=27.5e-3 nrs=27.5e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X167 n312 n15 n320 DVSS nfet_06v0 m=1.0 w=10.6e-6 l=700e-9 nf=1.0 as=4.664e-12 ++ ad=4.664e-12 ps=22.08e-6 pd=22.08e-6 nrd=41.509e-3 nrs=41.509e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X168 n275 n15 n312 DVSS nfet_06v0 m=1.0 w=12e-6 l=700e-9 nf=1.0 as=5.28e-12 ++ ad=5.28e-12 ps=24.88e-6 pd=24.88e-6 nrd=36.667e-3 nrs=36.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X169 n313 n258 DVSS DVSS nfet_06v0 m=1.0 w=4e-6 l=700e-9 nf=1.0 as=1.76e-12 ++ ad=1.76e-12 ps=8.88e-6 pd=8.88e-6 nrd=110e-3 nrs=110e-3 sa=440e-9 sb=440e-9 ++ sd=0.0 dtemp=0.0 par=1 +X170 n275 n258 n310 DVSS nfet_06v0 m=1.0 w=1.5e-6 l=700e-9 nf=1.0 as=660e-15 ++ ad=660e-15 ps=3.88e-6 pd=3.88e-6 nrd=293.333e-3 nrs=293.333e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X171 n275 n258 n314 DVSS nfet_06v0 m=1.0 w=1.5e-6 l=700e-9 nf=1.0 as=660e-15 ++ ad=660e-15 ps=3.88e-6 pd=3.88e-6 nrd=293.333e-3 nrs=293.333e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X172 DVDD n310 n312 DVSS nfet_06v0 m=1.0 w=1.3e-6 l=700e-9 nf=1.0 as=572e-15 ++ ad=572e-15 ps=3.48e-6 pd=3.48e-6 nrd=338.462e-3 nrs=338.462e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X173 DVSS n313 n310 DVSS nfet_06v0 m=1.0 w=1.5e-6 l=700e-9 nf=1.0 as=660e-15 ++ ad=660e-15 ps=3.88e-6 pd=3.88e-6 nrd=293.333e-3 nrs=293.333e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X174 n328 n275 DVDD DVDD pfet_06v0 m=1.0 w=2e-6 l=700e-9 nf=1.0 as=880e-15 ++ ad=880e-15 ps=4.88e-6 pd=4.88e-6 nrd=220e-3 nrs=220e-3 sa=440e-9 sb=440e-9 ++ sd=0.0 dtemp=0.0 par=1 +X175 n325 n328 VDD VDD pfet_06v0 m=1.0 w=10e-6 l=700e-9 nf=1.0 as=4.4e-12 ++ ad=4.4e-12 ps=20.88e-6 pd=20.88e-6 nrd=44e-3 nrs=44e-3 sa=440e-9 sb=440e-9 ++ sd=0.0 dtemp=0.0 par=1 +X176 Y n325 VDD VDD pfet_06v0 m=1.0 w=21e-6 l=700e-9 nf=1.0 as=9.24e-12 ++ ad=9.24e-12 ps=42.88e-6 pd=42.88e-6 nrd=20.952e-3 nrs=20.952e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X177 n328 n275 DVSS DVSS nfet_06v0 m=1.0 w=8e-6 l=700e-9 nf=1.0 as=3.52e-12 ++ ad=3.52e-12 ps=16.88e-6 pd=16.88e-6 nrd=55e-3 nrs=55e-3 sa=440e-9 sb=440e-9 ++ sd=0.0 dtemp=0.0 par=1 +X178 Y n325 VSS VSS nfet_06v0 m=1.0 w=9e-6 l=700e-9 nf=1.0 as=3.96e-12 ++ ad=3.96e-12 ps=18.88e-6 pd=18.88e-6 nrd=48.889e-3 nrs=48.889e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X179 n325 n328 VSS VSS nfet_06v0 m=1.0 w=2.5e-6 l=700e-9 nf=1.0 as=1.1e-12 ++ ad=1.1e-12 ps=5.88e-6 pd=5.88e-6 nrd=176e-3 nrs=176e-3 sa=440e-9 sb=440e-9 ++ sd=0.0 dtemp=0.0 par=1 +X180 n261 n335 VDD VDD pfet_06v0 m=1.0 w=3e-6 l=700e-9 nf=1.0 as=1.32e-12 ++ ad=1.32e-12 ps=6.88e-6 pd=6.88e-6 nrd=146.667e-3 nrs=146.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X181 n261 PU VDD VDD pfet_06v0 m=1.0 w=3e-6 l=700e-9 nf=1.0 as=1.32e-12 ++ ad=1.32e-12 ps=6.88e-6 pd=6.88e-6 nrd=146.667e-3 nrs=146.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X182 n336 PU VSS VSS nfet_06v0 m=1.0 w=3e-6 l=700e-9 nf=1.0 as=1.32e-12 ++ ad=1.32e-12 ps=6.88e-6 pd=6.88e-6 nrd=146.667e-3 nrs=146.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X183 n261 n335 n336 VSS nfet_06v0 m=1.0 w=3e-6 l=700e-9 nf=1.0 as=1.32e-12 ++ ad=1.32e-12 ps=6.88e-6 pd=6.88e-6 nrd=146.667e-3 nrs=146.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X184 n259 PD VDD VDD pfet_06v0 m=1.0 w=3e-6 l=700e-9 nf=1.0 as=1.32e-12 ++ ad=1.32e-12 ps=6.88e-6 pd=6.88e-6 nrd=146.667e-3 nrs=146.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X185 n259 n335 VDD VDD pfet_06v0 m=1.0 w=3e-6 l=700e-9 nf=1.0 as=1.32e-12 ++ ad=1.32e-12 ps=6.88e-6 pd=6.88e-6 nrd=146.667e-3 nrs=146.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X186 n342 n335 VSS VSS nfet_06v0 m=1.0 w=3e-6 l=700e-9 nf=1.0 as=1.32e-12 ++ ad=1.32e-12 ps=6.88e-6 pd=6.88e-6 nrd=146.667e-3 nrs=146.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X187 n259 PD n342 VSS nfet_06v0 m=1.0 w=3e-6 l=700e-9 nf=1.0 as=1.32e-12 ++ ad=1.32e-12 ps=6.88e-6 pd=6.88e-6 nrd=146.667e-3 nrs=146.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X188 n348 n354 n335 VDD pfet_06v0 m=1.0 w=3e-6 l=700e-9 nf=1.0 as=1.32e-12 ++ ad=1.32e-12 ps=6.88e-6 pd=6.88e-6 nrd=146.667e-3 nrs=146.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X189 PU PD n335 VDD pfet_06v0 m=1.0 w=3e-6 l=700e-9 nf=1.0 as=1.32e-12 ++ ad=1.32e-12 ps=6.88e-6 pd=6.88e-6 nrd=146.667e-3 nrs=146.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X190 n354 PD VDD VDD pfet_06v0 m=1.0 w=3e-6 l=700e-9 nf=1.0 as=1.32e-12 ++ ad=1.32e-12 ps=6.88e-6 pd=6.88e-6 nrd=146.667e-3 nrs=146.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X191 n348 PU VDD VDD pfet_06v0 m=1.0 w=3e-6 l=700e-9 nf=1.0 as=1.32e-12 ++ ad=1.32e-12 ps=6.88e-6 pd=6.88e-6 nrd=146.667e-3 nrs=146.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X192 n348 PD n335 VSS nfet_06v0 m=1.0 w=1.5e-6 l=700e-9 nf=1.0 as=660e-15 ++ ad=660e-15 ps=3.88e-6 pd=3.88e-6 nrd=293.333e-3 nrs=293.333e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X193 PU n354 n335 VSS nfet_06v0 m=1.0 w=1.5e-6 l=700e-9 nf=1.0 as=660e-15 ++ ad=660e-15 ps=3.88e-6 pd=3.88e-6 nrd=293.333e-3 nrs=293.333e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X194 n354 PD VSS VSS nfet_06v0 m=1.0 w=1.5e-6 l=700e-9 nf=1.0 as=660e-15 ++ ad=660e-15 ps=3.88e-6 pd=3.88e-6 nrd=293.333e-3 nrs=293.333e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X195 n348 PU VSS VSS nfet_06v0 m=1.0 w=1.5e-6 l=700e-9 nf=1.0 as=660e-15 ++ ad=660e-15 ps=3.88e-6 pd=3.88e-6 nrd=293.333e-3 nrs=293.333e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X196 n15 n357 DVDD ppolyf_u r_width=800e-9 r_length=23e-6 m=1.0 r=9.94533e3 par=1 +X197 n357 n356 DVDD ppolyf_u r_width=800e-9 r_length=35.7e-6 m=1.0 r=15.3065e3 par=1 +X198 n356 n355 DVDD ppolyf_u r_width=800e-9 r_length=35.7e-6 m=1.0 r=15.3065e3 par=1 +X199 n355 n358 DVDD ppolyf_u r_width=800e-9 r_length=35.7e-6 m=1.0 r=15.3065e3 par=1 +X200 n358 n363 DVDD ppolyf_u r_width=800e-9 r_length=35.7e-6 m=1.0 r=15.3065e3 par=1 +X201 n363 n362 DVDD ppolyf_u r_width=800e-9 r_length=35.7e-6 m=1.0 r=15.3065e3 par=1 +X202 n362 n359 DVDD ppolyf_u r_width=800e-9 r_length=35.7e-6 m=1.0 r=15.3065e3 par=1 +X203 n359 n360 DVDD ppolyf_u r_width=800e-9 r_length=35.7e-6 m=1.0 r=15.3065e3 par=1 +X204 n360 n276 DVSS DVSS nfet_06v0 m=1.0 w=1.5e-6 l=700e-9 nf=1.0 as=660e-15 ++ ad=660e-15 ps=3.88e-6 pd=3.88e-6 nrd=293.333e-3 nrs=293.333e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X205 n360 n260 DVDD DVDD pfet_06v0 m=1.0 w=3e-6 l=700e-9 nf=1.0 as=1.32e-12 ++ ad=1.32e-12 ps=6.88e-6 pd=6.88e-6 nrd=146.667e-3 nrs=146.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +D206 DVSS n15 diode_nd2ps_06v0 m=2.0 area=20e-12 pj=42e-6 +D207 n15 DVDD diode_pd2nw_06v0 m=2.0 area=20e-12 pj=42e-6 +X208 PAD n15 DVDD ppolyf_u r_width=2.5e-6 r_length=2.8e-6 m=1.0 r=432.59 par=1 +X209 PAD n15 DVDD ppolyf_u r_width=2.5e-6 r_length=2.8e-6 m=1.0 r=449.157 par=1 +X210 PAD n15 DVDD ppolyf_u r_width=2.5e-6 r_length=2.8e-6 m=1.0 r=432.59 par=1 +X211 PAD n15 DVDD ppolyf_u r_width=2.5e-6 r_length=2.8e-6 m=1.0 r=449.157 par=1 +.ENDS + + +******* EOF + +* Copyright 2022 GlobalFoundries PDK Authors +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. + +.SUBCKT gf180mcu_fd_io__in_s DVDD DVSS PAD PD PU VDD VSS Y +X0 DVDD DVSS cap_nmos_06v0 m=8.0 c_length=1.5e-6 c_width=5e-6 +X1 DVDD DVSS cap_nmos_06v0 m=4.0 c_length=3e-6 c_width=3e-6 +X2 n6 VSS VDD ppolyf_u r_width=800e-9 r_length=3.9e-6 m=1.0 r=1.88247e3 par=1 +X3 VDD n1 VDD ppolyf_u r_width=800e-9 r_length=3.9e-6 m=1.0 r=1.88247e3 par=1 +X4 n62 n70 DVSS DVSS nfet_06v0 m=1.0 w=3e-6 l=700e-9 nf=1.0 as=1.32e-12 ad=1.32e-12 ++ ps=6.88e-6 pd=6.88e-6 nrd=146.667e-3 nrs=146.667e-3 sa=440e-9 sb=440e-9 ++ sd=0.0 dtemp=0.0 par=1 +X5 n32 n62 DVSS DVSS nfet_06v0 m=1.0 w=3e-6 l=700e-9 nf=1.0 as=1.32e-12 ad=1.32e-12 ++ ps=6.88e-6 pd=6.88e-6 nrd=146.667e-3 nrs=146.667e-3 sa=440e-9 sb=440e-9 ++ sd=0.0 dtemp=0.0 par=1 +X6 n67 n6 VSS VSS nfet_06v0 m=1.0 w=3e-6 l=700e-9 nf=1.0 as=1.32e-12 ad=1.32e-12 ++ ps=6.88e-6 pd=6.88e-6 nrd=146.667e-3 nrs=146.667e-3 sa=440e-9 sb=440e-9 ++ sd=0.0 dtemp=0.0 par=1 +X7 n70 n6 n67 VSS nfet_06v0 m=1.0 w=3e-6 l=700e-9 nf=1.0 as=1.32e-12 ad=1.32e-12 ++ ps=6.88e-6 pd=6.88e-6 nrd=146.667e-3 nrs=146.667e-3 sa=440e-9 sb=440e-9 ++ sd=0.0 dtemp=0.0 par=1 +X8 n62 n70 DVDD DVDD pfet_06v0 m=1.0 w=6e-6 l=700e-9 nf=1.0 as=2.64e-12 ad=2.64e-12 ++ ps=12.88e-6 pd=12.88e-6 nrd=73.333e-3 nrs=73.333e-3 sa=440e-9 sb=440e-9 ++ sd=0.0 dtemp=0.0 par=1 +X9 n32 n62 DVDD DVDD pfet_06v0 m=1.0 w=6e-6 l=700e-9 nf=1.0 as=2.64e-12 ad=2.64e-12 ++ ps=12.88e-6 pd=12.88e-6 nrd=73.333e-3 nrs=73.333e-3 sa=440e-9 sb=440e-9 ++ sd=0.0 dtemp=0.0 par=1 +X10 n70 n6 VDD VDD pfet_06v0 m=1.0 w=3e-6 l=700e-9 nf=1.0 as=1.32e-12 ad=1.32e-12 ++ ps=6.88e-6 pd=6.88e-6 nrd=146.667e-3 nrs=146.667e-3 sa=440e-9 sb=440e-9 ++ sd=0.0 dtemp=0.0 par=1 +X11 n70 n6 VDD VDD pfet_06v0 m=1.0 w=3e-6 l=700e-9 nf=1.0 as=1.32e-12 ad=1.32e-12 ++ ps=6.88e-6 pd=6.88e-6 nrd=146.667e-3 nrs=146.667e-3 sa=440e-9 sb=440e-9 ++ sd=0.0 dtemp=0.0 par=1 +X12 PAD n38 DVDD DVDD pfet_06v0_dss m=1.0 w=80e-6 l=700e-9 nf=2.0 s_sab=280e-9 ++ d_sab=2.78e-6 par=1 dtemp=0.0 +X13 PAD n50 DVSS DVSS nfet_06v0_dss m=1.0 w=38e-6 l=1.15e-6 nf=1.0 s_sab=280e-9 ++ d_sab=3.78e-6 par=1 dtemp=0.0 +X14 PAD n47 DVSS DVSS nfet_06v0_dss m=1.0 w=38e-6 l=1.15e-6 nf=1.0 s_sab=280e-9 ++ d_sab=3.78e-6 par=1 dtemp=0.0 +X15 PAD n43 DVDD DVDD pfet_06v0_dss m=1.0 w=40e-6 l=700e-9 nf=1.0 s_sab=280e-9 ++ d_sab=2.78e-6 par=1 dtemp=0.0 +X16 PAD n37 DVDD DVDD pfet_06v0_dss m=1.0 w=80e-6 l=700e-9 nf=2.0 s_sab=280e-9 ++ d_sab=2.78e-6 par=1 dtemp=0.0 +X17 PAD n51 DVSS DVSS nfet_06v0_dss m=1.0 w=38e-6 l=1.15e-6 nf=1.0 s_sab=280e-9 ++ d_sab=3.78e-6 par=1 dtemp=0.0 +X18 PAD n46 DVSS DVSS nfet_06v0_dss m=1.0 w=38e-6 l=1.15e-6 nf=1.0 s_sab=280e-9 ++ d_sab=3.78e-6 par=1 dtemp=0.0 +X19 PAD n42 DVDD DVDD pfet_06v0_dss m=1.0 w=40e-6 l=700e-9 nf=1.0 s_sab=280e-9 ++ d_sab=2.78e-6 par=1 dtemp=0.0 +X20 PAD n39 DVDD DVDD pfet_06v0_dss m=1.0 w=80e-6 l=700e-9 nf=2.0 s_sab=280e-9 ++ d_sab=2.78e-6 par=1 dtemp=0.0 +X21 PAD n49 DVSS DVSS nfet_06v0_dss m=1.0 w=38e-6 l=1.15e-6 nf=1.0 s_sab=280e-9 ++ d_sab=3.78e-6 par=1 dtemp=0.0 +X22 PAD n48 DVSS DVSS nfet_06v0_dss m=1.0 w=38e-6 l=1.15e-6 nf=1.0 s_sab=280e-9 ++ d_sab=3.78e-6 par=1 dtemp=0.0 +X23 PAD n44 DVDD DVDD pfet_06v0_dss m=1.0 w=40e-6 l=700e-9 nf=1.0 s_sab=280e-9 ++ d_sab=2.78e-6 par=1 dtemp=0.0 +X24 PAD n40 DVDD DVDD pfet_06v0_dss m=1.0 w=80e-6 l=700e-9 nf=2.0 s_sab=280e-9 ++ d_sab=2.78e-6 par=1 dtemp=0.0 +X25 PAD n52 DVSS DVSS nfet_06v0_dss m=1.0 w=38e-6 l=1.15e-6 nf=1.0 s_sab=280e-9 ++ d_sab=3.78e-6 par=1 dtemp=0.0 +X26 PAD n45 DVSS DVSS nfet_06v0_dss m=1.0 w=38e-6 l=1.15e-6 nf=1.0 s_sab=280e-9 ++ d_sab=3.78e-6 par=1 dtemp=0.0 +X27 PAD n41 DVDD DVDD pfet_06v0_dss m=1.0 w=40e-6 l=700e-9 nf=1.0 s_sab=280e-9 ++ d_sab=2.78e-6 par=1 dtemp=0.0 +X28 n53 n36 DVSS DVSS nfet_06v0 m=1.0 w=3e-6 l=700e-9 nf=2.0 as=1.32e-12 ad=780e-15 ++ ps=7.76e-6 pd=4.04e-6 nrd=86.667e-3 nrs=146.667e-3 sa=440e-9 sb=440e-9 ++ sd=520e-9 dtemp=0.0 par=1 +X29 n170 n6 VSS VSS nfet_06v0 m=1.0 w=1.5e-6 l=700e-9 nf=1.0 as=660e-15 ++ ad=660e-15 ps=3.88e-6 pd=3.88e-6 nrd=293.333e-3 nrs=293.333e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X30 n36 n170 DVSS DVSS nfet_06v0 m=1.0 w=3e-6 l=700e-9 nf=2.0 as=1.32e-12 ++ ad=780e-15 ps=7.76e-6 pd=4.04e-6 nrd=86.667e-3 nrs=146.667e-3 sa=440e-9 ++ sb=440e-9 sd=520e-9 dtemp=0.0 par=1 +X31 n53 n36 DVDD DVDD pfet_06v0 m=1.0 w=6e-6 l=700e-9 nf=2.0 as=2.64e-12 ++ ad=1.56e-12 ps=13.76e-6 pd=7.04e-6 nrd=43.333e-3 nrs=73.333e-3 sa=440e-9 ++ sb=440e-9 sd=520e-9 dtemp=0.0 par=1 +X32 n170 n6 VDD VDD pfet_06v0 m=1.0 w=3e-6 l=700e-9 nf=1.0 as=1.32e-12 ++ ad=1.32e-12 ps=6.88e-6 pd=6.88e-6 nrd=146.667e-3 nrs=146.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X33 n36 n170 DVDD DVDD pfet_06v0 m=1.0 w=6e-6 l=700e-9 nf=2.0 as=2.64e-12 ++ ad=1.56e-12 ps=13.76e-6 pd=7.04e-6 nrd=43.333e-3 nrs=73.333e-3 sa=440e-9 ++ sb=440e-9 sd=520e-9 dtemp=0.0 par=1 +D34 n6 VDD diode_pd2nw_06v0 m=1.0 area=1e-12 pj=4e-6 +D35 n6 VDD diode_pd2nw_06v0 m=1.0 area=1e-12 pj=4e-6 +D36 VSS n6 diode_pd2nw_06v0 m=1.0 area=230.4e-15 pj=1.92e-6 +D37 VSS n6 diode_pd2nw_06v0 m=1.0 area=230.4e-15 pj=1.92e-6 +X38 n183 n6 VSS VSS nfet_06v0 m=1.0 w=3e-6 l=700e-9 nf=1.0 as=1.32e-12 ++ ad=1.32e-12 ps=6.88e-6 pd=6.88e-6 nrd=146.667e-3 nrs=146.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X39 n174 n6 n183 VSS nfet_06v0 m=1.0 w=3e-6 l=700e-9 nf=1.0 as=1.32e-12 ++ ad=1.32e-12 ps=6.88e-6 pd=6.88e-6 nrd=146.667e-3 nrs=146.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X40 n34 n31 DVSS DVSS nfet_06v0 m=1.0 w=3e-6 l=700e-9 nf=1.0 as=1.32e-12 ++ ad=1.32e-12 ps=6.88e-6 pd=6.88e-6 nrd=146.667e-3 nrs=146.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X41 n31 n174 DVSS DVSS nfet_06v0 m=1.0 w=3e-6 l=700e-9 nf=1.0 as=1.32e-12 ++ ad=1.32e-12 ps=6.88e-6 pd=6.88e-6 nrd=146.667e-3 nrs=146.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X42 n174 n6 VDD VDD pfet_06v0 m=1.0 w=3e-6 l=700e-9 nf=1.0 as=1.32e-12 ++ ad=1.32e-12 ps=6.88e-6 pd=6.88e-6 nrd=146.667e-3 nrs=146.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X43 n174 n6 VDD VDD pfet_06v0 m=1.0 w=3e-6 l=700e-9 nf=1.0 as=1.32e-12 ++ ad=1.32e-12 ps=6.88e-6 pd=6.88e-6 nrd=146.667e-3 nrs=146.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X44 n34 n31 DVDD DVDD pfet_06v0 m=1.0 w=6e-6 l=700e-9 nf=1.0 as=2.64e-12 ++ ad=2.64e-12 ps=12.88e-6 pd=12.88e-6 nrd=73.333e-3 nrs=73.333e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X45 n31 n174 DVDD DVDD pfet_06v0 m=1.0 w=6e-6 l=700e-9 nf=1.0 as=2.64e-12 ++ ad=2.64e-12 ps=12.88e-6 pd=12.88e-6 nrd=73.333e-3 nrs=73.333e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +D46 VSS n6 diode_pd2nw_06v0 m=1.0 area=230.4e-15 pj=1.92e-6 +D47 VSS n6 diode_pd2nw_06v0 m=1.0 area=230.4e-15 pj=1.92e-6 +X48 n193 n6 VSS VSS nfet_06v0 m=1.0 w=3e-6 l=700e-9 nf=1.0 as=1.32e-12 ++ ad=1.32e-12 ps=6.88e-6 pd=6.88e-6 nrd=146.667e-3 nrs=146.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X49 n184 n6 n193 VSS nfet_06v0 m=1.0 w=3e-6 l=700e-9 nf=1.0 as=1.32e-12 ++ ad=1.32e-12 ps=6.88e-6 pd=6.88e-6 nrd=146.667e-3 nrs=146.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X50 n30 n28 DVSS DVSS nfet_06v0 m=1.0 w=3e-6 l=700e-9 nf=1.0 as=1.32e-12 ++ ad=1.32e-12 ps=6.88e-6 pd=6.88e-6 nrd=146.667e-3 nrs=146.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X51 n28 n184 DVSS DVSS nfet_06v0 m=1.0 w=3e-6 l=700e-9 nf=1.0 as=1.32e-12 ++ ad=1.32e-12 ps=6.88e-6 pd=6.88e-6 nrd=146.667e-3 nrs=146.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X52 n184 n6 VDD VDD pfet_06v0 m=1.0 w=3e-6 l=700e-9 nf=1.0 as=1.32e-12 ++ ad=1.32e-12 ps=6.88e-6 pd=6.88e-6 nrd=146.667e-3 nrs=146.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X53 n184 n6 VDD VDD pfet_06v0 m=1.0 w=3e-6 l=700e-9 nf=1.0 as=1.32e-12 ++ ad=1.32e-12 ps=6.88e-6 pd=6.88e-6 nrd=146.667e-3 nrs=146.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X54 n30 n28 DVDD DVDD pfet_06v0 m=1.0 w=6e-6 l=700e-9 nf=1.0 as=2.64e-12 ++ ad=2.64e-12 ps=12.88e-6 pd=12.88e-6 nrd=73.333e-3 nrs=73.333e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X55 n28 n184 DVDD DVDD pfet_06v0 m=1.0 w=6e-6 l=700e-9 nf=1.0 as=2.64e-12 ++ ad=2.64e-12 ps=12.88e-6 pd=12.88e-6 nrd=73.333e-3 nrs=73.333e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +D56 VSS VDD diode_pd2nw_06v0 m=1.0 area=230.4e-15 pj=1.92e-6 +D57 VSS n6 diode_pd2nw_06v0 m=1.0 area=230.4e-15 pj=1.92e-6 +X58 n203 VDD VSS VSS nfet_06v0 m=1.0 w=3e-6 l=700e-9 nf=1.0 as=1.32e-12 ++ ad=1.32e-12 ps=6.88e-6 pd=6.88e-6 nrd=146.667e-3 nrs=146.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X59 n194 n6 n203 VSS nfet_06v0 m=1.0 w=3e-6 l=700e-9 nf=1.0 as=1.32e-12 ++ ad=1.32e-12 ps=6.88e-6 pd=6.88e-6 nrd=146.667e-3 nrs=146.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X60 n27 n26 DVSS DVSS nfet_06v0 m=1.0 w=3e-6 l=700e-9 nf=1.0 as=1.32e-12 ++ ad=1.32e-12 ps=6.88e-6 pd=6.88e-6 nrd=146.667e-3 nrs=146.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X61 n26 n194 DVSS DVSS nfet_06v0 m=1.0 w=3e-6 l=700e-9 nf=1.0 as=1.32e-12 ++ ad=1.32e-12 ps=6.88e-6 pd=6.88e-6 nrd=146.667e-3 nrs=146.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X62 n194 VDD VDD VDD pfet_06v0 m=1.0 w=3e-6 l=700e-9 nf=1.0 as=1.32e-12 ++ ad=1.32e-12 ps=6.88e-6 pd=6.88e-6 nrd=146.667e-3 nrs=146.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X63 n194 n6 VDD VDD pfet_06v0 m=1.0 w=3e-6 l=700e-9 nf=1.0 as=1.32e-12 ++ ad=1.32e-12 ps=6.88e-6 pd=6.88e-6 nrd=146.667e-3 nrs=146.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X64 n27 n26 DVDD DVDD pfet_06v0 m=1.0 w=6e-6 l=700e-9 nf=1.0 as=2.64e-12 ++ ad=2.64e-12 ps=12.88e-6 pd=12.88e-6 nrd=73.333e-3 nrs=73.333e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X65 n26 n194 DVDD DVDD pfet_06v0 m=1.0 w=6e-6 l=700e-9 nf=1.0 as=2.64e-12 ++ ad=2.64e-12 ps=12.88e-6 pd=12.88e-6 nrd=73.333e-3 nrs=73.333e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X66 n41 n53 n40 DVSS nfet_06v0 m=1.0 w=12e-6 l=700e-9 nf=1.0 as=5.28e-12 ++ ad=5.28e-12 ps=24.88e-6 pd=24.88e-6 nrd=36.667e-3 nrs=36.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X67 n40 DVDD n41 DVSS nfet_06v0 m=1.0 w=1.2e-6 l=700e-9 nf=1.0 as=528e-15 ++ ad=528e-15 ps=3.28e-6 pd=3.28e-6 nrd=366.667e-3 nrs=366.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X68 n45 n204 DVSS DVSS nfet_06v0 m=1.0 w=12e-6 l=700e-9 nf=1.0 as=5.28e-12 ++ ad=5.28e-12 ps=24.88e-6 pd=24.88e-6 nrd=36.667e-3 nrs=36.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X69 n52 n204 DVSS DVSS nfet_06v0 m=1.0 w=12e-6 l=700e-9 nf=1.0 as=5.28e-12 ++ ad=5.28e-12 ps=24.88e-6 pd=24.88e-6 nrd=36.667e-3 nrs=36.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X70 n41 n209 DVSS DVSS nfet_06v0 m=1.0 w=12e-6 l=700e-9 nf=1.0 as=5.28e-12 ++ ad=5.28e-12 ps=24.88e-6 pd=24.88e-6 nrd=36.667e-3 nrs=36.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X71 n209 n32 DVSS DVSS nfet_06v0 m=1.0 w=6e-6 l=700e-9 nf=1.0 as=2.64e-12 ++ ad=2.64e-12 ps=12.88e-6 pd=12.88e-6 nrd=73.333e-3 nrs=73.333e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X72 n209 n34 DVSS DVSS nfet_06v0 m=1.0 w=6e-6 l=700e-9 nf=1.0 as=2.64e-12 ++ ad=2.64e-12 ps=12.88e-6 pd=12.88e-6 nrd=73.333e-3 nrs=73.333e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X73 n204 n31 n209 DVSS nfet_06v0 m=1.0 w=6e-6 l=700e-9 nf=1.0 as=2.64e-12 ++ ad=2.64e-12 ps=12.88e-6 pd=12.88e-6 nrd=73.333e-3 nrs=73.333e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X74 n45 n36 n52 DVDD pfet_06v0 m=1.0 w=24e-6 l=700e-9 nf=1.0 as=10.56e-12 ++ ad=10.56e-12 ps=48.88e-6 pd=48.88e-6 nrd=18.333e-3 nrs=18.333e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X75 n204 n31 DVDD DVDD pfet_06v0 m=1.0 w=12e-6 l=700e-9 nf=1.0 as=5.28e-12 ++ ad=5.28e-12 ps=24.88e-6 pd=24.88e-6 nrd=36.667e-3 nrs=36.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X76 n41 n209 DVDD DVDD pfet_06v0 m=1.0 w=24e-6 l=700e-9 nf=1.0 as=10.56e-12 ++ ad=10.56e-12 ps=48.88e-6 pd=48.88e-6 nrd=18.333e-3 nrs=18.333e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X77 n52 n204 DVDD DVDD pfet_06v0 m=1.0 w=24e-6 l=700e-9 nf=1.0 as=10.56e-12 ++ ad=10.56e-12 ps=48.88e-6 pd=48.88e-6 nrd=18.333e-3 nrs=18.333e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X78 n45 DVSS n52 DVDD pfet_06v0 m=1.0 w=1.2e-6 l=700e-9 nf=1.0 as=528e-15 ++ ad=528e-15 ps=3.28e-6 pd=3.28e-6 nrd=366.667e-3 nrs=366.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X79 n204 n32 DVDD DVDD pfet_06v0 m=1.0 w=12e-6 l=700e-9 nf=1.0 as=5.28e-12 ++ ad=5.28e-12 ps=24.88e-6 pd=24.88e-6 nrd=36.667e-3 nrs=36.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X80 n209 n34 n204 DVDD pfet_06v0 m=1.0 w=12e-6 l=700e-9 nf=1.0 as=5.28e-12 ++ ad=5.28e-12 ps=24.88e-6 pd=24.88e-6 nrd=36.667e-3 nrs=36.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X81 n40 n209 DVDD DVDD pfet_06v0 m=1.0 w=24e-6 l=700e-9 nf=1.0 as=10.56e-12 ++ ad=10.56e-12 ps=48.88e-6 pd=48.88e-6 nrd=18.333e-3 nrs=18.333e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X82 n42 n53 n37 DVSS nfet_06v0 m=1.0 w=12e-6 l=700e-9 nf=1.0 as=5.28e-12 ++ ad=5.28e-12 ps=24.88e-6 pd=24.88e-6 nrd=36.667e-3 nrs=36.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X83 n37 DVDD n42 DVSS nfet_06v0 m=1.0 w=1.2e-6 l=700e-9 nf=1.0 as=528e-15 ++ ad=528e-15 ps=3.28e-6 pd=3.28e-6 nrd=366.667e-3 nrs=366.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X84 n46 n217 DVSS DVSS nfet_06v0 m=1.0 w=12e-6 l=700e-9 nf=1.0 as=5.28e-12 ++ ad=5.28e-12 ps=24.88e-6 pd=24.88e-6 nrd=36.667e-3 nrs=36.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X85 n51 n217 DVSS DVSS nfet_06v0 m=1.0 w=12e-6 l=700e-9 nf=1.0 as=5.28e-12 ++ ad=5.28e-12 ps=24.88e-6 pd=24.88e-6 nrd=36.667e-3 nrs=36.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X86 n42 n222 DVSS DVSS nfet_06v0 m=1.0 w=12e-6 l=700e-9 nf=1.0 as=5.28e-12 ++ ad=5.28e-12 ps=24.88e-6 pd=24.88e-6 nrd=36.667e-3 nrs=36.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X87 n222 n32 DVSS DVSS nfet_06v0 m=1.0 w=6e-6 l=700e-9 nf=1.0 as=2.64e-12 ++ ad=2.64e-12 ps=12.88e-6 pd=12.88e-6 nrd=73.333e-3 nrs=73.333e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X88 n222 n30 DVSS DVSS nfet_06v0 m=1.0 w=6e-6 l=700e-9 nf=1.0 as=2.64e-12 ++ ad=2.64e-12 ps=12.88e-6 pd=12.88e-6 nrd=73.333e-3 nrs=73.333e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X89 n217 n28 n222 DVSS nfet_06v0 m=1.0 w=6e-6 l=700e-9 nf=1.0 as=2.64e-12 ++ ad=2.64e-12 ps=12.88e-6 pd=12.88e-6 nrd=73.333e-3 nrs=73.333e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X90 n46 n36 n51 DVDD pfet_06v0 m=1.0 w=24e-6 l=700e-9 nf=1.0 as=10.56e-12 ++ ad=10.56e-12 ps=48.88e-6 pd=48.88e-6 nrd=18.333e-3 nrs=18.333e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X91 n217 n28 DVDD DVDD pfet_06v0 m=1.0 w=12e-6 l=700e-9 nf=1.0 as=5.28e-12 ++ ad=5.28e-12 ps=24.88e-6 pd=24.88e-6 nrd=36.667e-3 nrs=36.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X92 n42 n222 DVDD DVDD pfet_06v0 m=1.0 w=24e-6 l=700e-9 nf=1.0 as=10.56e-12 ++ ad=10.56e-12 ps=48.88e-6 pd=48.88e-6 nrd=18.333e-3 nrs=18.333e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X93 n51 n217 DVDD DVDD pfet_06v0 m=1.0 w=24e-6 l=700e-9 nf=1.0 as=10.56e-12 ++ ad=10.56e-12 ps=48.88e-6 pd=48.88e-6 nrd=18.333e-3 nrs=18.333e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X94 n46 DVSS n51 DVDD pfet_06v0 m=1.0 w=1.2e-6 l=700e-9 nf=1.0 as=528e-15 ++ ad=528e-15 ps=3.28e-6 pd=3.28e-6 nrd=366.667e-3 nrs=366.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X95 n217 n32 DVDD DVDD pfet_06v0 m=1.0 w=12e-6 l=700e-9 nf=1.0 as=5.28e-12 ++ ad=5.28e-12 ps=24.88e-6 pd=24.88e-6 nrd=36.667e-3 nrs=36.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X96 n222 n30 n217 DVDD pfet_06v0 m=1.0 w=12e-6 l=700e-9 nf=1.0 as=5.28e-12 ++ ad=5.28e-12 ps=24.88e-6 pd=24.88e-6 nrd=36.667e-3 nrs=36.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X97 n37 n222 DVDD DVDD pfet_06v0 m=1.0 w=24e-6 l=700e-9 nf=1.0 as=10.56e-12 ++ ad=10.56e-12 ps=48.88e-6 pd=48.88e-6 nrd=18.333e-3 nrs=18.333e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X98 n43 n53 n38 DVSS nfet_06v0 m=1.0 w=12e-6 l=700e-9 nf=1.0 as=5.28e-12 ++ ad=5.28e-12 ps=24.88e-6 pd=24.88e-6 nrd=36.667e-3 nrs=36.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X99 n38 DVDD n43 DVSS nfet_06v0 m=1.0 w=1.2e-6 l=700e-9 nf=1.0 as=528e-15 ++ ad=528e-15 ps=3.28e-6 pd=3.28e-6 nrd=366.667e-3 nrs=366.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X100 n47 n230 DVSS DVSS nfet_06v0 m=1.0 w=12e-6 l=700e-9 nf=1.0 as=5.28e-12 ++ ad=5.28e-12 ps=24.88e-6 pd=24.88e-6 nrd=36.667e-3 nrs=36.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X101 n50 n230 DVSS DVSS nfet_06v0 m=1.0 w=12e-6 l=700e-9 nf=1.0 as=5.28e-12 ++ ad=5.28e-12 ps=24.88e-6 pd=24.88e-6 nrd=36.667e-3 nrs=36.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X102 n43 n235 DVSS DVSS nfet_06v0 m=1.0 w=12e-6 l=700e-9 nf=1.0 as=5.28e-12 ++ ad=5.28e-12 ps=24.88e-6 pd=24.88e-6 nrd=36.667e-3 nrs=36.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X103 n235 n32 DVSS DVSS nfet_06v0 m=1.0 w=6e-6 l=700e-9 nf=1.0 as=2.64e-12 ++ ad=2.64e-12 ps=12.88e-6 pd=12.88e-6 nrd=73.333e-3 nrs=73.333e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X104 n235 n30 DVSS DVSS nfet_06v0 m=1.0 w=6e-6 l=700e-9 nf=1.0 as=2.64e-12 ++ ad=2.64e-12 ps=12.88e-6 pd=12.88e-6 nrd=73.333e-3 nrs=73.333e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X105 n230 n28 n235 DVSS nfet_06v0 m=1.0 w=6e-6 l=700e-9 nf=1.0 as=2.64e-12 ++ ad=2.64e-12 ps=12.88e-6 pd=12.88e-6 nrd=73.333e-3 nrs=73.333e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X106 n47 n36 n50 DVDD pfet_06v0 m=1.0 w=24e-6 l=700e-9 nf=1.0 as=10.56e-12 ++ ad=10.56e-12 ps=48.88e-6 pd=48.88e-6 nrd=18.333e-3 nrs=18.333e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X107 n230 n28 DVDD DVDD pfet_06v0 m=1.0 w=12e-6 l=700e-9 nf=1.0 as=5.28e-12 ++ ad=5.28e-12 ps=24.88e-6 pd=24.88e-6 nrd=36.667e-3 nrs=36.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X108 n43 n235 DVDD DVDD pfet_06v0 m=1.0 w=24e-6 l=700e-9 nf=1.0 as=10.56e-12 ++ ad=10.56e-12 ps=48.88e-6 pd=48.88e-6 nrd=18.333e-3 nrs=18.333e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X109 n50 n230 DVDD DVDD pfet_06v0 m=1.0 w=24e-6 l=700e-9 nf=1.0 as=10.56e-12 ++ ad=10.56e-12 ps=48.88e-6 pd=48.88e-6 nrd=18.333e-3 nrs=18.333e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X110 n47 DVSS n50 DVDD pfet_06v0 m=1.0 w=1.2e-6 l=700e-9 nf=1.0 as=528e-15 ++ ad=528e-15 ps=3.28e-6 pd=3.28e-6 nrd=366.667e-3 nrs=366.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X111 n230 n32 DVDD DVDD pfet_06v0 m=1.0 w=12e-6 l=700e-9 nf=1.0 as=5.28e-12 ++ ad=5.28e-12 ps=24.88e-6 pd=24.88e-6 nrd=36.667e-3 nrs=36.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X112 n235 n30 n230 DVDD pfet_06v0 m=1.0 w=12e-6 l=700e-9 nf=1.0 as=5.28e-12 ++ ad=5.28e-12 ps=24.88e-6 pd=24.88e-6 nrd=36.667e-3 nrs=36.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X113 n38 n235 DVDD DVDD pfet_06v0 m=1.0 w=24e-6 l=700e-9 nf=1.0 as=10.56e-12 ++ ad=10.56e-12 ps=48.88e-6 pd=48.88e-6 nrd=18.333e-3 nrs=18.333e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X114 n44 n53 n39 DVSS nfet_06v0 m=1.0 w=12e-6 l=700e-9 nf=1.0 as=5.28e-12 ++ ad=5.28e-12 ps=24.88e-6 pd=24.88e-6 nrd=36.667e-3 nrs=36.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X115 n39 DVDD n44 DVSS nfet_06v0 m=1.0 w=1.2e-6 l=700e-9 nf=1.0 as=528e-15 ++ ad=528e-15 ps=3.28e-6 pd=3.28e-6 nrd=366.667e-3 nrs=366.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X116 n48 n243 DVSS DVSS nfet_06v0 m=1.0 w=12e-6 l=700e-9 nf=1.0 as=5.28e-12 ++ ad=5.28e-12 ps=24.88e-6 pd=24.88e-6 nrd=36.667e-3 nrs=36.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X117 n49 n243 DVSS DVSS nfet_06v0 m=1.0 w=12e-6 l=700e-9 nf=1.0 as=5.28e-12 ++ ad=5.28e-12 ps=24.88e-6 pd=24.88e-6 nrd=36.667e-3 nrs=36.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X118 n44 n248 DVSS DVSS nfet_06v0 m=1.0 w=12e-6 l=700e-9 nf=1.0 as=5.28e-12 ++ ad=5.28e-12 ps=24.88e-6 pd=24.88e-6 nrd=36.667e-3 nrs=36.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X119 n248 n32 DVSS DVSS nfet_06v0 m=1.0 w=6e-6 l=700e-9 nf=1.0 as=2.64e-12 ++ ad=2.64e-12 ps=12.88e-6 pd=12.88e-6 nrd=73.333e-3 nrs=73.333e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X120 n248 n27 DVSS DVSS nfet_06v0 m=1.0 w=6e-6 l=700e-9 nf=1.0 as=2.64e-12 ++ ad=2.64e-12 ps=12.88e-6 pd=12.88e-6 nrd=73.333e-3 nrs=73.333e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X121 n243 n26 n248 DVSS nfet_06v0 m=1.0 w=6e-6 l=700e-9 nf=1.0 as=2.64e-12 ++ ad=2.64e-12 ps=12.88e-6 pd=12.88e-6 nrd=73.333e-3 nrs=73.333e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X122 n48 n36 n49 DVDD pfet_06v0 m=1.0 w=24e-6 l=700e-9 nf=1.0 as=10.56e-12 ++ ad=10.56e-12 ps=48.88e-6 pd=48.88e-6 nrd=18.333e-3 nrs=18.333e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X123 n243 n26 DVDD DVDD pfet_06v0 m=1.0 w=12e-6 l=700e-9 nf=1.0 as=5.28e-12 ++ ad=5.28e-12 ps=24.88e-6 pd=24.88e-6 nrd=36.667e-3 nrs=36.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X124 n44 n248 DVDD DVDD pfet_06v0 m=1.0 w=24e-6 l=700e-9 nf=1.0 as=10.56e-12 ++ ad=10.56e-12 ps=48.88e-6 pd=48.88e-6 nrd=18.333e-3 nrs=18.333e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X125 n49 n243 DVDD DVDD pfet_06v0 m=1.0 w=24e-6 l=700e-9 nf=1.0 as=10.56e-12 ++ ad=10.56e-12 ps=48.88e-6 pd=48.88e-6 nrd=18.333e-3 nrs=18.333e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X126 n48 DVSS n49 DVDD pfet_06v0 m=1.0 w=1.2e-6 l=700e-9 nf=1.0 as=528e-15 ++ ad=528e-15 ps=3.28e-6 pd=3.28e-6 nrd=366.667e-3 nrs=366.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X127 n243 n32 DVDD DVDD pfet_06v0 m=1.0 w=12e-6 l=700e-9 nf=1.0 as=5.28e-12 ++ ad=5.28e-12 ps=24.88e-6 pd=24.88e-6 nrd=36.667e-3 nrs=36.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X128 n248 n27 n243 DVDD pfet_06v0 m=1.0 w=12e-6 l=700e-9 nf=1.0 as=5.28e-12 ++ ad=5.28e-12 ps=24.88e-6 pd=24.88e-6 nrd=36.667e-3 nrs=36.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X129 n39 n248 DVDD DVDD pfet_06v0 m=1.0 w=24e-6 l=700e-9 nf=1.0 as=10.56e-12 ++ ad=10.56e-12 ps=48.88e-6 pd=48.88e-6 nrd=18.333e-3 nrs=18.333e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X130 n268 n257 DVSS DVSS nfet_06v0 m=1.0 w=3e-6 l=700e-9 nf=2.0 as=1.32e-12 ++ ad=780e-15 ps=7.76e-6 pd=4.04e-6 nrd=86.667e-3 nrs=146.667e-3 sa=440e-9 ++ sb=440e-9 sd=520e-9 dtemp=0.0 par=1 +X131 n281 n1 VSS VSS nfet_06v0 m=1.0 w=1.5e-6 l=700e-9 nf=1.0 as=660e-15 ++ ad=660e-15 ps=3.88e-6 pd=3.88e-6 nrd=293.333e-3 nrs=293.333e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X132 n257 n281 DVSS DVSS nfet_06v0 m=1.0 w=3e-6 l=700e-9 nf=2.0 as=1.32e-12 ++ ad=780e-15 ps=7.76e-6 pd=4.04e-6 nrd=86.667e-3 nrs=146.667e-3 sa=440e-9 ++ sb=440e-9 sd=520e-9 dtemp=0.0 par=1 +X133 n268 n257 DVDD DVDD pfet_06v0 m=1.0 w=6e-6 l=700e-9 nf=2.0 as=2.64e-12 ++ ad=1.56e-12 ps=13.76e-6 pd=7.04e-6 nrd=43.333e-3 nrs=73.333e-3 sa=440e-9 ++ sb=440e-9 sd=520e-9 dtemp=0.0 par=1 +X134 n281 n1 VDD VDD pfet_06v0 m=1.0 w=3e-6 l=700e-9 nf=1.0 as=1.32e-12 ++ ad=1.32e-12 ps=6.88e-6 pd=6.88e-6 nrd=146.667e-3 nrs=146.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X135 n257 n281 DVDD DVDD pfet_06v0 m=1.0 w=6e-6 l=700e-9 nf=2.0 as=2.64e-12 ++ ad=1.56e-12 ps=13.76e-6 pd=7.04e-6 nrd=43.333e-3 nrs=73.333e-3 sa=440e-9 ++ sb=440e-9 sd=520e-9 dtemp=0.0 par=1 +X136 n274 n258 DVSS DVSS nfet_06v0 m=1.0 w=3e-6 l=700e-9 nf=2.0 as=1.32e-12 ++ ad=780e-15 ps=7.76e-6 pd=4.04e-6 nrd=86.667e-3 nrs=146.667e-3 sa=440e-9 ++ sb=440e-9 sd=520e-9 dtemp=0.0 par=1 +X137 n289 n1 VSS VSS nfet_06v0 m=1.0 w=1.5e-6 l=700e-9 nf=1.0 as=660e-15 ++ ad=660e-15 ps=3.88e-6 pd=3.88e-6 nrd=293.333e-3 nrs=293.333e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X138 n258 n289 DVSS DVSS nfet_06v0 m=1.0 w=3e-6 l=700e-9 nf=2.0 as=1.32e-12 ++ ad=780e-15 ps=7.76e-6 pd=4.04e-6 nrd=86.667e-3 nrs=146.667e-3 sa=440e-9 ++ sb=440e-9 sd=520e-9 dtemp=0.0 par=1 +X139 n274 n258 DVDD DVDD pfet_06v0 m=1.0 w=6e-6 l=700e-9 nf=2.0 as=2.64e-12 ++ ad=1.56e-12 ps=13.76e-6 pd=7.04e-6 nrd=43.333e-3 nrs=73.333e-3 sa=440e-9 ++ sb=440e-9 sd=520e-9 dtemp=0.0 par=1 +X140 n289 n1 VDD VDD pfet_06v0 m=1.0 w=3e-6 l=700e-9 nf=1.0 as=1.32e-12 ++ ad=1.32e-12 ps=6.88e-6 pd=6.88e-6 nrd=146.667e-3 nrs=146.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X141 n258 n289 DVDD DVDD pfet_06v0 m=1.0 w=6e-6 l=700e-9 nf=2.0 as=2.64e-12 ++ ad=1.56e-12 ps=13.76e-6 pd=7.04e-6 nrd=43.333e-3 nrs=73.333e-3 sa=440e-9 ++ sb=440e-9 sd=520e-9 dtemp=0.0 par=1 +X142 n272 n260 DVSS DVSS nfet_06v0 m=1.0 w=3e-6 l=700e-9 nf=2.0 as=1.32e-12 ++ ad=780e-15 ps=7.76e-6 pd=4.04e-6 nrd=86.667e-3 nrs=146.667e-3 sa=440e-9 ++ sb=440e-9 sd=520e-9 dtemp=0.0 par=1 +X143 n297 n261 VSS VSS nfet_06v0 m=1.0 w=1.5e-6 l=700e-9 nf=1.0 as=660e-15 ++ ad=660e-15 ps=3.88e-6 pd=3.88e-6 nrd=293.333e-3 nrs=293.333e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X144 n260 n297 DVSS DVSS nfet_06v0 m=1.0 w=3e-6 l=700e-9 nf=2.0 as=1.32e-12 ++ ad=780e-15 ps=7.76e-6 pd=4.04e-6 nrd=86.667e-3 nrs=146.667e-3 sa=440e-9 ++ sb=440e-9 sd=520e-9 dtemp=0.0 par=1 +X145 n272 n260 DVDD DVDD pfet_06v0 m=1.0 w=6e-6 l=700e-9 nf=2.0 as=2.64e-12 ++ ad=1.56e-12 ps=13.76e-6 pd=7.04e-6 nrd=43.333e-3 nrs=73.333e-3 sa=440e-9 ++ sb=440e-9 sd=520e-9 dtemp=0.0 par=1 +X146 n297 n261 VDD VDD pfet_06v0 m=1.0 w=3e-6 l=700e-9 nf=1.0 as=1.32e-12 ++ ad=1.32e-12 ps=6.88e-6 pd=6.88e-6 nrd=146.667e-3 nrs=146.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X147 n260 n297 DVDD DVDD pfet_06v0 m=1.0 w=6e-6 l=700e-9 nf=2.0 as=2.64e-12 ++ ad=1.56e-12 ps=13.76e-6 pd=7.04e-6 nrd=43.333e-3 nrs=73.333e-3 sa=440e-9 ++ sb=440e-9 sd=520e-9 dtemp=0.0 par=1 +X148 n276 n263 DVSS DVSS nfet_06v0 m=1.0 w=3e-6 l=700e-9 nf=2.0 as=1.32e-12 ++ ad=780e-15 ps=7.76e-6 pd=4.04e-6 nrd=86.667e-3 nrs=146.667e-3 sa=440e-9 ++ sb=440e-9 sd=520e-9 dtemp=0.0 par=1 +X149 n305 n259 VSS VSS nfet_06v0 m=1.0 w=1.5e-6 l=700e-9 nf=1.0 as=660e-15 ++ ad=660e-15 ps=3.88e-6 pd=3.88e-6 nrd=293.333e-3 nrs=293.333e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X150 n263 n305 DVSS DVSS nfet_06v0 m=1.0 w=3e-6 l=700e-9 nf=2.0 as=1.32e-12 ++ ad=780e-15 ps=7.76e-6 pd=4.04e-6 nrd=86.667e-3 nrs=146.667e-3 sa=440e-9 ++ sb=440e-9 sd=520e-9 dtemp=0.0 par=1 +X151 n276 n263 DVDD DVDD pfet_06v0 m=1.0 w=6e-6 l=700e-9 nf=2.0 as=2.64e-12 ++ ad=1.56e-12 ps=13.76e-6 pd=7.04e-6 nrd=43.333e-3 nrs=73.333e-3 sa=440e-9 ++ sb=440e-9 sd=520e-9 dtemp=0.0 par=1 +X152 n305 n259 VDD VDD pfet_06v0 m=1.0 w=3e-6 l=700e-9 nf=1.0 as=1.32e-12 ++ ad=1.32e-12 ps=6.88e-6 pd=6.88e-6 nrd=146.667e-3 nrs=146.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X153 n263 n305 DVDD DVDD pfet_06v0 m=1.0 w=6e-6 l=700e-9 nf=2.0 as=2.64e-12 ++ ad=1.56e-12 ps=13.76e-6 pd=7.04e-6 nrd=43.333e-3 nrs=73.333e-3 sa=440e-9 ++ sb=440e-9 sd=520e-9 dtemp=0.0 par=1 +D154 PD VDD diode_pd2nw_06v0 m=1.0 area=1e-12 pj=4e-6 +D155 n1 VDD diode_pd2nw_06v0 m=1.0 area=1e-12 pj=4e-6 +D156 n1 VDD diode_pd2nw_06v0 m=1.0 area=1e-12 pj=4e-6 +D157 PU VDD diode_pd2nw_06v0 m=1.0 area=1e-12 pj=4e-6 +X158 n313 n258 DVDD DVDD pfet_06v0 m=1.0 w=8e-6 l=700e-9 nf=1.0 as=3.52e-12 ++ ad=3.52e-12 ps=16.88e-6 pd=16.88e-6 nrd=55e-3 nrs=55e-3 sa=440e-9 sb=440e-9 ++ sd=0.0 dtemp=0.0 par=1 +X159 DVDD n258 n314 DVDD pfet_06v0 m=1.0 w=3e-6 l=700e-9 nf=1.0 as=1.32e-12 ++ ad=1.32e-12 ps=6.88e-6 pd=6.88e-6 nrd=146.667e-3 nrs=146.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X160 n315 n15 DVDD DVDD pfet_06v0 m=1.0 w=3.8e-6 l=700e-9 nf=1.0 as=1.672e-12 ++ ad=1.672e-12 ps=8.48e-6 pd=8.48e-6 nrd=115.789e-3 nrs=115.789e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X161 DVSS n314 n315 DVDD pfet_06v0 m=1.0 w=3.8e-6 l=700e-9 nf=1.0 as=1.672e-12 ++ ad=1.672e-12 ps=8.48e-6 pd=8.48e-6 nrd=115.789e-3 nrs=115.789e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X162 n275 n257 DVDD DVDD pfet_06v0 m=1.0 w=6e-6 l=700e-9 nf=1.0 as=2.64e-12 ++ ad=2.64e-12 ps=12.88e-6 pd=12.88e-6 nrd=73.333e-3 nrs=73.333e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X163 n275 n313 n310 DVDD pfet_06v0 m=1.0 w=2e-6 l=700e-9 nf=1.0 as=880e-15 ++ ad=880e-15 ps=4.88e-6 pd=4.88e-6 nrd=220e-3 nrs=220e-3 sa=440e-9 sb=440e-9 ++ sd=0.0 dtemp=0.0 par=1 +X164 n275 n313 n314 DVDD pfet_06v0 m=1.0 w=2e-6 l=700e-9 nf=1.0 as=880e-15 ++ ad=880e-15 ps=4.88e-6 pd=4.88e-6 nrd=220e-3 nrs=220e-3 sa=440e-9 sb=440e-9 ++ sd=0.0 dtemp=0.0 par=1 +X165 n275 n15 n315 DVDD pfet_06v0 m=1.0 w=4.3e-6 l=700e-9 nf=1.0 as=1.892e-12 ++ ad=1.892e-12 ps=9.48e-6 pd=9.48e-6 nrd=102.326e-3 nrs=102.326e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X166 n320 n257 DVSS DVSS nfet_06v0 m=1.0 w=16e-6 l=700e-9 nf=1.0 as=7.04e-12 ++ ad=7.04e-12 ps=32.88e-6 pd=32.88e-6 nrd=27.5e-3 nrs=27.5e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X167 n312 n15 n320 DVSS nfet_06v0 m=1.0 w=10.6e-6 l=700e-9 nf=1.0 as=4.664e-12 ++ ad=4.664e-12 ps=22.08e-6 pd=22.08e-6 nrd=41.509e-3 nrs=41.509e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X168 n275 n15 n312 DVSS nfet_06v0 m=1.0 w=12e-6 l=700e-9 nf=1.0 as=5.28e-12 ++ ad=5.28e-12 ps=24.88e-6 pd=24.88e-6 nrd=36.667e-3 nrs=36.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X169 n313 n258 DVSS DVSS nfet_06v0 m=1.0 w=4e-6 l=700e-9 nf=1.0 as=1.76e-12 ++ ad=1.76e-12 ps=8.88e-6 pd=8.88e-6 nrd=110e-3 nrs=110e-3 sa=440e-9 sb=440e-9 ++ sd=0.0 dtemp=0.0 par=1 +X170 n275 n258 n310 DVSS nfet_06v0 m=1.0 w=1.5e-6 l=700e-9 nf=1.0 as=660e-15 ++ ad=660e-15 ps=3.88e-6 pd=3.88e-6 nrd=293.333e-3 nrs=293.333e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X171 n275 n258 n314 DVSS nfet_06v0 m=1.0 w=1.5e-6 l=700e-9 nf=1.0 as=660e-15 ++ ad=660e-15 ps=3.88e-6 pd=3.88e-6 nrd=293.333e-3 nrs=293.333e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X172 DVDD n310 n312 DVSS nfet_06v0 m=1.0 w=1.3e-6 l=700e-9 nf=1.0 as=572e-15 ++ ad=572e-15 ps=3.48e-6 pd=3.48e-6 nrd=338.462e-3 nrs=338.462e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X173 DVSS n313 n310 DVSS nfet_06v0 m=1.0 w=1.5e-6 l=700e-9 nf=1.0 as=660e-15 ++ ad=660e-15 ps=3.88e-6 pd=3.88e-6 nrd=293.333e-3 nrs=293.333e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X174 n328 n275 DVDD DVDD pfet_06v0 m=1.0 w=2e-6 l=700e-9 nf=1.0 as=880e-15 ++ ad=880e-15 ps=4.88e-6 pd=4.88e-6 nrd=220e-3 nrs=220e-3 sa=440e-9 sb=440e-9 ++ sd=0.0 dtemp=0.0 par=1 +X175 n325 n328 VDD VDD pfet_06v0 m=1.0 w=10e-6 l=700e-9 nf=1.0 as=4.4e-12 ++ ad=4.4e-12 ps=20.88e-6 pd=20.88e-6 nrd=44e-3 nrs=44e-3 sa=440e-9 sb=440e-9 ++ sd=0.0 dtemp=0.0 par=1 +X176 Y n325 VDD VDD pfet_06v0 m=1.0 w=21e-6 l=700e-9 nf=1.0 as=9.24e-12 ++ ad=9.24e-12 ps=42.88e-6 pd=42.88e-6 nrd=20.952e-3 nrs=20.952e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X177 n328 n275 DVSS DVSS nfet_06v0 m=1.0 w=8e-6 l=700e-9 nf=1.0 as=3.52e-12 ++ ad=3.52e-12 ps=16.88e-6 pd=16.88e-6 nrd=55e-3 nrs=55e-3 sa=440e-9 sb=440e-9 ++ sd=0.0 dtemp=0.0 par=1 +X178 Y n325 VSS VSS nfet_06v0 m=1.0 w=9e-6 l=700e-9 nf=1.0 as=3.96e-12 ++ ad=3.96e-12 ps=18.88e-6 pd=18.88e-6 nrd=48.889e-3 nrs=48.889e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X179 n325 n328 VSS VSS nfet_06v0 m=1.0 w=2.5e-6 l=700e-9 nf=1.0 as=1.1e-12 ++ ad=1.1e-12 ps=5.88e-6 pd=5.88e-6 nrd=176e-3 nrs=176e-3 sa=440e-9 sb=440e-9 ++ sd=0.0 dtemp=0.0 par=1 +X180 n261 n335 VDD VDD pfet_06v0 m=1.0 w=3e-6 l=700e-9 nf=1.0 as=1.32e-12 ++ ad=1.32e-12 ps=6.88e-6 pd=6.88e-6 nrd=146.667e-3 nrs=146.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X181 n261 PU VDD VDD pfet_06v0 m=1.0 w=3e-6 l=700e-9 nf=1.0 as=1.32e-12 ++ ad=1.32e-12 ps=6.88e-6 pd=6.88e-6 nrd=146.667e-3 nrs=146.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X182 n336 PU VSS VSS nfet_06v0 m=1.0 w=3e-6 l=700e-9 nf=1.0 as=1.32e-12 ++ ad=1.32e-12 ps=6.88e-6 pd=6.88e-6 nrd=146.667e-3 nrs=146.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X183 n261 n335 n336 VSS nfet_06v0 m=1.0 w=3e-6 l=700e-9 nf=1.0 as=1.32e-12 ++ ad=1.32e-12 ps=6.88e-6 pd=6.88e-6 nrd=146.667e-3 nrs=146.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X184 n259 PD VDD VDD pfet_06v0 m=1.0 w=3e-6 l=700e-9 nf=1.0 as=1.32e-12 ++ ad=1.32e-12 ps=6.88e-6 pd=6.88e-6 nrd=146.667e-3 nrs=146.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X185 n259 n335 VDD VDD pfet_06v0 m=1.0 w=3e-6 l=700e-9 nf=1.0 as=1.32e-12 ++ ad=1.32e-12 ps=6.88e-6 pd=6.88e-6 nrd=146.667e-3 nrs=146.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X186 n342 n335 VSS VSS nfet_06v0 m=1.0 w=3e-6 l=700e-9 nf=1.0 as=1.32e-12 ++ ad=1.32e-12 ps=6.88e-6 pd=6.88e-6 nrd=146.667e-3 nrs=146.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X187 n259 PD n342 VSS nfet_06v0 m=1.0 w=3e-6 l=700e-9 nf=1.0 as=1.32e-12 ++ ad=1.32e-12 ps=6.88e-6 pd=6.88e-6 nrd=146.667e-3 nrs=146.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X188 n348 n354 n335 VDD pfet_06v0 m=1.0 w=3e-6 l=700e-9 nf=1.0 as=1.32e-12 ++ ad=1.32e-12 ps=6.88e-6 pd=6.88e-6 nrd=146.667e-3 nrs=146.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X189 PU PD n335 VDD pfet_06v0 m=1.0 w=3e-6 l=700e-9 nf=1.0 as=1.32e-12 ++ ad=1.32e-12 ps=6.88e-6 pd=6.88e-6 nrd=146.667e-3 nrs=146.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X190 n354 PD VDD VDD pfet_06v0 m=1.0 w=3e-6 l=700e-9 nf=1.0 as=1.32e-12 ++ ad=1.32e-12 ps=6.88e-6 pd=6.88e-6 nrd=146.667e-3 nrs=146.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X191 n348 PU VDD VDD pfet_06v0 m=1.0 w=3e-6 l=700e-9 nf=1.0 as=1.32e-12 ++ ad=1.32e-12 ps=6.88e-6 pd=6.88e-6 nrd=146.667e-3 nrs=146.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X192 n348 PD n335 VSS nfet_06v0 m=1.0 w=1.5e-6 l=700e-9 nf=1.0 as=660e-15 ++ ad=660e-15 ps=3.88e-6 pd=3.88e-6 nrd=293.333e-3 nrs=293.333e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X193 PU n354 n335 VSS nfet_06v0 m=1.0 w=1.5e-6 l=700e-9 nf=1.0 as=660e-15 ++ ad=660e-15 ps=3.88e-6 pd=3.88e-6 nrd=293.333e-3 nrs=293.333e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X194 n354 PD VSS VSS nfet_06v0 m=1.0 w=1.5e-6 l=700e-9 nf=1.0 as=660e-15 ++ ad=660e-15 ps=3.88e-6 pd=3.88e-6 nrd=293.333e-3 nrs=293.333e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X195 n348 PU VSS VSS nfet_06v0 m=1.0 w=1.5e-6 l=700e-9 nf=1.0 as=660e-15 ++ ad=660e-15 ps=3.88e-6 pd=3.88e-6 nrd=293.333e-3 nrs=293.333e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X196 n15 n357 DVDD ppolyf_u r_width=800e-9 r_length=23e-6 m=1.0 r=9.94533e3 par=1 +X197 n357 n356 DVDD ppolyf_u r_width=800e-9 r_length=35.7e-6 m=1.0 r=15.3065e3 par=1 +X198 n356 n355 DVDD ppolyf_u r_width=800e-9 r_length=35.7e-6 m=1.0 r=15.3065e3 par=1 +X199 n355 n358 DVDD ppolyf_u r_width=800e-9 r_length=35.7e-6 m=1.0 r=15.3065e3 par=1 +X200 n358 n363 DVDD ppolyf_u r_width=800e-9 r_length=35.7e-6 m=1.0 r=15.3065e3 par=1 +X201 n363 n362 DVDD ppolyf_u r_width=800e-9 r_length=35.7e-6 m=1.0 r=15.3065e3 par=1 +X202 n362 n359 DVDD ppolyf_u r_width=800e-9 r_length=35.7e-6 m=1.0 r=15.3065e3 par=1 +X203 n359 n360 DVDD ppolyf_u r_width=800e-9 r_length=35.7e-6 m=1.0 r=15.3065e3 par=1 +X204 n360 n276 DVSS DVSS nfet_06v0 m=1.0 w=1.5e-6 l=700e-9 nf=1.0 as=660e-15 ++ ad=660e-15 ps=3.88e-6 pd=3.88e-6 nrd=293.333e-3 nrs=293.333e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +X205 n360 n260 DVDD DVDD pfet_06v0 m=1.0 w=3e-6 l=700e-9 nf=1.0 as=1.32e-12 ++ ad=1.32e-12 ps=6.88e-6 pd=6.88e-6 nrd=146.667e-3 nrs=146.667e-3 sa=440e-9 ++ sb=440e-9 sd=0.0 dtemp=0.0 par=1 +D206 DVSS n15 diode_nd2ps_06v0 m=2.0 area=20e-12 pj=42e-6 +D207 n15 DVDD diode_pd2nw_06v0 m=2.0 area=20e-12 pj=42e-6 +X208 PAD n15 DVDD ppolyf_u r_width=2.5e-6 r_length=2.8e-6 m=1.0 r=432.59 par=1 +X209 PAD n15 DVDD ppolyf_u r_width=2.5e-6 r_length=2.8e-6 m=1.0 r=449.157 par=1 +X210 PAD n15 DVDD ppolyf_u r_width=2.5e-6 r_length=2.8e-6 m=1.0 r=432.59 par=1 +X211 PAD n15 DVDD ppolyf_u r_width=2.5e-6 r_length=2.8e-6 m=1.0 r=449.157 par=1 +.ENDS + + +******* EOF + diff --git a/blocks/composite/regulated_cascoded_cmirror/xschem/Chipathon2025_pads/xschem/gf180mcu_fd_io__asig_5p0_extracted.spice b/blocks/composite/regulated_cascoded_cmirror/xschem/Chipathon2025_pads/xschem/gf180mcu_fd_io__asig_5p0_extracted.spice new file mode 100644 index 00000000..3db4bff3 --- /dev/null +++ b/blocks/composite/regulated_cascoded_cmirror/xschem/Chipathon2025_pads/xschem/gf180mcu_fd_io__asig_5p0_extracted.spice @@ -0,0 +1,19844 @@ +.subckt gf180mcu_fd_io__asig_5p0_extracted DVSS DVDD VSS VDD PAD ASIG5V +cDVDD/0 DVDD:16209 vss 7.57208f +cDVDD/1 DVDD:16205 vss 79.679f +cDVDD/2 DVDD:16160 vss 7.5076f +cDVDD/3 DVDD:16156 vss 78.2189f +cDVDD/4 DVDD:16083 vss 20.7374f +cDVDD/5 DVDD:15976 vss 21.0976f +cDVDD/6 DVDD:15870 vss 20.8618f +cDVDD/7 DVDD:15757 vss 0.56211f +cDVDD/8 DVDD:15753 vss 0.581688f +cDVDD/9 DVDD:15743 vss 0.221594f +cDVDD/10 DVDD:15733 vss 0.1849f +cDVDD/11 DVDD:15724 vss 0.526184f +cDVDD/12 DVDD:15714 vss 0.26583f +cDVDD/13 DVDD:15704 vss 0.303359f +cDVDD/14 DVDD:15695 vss 2.74937f +cDVDD/15 DVDD:15691 vss 0.101053f +cDVDD/16 DVDD:15686 vss 0.457353f +cDVDD/17 DVDD:15677 vss 14.1501f +cDVDD/18 DVDD:15468 vss 28.2397f +cDVDD/19 DVDD:15436 vss 202.45f +cDVDD/20 DVDD:15435 vss 5.38399f +cDVDD/21 DVDD:15426 vss 33.6478f +cDVDD/22 DVDD:15416 vss 16.376f +cDVDD/23 DVDD:15412 vss 1.61205f +cDVDD/24 DVDD:15373 vss 23.1914f +cDVDD/25 DVDD:15295 vss 17.1363f +cDVDD/26 DVDD:15004 vss 32.7136f +cDVDD/27 DVDD:14722 vss 26.6155f +cDVDD/28 DVDD:14437 vss 26.6155f +cDVDD/29 DVDD:14155 vss 32.7132f +cDVDD/30 DVDD:14082 vss 16.468f +cDVDD/31 DVDD:14078 vss 1.62203f +cDVDD/32 DVDD:14039 vss 23.4037f +cDVDD/33 DVDD:13961 vss 17.1363f +cDVDD/34 DVDD:13695 vss 1.19876f +cDVDD/35 DVDD:13645 vss 2.93002f +cDVDD/36 DVDD:13626 vss 3.93797f +cDVDD/37 DVDD:13607 vss 3.46682f +cDVDD/38 DVDD:13599 vss 1.17601f +cDVDD/39 DVDD:13432 vss 31.9204f +cDVDD/40 DVDD:13120 vss 36.606f +cDVDD/41 DVDD:12805 vss 30.0321f +cDVDD/42 DVDD:12490 vss 30.0321f +cDVDD/43 DVDD:12069 vss 36.6052f +cDVDD/44 DVDD:11910 vss 6.35693f +cDVDD/45 DVDD:11814 vss 6.45956f +cDVDD/46 DVDD:11718 vss 6.45956f +cDVDD/47 DVDD:11622 vss 6.35822f +cDVDD/48 DVDD:11300 vss 16.3982f +cDVDD/49 DVDD:11280 vss 0.60798f +cDVDD/50 DVDD:11228 vss 2.20998f +cDVDD/51 DVDD:11223 vss 0.246528f +cDVDD/52 DVDD:11183 vss 2.61894f +cDVDD/53 DVDD:11175 vss 0.283361f +cDVDD/54 DVDD:11149 vss 12.246f +cDVDD/55 DVDD:11112 vss 12.276f +cDVDD/56 DVDD:11080 vss 8.21533f +cDVDD/57 DVDD vss 13.7761f +cDVDD/58 DVDD:11060 vss 16.7658f +cDVDD/59 DVDD:11056 vss 10.008f +cDVDD/60 DVDD:10963 vss 16.9075f +cDVDD/61 DVDD:10959 vss 10.0118f +cDVDD/62 DVDD:10866 vss 16.7995f +cDVDD/63 DVDD:10862 vss 10.002f +cDVDD/64 DVDD:10771 vss 0.18771f +cDVDD/65 DVDD:10766 vss 0.314239f +cDVDD/66 DVDD:10761 vss 0.675686f +cDVDD/67 DVDD:10757 vss 0.20557f +cDVDD/68 DVDD:10752 vss 0.205558f +cDVDD/69 DVDD:10727 vss 1.00758f +cDVDD/70 DVDD:10717 vss 1.00236f +cDVDD/71 DVDD:10688 vss 3.72855f +cDVDD/72 DVDD:10683 vss 0.197672f +cDVDD/73 DVDD:10663 vss 2.33273f +cDVDD/74 DVDD:10658 vss 0.193915f +cDVDD/75 D8:neg vss 0.845741f +cDVDD/76 DVDD:9148 vss 0.459122f +cDVDD/77 DVDD:9140 vss 12.6303f +cDVDD/78 DVDD:9133 vss 2.45177f +cDVDD/79 DVDD:9125 vss 2.42021f +cDVDD/80 DVDD:9116 vss 0.607574f +cDVDD/81 X52/X1/X2/X1/C0:pos vss 4.1609f +cDVDD/82 DVDD:9086 vss 0.058323f +cDVDD/83 DVDD:9078 vss 16.9289f +cDVDD/84 DVDD:9071 vss 2.39888f +cDVDD/85 DVDD:9063 vss 2.44184f +cDVDD/86 DVDD:9054 vss 0.0771812f +cDVDD/87 X52/X1/X2/X0/C0:pos vss 4.95726f +cDVDD/88 DVDD:8976 vss 0.058323f +cDVDD/89 DVDD:8968 vss 16.9289f +cDVDD/90 DVDD:8961 vss 2.39888f +cDVDD/91 DVDD:8953 vss 2.44184f +cDVDD/92 DVDD:8944 vss 0.0771812f +cDVDD/93 X52/X1/X1/X1/C0:pos vss 4.95726f +cDVDD/94 DVDD:8906 vss 14.3793f +cDVDD/95 DVDD:8899 vss 2.39421f +cDVDD/96 DVDD:8891 vss 2.42622f +cDVDD/97 X52/X1/X1/X0/C0:pos vss 4.20338f +cDVDD/98 DVDD:8698 vss 0.457738f +cDVDD/99 DVDD:8690 vss 12.4577f +cDVDD/100 DVDD:8683 vss 2.39209f +cDVDD/101 DVDD:8675 vss 2.42019f +cDVDD/102 DVDD:8666 vss 0.605744f +cDVDD/103 X52/X0/X2/X1/C0:pos vss 4.16126f +cDVDD/104 DVDD:8636 vss 0.0568369f +cDVDD/105 DVDD:8628 vss 16.7695f +cDVDD/106 DVDD:8621 vss 2.3988f +cDVDD/107 DVDD:8613 vss 2.44179f +cDVDD/108 DVDD:8604 vss 0.0752146f +cDVDD/109 X52/X0/X2/X0/C0:pos vss 4.95799f +cDVDD/110 DVDD:8526 vss 0.0568369f +cDVDD/111 DVDD:8518 vss 16.7695f +cDVDD/112 DVDD:8511 vss 2.3988f +cDVDD/113 DVDD:8503 vss 2.44179f +cDVDD/114 DVDD:8494 vss 0.0752146f +cDVDD/115 X52/X0/X1/X1/C0:pos vss 4.95799f +cDVDD/116 DVDD:8456 vss 14.4709f +cDVDD/117 DVDD:8449 vss 2.39809f +cDVDD/118 DVDD:8441 vss 2.42619f +cDVDD/119 X52/X0/X1/X0/C0:pos vss 4.20791f +cDVDD/120 DVDD:8104 vss 0.457289f +cDVDD/121 DVDD:8096 vss 12.2929f +cDVDD/122 DVDD:8089 vss 2.39213f +cDVDD/123 DVDD:8081 vss 2.40438f +cDVDD/124 DVDD:8072 vss 0.605149f +cDVDD/125 X51/X1/X2/X1/C0:pos vss 4.16073f +cDVDD/126 DVDD:8042 vss 0.056491f +cDVDD/127 DVDD:8034 vss 16.636f +cDVDD/128 DVDD:8027 vss 2.39888f +cDVDD/129 DVDD:8019 vss 2.43633f +cDVDD/130 DVDD:8010 vss 0.0747568f +cDVDD/131 X51/X1/X2/X0/C0:pos vss 4.95687f +cDVDD/132 DVDD:7932 vss 0.056491f +cDVDD/133 DVDD:7924 vss 16.636f +cDVDD/134 DVDD:7917 vss 2.39888f +cDVDD/135 DVDD:7909 vss 2.43633f +cDVDD/136 DVDD:7900 vss 0.0747568f +cDVDD/137 X51/X1/X1/X1/C0:pos vss 4.95687f +cDVDD/138 DVDD:7862 vss 14.3236f +cDVDD/139 DVDD:7855 vss 2.39813f +cDVDD/140 DVDD:7847 vss 2.41038f +cDVDD/141 X51/X1/X1/X0/C0:pos vss 4.20739f +cDVDD/142 DVDD:7654 vss 0.455658f +cDVDD/143 DVDD:7646 vss 12.541f +cDVDD/144 DVDD:7639 vss 2.39209f +cDVDD/145 DVDD:7631 vss 2.40438f +cDVDD/146 DVDD:7622 vss 0.602991f +cDVDD/147 X51/X0/X2/X1/C0:pos vss 4.16126f +cDVDD/148 DVDD:7592 vss 0.0547567f +cDVDD/149 DVDD:7584 vss 16.8412f +cDVDD/150 DVDD:7577 vss 2.3988f +cDVDD/151 DVDD:7569 vss 2.43633f +cDVDD/152 DVDD:7560 vss 0.0724618f +cDVDD/153 X51/X0/X2/X0/C0:pos vss 4.95798f +cDVDD/154 DVDD:7482 vss 0.0547567f +cDVDD/155 DVDD:7474 vss 16.8412f +cDVDD/156 DVDD:7467 vss 2.3988f +cDVDD/157 DVDD:7459 vss 2.43633f +cDVDD/158 DVDD:7450 vss 0.0724618f +cDVDD/159 X51/X0/X1/X1/C0:pos vss 4.95798f +cDVDD/160 DVDD:7412 vss 14.4612f +cDVDD/161 DVDD:7405 vss 2.39809f +cDVDD/162 DVDD:7397 vss 2.40362f +cDVDD/163 X51/X0/X1/X0/C0:pos vss 4.20829f +cDVDD/164 DVDD:7060 vss 0.459993f +cDVDD/165 DVDD:7052 vss 12.663f +cDVDD/166 DVDD:7045 vss 2.39209f +cDVDD/167 DVDD:7037 vss 2.40979f +cDVDD/168 DVDD:7028 vss 0.608728f +cDVDD/169 X50/X1/X2/X1/C0:pos vss 4.1609f +cDVDD/170 DVDD:6998 vss 0.0590918f +cDVDD/171 DVDD:6990 vss 16.9175f +cDVDD/172 DVDD:6983 vss 2.3988f +cDVDD/173 DVDD:6975 vss 2.43633f +cDVDD/174 DVDD:6966 vss 0.0781985f +cDVDD/175 X50/X1/X2/X0/C0:pos vss 4.95727f +cDVDD/176 DVDD:6888 vss 0.0590918f +cDVDD/177 DVDD:6880 vss 16.9175f +cDVDD/178 DVDD:6873 vss 2.3988f +cDVDD/179 DVDD:6865 vss 2.44121f +cDVDD/180 DVDD:6856 vss 0.0781985f +cDVDD/181 X50/X1/X1/X1/C0:pos vss 4.95727f +cDVDD/182 DVDD:6818 vss 13.9735f +cDVDD/183 DVDD:6811 vss 2.39422f +cDVDD/184 DVDD:6803 vss 2.40359f +cDVDD/185 X50/X1/X1/X0/C0:pos vss 4.19337f +cDVDD/186 DVDD:6610 vss 0.455658f +cDVDD/187 DVDD:6602 vss 12.296f +cDVDD/188 DVDD:6595 vss 2.39752f +cDVDD/189 DVDD:6587 vss 2.40979f +cDVDD/190 DVDD:6578 vss 0.602991f +cDVDD/191 X50/X0/X2/X1/C0:pos vss 4.16054f +cDVDD/192 DVDD:6548 vss 0.0547567f +cDVDD/193 DVDD:6540 vss 16.6032f +cDVDD/194 DVDD:6533 vss 2.40613f +cDVDD/195 DVDD:6525 vss 2.43633f +cDVDD/196 DVDD:6516 vss 0.0724618f +cDVDD/197 X50/X0/X2/X0/C0:pos vss 4.95654f +cDVDD/198 DVDD:6438 vss 0.0547567f +cDVDD/199 DVDD:6430 vss 16.6032f +cDVDD/200 DVDD:6423 vss 2.40429f +cDVDD/201 DVDD:6415 vss 2.44121f +cDVDD/202 DVDD:6406 vss 0.0724618f +cDVDD/203 X50/X0/X1/X1/C0:pos vss 4.95654f +cDVDD/204 DVDD:6368 vss 13.4264f +cDVDD/205 DVDD:6361 vss 2.40119f +cDVDD/206 DVDD:6353 vss 2.40979f +cDVDD/207 X50/X0/X1/X0/C0:pos vss 4.16355f +cDVDD/208 DVDD:6016 vss 0.458129f +cDVDD/209 DVDD:6008 vss 12.5082f +cDVDD/210 DVDD:6001 vss 2.40119f +cDVDD/211 DVDD:5993 vss 2.40979f +cDVDD/212 DVDD:5984 vss 0.606261f +cDVDD/213 X49/X1/X2/X1/C0:pos vss 4.16126f +cDVDD/214 DVDD:5954 vss 0.0572278f +cDVDD/215 DVDD:5946 vss 16.7737f +cDVDD/216 DVDD:5939 vss 2.40613f +cDVDD/217 DVDD:5931 vss 2.43633f +cDVDD/218 DVDD:5922 vss 0.0757318f +cDVDD/219 X49/X1/X2/X0/C0:pos vss 4.95794f +cDVDD/220 DVDD:5844 vss 0.0572278f +cDVDD/221 DVDD:5836 vss 16.7737f +cDVDD/222 DVDD:5829 vss 2.40429f +cDVDD/223 DVDD:5821 vss 2.44121f +cDVDD/224 DVDD:5812 vss 0.0757318f +cDVDD/225 X49/X1/X1/X1/C0:pos vss 4.95794f +cDVDD/226 DVDD:5774 vss 13.7264f +cDVDD/227 DVDD:5767 vss 2.40119f +cDVDD/228 DVDD:5759 vss 2.40979f +cDVDD/229 X49/X1/X1/X0/C0:pos vss 4.18159f +cDVDD/230 DVDD:5566 vss 0.455658f +cDVDD/231 DVDD:5558 vss 12.2936f +cDVDD/232 DVDD:5551 vss 2.40119f +cDVDD/233 DVDD:5543 vss 2.40762f +cDVDD/234 DVDD:5534 vss 0.602991f +cDVDD/235 X49/X0/X2/X1/C0:pos vss 4.16054f +cDVDD/236 DVDD:5504 vss 0.0547567f +cDVDD/237 DVDD:5496 vss 16.5989f +cDVDD/238 DVDD:5489 vss 2.40796f +cDVDD/239 DVDD:5481 vss 2.43417f +cDVDD/240 DVDD:5472 vss 0.0724618f +cDVDD/241 X49/X0/X2/X0/C0:pos vss 4.95654f +cDVDD/242 DVDD:5394 vss 0.0547567f +cDVDD/243 DVDD:5386 vss 16.5989f +cDVDD/244 DVDD:5379 vss 2.40613f +cDVDD/245 DVDD:5371 vss 2.44391f +cDVDD/246 DVDD:5362 vss 0.0724618f +cDVDD/247 X49/X0/X1/X1/C0:pos vss 4.95654f +cDVDD/248 DVDD:5324 vss 13.4269f +cDVDD/249 DVDD:5317 vss 2.40119f +cDVDD/250 DVDD:5309 vss 2.40762f +cDVDD/251 X49/X0/X1/X0/C0:pos vss 4.16349f +cDVDD/252 DVDD:5116 vss 0.391353f +cDVDD/253 DVDD:5108 vss 12.6482f +cDVDD/254 DVDD:5101 vss 2.38986f +cDVDD/255 DVDD:5093 vss 2.42012f +cDVDD/256 DVDD:5084 vss 0.517893f +cDVDD/257 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0.00251351 +rDVDD/5650 DVDD:865 DVDD:929 0.00121622 +rDVDD/5651 DVDD:865 X46/X30/D0:neg 1.73333 +rDVDD/5652 DVDD:863 DVDD:4210 0.0292703 +rDVDD/5653 DVDD:863 DVDD:927 0.00121622 +rDVDD/5654 DVDD:863 X46/X30/D0:neg 1.73333 +rDVDD/5655 DVDD:861 DVDD:4208 0.056027 +rDVDD/5656 DVDD:861 DVDD:925 0.00113514 +rDVDD/5657 DVDD:861 X46/X30/D0:neg 1.73333 +rDVDD/5658 DVDD:859 DVDD:4206 0.0827838 +rDVDD/5659 DVDD:859 DVDD:923 0.00113514 +rDVDD/5660 DVDD:859 X46/X30/D0:neg 1.73333 +rDVDD/5661 DVDD:855 DVDD:4202 0.00486486 +rDVDD/5662 DVDD:855 DVDD:4200 0.0827027 +rDVDD/5663 DVDD:855 X46/X30/D0:neg 1.73333 +rDVDD/5664 DVDD:853 DVDD:936 0.00113514 +rDVDD/5665 DVDD:853 DVDD:4198 0.0559459 +rDVDD/5666 DVDD:853 X46/X30/D0:neg 1.73333 +rDVDD/5667 DVDD:851 DVDD:934 0.00121622 +rDVDD/5668 DVDD:851 DVDD:4196 0.0291892 +rDVDD/5669 DVDD:851 X46/X30/D0:neg 1.73333 +rDVDD/5670 DVDD:849 DVDD:932 0.00121622 +rDVDD/5671 DVDD:849 DVDD:4194 0.00243243 +rDVDD/5672 DVDD:849 X46/X30/D0:neg 1.73333 +rDVDD/5673 DVDD:845 DVDD:4192 0.0072973 +rDVDD/5674 DVDD:845 DVDD:4190 0.0802703 +rDVDD/5675 DVDD:845 X46/X30/D0:neg 1.73333 +rDVDD/5676 DVDD:843 DVDD:945 0.00356757 +rDVDD/5677 DVDD:843 DVDD:4188 0.0535135 +rDVDD/5678 DVDD:843 X46/X30/D0:neg 1.73333 +rDVDD/5679 DVDD:841 DVDD:943 0.00364865 +rDVDD/5680 DVDD:841 DVDD:4186 0.0267568 +rDVDD/5681 DVDD:841 X46/X30/D0:neg 1.73333 +rDVDD/5682 DVDD:834 DVDD:4032 0.0268378 +rDVDD/5683 DVDD:834 DVDD:882 0.00364865 +rDVDD/5684 DVDD:834 X46/X30/D0:neg 1.73333 +rDVDD/5685 DVDD:832 DVDD:4030 0.0535946 +rDVDD/5686 DVDD:832 DVDD:880 0.00356757 +rDVDD/5687 DVDD:832 X46/X30/D0:neg 1.73333 +rDVDD/5688 DVDD:830 DVDD:4028 0.0803514 +rDVDD/5689 DVDD:830 DVDD:878 0.00356757 +rDVDD/5690 DVDD:830 X46/X30/D0:neg 1.73333 +rDVDD/5691 DVDD:824 DVDD:4022 0.0292703 +rDVDD/5692 DVDD:824 DVDD:891 0.00121622 +rDVDD/5693 DVDD:824 X46/X30/D0:neg 1.73333 +rDVDD/5694 DVDD:822 DVDD:4020 0.056027 +rDVDD/5695 DVDD:822 DVDD:889 0.00113514 +rDVDD/5696 DVDD:822 X46/X30/D0:neg 1.73333 +rDVDD/5697 DVDD:820 DVDD:4018 0.0827838 +rDVDD/5698 DVDD:820 DVDD:887 0.00113514 +rDVDD/5699 DVDD:820 X46/X30/D0:neg 1.73333 +rDVDD/5700 DVDD:816 DVDD:902 0.00113514 +rDVDD/5701 DVDD:816 DVDD:4012 0.0827027 +rDVDD/5702 DVDD:816 X46/X30/D0:neg 1.73333 +rDVDD/5703 DVDD:814 DVDD:900 0.00113514 +rDVDD/5704 DVDD:814 DVDD:4010 0.0559459 +rDVDD/5705 DVDD:814 X46/X30/D0:neg 1.73333 +rDVDD/5706 DVDD:812 DVDD:898 0.00121622 +rDVDD/5707 DVDD:812 DVDD:4008 0.0291892 +rDVDD/5708 DVDD:812 X46/X30/D0:neg 1.73333 +rDVDD/5709 DVDD:810 DVDD:896 0.00121622 +rDVDD/5710 DVDD:810 DVDD:4006 0.00243243 +rDVDD/5711 DVDD:810 X46/X30/D0:neg 1.73333 +rDVDD/5712 DVDD:806 DVDD:911 0.00356757 +rDVDD/5713 DVDD:806 DVDD:4002 0.0802703 +rDVDD/5714 DVDD:806 X46/X30/D0:neg 1.73333 +rDVDD/5715 DVDD:804 DVDD:909 0.00356757 +rDVDD/5716 DVDD:804 DVDD:4000 0.0535135 +rDVDD/5717 DVDD:804 X46/X30/D0:neg 1.73333 +rDVDD/5718 DVDD:802 DVDD:907 0.00364865 +rDVDD/5719 DVDD:802 DVDD:3998 0.0267568 +rDVDD/5720 DVDD:802 X46/X30/D0:neg 1.73333 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0.0192308 +rDVDD/5771 DVDD:731 DVDD:791 0.0384615 +rDVDD/5772 DVDD:731 X46/D0:neg 0.67826 +rDVDD/5773 DVDD:729 DVDD:761 0.0384615 +rDVDD/5774 DVDD:729 DVDD:789 0.0384615 +rDVDD/5775 DVDD:729 X46/D0:neg 0.67826 +rDVDD/5776 DVDD:727 DVDD:759 0.0384615 +rDVDD/5777 DVDD:727 DVDD:787 0.0192308 +rDVDD/5778 DVDD:727 X46/D0:neg 0.67826 +rDVDD/5779 DVDD:725 DVDD:757 0.0192308 +rDVDD/5780 DVDD:725 DVDD:785 0.0384615 +rDVDD/5781 DVDD:725 X46/D0:neg 0.67826 +rDVDD/5782 DVDD:723 DVDD:755 0.0384615 +rDVDD/5783 DVDD:723 DVDD:783 0.0384615 +rDVDD/5784 DVDD:723 X46/D0:neg 0.67826 +rDVDD/5785 DVDD:721 DVDD:753 0.0191923 +rDVDD/5786 DVDD:721 DVDD:781 0.0384615 +rDVDD/5787 DVDD:721 X46/D0:neg 0.67826 +rDVDD/5788 DVDD:719 DVDD:751 0.0384615 +rDVDD/5789 DVDD:719 DVDD:779 0.0384615 +rDVDD/5790 DVDD:719 X46/D0:neg 0.67826 +rDVDD/5791 DVDD:717 DVDD:749 0.0384615 +rDVDD/5792 DVDD:717 DVDD:777 0.0192308 +rDVDD/5793 DVDD:717 X46/D0:neg 0.67826 +rDVDD/5794 DVDD:715 DVDD:747 0.0192308 +rDVDD/5795 DVDD:715 DVDD:775 0.0384615 +rDVDD/5796 DVDD:715 X46/D0:neg 0.67826 +rDVDD/5797 DVDD:713 DVDD:745 0.0384615 +rDVDD/5798 DVDD:713 DVDD:773 0.0384615 +rDVDD/5799 DVDD:713 X46/D0:neg 0.67826 +rDVDD/5800 DVDD:711 DVDD:743 0.0192308 +rDVDD/5801 DVDD:711 DVDD:771 0.0384615 +rDVDD/5802 DVDD:711 X46/D0:neg 0.67826 +rDVDD/5803 DVDD:709 DVDD:741 0.0384615 +rDVDD/5804 DVDD:709 X46/D0:neg 0.67826 +rDVDD/5805 DVDD:707 DVDD:2096 0.0482197 +rDVDD/5806 DVDD:707 DVDD:709 0.0570659 +rDVDD/5807 DVDD:707 X46/D0:neg 0.185714 +rDVDD/5808 DVDD:702 X46/D0:neg 0.67826 +rDVDD/5809 DVDD:700 X46/D0:neg 0.67826 +rDVDD/5810 DVDD:698 X46/D0:neg 0.67826 +rDVDD/5811 DVDD:696 X46/D0:neg 0.67826 +rDVDD/5812 DVDD:694 X46/D0:neg 0.67826 +rDVDD/5813 DVDD:692 X46/D0:neg 0.67826 +rDVDD/5814 DVDD:690 X46/D0:neg 0.67826 +rDVDD/5815 DVDD:688 X46/D0:neg 0.67826 +rDVDD/5816 DVDD:686 X46/D0:neg 0.67826 +rDVDD/5817 DVDD:684 X46/D0:neg 0.67826 +rDVDD/5818 DVDD:682 X46/D0:neg 0.67826 +rDVDD/5819 DVDD:680 X46/D0:neg 0.67826 +rDVDD/5820 DVDD:678 X46/D0:neg 0.67826 +rDVDD/5821 DVDD:672 DVDD:702 0.0192308 +rDVDD/5822 DVDD:672 X46/D0:neg 0.67826 +rDVDD/5823 DVDD:670 DVDD:700 0.0192308 +rDVDD/5824 DVDD:670 X46/D0:neg 0.67826 +rDVDD/5825 DVDD:668 DVDD:698 0.0192308 +rDVDD/5826 DVDD:668 X46/D0:neg 0.67826 +rDVDD/5827 DVDD:666 DVDD:696 0.0192308 +rDVDD/5828 DVDD:666 X46/D0:neg 0.67826 +rDVDD/5829 DVDD:664 DVDD:694 0.0384615 +rDVDD/5830 DVDD:664 X46/D0:neg 0.67826 +rDVDD/5831 DVDD:662 DVDD:692 0.0192308 +rDVDD/5832 DVDD:662 X46/D0:neg 0.67826 +rDVDD/5833 DVDD:660 DVDD:690 0.0192308 +rDVDD/5834 DVDD:660 X46/D0:neg 0.67826 +rDVDD/5835 DVDD:658 DVDD:688 0.0192308 +rDVDD/5836 DVDD:658 X46/D0:neg 0.67826 +rDVDD/5837 DVDD:656 DVDD:686 0.0192308 +rDVDD/5838 DVDD:656 X46/D0:neg 0.67826 +rDVDD/5839 DVDD:654 DVDD:684 0.0384615 +rDVDD/5840 DVDD:654 X46/D0:neg 0.67826 +rDVDD/5841 DVDD:652 DVDD:682 0.0192308 +rDVDD/5842 DVDD:652 X46/D0:neg 0.67826 +rDVDD/5843 DVDD:650 DVDD:680 0.0192308 +rDVDD/5844 DVDD:650 X46/D0:neg 0.67826 +rDVDD/5845 DVDD:648 DVDD:678 0.0192308 +rDVDD/5846 DVDD:648 X46/D0:neg 0.67826 +rDVDD/5847 DVDD:642 DVDD:2093 0.0482582 +rDVDD/5848 DVDD:642 DVDD:702 0.0378736 +rDVDD/5849 DVDD:642 X46/D0:neg 0.226087 +rDVDD/5850 DVDD:640 DVDD:672 0.0384615 +rDVDD/5851 DVDD:640 DVDD:700 0.0384615 +rDVDD/5852 DVDD:640 X46/D0:neg 0.67826 +rDVDD/5853 DVDD:638 DVDD:670 0.0192308 +rDVDD/5854 DVDD:638 DVDD:698 0.0384615 +rDVDD/5855 DVDD:638 X46/D0:neg 0.67826 +rDVDD/5856 DVDD:636 DVDD:668 0.0384615 +rDVDD/5857 DVDD:636 DVDD:696 0.0384615 +rDVDD/5858 DVDD:636 X46/D0:neg 0.67826 +rDVDD/5859 DVDD:634 DVDD:666 0.0384615 +rDVDD/5860 DVDD:634 DVDD:694 0.0192308 +rDVDD/5861 DVDD:634 X46/D0:neg 0.67826 +rDVDD/5862 DVDD:632 DVDD:664 0.0192308 +rDVDD/5863 DVDD:632 DVDD:692 0.0384615 +rDVDD/5864 DVDD:632 X46/D0:neg 0.67826 +rDVDD/5865 DVDD:630 DVDD:662 0.0384615 +rDVDD/5866 DVDD:630 DVDD:690 0.0384615 +rDVDD/5867 DVDD:630 X46/D0:neg 0.67826 +rDVDD/5868 DVDD:628 DVDD:660 0.0191923 +rDVDD/5869 DVDD:628 DVDD:688 0.0384615 +rDVDD/5870 DVDD:628 X46/D0:neg 0.67826 +rDVDD/5871 DVDD:626 DVDD:658 0.0384615 +rDVDD/5872 DVDD:626 DVDD:686 0.0384615 +rDVDD/5873 DVDD:626 X46/D0:neg 0.67826 +rDVDD/5874 DVDD:624 DVDD:656 0.0384615 +rDVDD/5875 DVDD:624 DVDD:684 0.0192308 +rDVDD/5876 DVDD:624 X46/D0:neg 0.67826 +rDVDD/5877 DVDD:622 DVDD:654 0.0192308 +rDVDD/5878 DVDD:622 DVDD:682 0.0384615 +rDVDD/5879 DVDD:622 X46/D0:neg 0.67826 +rDVDD/5880 DVDD:620 DVDD:652 0.0384615 +rDVDD/5881 DVDD:620 DVDD:680 0.0384615 +rDVDD/5882 DVDD:620 X46/D0:neg 0.67826 +rDVDD/5883 DVDD:618 DVDD:650 0.0192308 +rDVDD/5884 DVDD:618 DVDD:678 0.0384615 +rDVDD/5885 DVDD:618 X46/D0:neg 0.67826 +rDVDD/5886 DVDD:616 DVDD:648 0.0384615 +rDVDD/5887 DVDD:616 X46/D0:neg 0.67826 +rDVDD/5888 DVDD:614 DVDD:2246 0.0482582 +rDVDD/5889 DVDD:614 DVDD:616 0.0570659 +rDVDD/5890 DVDD:614 X46/D0:neg 0.185714 +rDVDD/5891 DVDD:611 D8:neg 0.4 +rDVDD/5892 DVDD:609 DVDD:611 0.0733696 +rDVDD/5893 DVDD:609 D8:neg 0.4 +rDVDD/5894 DVDD:607 DVDD:609 0.0733696 +rDVDD/5895 DVDD:607 DVDD:12287 0.0322337 +rDVDD/5896 DVDD:607 D8:neg 0.4 +rDVDD/5897 DVDD:605 DVDD:12287 0.0411359 +rDVDD/5898 DVDD:605 DVDD:12291 0.0116902 +rDVDD/5899 DVDD:605 D8:neg 0.4 +rDVDD/5900 DVDD:603 DVDD:12291 0.0861359 +rDVDD/5901 DVDD:603 D8:neg 0.4 +rDVDD/5902 DVDD:601 DVDD:603 0.0733696 +rDVDD/5903 DVDD:601 D8:neg 0.4 +rDVDD/5904 DVDD:599 DVDD:601 0.0733696 +rDVDD/5905 DVDD:599 D8:neg 0.4 +rDVDD/5906 DVDD:597 DVDD:599 0.0733696 +rDVDD/5907 DVDD:597 D8:neg 0.4 +rDVDD/5908 DVDD:595 DVDD:597 0.0978261 +rDVDD/5909 DVDD:595 D8:neg 0.4 +rDVDD/5910 DVDD:593 DVDD:595 0.0733696 +rDVDD/5911 DVDD:593 DVDD:12300 0.0253859 +rDVDD/5912 DVDD:593 D8:neg 0.4 +rDVDD/5913 DVDD:591 DVDD:12300 0.0479837 +rDVDD/5914 DVDD:591 DVDD:12304 0.00484239 +rDVDD/5915 DVDD:591 D8:neg 0.4 +rDVDD/5916 DVDD:589 DVDD:12304 0.0685272 +rDVDD/5917 DVDD:589 D8:neg 0.4 +rDVDD/5918 DVDD:587 DVDD:589 0.0978261 +rDVDD/5919 DVDD:587 D8:neg 0.4 +rDVDD/5920 DVDD:585 DVDD:587 0.0733696 +rDVDD/5921 DVDD:585 D8:neg 0.4 +rDVDD/5922 DVDD:583 DVDD:585 0.0733206 +rDVDD/5923 DVDD:583 D8:neg 0.4 +rDVDD/5924 DVDD:581 DVDD:583 0.0733696 +rDVDD/5925 DVDD:581 D8:neg 0.4 +rDVDD/5926 DVDD:579 DVDD:581 0.0978261 +rDVDD/5927 DVDD:579 D8:neg 0.4 +rDVDD/5928 DVDD:577 DVDD:579 0.0733696 +rDVDD/5929 DVDD:577 DVDD:12314 0.0440217 +rDVDD/5930 DVDD:577 D8:neg 0.4 +rDVDD/5931 DVDD:575 DVDD:12314 0.0293478 +rDVDD/5932 DVDD:575 DVDD:12318 0.0234783 +rDVDD/5933 DVDD:575 D8:neg 0.4 +rDVDD/5934 DVDD:573 DVDD:12318 0.0498913 +rDVDD/5935 DVDD:573 D8:neg 0.4 +rDVDD/5936 DVDD:571 DVDD:573 0.0978261 +rDVDD/5937 DVDD:571 D8:neg 0.4 +rDVDD/5938 DVDD:569 DVDD:571 0.0733696 +rDVDD/5939 DVDD:569 D8:neg 0.4 +rDVDD/5940 DVDD:567 DVDD:569 0.0733696 +rDVDD/5941 DVDD:567 D8:neg 0.4 +rDVDD/5942 DVDD:565 DVDD:567 0.0733696 +rDVDD/5943 DVDD:565 D8:neg 0.4 +rDVDD/5944 DVDD:563 DVDD:565 0.0978261 +rDVDD/5945 DVDD:563 DVDD:12327 0.0371739 +rDVDD/5946 DVDD:563 D8:neg 0.4 +rDVDD/5947 DVDD:561 DVDD:12327 0.0361957 +rDVDD/5948 DVDD:561 DVDD:12331 0.0166304 +rDVDD/5949 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DVDD:186 X28/D0:neg 1.73333 +rDVDD/6314 DVDD:184 DVDD:186 0.045 +rDVDD/6315 DVDD:184 X28/D0:neg 1.73333 +rDVDD/6316 DVDD:182 DVDD:184 0.09 +rDVDD/6317 DVDD:182 X28/D0:neg 1.73333 +rDVDD/6318 DVDD:180 DVDD:182 0.045 +rDVDD/6319 DVDD:180 X28/D0:neg 1.73333 +rDVDD/6320 DVDD:178 DVDD:180 0.09 +rDVDD/6321 DVDD:178 X28/D0:neg 1.73333 +rDVDD/6322 DVDD:176 DVDD:178 0.045 +rDVDD/6323 DVDD:176 DVDD:11707 0.0135 +rDVDD/6324 DVDD:176 X28/D0:neg 1.73333 +rDVDD/6325 DVDD:174 DVDD:11710 0.0279 +rDVDD/6326 DVDD:174 X28/D0:neg 1.73333 +rDVDD/6327 DVDD:172 DVDD:174 0.045 +rDVDD/6328 DVDD:172 DVDD:11715 0.0243 +rDVDD/6329 DVDD:172 X28/D0:neg 1.73333 +rDVDD/6330 X27/D0:neg DVDD:11596 1.73333 +rDVDD/6331 X27/D0:neg DVDD:11593 1.73333 +rDVDD/6332 X27/D0:neg DVDD:11590 1.73333 +rDVDD/6333 X27/D0:neg DVDD:11587 1.73333 +rDVDD/6334 X27/D0:neg DVDD:11564 1.73333 +rDVDD/6335 X27/D0:neg DVDD:11561 1.73333 +rDVDD/6336 X27/D0:neg DVDD:11535 0.894532 +rDVDD/6337 X27/D0:neg DVDD:11622 1.31989 +rDVDD/6338 DVDD:161 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+rDVDD/6417 DVDD:75 DVDD:77 0.045 +rDVDD/6418 DVDD:75 X27/D0:neg 1.73333 +rDVDD/6419 DVDD:73 DVDD:75 0.09 +rDVDD/6420 DVDD:73 X27/D0:neg 1.73333 +rDVDD/6421 DVDD:71 DVDD:73 0.045 +rDVDD/6422 DVDD:71 X27/D0:neg 1.73333 +rDVDD/6423 DVDD:69 DVDD:71 0.09 +rDVDD/6424 DVDD:69 X27/D0:neg 1.73333 +rDVDD/6425 DVDD:67 DVDD:69 0.045 +rDVDD/6426 DVDD:67 DVDD:11611 0.0135 +rDVDD/6427 DVDD:67 X27/D0:neg 1.73333 +rDVDD/6428 DVDD:65 DVDD:11614 0.0279 +rDVDD/6429 DVDD:65 X27/D0:neg 1.73333 +rDVDD/6430 DVDD:63 DVDD:65 0.045 +rDVDD/6431 DVDD:63 DVDD:11619 0.0243 +rDVDD/6432 DVDD:63 X27/D0:neg 1.73333 +rDVDD/6433 DVDD:57 DVDD:496 0.0544906 +rDVDD/6434 DVDD:57 D8:neg 0.371429 +rDVDD/6435 DVDD:55 DVDD:57 0.041333 +rDVDD/6436 DVDD:55 D8:neg 0.371429 +rDVDD/6437 DVDD:53 DVDD:55 0.0978261 +rDVDD/6438 DVDD:53 D8:neg 0.371429 +rDVDD/6439 DVDD:51 DVDD:53 0.0733696 +rDVDD/6440 DVDD:51 D8:neg 0.371429 +rDVDD/6441 DVDD:49 DVDD:51 0.0978261 +rDVDD/6442 DVDD:49 D8:neg 0.371429 +rDVDD/6443 DVDD:47 DVDD:49 0.0733696 +rDVDD/6444 DVDD:47 D8:neg 0.371429 +rDVDD/6445 DVDD:45 DVDD:47 0.0978261 +rDVDD/6446 DVDD:45 D8:neg 0.371429 +rDVDD/6447 DVDD:43 DVDD:45 0.0733206 +rDVDD/6448 DVDD:43 D8:neg 0.371429 +rDVDD/6449 DVDD:41 DVDD:43 0.0978261 +rDVDD/6450 DVDD:41 D8:neg 0.371429 +rDVDD/6451 DVDD:39 DVDD:41 0.0733696 +rDVDD/6452 DVDD:39 D8:neg 0.371429 +rDVDD/6453 DVDD:37 DVDD:39 0.0978261 +rDVDD/6454 DVDD:37 D8:neg 0.371429 +rDVDD/6455 DVDD:35 DVDD:37 0.0733696 +rDVDD/6456 DVDD:35 D8:neg 0.371429 +rDVDD/6457 DVDD:33 DVDD:35 0.0978261 +rDVDD/6458 DVDD:33 D8:neg 0.371429 +rDVDD/6459 DVDD:31 DVDD:555 0.0544906 +rDVDD/6460 DVDD:31 DVDD:33 0.0657406 +rDVDD/6461 DVDD:31 D8:neg 0.371429 +rDVDD/6462 DVDD:28 DVDD:552 0.0789961 +rDVDD/6463 DVDD:28 D8:neg 0.371429 +rDVDD/6464 DVDD:26 DVDD:28 0.041333 +rDVDD/6465 DVDD:26 D8:neg 0.371429 +rDVDD/6466 DVDD:24 DVDD:26 0.0978261 +rDVDD/6467 DVDD:24 D8:neg 0.371429 +rDVDD/6468 DVDD:22 DVDD:24 0.0733696 +rDVDD/6469 DVDD:22 D8:neg 0.371429 +rDVDD/6470 DVDD:20 DVDD:22 0.0978261 +rDVDD/6471 DVDD:20 D8:neg 0.371429 +rDVDD/6472 DVDD:18 DVDD:20 0.0733696 +rDVDD/6473 DVDD:18 D8:neg 0.371429 +rDVDD/6474 DVDD:16 DVDD:18 0.0978261 +rDVDD/6475 DVDD:16 D8:neg 0.371429 +rDVDD/6476 DVDD:14 DVDD:16 0.0733206 +rDVDD/6477 DVDD:14 D8:neg 0.371429 +rDVDD/6478 DVDD:12 DVDD:14 0.0978261 +rDVDD/6479 DVDD:12 D8:neg 0.371429 +rDVDD/6480 DVDD:10 DVDD:12 0.0733696 +rDVDD/6481 DVDD:10 D8:neg 0.371429 +rDVDD/6482 DVDD:8 DVDD:10 0.0978261 +rDVDD/6483 DVDD:8 D8:neg 0.371429 +rDVDD/6484 DVDD:6 DVDD:8 0.0733696 +rDVDD/6485 DVDD:6 D8:neg 0.371429 +rDVDD/6486 DVDD:4 DVDD:6 0.0978261 +rDVDD/6487 DVDD:4 D8:neg 0.371429 +rDVDD/6488 DVDD:2 DVDD:611 0.0789961 +rDVDD/6489 DVDD:2 DVDD:4 0.0657406 +rDVDD/6490 DVDD:2 D8:neg 0.371429 +rDVDD/6491 X46/D1:neg X46/X30/D0:neg 0.01 +rDVDD/6492 X46/X33/D0:neg X46/X30/D0:neg 0.01 +rDVDD/6493 X46/X32/D0:neg X46/X30/D0:neg 0.01 +rDVDD/6494 X46/X31/D0:neg X46/X30/D0:neg 0.01 +cVDD/0 VDD:435 vss 66.3382f +cVDD/1 VDD:336 vss 28.0005f +cVDD/2 VDD:191 vss 19.5806f +cVDD/3 VDD:94 vss 19.5214f +rVDD/4 VDD:435 VDD:436 0.143617 +rVDD/5 VDD:433 VDD:436 0.0365143 +rVDD/6 VDD:432 VDD:435 0.0365143 +rVDD/7 VDD:432 VDD:433 0.143617 +rVDD/8 VDD:430 VDD:433 0.00912857 +rVDD/9 VDD:429 VDD:432 0.00912857 +rVDD/10 VDD:429 VDD:430 0.143617 +rVDD/11 VDD:427 VDD:430 0.0456429 +rVDD/12 VDD:426 VDD:429 0.0456429 +rVDD/13 VDD:426 VDD:427 0.143617 +rVDD/14 VDD:422 VDD:427 0.0365143 +rVDD/15 VDD:421 VDD:426 0.0365143 +rVDD/16 VDD:421 VDD:422 0.0718085 +rVDD/17 VDD:419 VDD:422 0.0456429 +rVDD/18 VDD:418 VDD:421 0.0456429 +rVDD/19 VDD:418 VDD:419 0.143617 +rVDD/20 VDD:413 VDD:418 0.0365143 +rVDD/21 VDD:410 VDD:413 0.0456429 +rVDD/22 VDD:405 VDD:410 0.0456429 +rVDD/23 VDD:402 VDD:405 0.0456429 +rVDD/24 VDD:397 VDD:402 0.0365143 +rVDD/25 VDD:394 VDD:397 0.0456429 +rVDD/26 VDD:391 VDD:394 0.0365143 +rVDD/27 VDD:388 VDD:391 0.00912857 +rVDD/28 VDD:385 VDD:388 0.0456429 +rVDD/29 VDD:380 VDD:385 0.0365143 +rVDD/30 VDD:380 VDD:381 0.0718085 +rVDD/31 VDD:378 VDD:381 0.0456429 +rVDD/32 VDD:377 VDD:380 0.0456429 +rVDD/33 VDD:377 VDD:378 0.143617 +rVDD/34 VDD:372 VDD:377 0.0365143 +rVDD/35 VDD:369 VDD:372 0.0456429 +rVDD/36 VDD:364 VDD:369 0.0456429 +rVDD/37 VDD:361 VDD:364 0.0456429 +rVDD/38 VDD:361 VDD:362 0.143617 +rVDD/39 VDD:357 VDD 0.0438429 +rVDD/40 VDD:357 VDD:362 0.0365143 +rVDD/41 VDD:356 VDD:361 0.0365143 +rVDD/42 VDD:356 VDD:357 0.0718085 +rVDD/43 VDD:350 VDD 0.0018 +rVDD/44 VDD:349 VDD 0.0018 +rVDD/45 VDD:349 VDD:350 0.143617 +rVDD/46 VDD:346 VDD:350 0.0365143 +rVDD/47 VDD:346 VDD:349 0.180131 +rVDD/48 VDD:336 VDD:337 0.143617 +rVDD/49 VDD:334 VDD:337 0.0365143 +rVDD/50 VDD:333 VDD:336 0.0365143 +rVDD/51 VDD:333 VDD:334 0.143617 +rVDD/52 VDD:331 VDD:334 0.00912857 +rVDD/53 VDD:330 VDD:333 0.00912857 +rVDD/54 VDD:330 VDD:331 0.143617 +rVDD/55 VDD:328 VDD:331 0.0456429 +rVDD/56 VDD:327 VDD:330 0.0456429 +rVDD/57 VDD:327 VDD:328 0.143617 +rVDD/58 VDD:323 VDD:328 0.0365143 +rVDD/59 VDD:322 VDD:327 0.0365143 +rVDD/60 VDD:322 VDD:323 0.0718085 +rVDD/61 VDD:320 VDD:323 0.0456429 +rVDD/62 VDD:319 VDD:322 0.0456429 +rVDD/63 VDD:319 VDD:320 0.143617 +rVDD/64 VDD:314 VDD:319 0.0365143 +rVDD/65 VDD:311 VDD:314 0.0456429 +rVDD/66 VDD:306 VDD:311 0.0456429 +rVDD/67 VDD:303 VDD:306 0.0456429 +rVDD/68 VDD:298 VDD:303 0.0365143 +rVDD/69 VDD:295 VDD:298 0.0456429 +rVDD/70 VDD:292 VDD:295 0.0365143 +rVDD/71 VDD:289 VDD:292 0.00912857 +rVDD/72 VDD:286 VDD:289 0.0456429 +rVDD/73 VDD:281 VDD:286 0.0365143 +rVDD/74 VDD:281 VDD:282 0.0718085 +rVDD/75 VDD:279 VDD:282 0.0456429 +rVDD/76 VDD:278 VDD:281 0.0456429 +rVDD/77 VDD:278 VDD:279 0.143617 +rVDD/78 VDD:273 VDD:278 0.0365143 +rVDD/79 VDD:270 VDD:273 0.0456429 +rVDD/80 VDD:265 VDD:270 0.0456429 +rVDD/81 VDD:262 VDD:265 0.0456429 +rVDD/82 VDD:262 VDD:263 0.143617 +rVDD/83 VDD:258 VDD 0.0438429 +rVDD/84 VDD:258 VDD:263 0.0365143 +rVDD/85 VDD:257 VDD:262 0.0365143 +rVDD/86 VDD:257 VDD:258 0.0718085 +rVDD/87 VDD:251 VDD 0.0018 +rVDD/88 VDD:250 VDD 0.0018 +rVDD/89 VDD:250 VDD:251 0.143617 +rVDD/90 VDD:247 VDD:251 0.0365143 +rVDD/91 VDD:247 VDD:250 0.180131 +rVDD/92 VDD:243 VDD:356 0.0327214 +rVDD/93 VDD:239 VDD:243 4.5558 +rVDD/94 VDD:236 VDD:239 0.0558 +rVDD/95 VDD:233 VDD:236 0.1116 +rVDD/96 VDD:230 VDD:233 0.0558 +rVDD/97 VDD:227 VDD:230 0.1116 +rVDD/98 VDD:224 VDD:227 0.0558 +rVDD/99 VDD:222 VDD 0.00315 +rVDD/100 VDD:222 VDD:239 1.5 +rVDD/101 VDD:222 VDD:236 1.5 +rVDD/102 VDD:222 VDD:233 1.5 +rVDD/103 VDD:222 VDD:230 1.5 +rVDD/104 VDD:222 VDD:227 1.5 +rVDD/105 VDD:222 VDD:224 1.5 +rVDD/106 VDD:222 VDD:243 0.00797143 +rVDD/107 VDD:221 VDD:224 0.1116 +rVDD/108 VDD:221 VDD:222 1.5 +rVDD/109 VDD:219 VDD:257 0.0327214 +rVDD/110 VDD:218 VDD:221 4.482 +rVDD/111 VDD:218 VDD:219 4.5 +rVDD/112 VDD:197 VDD 0.00315 +rVDD/113 VDD:197 VDD:218 0.387402 +rVDD/114 VDD:197 VDD:219 0.00797143 +rVDD/115 VDD:191 VDD:435 0.166179 +rVDD/116 VDD:191 VDD:436 0.0456429 +rVDD/117 VDD:187 VDD:191 0.140821 +rVDD/118 VDD:187 VDD:436 0.143617 +rVDD/119 VDD:184 VDD:187 0.0162286 +rVDD/120 VDD:184 VDD:433 0.143617 +rVDD/121 VDD:181 VDD:184 0.00405714 +rVDD/122 VDD:181 VDD:430 0.143617 +rVDD/123 VDD:178 VDD:181 0.0202857 +rVDD/124 VDD:178 VDD:427 0.143617 +rVDD/125 VDD:173 VDD:178 0.0162286 +rVDD/126 VDD:173 VDD:422 0.0718085 +rVDD/127 VDD:170 VDD:173 0.0202857 +rVDD/128 VDD:170 VDD:419 0.143617 +rVDD/129 VDD:166 VDD:413 0.0718085 +rVDD/130 VDD:166 VDD:419 0.0365143 +rVDD/131 VDD:165 VDD:170 0.0162286 +rVDD/132 VDD:165 VDD:166 0.0718085 +rVDD/133 VDD:163 VDD:410 0.143617 +rVDD/134 VDD:163 VDD:166 0.0456429 +rVDD/135 VDD:162 VDD:165 0.0202857 +rVDD/136 VDD:162 VDD:163 0.143617 +rVDD/137 VDD:158 VDD:405 0.0718085 +rVDD/138 VDD:158 VDD:163 0.0456429 +rVDD/139 VDD:157 VDD:162 0.0202857 +rVDD/140 VDD:157 VDD:158 0.0718085 +rVDD/141 VDD:155 VDD:402 0.143617 +rVDD/142 VDD:155 VDD:158 0.0456429 +rVDD/143 VDD:154 VDD:157 0.0202857 +rVDD/144 VDD:154 VDD:155 0.143617 +rVDD/145 VDD:150 VDD:397 0.0718085 +rVDD/146 VDD:150 VDD:155 0.0365143 +rVDD/147 VDD:149 VDD:154 0.0162286 +rVDD/148 VDD:149 VDD:150 0.0718085 +rVDD/149 VDD:147 VDD:394 0.143617 +rVDD/150 VDD:147 VDD:150 0.0456429 +rVDD/151 VDD:146 VDD:149 0.0202857 +rVDD/152 VDD:146 VDD:147 0.143617 +rVDD/153 VDD:144 VDD:391 0.143617 +rVDD/154 VDD:144 VDD:147 0.0365143 +rVDD/155 VDD:143 VDD:146 0.0162286 +rVDD/156 VDD:143 VDD:144 0.143617 +rVDD/157 VDD:141 VDD:388 0.143617 +rVDD/158 VDD:141 VDD:144 0.00912857 +rVDD/159 VDD:140 VDD:143 0.00405714 +rVDD/160 VDD:140 VDD:141 0.143617 +rVDD/161 VDD:138 VDD:385 0.143617 +rVDD/162 VDD:138 VDD:381 0.0365143 +rVDD/163 VDD:138 VDD:141 0.0456429 +rVDD/164 VDD:137 VDD:140 0.0202857 +rVDD/165 VDD:137 VDD:138 0.143617 +rVDD/166 VDD:132 VDD:137 0.0162286 +rVDD/167 VDD:132 VDD:381 0.0718085 +rVDD/168 VDD:129 VDD:132 0.0202857 +rVDD/169 VDD:129 VDD:378 0.143617 +rVDD/170 VDD:125 VDD:372 0.0718085 +rVDD/171 VDD:125 VDD:378 0.0365143 +rVDD/172 VDD:124 VDD:129 0.0162286 +rVDD/173 VDD:124 VDD:125 0.0718085 +rVDD/174 VDD:122 VDD:369 0.143617 +rVDD/175 VDD:122 VDD:125 0.0456429 +rVDD/176 VDD:121 VDD:124 0.0202857 +rVDD/177 VDD:121 VDD:122 0.143617 +rVDD/178 VDD:117 VDD:364 0.0718085 +rVDD/179 VDD:117 VDD:362 0.0456429 +rVDD/180 VDD:117 VDD:122 0.0456429 +rVDD/181 VDD:116 VDD:121 0.0202857 +rVDD/182 VDD:116 VDD:117 0.0718085 +rVDD/183 VDD:113 VDD:116 0.0202857 +rVDD/184 VDD:113 VDD:362 0.143617 +rVDD/185 VDD:108 VDD:113 0.0162286 +rVDD/186 VDD:108 VDD:357 0.0718085 +rVDD/187 VDD VDD:108 0.0194857 +rVDD/188 VDD:103 VDD 0.0008 +rVDD/189 VDD:103 VDD:350 0.143617 +rVDD/190 VDD:103 VDD:346 0.159846 +rVDD/191 VDD:94 VDD:336 0.166179 +rVDD/192 VDD:94 VDD:337 0.0456429 +rVDD/193 VDD:90 VDD:94 0.140821 +rVDD/194 VDD:90 VDD:337 0.143617 +rVDD/195 VDD:87 VDD:90 0.0162286 +rVDD/196 VDD:87 VDD:334 0.143617 +rVDD/197 VDD:84 VDD:87 0.00405714 +rVDD/198 VDD:84 VDD:331 0.143617 +rVDD/199 VDD:81 VDD:84 0.0202857 +rVDD/200 VDD:81 VDD:328 0.143617 +rVDD/201 VDD:76 VDD:81 0.0162286 +rVDD/202 VDD:76 VDD:323 0.0718085 +rVDD/203 VDD:73 VDD:76 0.0202857 +rVDD/204 VDD:73 VDD:320 0.143617 +rVDD/205 VDD:69 VDD:314 0.0718085 +rVDD/206 VDD:69 VDD:320 0.0365143 +rVDD/207 VDD:68 VDD:73 0.0162286 +rVDD/208 VDD:68 VDD:69 0.0718085 +rVDD/209 VDD:66 VDD:311 0.143617 +rVDD/210 VDD:66 VDD:69 0.0456429 +rVDD/211 VDD:65 VDD:68 0.0202857 +rVDD/212 VDD:65 VDD:66 0.143617 +rVDD/213 VDD:61 VDD:306 0.0718085 +rVDD/214 VDD:61 VDD:66 0.0456429 +rVDD/215 VDD:60 VDD:65 0.0202857 +rVDD/216 VDD:60 VDD:61 0.0718085 +rVDD/217 VDD:58 VDD:303 0.143617 +rVDD/218 VDD:58 VDD:61 0.0456429 +rVDD/219 VDD:57 VDD:60 0.0202857 +rVDD/220 VDD:57 VDD:58 0.143617 +rVDD/221 VDD:53 VDD:298 0.0718085 +rVDD/222 VDD:53 VDD:58 0.0365143 +rVDD/223 VDD:52 VDD:57 0.0162286 +rVDD/224 VDD:52 VDD:53 0.0718085 +rVDD/225 VDD:50 VDD:295 0.143617 +rVDD/226 VDD:50 VDD:53 0.0456429 +rVDD/227 VDD:49 VDD:52 0.0202857 +rVDD/228 VDD:49 VDD:50 0.143617 +rVDD/229 VDD:47 VDD:292 0.143617 +rVDD/230 VDD:47 VDD:50 0.0365143 +rVDD/231 VDD:46 VDD:49 0.0162286 +rVDD/232 VDD:46 VDD:47 0.143617 +rVDD/233 VDD:44 VDD:289 0.143617 +rVDD/234 VDD:44 VDD:47 0.00912857 +rVDD/235 VDD:43 VDD:46 0.00405714 +rVDD/236 VDD:43 VDD:44 0.143617 +rVDD/237 VDD:41 VDD:286 0.143617 +rVDD/238 VDD:41 VDD:282 0.0365143 +rVDD/239 VDD:41 VDD:44 0.0456429 +rVDD/240 VDD:40 VDD:43 0.0202857 +rVDD/241 VDD:40 VDD:41 0.143617 +rVDD/242 VDD:35 VDD:40 0.0162286 +rVDD/243 VDD:35 VDD:282 0.0718085 +rVDD/244 VDD:32 VDD:35 0.0202857 +rVDD/245 VDD:32 VDD:279 0.143617 +rVDD/246 VDD:28 VDD:273 0.0718085 +rVDD/247 VDD:28 VDD:279 0.0365143 +rVDD/248 VDD:27 VDD:32 0.0162286 +rVDD/249 VDD:27 VDD:28 0.0718085 +rVDD/250 VDD:25 VDD:270 0.143617 +rVDD/251 VDD:25 VDD:28 0.0456429 +rVDD/252 VDD:24 VDD:27 0.0202857 +rVDD/253 VDD:24 VDD:25 0.143617 +rVDD/254 VDD:20 VDD:265 0.0718085 +rVDD/255 VDD:20 VDD:263 0.0456429 +rVDD/256 VDD:20 VDD:25 0.0456429 +rVDD/257 VDD:19 VDD:24 0.0202857 +rVDD/258 VDD:19 VDD:20 0.0718085 +rVDD/259 VDD:16 VDD:19 0.0202857 +rVDD/260 VDD:16 VDD:263 0.143617 +rVDD/261 VDD:11 VDD:16 0.0162286 +rVDD/262 VDD:11 VDD:258 0.0718085 +rVDD/263 VDD VDD:11 0.0194857 +rVDD/264 VDD:6 VDD 0.0008 +rVDD/265 VDD:6 VDD:251 0.143617 +rVDD/266 VDD:6 VDD:247 0.159846 +cPAD/0 PAD:15142 vss 0.500352f +cPAD/1 PAD:15004 vss 0.655995f +cPAD/2 PAD:14602 vss 0.533546f +cPAD/3 PAD:14601 vss 1.76086f +cPAD/4 PAD:9454 vss 0.533557f +cPAD/5 PAD:9453 vss 1.76087f +cPAD/6 PAD:9449 vss 0.23336f +cPAD/7 PAD:9304 vss 0.947604f +cPAD/8 PAD:8893 vss 13.2863f +cPAD/9 PAD:8891 vss 8.24412f +cPAD/10 PAD:8890 vss 3.62466f +cPAD/11 PAD:8723 vss 1.97215f +cPAD/12 PAD:8553 vss 1.52711f +cPAD/13 PAD:8383 vss 1.52711f +cPAD/14 PAD:8213 vss 1.52711f +cPAD/15 PAD:8043 vss 1.52711f +cPAD/16 PAD:7873 vss 1.52711f +cPAD/17 PAD:7703 vss 1.52711f +cPAD/18 PAD:7533 vss 1.52711f +cPAD/19 PAD:7363 vss 1.52711f +cPAD/20 PAD:7193 vss 1.52711f +cPAD/21 PAD:7023 vss 1.52711f +cPAD/22 PAD:6853 vss 1.52711f +cPAD/23 PAD:6683 vss 1.52711f +cPAD/24 PAD:6513 vss 1.52711f +cPAD/25 PAD:6343 vss 1.52711f +cPAD/26 PAD:6173 vss 1.52711f +cPAD/27 PAD:6003 vss 1.52711f +cPAD/28 PAD:5833 vss 1.52711f +cPAD/29 PAD:5663 vss 1.52711f +cPAD/30 PAD:5493 vss 1.52711f +cPAD/31 PAD:5323 vss 1.52711f +cPAD/32 PAD:5153 vss 1.52711f +cPAD/33 PAD:4983 vss 1.52711f +cPAD/34 PAD:4813 vss 1.52711f +cPAD/35 PAD:4643 vss 1.52711f +cPAD/36 PAD:4473 vss 1.52711f +cPAD/37 PAD:4303 vss 1.52711f +cPAD/38 PAD:4133 vss 1.52711f +cPAD/39 PAD:3963 vss 2.00416f +cPAD/40 PAD:3769 vss 5.61282f +cPAD/41 PAD:3725 vss 5.31154f +cPAD/42 R7:pos vss 0.072827f +cPAD/43 R6:pos vss 0.072827f +cPAD/44 R5:pos vss 0.072827f +cPAD/45 R4:pos vss 0.072827f +cPAD/46 R3:pos vss 0.072827f +rPAD/47 PAD:16978 PAD:16979 0.0786026 +rPAD/48 PAD:15142 PAD:16890 0.0292349 +rPAD/49 PAD:15137 PAD:16890 0.000724832 +rPAD/50 PAD:15134 PAD:16832 0.0314094 +rPAD/51 PAD:15134 PAD:15137 0.0599195 +rPAD/52 PAD:15130 PAD:16774 0.0347919 +rPAD/53 PAD:15130 PAD:16832 0.0135302 +rPAD/54 PAD:15129 PAD:15130 0.346154 +rPAD/55 PAD:15126 PAD:16716 0.0381745 +rPAD/56 PAD:15126 PAD:16774 0.0101477 +rPAD/57 PAD:15125 PAD:15126 0.346154 +rPAD/58 PAD:15090 PAD:16194 0.0386577 +rPAD/59 PAD:15090 PAD:16252 0.00966443 +rPAD/60 PAD:15086 PAD:16136 0.0270604 +rPAD/61 PAD:15086 PAD:16194 0.0212617 +rPAD/62 PAD:15082 PAD:16078 0.030443 +rPAD/63 PAD:15082 PAD:16136 0.0178792 +rPAD/64 PAD:15038 PAD:15440 0.0227114 +rPAD/65 PAD:15038 PAD:15498 0.0256107 +rPAD/66 PAD:15034 PAD:15382 0.026094 +rPAD/67 PAD:15034 PAD:15440 0.0222282 +rPAD/68 PAD:15030 PAD:15324 0.0294765 +rPAD/69 PAD:15030 PAD:15382 0.0188456 +rPAD/70 PAD:15026 PAD:15266 0.0328591 +rPAD/71 PAD:15026 PAD:15324 0.0154631 +rPAD/72 PAD:15014 PAD:15017 0.0449396 +rPAD/73 PAD:14987 PAD:14989 0.0182751 +rPAD/74 PAD:14981 PAD:14983 0.0233843 +rPAD/75 PAD:14971 PAD:14973 0.00569869 +rPAD/76 PAD:14968 PAD:14971 0.0558079 +rPAD/77 PAD:14966 PAD:14968 0.0170961 +rPAD/78 PAD:14961 PAD:14963 0.0119869 +rPAD/79 PAD:14948 PAD:17001 0.0524672 +rPAD/80 PAD:14948 PAD:17003 0.0261354 +rPAD/81 PAD:14947 PAD:14949 0.0261354 +rPAD/82 PAD:14947 PAD:14948 0.9 +rPAD/83 PAD:14945 PAD:14947 0.0524672 +rPAD/84 PAD:14943 PAD:16999 0.0473581 +rPAD/85 PAD:14943 PAD:17001 0.0312445 +rPAD/86 PAD:14942 PAD:14943 0.9 +rPAD/87 PAD:14940 PAD:14942 0.0473581 +rPAD/88 PAD:14939 PAD:16997 0.0701528 +rPAD/89 PAD:14939 PAD:16999 0.00844978 +rPAD/90 PAD:14938 PAD:14940 0.00844978 +rPAD/91 PAD:14938 PAD:14939 0.9 +rPAD/92 PAD:14934 PAD:16997 0.013559 +rPAD/93 PAD:14933 PAD:14935 0.013559 +rPAD/94 PAD:14933 PAD:14934 0.9 +rPAD/95 PAD:14930 PAD:16994 0.00923581 +rPAD/96 PAD:14930 PAD:14934 0.0558079 +rPAD/97 PAD:14929 PAD:14930 0.9 +rPAD/98 PAD:14927 PAD:14929 0.00923581 +rPAD/99 PAD:14924 PAD:16992 0.00412664 +rPAD/100 PAD:14924 PAD:16994 0.074476 +rPAD/101 PAD:14923 PAD:14924 0.9 +rPAD/102 PAD:14921 PAD:14923 0.00412664 +rPAD/103 PAD:14911 PAD:14913 0.0218122 +rPAD/104 PAD:14909 PAD:14911 0.0339956 +rPAD/105 PAD:14904 PAD:14906 0.0391048 +rPAD/106 PAD:14899 PAD:14901 0.01631 +rPAD/107 PAD:14893 PAD:14895 0.0214192 +rPAD/108 PAD:14890 PAD:16979 0.00137555 +rPAD/109 PAD:14889 PAD:14890 0.9 +rPAD/110 PAD:14887 PAD:14889 0.00137555 +rPAD/111 PAD:14884 PAD:16978 0.00373362 +rPAD/112 PAD:14883 PAD:14885 0.00373362 +rPAD/113 PAD:14883 PAD:14884 0.9 +rPAD/114 PAD:14880 PAD:14883 0.0558079 +rPAD/115 PAD:14878 PAD:14880 0.0190611 +rPAD/116 PAD:14873 PAD:14875 0.013952 +rPAD/117 PAD:14865 PAD:16969 0.0316376 +rPAD/118 PAD:14865 PAD:16971 0.0469651 +rPAD/119 PAD:14864 PAD:14865 0.9 +rPAD/120 PAD:14860 PAD:16967 0.0544323 +rPAD/121 PAD:14860 PAD:16969 0.0241703 +rPAD/122 PAD:14855 PAD:16965 0.0493231 +rPAD/123 PAD:14855 PAD:16967 0.0292795 +rPAD/124 PAD:14850 PAD:14852 0.00648472 +rPAD/125 PAD:14846 PAD:16963 0.0115939 +rPAD/126 PAD:14845 PAD:14847 0.0115939 +rPAD/127 PAD:14845 PAD:14846 0.9 +rPAD/128 PAD:14842 PAD:16960 0.0112009 +rPAD/129 PAD:14842 PAD:14846 0.0558079 +rPAD/130 PAD:14841 PAD:14842 0.9 +rPAD/131 PAD:14839 PAD:14841 0.0112009 +rPAD/132 PAD:14836 PAD:16958 0.0060917 +rPAD/133 PAD:14836 PAD:16960 0.0725109 +rPAD/134 PAD:14835 PAD:14836 0.9 +rPAD/135 PAD:14833 PAD:14835 0.0060917 +rPAD/136 PAD:14831 PAD:16958 0.0497162 +rPAD/137 PAD:14827 PAD:15144 0.0224017 +rPAD/138 PAD:14827 PAD:14831 0.0925546 +rPAD/139 PAD:14823 PAD:15144 0.00196507 +rPAD/140 PAD:14822 PAD:14823 0.9 +rPAD/141 PAD:14814 PAD:16890 0.026775 +rPAD/142 PAD:14811 PAD:14814 0.0279 +rPAD/143 PAD:14803 PAD:14806 0.01395 +rPAD/144 PAD:14792 PAD:14795 0.01395 +rPAD/145 PAD:14792 PAD:14793 0.586956 +rPAD/146 PAD:14785 PAD:14788 0.01395 +rPAD/147 PAD:14785 PAD:14786 0.586956 +rPAD/148 PAD:14782 PAD:14785 0.01395 +rPAD/149 PAD:14778 PAD:14779 0.586956 +rPAD/150 PAD:14771 PAD:14774 0.01395 +rPAD/151 PAD:14764 PAD:14767 0.01395 +rPAD/152 PAD:14764 PAD:14765 0.586956 +rPAD/153 PAD:14761 PAD:14765 0.0279 +rPAD/154 PAD:14760 PAD:14761 0.586956 +rPAD/155 PAD:14758 PAD:14761 0.01395 +rPAD/156 PAD:14754 PAD:14758 0.0279 +rPAD/157 PAD:14753 PAD:14754 0.586956 +rPAD/158 PAD:14751 PAD:14754 0.01395 +rPAD/159 PAD:14750 PAD:14753 0.01395 +rPAD/160 PAD:14750 PAD:14751 0.586956 +rPAD/161 PAD:14747 PAD:14751 0.0279 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PAD:150 PAD:9651 0.586956 +rPAD/11352 PAD:148 PAD:9640 0.586956 +rPAD/11353 PAD:148 PAD:9638 0.01395 +rPAD/11354 PAD:148 PAD:9645 0.0279 +rPAD/11355 PAD:144 PAD:9619 0.586956 +rPAD/11356 PAD:144 PAD:9617 0.01395 +rPAD/11357 PAD:136 PAD:9577 0.586956 +rPAD/11358 PAD:136 PAD:9574 0.0279 +rPAD/11359 PAD:134 PAD:9566 0.586956 +rPAD/11360 PAD:134 PAD:9564 0.01395 +rPAD/11361 PAD:132 PAD:3860 0.586956 +rPAD/11362 PAD:124 PAD:9513 0.586956 +rPAD/11363 PAD:124 PAD:9511 0.01395 +rPAD/11364 PAD:122 PAD:9500 0.0279 +rPAD/11365 PAD:122 PAD:3815 0.586956 +rPAD/11366 PAD:120 PAD:9492 0.586956 +rPAD/11367 PAD:118 PAD:9481 0.586956 +rPAD/11368 PAD:118 PAD:9486 0.0279 +rPAD/11369 PAD:114 PAD:9460 0.586956 +rPAD/11370 PAD:114 PAD:9458 0.01395 +rPAD/11371 PAD:114 PAD:9465 0.0279 +rPAD/11372 PAD:113 PAD:154 9.79717e-05 +rPAD/11373 PAD:113 PAD:9663 0.586956 +rPAD/11374 PAD:113 PAD:150 0.586956 +rPAD/11375 PAD:113 PAD:148 0.586956 +rPAD/11376 PAD:113 PAD:9631 0.586956 +rPAD/11377 PAD:113 PAD:144 0.586956 +rPAD/11378 PAD:113 PAD:9610 0.586956 +rPAD/11379 PAD:113 PAD:9599 0.586956 +rPAD/11380 PAD:113 PAD:9588 0.586956 +rPAD/11381 PAD:113 PAD:136 0.586956 +rPAD/11382 PAD:113 PAD:134 0.586956 +rPAD/11383 PAD:113 PAD:132 0.586956 +rPAD/11384 PAD:113 PAD:9546 0.586956 +rPAD/11385 PAD:113 PAD:9535 0.586956 +rPAD/11386 PAD:113 PAD:9525 0.586956 +rPAD/11387 PAD:113 PAD:124 0.586956 +rPAD/11388 PAD:113 PAD:122 0.586956 +rPAD/11389 PAD:113 PAD:120 0.586956 +rPAD/11390 PAD:113 PAD:118 0.586956 +rPAD/11391 PAD:113 PAD:9472 0.586956 +rPAD/11392 PAD:113 PAD:114 0.586956 +rPAD/11393 PAD:110 PAD:113 0.00037964 +rPAD/11394 PAD:110 PAD:14827 0.9 +rPAD/11395 PAD:106 PAD:9658 0.586956 +rPAD/11396 PAD:106 PAD:9663 0.0279 +rPAD/11397 PAD:104 PAD:9647 0.586956 +rPAD/11398 PAD:104 PAD:9645 0.01395 +rPAD/11399 PAD:104 PAD:150 0.0279 +rPAD/11400 PAD:100 PAD:9626 0.586956 +rPAD/11401 PAD:100 PAD:9631 0.0279 +rPAD/11402 PAD:94 PAD:9594 0.586956 +rPAD/11403 PAD:94 PAD:9599 0.0279 +rPAD/11404 PAD:92 PAD:9584 0.586956 +rPAD/11405 PAD:92 PAD:9588 0.01395 +rPAD/11406 PAD:86 PAD:9552 0.586956 +rPAD/11407 PAD:86 PAD:132 0.0279 +rPAD/11408 PAD:82 PAD:9531 0.586956 +rPAD/11409 PAD:82 PAD:9535 0.01395 +rPAD/11410 PAD:80 PAD:9520 0.586956 +rPAD/11411 PAD:80 PAD:9525 0.0279 +rPAD/11412 PAD:74 PAD:9488 0.586956 +rPAD/11413 PAD:74 PAD:9486 0.01395 +rPAD/11414 PAD:74 PAD:120 0.0279 +rPAD/11415 PAD:72 PAD:9478 0.586956 +rPAD/11416 PAD:72 PAD:9476 0.01395 +rPAD/11417 PAD:72 PAD:118 0.01395 +rPAD/11418 PAD:70 PAD:9467 0.586956 +rPAD/11419 PAD:70 PAD:9465 0.01395 +rPAD/11420 PAD:70 PAD:9472 0.0279 +rPAD/11421 PAD:65 PAD:110 0.00037964 +rPAD/11422 PAD:65 PAD:9666 0.225 +rPAD/11423 PAD:65 PAD:106 0.586956 +rPAD/11424 PAD:65 PAD:104 0.586956 +rPAD/11425 PAD:65 PAD:9638 0.586956 +rPAD/11426 PAD:65 PAD:100 0.586956 +rPAD/11427 PAD:65 PAD:9617 0.586956 +rPAD/11428 PAD:65 PAD:9606 0.586956 +rPAD/11429 PAD:65 PAD:94 0.586956 +rPAD/11430 PAD:65 PAD:92 0.586956 +rPAD/11431 PAD:65 PAD:9574 0.586956 +rPAD/11432 PAD:65 PAD:9564 0.586956 +rPAD/11433 PAD:65 PAD:86 0.586956 +rPAD/11434 PAD:65 PAD:9542 0.586956 +rPAD/11435 PAD:65 PAD:82 0.586956 +rPAD/11436 PAD:65 PAD:80 0.586956 +rPAD/11437 PAD:65 PAD:9511 0.586956 +rPAD/11438 PAD:65 PAD:9500 0.586956 +rPAD/11439 PAD:65 PAD:74 0.586956 +rPAD/11440 PAD:65 PAD:72 0.586956 +rPAD/11441 PAD:65 PAD:70 0.586956 +rPAD/11442 PAD:65 PAD:9458 0.586956 +rPAD/11443 PAD:65 PAD:14823 0.9 +rPAD/11444 PAD:63 PAD:15008 0.346154 +rPAD/11445 PAD:63 PAD:15145 0.0123221 +rPAD/11446 PAD:62 PAD:65 0.000281669 +rPAD/11447 PAD:62 PAD:63 0.346154 +rPAD/11448 PAD:60 PAD:9655 0.586956 +rPAD/11449 PAD:60 PAD:150 0.0279 +rPAD/11450 PAD:60 PAD:106 0.01395 +rPAD/11451 PAD:56 PAD:9634 0.586956 +rPAD/11452 PAD:56 PAD:9631 0.0279 +rPAD/11453 PAD:56 PAD:9638 0.01395 +rPAD/11454 PAD:54 PAD:9623 0.586956 +rPAD/11455 PAD:54 PAD:144 0.0279 +rPAD/11456 PAD:54 PAD:100 0.01395 +rPAD/11457 PAD:48 PAD:9591 0.586956 +rPAD/11458 PAD:48 PAD:9588 0.0279 +rPAD/11459 PAD:48 PAD:94 0.01395 +rPAD/11460 PAD:46 PAD:9581 0.586956 +rPAD/11461 PAD:46 PAD:136 0.0279 +rPAD/11462 PAD:46 PAD:92 0.01395 +rPAD/11463 PAD:44 PAD:9570 0.586956 +rPAD/11464 PAD:44 PAD:134 0.0279 +rPAD/11465 PAD:44 PAD:9574 0.01395 +rPAD/11466 PAD:42 PAD:9559 0.586956 +rPAD/11467 PAD:42 PAD:132 0.01395 +rPAD/11468 PAD:42 PAD:9564 0.0279 +rPAD/11469 PAD:40 PAD:9549 0.586956 +rPAD/11470 PAD:40 PAD:9546 0.0279 +rPAD/11471 PAD:40 PAD:86 0.01395 +rPAD/11472 PAD:38 PAD:9538 0.586956 +rPAD/11473 PAD:38 PAD:9535 0.0279 +rPAD/11474 PAD:38 PAD:9542 0.01395 +rPAD/11475 PAD:36 PAD:9528 0.586956 +rPAD/11476 PAD:36 PAD:9525 0.0279 +rPAD/11477 PAD:36 PAD:82 0.01395 +rPAD/11478 PAD:34 PAD:9517 0.586956 +rPAD/11479 PAD:34 PAD:124 0.0279 +rPAD/11480 PAD:34 PAD:80 0.01395 +rPAD/11481 PAD:32 PAD:9506 0.586956 +rPAD/11482 PAD:32 PAD:122 0.01395 +rPAD/11483 PAD:32 PAD:9511 0.0279 +rPAD/11484 PAD:30 PAD:9496 0.586956 +rPAD/11485 PAD:30 PAD:120 0.0279 +rPAD/11486 PAD:30 PAD:9500 0.01395 +rPAD/11487 PAD:19 PAD:9086 0.9 +rPAD/11488 PAD:19 PAD:14823 0.0487336 +rPAD/11489 PAD:18 PAD:62 0.000477612 +rPAD/11490 PAD:18 PAD:60 0.586956 +rPAD/11491 PAD:18 PAD:9645 0.586956 +rPAD/11492 PAD:18 PAD:56 0.586956 +rPAD/11493 PAD:18 PAD:54 0.586956 +rPAD/11494 PAD:18 PAD:9613 0.586956 +rPAD/11495 PAD:18 PAD:9603 0.586956 +rPAD/11496 PAD:18 PAD:48 0.586956 +rPAD/11497 PAD:18 PAD:46 0.586956 +rPAD/11498 PAD:18 PAD:44 0.586956 +rPAD/11499 PAD:18 PAD:42 0.586956 +rPAD/11500 PAD:18 PAD:40 0.586956 +rPAD/11501 PAD:18 PAD:38 0.586956 +rPAD/11502 PAD:18 PAD:36 0.586956 +rPAD/11503 PAD:18 PAD:34 0.586956 +rPAD/11504 PAD:18 PAD:32 0.586956 +rPAD/11505 PAD:18 PAD:30 0.586956 +rPAD/11506 PAD:18 PAD:9486 0.586956 +rPAD/11507 PAD:18 PAD:9476 0.586956 +rPAD/11508 PAD:18 PAD:9465 0.586956 +rPAD/11509 PAD:18 PAD:9454 0.586956 +rPAD/11510 PAD:18 PAD:19 0.9 +rPAD/11511 R7:pos PAD:9423 0.0184795 +rPAD/11512 R6:pos PAD:9410 0.0184795 +rPAD/11513 R5:pos PAD:9397 0.0184795 +rPAD/11514 R4:pos PAD:9387 0.0184795 +rPAD/11515 R3:pos PAD:9370 0.0184795 +rPAD/11516 R2:pos PAD:9358 0.0184795 +rPAD/11517 R1:pos PAD:9345 0.0184795 +rPAD/11518 R0:pos PAD:9332 0.0184795 +cASIG5V/0 ASIG5V vss 73.974f +cASIG5V/1 ASIG5V vss 76.9788f +cASIG5V/2 ASIG5V vss 71.7842f +cASIG5V/3 ASIG5V vss 73.8848f +cASIG5V/4 ASIG5V vss 73.914f +cASIG5V/5 ASIG5V vss 71.7842f +cASIG5V/6 ASIG5V vss 74.11f +cASIG5V/7 ASIG5V vss 73.974f +cASIG5V/8 ASIG5V:1383 vss 28.7583f +cASIG5V/9 ASIG5V:1369 vss 36.9812f +cASIG5V/10 ASIG5V:1367 vss 28.7641f +cASIG5V/11 ASIG5V:1353 vss 36.8883f +cASIG5V/12 ASIG5V:1351 vss 28.7583f +cASIG5V/13 ASIG5V:1337 vss 36.0371f +cASIG5V/14 ASIG5V:1335 vss 28.7295f +cASIG5V/15 ASIG5V:1321 vss 36.7911f +cASIG5V/16 ASIG5V:1319 vss 28.7295f +cASIG5V/17 ASIG5V:1305 vss 36.7911f +cASIG5V/18 ASIG5V:1303 vss 28.7583f +cASIG5V/19 ASIG5V:1289 vss 36.0371f +cASIG5V/20 ASIG5V:1287 vss 28.7596f +cASIG5V/21 ASIG5V:1273 vss 36.8821f +cASIG5V/22 ASIG5V:1271 vss 28.7583f +cASIG5V/23 ASIG5V:1257 vss 36.9812f +cASIG5V/24 X46/X33/D0:pos vss 2.87453f +cASIG5V/25 ASIG5V:768 vss 7.64287f +cASIG5V/26 ASIG5V:663 vss 7.77059f +cASIG5V/27 X46/X31/D0:pos vss 2.88048f +cASIG5V/28 ASIG5V:558 vss 7.75131f +cASIG5V/29 X46/X30/D0:pos vss 2.93548f +cASIG5V/30 ASIG5V:453 vss 7.58192f +cASIG5V/31 X46/X29/D0:neg vss 4.13411f +cASIG5V/32 ASIG5V:416 vss 6.51082f +cASIG5V/33 X46/X28/D0:neg vss 4.18183f +cASIG5V/34 ASIG5V:311 vss 6.54488f +cASIG5V/35 X46/X27/D0:neg vss 2.97197f +cASIG5V/36 ASIG5V:138 vss 7.73761f +cASIG5V/37 X46/X26/D0:neg vss 2.99591f +cASIG5V/38 ASIG5V:33 vss 7.52148f +lASIG5V/39 ASIG5V:3083 R7:neg 4.67374p +rASIG5V/40 ASIG5V:3083 ASIG5V:1383 0.361332 +rASIG5V/41 ASIG5V:1384 ASIG5V:1383 0.225 +lASIG5V/42 ASIG5V:3081 ASIG5V:1381 3.67204p +rASIG5V/43 ASIG5V:3081 ASIG5V:1383 0.283889 +rASIG5V/44 ASIG5V:1382 ASIG5V:1381 0.225 +lASIG5V/45 ASIG5V:3079 ASIG5V:1379 3.67204p +rASIG5V/46 ASIG5V:3079 ASIG5V:1381 0.283889 +rASIG5V/47 ASIG5V:1380 ASIG5V:1379 0.225 +lASIG5V/48 ASIG5V:3077 ASIG5V:1377 3.67204p +rASIG5V/49 ASIG5V:3077 ASIG5V:1379 0.283889 +rASIG5V/50 ASIG5V:1378 ASIG5V:1377 0.225 +lASIG5V/51 ASIG5V:3075 ASIG5V:1375 8.35625p +rASIG5V/52 ASIG5V:3075 ASIG5V:1377 0.64603 +rASIG5V/53 ASIG5V:1376 ASIG5V:1375 0.225 +lASIG5V/54 ASIG5V:3073 ASIG5V:1373 3.67204p +rASIG5V/55 ASIG5V:3073 ASIG5V:1375 0.283889 +rASIG5V/56 ASIG5V:1374 ASIG5V:1373 0.225 +lASIG5V/57 ASIG5V:3071 ASIG5V:1371 3.67204p +rASIG5V/58 ASIG5V:3071 ASIG5V:1373 0.283889 +rASIG5V/59 ASIG5V:1372 ASIG5V:1371 0.225 +lASIG5V/60 ASIG5V:3069 ASIG5V:1369 3.67204p +rASIG5V/61 ASIG5V:3069 ASIG5V:1371 0.283889 +lASIG5V/62 ASIG5V:3067 ASIG5V 96.4828p +rASIG5V/63 ASIG5V:3067 ASIG5V:1369 9.27884 +rASIG5V/64 ASIG5V:1370 ASIG5V:1369 0.225 +lASIG5V/65 ASIG5V:3065 R6:neg 4.81274p +rASIG5V/66 ASIG5V:3065 ASIG5V:1367 0.363399 +rASIG5V/67 ASIG5V:1368 ASIG5V:1367 0.225 +lASIG5V/68 ASIG5V:3063 ASIG5V:1365 3.78125p +rASIG5V/69 ASIG5V:3063 ASIG5V:1367 0.285513 +rASIG5V/70 ASIG5V:1366 ASIG5V:1365 0.225 +lASIG5V/71 ASIG5V:3061 ASIG5V:1363 3.78125p +rASIG5V/72 ASIG5V:3061 ASIG5V:1365 0.285513 +rASIG5V/73 ASIG5V:1364 ASIG5V:1363 0.225 +lASIG5V/74 ASIG5V:3059 ASIG5V:1361 3.78125p +rASIG5V/75 ASIG5V:3059 ASIG5V:1363 0.285513 +rASIG5V/76 ASIG5V:1362 ASIG5V:1361 0.225 +lASIG5V/77 ASIG5V:3057 ASIG5V:1359 8.60476p +rASIG5V/78 ASIG5V:3057 ASIG5V:1361 0.649726 +rASIG5V/79 ASIG5V:1360 ASIG5V:1359 0.225 +lASIG5V/80 ASIG5V:3055 ASIG5V:1357 3.78125p +rASIG5V/81 ASIG5V:3055 ASIG5V:1359 0.285513 +rASIG5V/82 ASIG5V:1358 ASIG5V:1357 0.225 +lASIG5V/83 ASIG5V:3053 ASIG5V:1355 3.78125p +rASIG5V/84 ASIG5V:3053 ASIG5V:1357 0.285513 +rASIG5V/85 ASIG5V:1356 ASIG5V:1355 0.225 +lASIG5V/86 ASIG5V:3051 ASIG5V:1353 3.78125p +rASIG5V/87 ASIG5V:3051 ASIG5V:1355 0.285513 +lASIG5V/88 ASIG5V:3049 ASIG5V 95.7151p +rASIG5V/89 ASIG5V:3049 ASIG5V:1353 9.41378 +rASIG5V/90 ASIG5V:1354 ASIG5V:1353 0.225 +lASIG5V/91 ASIG5V:3047 R5:neg 6.07088p +rASIG5V/92 ASIG5V:3047 ASIG5V:1351 0.369277 +rASIG5V/93 ASIG5V:1352 ASIG5V:1351 0.225 +lASIG5V/94 ASIG5V:3045 ASIG5V:1349 4.76974p +rASIG5V/95 ASIG5V:3045 ASIG5V:1351 0.290132 +rASIG5V/96 ASIG5V:1350 ASIG5V:1349 0.225 +lASIG5V/97 ASIG5V:3043 ASIG5V:1347 4.76974p +rASIG5V/98 ASIG5V:3043 ASIG5V:1349 0.290132 +rASIG5V/99 ASIG5V:1348 ASIG5V:1347 0.225 +lASIG5V/100 ASIG5V:3041 ASIG5V:1345 4.76974p +rASIG5V/101 ASIG5V:3041 ASIG5V:1347 0.290132 +rASIG5V/102 ASIG5V:1346 ASIG5V:1345 0.225 +lASIG5V/103 ASIG5V:3039 ASIG5V:1343 10.8542p +rASIG5V/104 ASIG5V:3039 ASIG5V:1345 0.660235 +rASIG5V/105 ASIG5V:1344 ASIG5V:1343 0.225 +lASIG5V/106 ASIG5V:3037 ASIG5V:1341 4.76974p +rASIG5V/107 ASIG5V:3037 ASIG5V:1343 0.290132 +rASIG5V/108 ASIG5V:1342 ASIG5V:1341 0.225 +lASIG5V/109 ASIG5V:3035 ASIG5V:1339 4.76974p +rASIG5V/110 ASIG5V:3035 ASIG5V:1341 0.290132 +rASIG5V/111 ASIG5V:1340 ASIG5V:1339 0.225 +lASIG5V/112 ASIG5V:3033 ASIG5V:1337 4.76974p +rASIG5V/113 ASIG5V:3033 ASIG5V:1339 0.290132 +lASIG5V/114 ASIG5V:3031 ASIG5V 111.72p +rASIG5V/115 ASIG5V:3031 ASIG5V:1337 9.12149 +rASIG5V/116 ASIG5V:1338 ASIG5V:1337 0.225 +lASIG5V/117 ASIG5V:3029 R4:neg 4.85504p +rASIG5V/118 ASIG5V:3029 ASIG5V:1335 0.384905 +rASIG5V/119 ASIG5V:1336 ASIG5V:1335 0.225 +lASIG5V/120 ASIG5V:3027 ASIG5V:1333 3.81448p +rASIG5V/121 ASIG5V:3027 ASIG5V:1335 0.30241 +rASIG5V/122 ASIG5V:1334 ASIG5V:1333 0.225 +lASIG5V/123 ASIG5V:3025 ASIG5V:1331 3.81448p +rASIG5V/124 ASIG5V:3025 ASIG5V:1333 0.30241 +rASIG5V/125 ASIG5V:1332 ASIG5V:1331 0.225 +lASIG5V/126 ASIG5V:3023 ASIG5V:1329 3.81448p +rASIG5V/127 ASIG5V:3023 ASIG5V:1331 0.30241 +rASIG5V/128 ASIG5V:1330 ASIG5V:1329 0.225 +lASIG5V/129 ASIG5V:3021 ASIG5V:1327 8.68038p +rASIG5V/130 ASIG5V:3021 ASIG5V:1329 0.688177 +rASIG5V/131 ASIG5V:1328 ASIG5V:1327 0.225 +lASIG5V/132 ASIG5V:3019 ASIG5V:1325 3.81448p +rASIG5V/133 ASIG5V:3019 ASIG5V:1327 0.30241 +rASIG5V/134 ASIG5V:1326 ASIG5V:1325 0.225 +lASIG5V/135 ASIG5V:3017 ASIG5V:1323 3.81448p +rASIG5V/136 ASIG5V:3017 ASIG5V:1325 0.30241 +rASIG5V/137 ASIG5V:1324 ASIG5V:1323 0.225 +lASIG5V/138 ASIG5V:3015 ASIG5V:1321 3.81448p +rASIG5V/139 ASIG5V:3015 ASIG5V:1323 0.30241 +lASIG5V/140 ASIG5V:3013 ASIG5V 111.621p +rASIG5V/141 ASIG5V:3013 ASIG5V:1321 8.9712 +rASIG5V/142 ASIG5V:1322 ASIG5V:1321 0.225 +lASIG5V/143 ASIG5V:3011 R3:neg 4.9324p +rASIG5V/144 ASIG5V:3011 ASIG5V:1319 0.38585 +rASIG5V/145 ASIG5V:1320 ASIG5V:1319 0.225 +lASIG5V/146 ASIG5V:3009 ASIG5V:1317 3.87526p +rASIG5V/147 ASIG5V:3009 ASIG5V:1319 0.303152 +rASIG5V/148 ASIG5V:1318 ASIG5V:1317 0.225 +lASIG5V/149 ASIG5V:3007 ASIG5V:1315 3.87526p +rASIG5V/150 ASIG5V:3007 ASIG5V:1317 0.303152 +rASIG5V/151 ASIG5V:1316 ASIG5V:1315 0.225 +lASIG5V/152 ASIG5V:3005 ASIG5V:1313 3.87526p +rASIG5V/153 ASIG5V:3005 ASIG5V:1315 0.303152 +rASIG5V/154 ASIG5V:1314 ASIG5V:1313 0.225 +lASIG5V/155 ASIG5V:3003 ASIG5V:1311 8.8187p +rASIG5V/156 ASIG5V:3003 ASIG5V:1313 0.689866 +rASIG5V/157 ASIG5V:1312 ASIG5V:1311 0.225 +lASIG5V/158 ASIG5V:3001 ASIG5V:1309 3.87526p +rASIG5V/159 ASIG5V:3001 ASIG5V:1311 0.303152 +rASIG5V/160 ASIG5V:1310 ASIG5V:1309 0.225 +lASIG5V/161 ASIG5V:2999 ASIG5V:1307 3.87526p +rASIG5V/162 ASIG5V:2999 ASIG5V:1309 0.303152 +rASIG5V/163 ASIG5V:1308 ASIG5V:1307 0.225 +lASIG5V/164 ASIG5V:2997 ASIG5V:1305 3.87526p +rASIG5V/165 ASIG5V:2997 ASIG5V:1307 0.303152 +lASIG5V/166 ASIG5V:2995 ASIG5V 118.329p +rASIG5V/167 ASIG5V:2995 ASIG5V:1305 8.96285 +rASIG5V/168 ASIG5V:1306 ASIG5V:1305 0.225 +lASIG5V/169 ASIG5V:2993 R2:neg 4.86713p +rASIG5V/170 ASIG5V:2993 ASIG5V:1303 0.364573 +rASIG5V/171 ASIG5V:1304 ASIG5V:1303 0.225 +lASIG5V/172 ASIG5V:2991 ASIG5V:1301 3.82398p +rASIG5V/173 ASIG5V:2991 ASIG5V:1303 0.286436 +rASIG5V/174 ASIG5V:1302 ASIG5V:1301 0.225 +lASIG5V/175 ASIG5V:2989 ASIG5V:1299 3.82398p +rASIG5V/176 ASIG5V:2989 ASIG5V:1301 0.286436 +rASIG5V/177 ASIG5V:1300 ASIG5V:1299 0.225 +lASIG5V/178 ASIG5V:2987 ASIG5V:1297 3.82398p +rASIG5V/179 ASIG5V:2987 ASIG5V:1299 0.286436 +rASIG5V/180 ASIG5V:1298 ASIG5V:1297 0.225 +lASIG5V/181 ASIG5V:2985 ASIG5V:1295 8.70201p +rASIG5V/182 ASIG5V:2985 ASIG5V:1297 0.651825 +rASIG5V/183 ASIG5V:1296 ASIG5V:1295 0.225 +lASIG5V/184 ASIG5V:2983 ASIG5V:1293 3.82398p +rASIG5V/185 ASIG5V:2983 ASIG5V:1295 0.286436 +rASIG5V/186 ASIG5V:1294 ASIG5V:1293 0.225 +lASIG5V/187 ASIG5V:2981 ASIG5V:1291 3.82398p +rASIG5V/188 ASIG5V:2981 ASIG5V:1293 0.286436 +rASIG5V/189 ASIG5V:1292 ASIG5V:1291 0.225 +lASIG5V/190 ASIG5V:2979 ASIG5V:1289 3.82398p +rASIG5V/191 ASIG5V:2979 ASIG5V:1291 0.286436 +lASIG5V/192 ASIG5V:2977 ASIG5V 118.347p +rASIG5V/193 ASIG5V:2977 ASIG5V:1289 9.11067 +rASIG5V/194 ASIG5V:1290 ASIG5V:1289 0.225 +lASIG5V/195 ASIG5V:2975 R1:neg 4.5083p +rASIG5V/196 ASIG5V:2975 ASIG5V:1287 0.362756 +rASIG5V/197 ASIG5V:1288 ASIG5V:1287 0.225 +lASIG5V/198 ASIG5V:2973 ASIG5V:1285 3.54206p +rASIG5V/199 ASIG5V:2973 ASIG5V:1287 0.285008 +rASIG5V/200 ASIG5V:1286 ASIG5V:1285 0.225 +lASIG5V/201 ASIG5V:2971 ASIG5V:1283 3.54206p +rASIG5V/202 ASIG5V:2971 ASIG5V:1285 0.285008 +rASIG5V/203 ASIG5V:1284 ASIG5V:1283 0.225 +lASIG5V/204 ASIG5V:2969 ASIG5V:1281 3.54206p +rASIG5V/205 ASIG5V:2969 ASIG5V:1283 0.285008 +rASIG5V/206 ASIG5V:1282 ASIG5V:1281 0.225 +lASIG5V/207 ASIG5V:2967 ASIG5V:1279 8.06045p +rASIG5V/208 ASIG5V:2967 ASIG5V:1281 0.648575 +rASIG5V/209 ASIG5V:1280 ASIG5V:1279 0.225 +lASIG5V/210 ASIG5V:2965 ASIG5V:1277 3.54206p +rASIG5V/211 ASIG5V:2965 ASIG5V:1279 0.285008 +rASIG5V/212 ASIG5V:1278 ASIG5V:1277 0.225 +lASIG5V/213 ASIG5V:2963 ASIG5V:1275 3.54206p +rASIG5V/214 ASIG5V:2963 ASIG5V:1277 0.285008 +rASIG5V/215 ASIG5V:1276 ASIG5V:1275 0.225 +lASIG5V/216 ASIG5V:2961 ASIG5V:1273 3.54206p +rASIG5V/217 ASIG5V:2961 ASIG5V:1275 0.285008 +lASIG5V/218 ASIG5V:2959 ASIG5V 102.413p +rASIG5V/219 ASIG5V:2959 ASIG5V:1273 9.39452 +rASIG5V/220 ASIG5V:1274 ASIG5V:1273 0.225 +lASIG5V/221 ASIG5V:2957 R0:neg 4.38046p +rASIG5V/222 ASIG5V:2957 ASIG5V:1271 0.361051 +rASIG5V/223 ASIG5V:1272 ASIG5V:1271 0.225 +lASIG5V/224 ASIG5V:2955 ASIG5V:1269 3.44162p +rASIG5V/225 ASIG5V:2955 ASIG5V:1271 0.283668 +rASIG5V/226 ASIG5V:1270 ASIG5V:1269 0.225 +lASIG5V/227 ASIG5V:2953 ASIG5V:1267 3.44162p +rASIG5V/228 ASIG5V:2953 ASIG5V:1269 0.283668 +rASIG5V/229 ASIG5V:1268 ASIG5V:1267 0.225 +lASIG5V/230 ASIG5V:2951 ASIG5V:1265 3.44162p +rASIG5V/231 ASIG5V:2951 ASIG5V:1267 0.283668 +rASIG5V/232 ASIG5V:1266 ASIG5V:1265 0.225 +lASIG5V/233 ASIG5V:2949 ASIG5V:1263 7.83188p +rASIG5V/234 ASIG5V:2949 ASIG5V:1265 0.645527 +rASIG5V/235 ASIG5V:1264 ASIG5V:1263 0.225 +lASIG5V/236 ASIG5V:2947 ASIG5V:1261 3.44162p +rASIG5V/237 ASIG5V:2947 ASIG5V:1263 0.283668 +rASIG5V/238 ASIG5V:1262 ASIG5V:1261 0.225 +lASIG5V/239 ASIG5V:2945 ASIG5V:1259 3.44162p +rASIG5V/240 ASIG5V:2945 ASIG5V:1261 0.283668 +rASIG5V/241 ASIG5V:1260 ASIG5V:1259 0.225 +lASIG5V/242 ASIG5V:2943 ASIG5V:1257 3.44162p +rASIG5V/243 ASIG5V:2943 ASIG5V:1259 0.283668 +lASIG5V/244 ASIG5V:2941 ASIG5V 99.8948p +rASIG5V/245 ASIG5V:2941 ASIG5V:1257 9.21806 +rASIG5V/246 ASIG5V:1258 ASIG5V:1257 0.225 +rASIG5V/247 X46/X33/D0:pos ASIG5V:1378 0.445714 +lASIG5V/248 ASIG5V:2939 ASIG5V:836 749.766f +rASIG5V/249 ASIG5V:2939 ASIG5V:1378 0.0463984 +rASIG5V/250 X46/X33/D0:pos ASIG5V:836 0.445714 +rASIG5V/251 X46/X33/D0:pos ASIG5V:834 0.445714 +lASIG5V/252 ASIG5V:2937 ASIG5V:832 514.303f +rASIG5V/253 ASIG5V:2937 ASIG5V:1362 0.031827 +rASIG5V/254 X46/X33/D0:pos ASIG5V:832 0.445714 +rASIG5V/255 X46/X33/D0:pos ASIG5V:830 0.445714 +lASIG5V/256 ASIG5V:2935 ASIG5V:828 285.035f +rASIG5V/257 ASIG5V:2935 ASIG5V:1346 0.0176391 +rASIG5V/258 X46/X33/D0:pos ASIG5V:828 0.445714 +rASIG5V/259 X46/X33/D0:pos ASIG5V:826 0.445714 +lASIG5V/260 ASIG5V:2933 ASIG5V:824 396.571f +rASIG5V/261 ASIG5V:2933 ASIG5V:1330 0.0245413 +rASIG5V/262 X46/X33/D0:pos ASIG5V:824 0.445714 +rASIG5V/263 X46/X33/D0:pos ASIG5V:822 0.445714 +rASIG5V/264 ASIG5V:820 X46/X33/D0:pos 0.445714 +lASIG5V/265 ASIG5V:2931 ASIG5V:1314 408.963f +rASIG5V/266 ASIG5V:2931 ASIG5V:818 0.0253082 +rASIG5V/267 ASIG5V:818 X46/X33/D0:pos 0.445714 +rASIG5V/268 ASIG5V:816 X46/X33/D0:pos 0.445714 +lASIG5V/269 ASIG5V:2929 ASIG5V:1298 297.428f +rASIG5V/270 ASIG5V:2929 ASIG5V:814 0.018406 +rASIG5V/271 ASIG5V:814 X46/X33/D0:pos 0.445714 +rASIG5V/272 ASIG5V:812 X46/X33/D0:pos 0.445714 +lASIG5V/273 ASIG5V:2927 ASIG5V:1282 495.713f +rASIG5V/274 ASIG5V:2927 ASIG5V:810 0.0306767 +rASIG5V/275 ASIG5V:810 X46/X33/D0:pos 0.445714 +rASIG5V/276 ASIG5V:808 X46/X33/D0:pos 0.445714 +rASIG5V/277 ASIG5V:806 X46/X33/D0:pos 0.445714 +lASIG5V/278 ASIG5V:2925 ASIG5V:834 625.838f +rASIG5V/279 ASIG5V:2925 ASIG5V:800 0.0387293 +rASIG5V/280 X46/X33/D0:pos ASIG5V:800 0.445714 +lASIG5V/281 ASIG5V:2923 ASIG5V:1362 111.535f +rASIG5V/282 ASIG5V:2923 ASIG5V:798 0.00690225 +rASIG5V/283 X46/X33/D0:pos ASIG5V:798 0.445714 +lASIG5V/284 ASIG5V:2921 ASIG5V:830 625.838f +rASIG5V/285 ASIG5V:2921 ASIG5V:796 0.0387293 +rASIG5V/286 X46/X33/D0:pos ASIG5V:796 0.445714 +lASIG5V/287 ASIG5V:2919 ASIG5V:1346 24.7857f +rASIG5V/288 ASIG5V:2919 ASIG5V:794 0.00153383 +rASIG5V/289 X46/X33/D0:pos ASIG5V:794 0.445714 +lASIG5V/290 ASIG5V:2917 ASIG5V:826 619.642f +rASIG5V/291 ASIG5V:2917 ASIG5V:792 0.0383458 +rASIG5V/292 X46/X33/D0:pos ASIG5V:792 0.445714 +lASIG5V/293 ASIG5V:2915 ASIG5V:1330 223.071f +rASIG5V/294 ASIG5V:2915 ASIG5V:790 0.0138045 +rASIG5V/295 X46/X33/D0:pos ASIG5V:790 0.445714 +lASIG5V/296 ASIG5V:2913 ASIG5V:822 619.642f +rASIG5V/297 ASIG5V:2913 ASIG5V:788 0.0383458 +rASIG5V/298 X46/X33/D0:pos ASIG5V:788 0.445714 +lASIG5V/299 ASIG5V:2911 ASIG5V:820 619.642f +rASIG5V/300 ASIG5V:2911 ASIG5V:786 0.0383458 +rASIG5V/301 ASIG5V:786 X46/X33/D0:pos 0.445714 +lASIG5V/302 ASIG5V:2909 ASIG5V:818 619.642f +rASIG5V/303 ASIG5V:2909 ASIG5V:784 0.0383458 +rASIG5V/304 ASIG5V:784 X46/X33/D0:pos 0.445714 +lASIG5V/305 ASIG5V:2907 ASIG5V:816 309.821f +rASIG5V/306 ASIG5V:2907 ASIG5V:782 0.0191729 +rASIG5V/307 ASIG5V:782 X46/X33/D0:pos 0.445714 +lASIG5V/308 ASIG5V:2905 ASIG5V:814 619.642f +rASIG5V/309 ASIG5V:2905 ASIG5V:780 0.0383458 +rASIG5V/310 ASIG5V:780 X46/X33/D0:pos 0.445714 +lASIG5V/311 ASIG5V:2903 ASIG5V:812 619.642f +rASIG5V/312 ASIG5V:2903 ASIG5V:778 0.0383458 +rASIG5V/313 ASIG5V:778 X46/X33/D0:pos 0.445714 +lASIG5V/314 ASIG5V:2901 ASIG5V:810 619.642f +rASIG5V/315 ASIG5V:2901 ASIG5V:776 0.0383458 +rASIG5V/316 ASIG5V:776 X46/X33/D0:pos 0.445714 +lASIG5V/317 ASIG5V:2899 ASIG5V:774 545.285f +rASIG5V/318 ASIG5V:2899 ASIG5V:1266 0.0337443 +lASIG5V/319 ASIG5V:2897 ASIG5V:808 619.642f +rASIG5V/320 ASIG5V:2897 ASIG5V:774 0.0383458 +rASIG5V/321 ASIG5V:774 X46/X33/D0:pos 0.445714 +lASIG5V/322 ASIG5V:2895 ASIG5V:806 619.642f +rASIG5V/323 ASIG5V:2895 ASIG5V:772 0.0383458 +rASIG5V/324 ASIG5V:772 X46/X33/D0:pos 0.445714 +lASIG5V/325 ASIG5V:2893 X46/X33/D0:pos 619.642f +rASIG5V/326 ASIG5V:2893 ASIG5V:772 0.352049 +lASIG5V/327 ASIG5V:2891 ASIG5V:768 625.838f +rASIG5V/328 ASIG5V:2891 ASIG5V:836 0.0387293 +lASIG5V/329 ASIG5V:2889 ASIG5V:768 625.838f +rASIG5V/330 ASIG5V:2889 X46/X33/D0:pos 0.270865 +rASIG5V/331 X46/X33/D0:pos ASIG5V:768 0.445714 +lASIG5V/332 ASIG5V:2887 ASIG5V:766 625.838f +rASIG5V/333 ASIG5V:2887 ASIG5V:834 0.0387293 +lASIG5V/334 ASIG5V:2885 ASIG5V:1378 501.91f +rASIG5V/335 ASIG5V:2885 ASIG5V:766 0.0310601 +rASIG5V/336 X46/X33/D0:pos ASIG5V:766 0.445714 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0.0135191 +lASIG5V/854 ASIG5V:2517 ASIG5V:471 632.611f +rASIG5V/855 ASIG5V:2517 ASIG5V:435 0.039762 +rASIG5V/856 ASIG5V:435 X46/X30/D0:pos 0.445714 +lASIG5V/857 ASIG5V:2515 ASIG5V:433 632.611f +rASIG5V/858 ASIG5V:2515 ASIG5V:501 0.039762 +lASIG5V/859 ASIG5V:2513 ASIG5V:469 632.611f +rASIG5V/860 ASIG5V:2513 ASIG5V:433 0.039762 +rASIG5V/861 ASIG5V:433 X46/X30/D0:pos 0.445714 +lASIG5V/862 ASIG5V:2511 ASIG5V:431 12.6522f +rASIG5V/863 ASIG5V:2511 ASIG5V:1304 0.000795239 +lASIG5V/864 ASIG5V:2509 ASIG5V:467 948.916f +rASIG5V/865 ASIG5V:2509 ASIG5V:431 0.0596429 +rASIG5V/866 ASIG5V:431 X46/X30/D0:pos 0.445714 +lASIG5V/867 ASIG5V:2507 ASIG5V:429 632.611f +rASIG5V/868 ASIG5V:2507 ASIG5V:497 0.039762 +lASIG5V/869 ASIG5V:2505 ASIG5V:465 632.611f +rASIG5V/870 ASIG5V:2505 ASIG5V:429 0.039762 +rASIG5V/871 ASIG5V:429 X46/X30/D0:pos 0.445714 +lASIG5V/872 ASIG5V:2503 ASIG5V:427 126.522f +rASIG5V/873 ASIG5V:2503 ASIG5V:1288 0.00795239 +lASIG5V/874 ASIG5V:2501 ASIG5V:463 632.611f +rASIG5V/875 ASIG5V:2501 ASIG5V:427 0.039762 +rASIG5V/876 ASIG5V:427 X46/X30/D0:pos 0.445714 +lASIG5V/877 ASIG5V:2499 ASIG5V:425 632.611f +rASIG5V/878 ASIG5V:2499 ASIG5V:493 0.039762 +lASIG5V/879 ASIG5V:2497 ASIG5V:461 632.611f +rASIG5V/880 ASIG5V:2497 ASIG5V:425 0.039762 +rASIG5V/881 ASIG5V:425 X46/X30/D0:pos 0.445714 +lASIG5V/882 ASIG5V:2495 ASIG5V:423 632.611f +rASIG5V/883 ASIG5V:2495 ASIG5V:491 0.039762 +lASIG5V/884 ASIG5V:2493 ASIG5V:1272 75.9133f +rASIG5V/885 ASIG5V:2493 ASIG5V:423 0.00477144 +rASIG5V/886 ASIG5V:423 X46/X30/D0:pos 0.445714 +rASIG5V/887 X46/X29/D0:neg ASIG5V:1370 0.445714 +lASIG5V/888 ASIG5V:2491 ASIG5V:416 508.117f +rASIG5V/889 ASIG5V:2491 ASIG5V:1370 0.04239 +rASIG5V/890 X46/X29/D0:neg ASIG5V:416 0.445714 +lASIG5V/891 ASIG5V:2489 ASIG5V:416 424.131f +rASIG5V/892 ASIG5V:2489 X46/X29/D0:neg 0.20226 +rASIG5V/893 X46/X29/D0:neg ASIG5V:414 0.445714 +lASIG5V/894 ASIG5V:2487 ASIG5V:412 348.543f +rASIG5V/895 ASIG5V:2487 ASIG5V:1354 0.0290774 +rASIG5V/896 X46/X29/D0:neg ASIG5V:412 0.445714 +rASIG5V/897 X46/X29/D0:neg ASIG5V:410 0.445714 +lASIG5V/898 ASIG5V:2485 ASIG5V:408 193.169f +rASIG5V/899 ASIG5V:2485 ASIG5V:1338 0.0161152 +rASIG5V/900 X46/X29/D0:neg ASIG5V:408 0.445714 +rASIG5V/901 X46/X29/D0:neg ASIG5V:406 0.445714 +lASIG5V/902 ASIG5V:2483 ASIG5V:404 268.756f +rASIG5V/903 ASIG5V:2483 ASIG5V:1322 0.0224212 +rASIG5V/904 X46/X29/D0:neg ASIG5V:404 0.445714 +rASIG5V/905 X46/X29/D0:neg ASIG5V:402 0.445714 +rASIG5V/906 ASIG5V:400 X46/X29/D0:neg 0.445714 +lASIG5V/907 ASIG5V:2481 ASIG5V:1306 277.155f +rASIG5V/908 ASIG5V:2481 ASIG5V:398 0.0231218 +rASIG5V/909 ASIG5V:398 X46/X29/D0:neg 0.445714 +rASIG5V/910 ASIG5V:396 X46/X29/D0:neg 0.445714 +lASIG5V/911 ASIG5V:2479 ASIG5V:1290 201.567f +rASIG5V/912 ASIG5V:2479 ASIG5V:394 0.0168159 +rASIG5V/913 ASIG5V:394 X46/X29/D0:neg 0.445714 +rASIG5V/914 ASIG5V:392 X46/X29/D0:neg 0.445714 +lASIG5V/915 ASIG5V:2477 ASIG5V:1274 335.945f +rASIG5V/916 ASIG5V:2477 ASIG5V:390 0.0280264 +rASIG5V/917 ASIG5V:390 X46/X29/D0:neg 0.445714 +rASIG5V/918 ASIG5V:388 X46/X29/D0:neg 0.445714 +rASIG5V/919 ASIG5V:386 X46/X29/D0:neg 0.445714 +lASIG5V/920 ASIG5V:2475 X46/X29/D0:neg 419.932f +rASIG5V/921 ASIG5V:2475 ASIG5V:386 0.23064 +lASIG5V/922 ASIG5V:2473 ASIG5V:414 424.131f +rASIG5V/923 ASIG5V:2473 ASIG5V:380 0.0353834 +rASIG5V/924 X46/X29/D0:neg ASIG5V:380 0.445714 +lASIG5V/925 ASIG5V:2471 ASIG5V:1354 75.5877f +rASIG5V/926 ASIG5V:2471 ASIG5V:378 0.00630595 +rASIG5V/927 X46/X29/D0:neg ASIG5V:378 0.445714 +lASIG5V/928 ASIG5V:2469 ASIG5V:410 424.131f +rASIG5V/929 ASIG5V:2469 ASIG5V:376 0.0353834 +rASIG5V/930 X46/X29/D0:neg ASIG5V:376 0.445714 +lASIG5V/931 ASIG5V:2467 ASIG5V:1338 16.7973f +rASIG5V/932 ASIG5V:2467 ASIG5V:374 0.00140132 +rASIG5V/933 X46/X29/D0:neg ASIG5V:374 0.445714 +lASIG5V/934 ASIG5V:2465 ASIG5V:406 419.932f +rASIG5V/935 ASIG5V:2465 ASIG5V:372 0.0350331 +rASIG5V/936 X46/X29/D0:neg ASIG5V:372 0.445714 +lASIG5V/937 ASIG5V:2463 ASIG5V:1322 151.175f +rASIG5V/938 ASIG5V:2463 ASIG5V:370 0.0126119 +rASIG5V/939 X46/X29/D0:neg ASIG5V:370 0.445714 +lASIG5V/940 ASIG5V:2461 ASIG5V:402 419.932f +rASIG5V/941 ASIG5V:2461 ASIG5V:368 0.0350331 +rASIG5V/942 X46/X29/D0:neg ASIG5V:368 0.445714 +lASIG5V/943 ASIG5V:2459 ASIG5V:400 419.932f +rASIG5V/944 ASIG5V:2459 ASIG5V:366 0.0350331 +rASIG5V/945 ASIG5V:366 X46/X29/D0:neg 0.445714 +lASIG5V/946 ASIG5V:2457 ASIG5V:398 419.932f +rASIG5V/947 ASIG5V:2457 ASIG5V:364 0.0350331 +rASIG5V/948 ASIG5V:364 X46/X29/D0:neg 0.445714 +lASIG5V/949 ASIG5V:2455 ASIG5V:396 209.966f +rASIG5V/950 ASIG5V:2455 ASIG5V:362 0.0175165 +rASIG5V/951 ASIG5V:362 X46/X29/D0:neg 0.445714 +lASIG5V/952 ASIG5V:2453 ASIG5V:394 419.932f +rASIG5V/953 ASIG5V:2453 ASIG5V:360 0.0350331 +rASIG5V/954 ASIG5V:360 X46/X29/D0:neg 0.445714 +lASIG5V/955 ASIG5V:2451 ASIG5V:392 419.932f +rASIG5V/956 ASIG5V:2451 ASIG5V:358 0.0350331 +rASIG5V/957 ASIG5V:358 X46/X29/D0:neg 0.445714 +lASIG5V/958 ASIG5V:2449 ASIG5V:390 419.932f +rASIG5V/959 ASIG5V:2449 ASIG5V:356 0.0350331 +rASIG5V/960 ASIG5V:356 X46/X29/D0:neg 0.445714 +lASIG5V/961 ASIG5V:2447 ASIG5V:354 369.54f +rASIG5V/962 ASIG5V:2447 ASIG5V:1258 0.0308291 +lASIG5V/963 ASIG5V:2445 ASIG5V:388 419.932f +rASIG5V/964 ASIG5V:2445 ASIG5V:354 0.0350331 +rASIG5V/965 ASIG5V:354 X46/X29/D0:neg 0.445714 +lASIG5V/966 ASIG5V:2443 ASIG5V:346 424.131f +rASIG5V/967 ASIG5V:2443 ASIG5V:414 0.0353834 +lASIG5V/968 ASIG5V:2441 ASIG5V:1370 340.145f +rASIG5V/969 ASIG5V:2441 ASIG5V:346 0.0283768 +rASIG5V/970 X46/X29/D0:neg ASIG5V:346 0.445714 +lASIG5V/971 ASIG5V:2439 ASIG5V:344 424.131f +rASIG5V/972 ASIG5V:2439 ASIG5V:412 0.0353834 +lASIG5V/973 ASIG5V:2437 ASIG5V:380 424.131f +rASIG5V/974 ASIG5V:2437 ASIG5V:344 0.0353834 +rASIG5V/975 X46/X29/D0:neg ASIG5V:344 0.445714 +lASIG5V/976 ASIG5V:2435 ASIG5V:342 424.131f +rASIG5V/977 ASIG5V:2435 ASIG5V:410 0.0353834 +lASIG5V/978 ASIG5V:2433 ASIG5V:378 424.131f +rASIG5V/979 ASIG5V:2433 ASIG5V:342 0.0353834 +rASIG5V/980 X46/X29/D0:neg ASIG5V:342 0.445714 +lASIG5V/981 ASIG5V:2431 ASIG5V:340 419.932f +rASIG5V/982 ASIG5V:2431 ASIG5V:408 0.0350331 +lASIG5V/983 ASIG5V:2429 ASIG5V:376 424.131f +rASIG5V/984 ASIG5V:2429 ASIG5V:340 0.0353834 +rASIG5V/985 X46/X29/D0:neg ASIG5V:340 0.445714 +lASIG5V/986 ASIG5V:2427 ASIG5V:338 209.966f +rASIG5V/987 ASIG5V:2427 ASIG5V:406 0.0175165 +lASIG5V/988 ASIG5V:2425 ASIG5V:374 629.898f +rASIG5V/989 ASIG5V:2425 ASIG5V:338 0.0525496 +rASIG5V/990 X46/X29/D0:neg ASIG5V:338 0.445714 +lASIG5V/991 ASIG5V:2423 ASIG5V:336 419.932f +rASIG5V/992 ASIG5V:2423 ASIG5V:404 0.0350331 +lASIG5V/993 ASIG5V:2421 ASIG5V:372 419.932f +rASIG5V/994 ASIG5V:2421 ASIG5V:336 0.0350331 +rASIG5V/995 X46/X29/D0:neg ASIG5V:336 0.445714 +lASIG5V/996 ASIG5V:2419 ASIG5V:334 419.932f +rASIG5V/997 ASIG5V:2419 ASIG5V:402 0.0350331 +lASIG5V/998 ASIG5V:2417 ASIG5V:370 419.932f +rASIG5V/999 ASIG5V:2417 ASIG5V:334 0.0350331 +rASIG5V/1000 X46/X29/D0:neg ASIG5V:334 0.445714 +lASIG5V/1001 ASIG5V:2415 ASIG5V:332 419.932f +rASIG5V/1002 ASIG5V:2415 ASIG5V:400 0.0350331 +lASIG5V/1003 ASIG5V:2413 ASIG5V:368 419.932f +rASIG5V/1004 ASIG5V:2413 ASIG5V:332 0.0350331 +rASIG5V/1005 ASIG5V:332 X46/X29/D0:neg 0.445714 +lASIG5V/1006 ASIG5V:2411 ASIG5V:330 142.777f +rASIG5V/1007 ASIG5V:2411 ASIG5V:1306 0.0119112 +lASIG5V/1008 ASIG5V:2409 ASIG5V:366 419.932f +rASIG5V/1009 ASIG5V:2409 ASIG5V:330 0.0350331 +rASIG5V/1010 ASIG5V:330 X46/X29/D0:neg 0.445714 +lASIG5V/1011 ASIG5V:2407 ASIG5V:328 419.932f +rASIG5V/1012 ASIG5V:2407 ASIG5V:396 0.0350331 +lASIG5V/1013 ASIG5V:2405 ASIG5V:364 419.932f +rASIG5V/1014 ASIG5V:2405 ASIG5V:328 0.0350331 +rASIG5V/1015 ASIG5V:328 X46/X29/D0:neg 0.445714 +lASIG5V/1016 ASIG5V:2403 ASIG5V:326 8.39864f +rASIG5V/1017 ASIG5V:2403 ASIG5V:1290 0.000700661 +lASIG5V/1018 ASIG5V:2401 ASIG5V:362 629.898f +rASIG5V/1019 ASIG5V:2401 ASIG5V:326 0.0525496 +rASIG5V/1020 ASIG5V:326 X46/X29/D0:neg 0.445714 +lASIG5V/1021 ASIG5V:2399 ASIG5V:324 419.932f +rASIG5V/1022 ASIG5V:2399 ASIG5V:392 0.0350331 +lASIG5V/1023 ASIG5V:2397 ASIG5V:360 419.932f +rASIG5V/1024 ASIG5V:2397 ASIG5V:324 0.0350331 +rASIG5V/1025 ASIG5V:324 X46/X29/D0:neg 0.445714 +lASIG5V/1026 ASIG5V:2395 ASIG5V:322 83.9864f +rASIG5V/1027 ASIG5V:2395 ASIG5V:1274 0.00700661 +lASIG5V/1028 ASIG5V:2393 ASIG5V:358 419.932f +rASIG5V/1029 ASIG5V:2393 ASIG5V:322 0.0350331 +rASIG5V/1030 ASIG5V:322 X46/X29/D0:neg 0.445714 +lASIG5V/1031 ASIG5V:2391 ASIG5V:320 419.932f +rASIG5V/1032 ASIG5V:2391 ASIG5V:388 0.0350331 +lASIG5V/1033 ASIG5V:2389 ASIG5V:356 419.932f +rASIG5V/1034 ASIG5V:2389 ASIG5V:320 0.0350331 +rASIG5V/1035 ASIG5V:320 X46/X29/D0:neg 0.445714 +lASIG5V/1036 ASIG5V:2387 ASIG5V:318 419.932f +rASIG5V/1037 ASIG5V:2387 ASIG5V:386 0.0350331 +lASIG5V/1038 ASIG5V:2385 ASIG5V:1258 50.3918f +rASIG5V/1039 ASIG5V:2385 ASIG5V:318 0.00420397 +rASIG5V/1040 ASIG5V:318 X46/X29/D0:neg 0.445714 +rASIG5V/1041 X46/X28/D0:neg ASIG5V:1372 0.445714 +lASIG5V/1042 ASIG5V:2383 ASIG5V:311 487.532f +rASIG5V/1043 ASIG5V:2383 ASIG5V:1372 0.0422446 +rASIG5V/1044 X46/X28/D0:neg ASIG5V:311 0.445714 +lASIG5V/1045 ASIG5V:2381 ASIG5V:311 406.948f +rASIG5V/1046 ASIG5V:2381 X46/X28/D0:neg 0.20208 +rASIG5V/1047 X46/X28/D0:neg ASIG5V:309 0.445714 +lASIG5V/1048 ASIG5V:2379 ASIG5V:307 334.423f +rASIG5V/1049 ASIG5V:2379 ASIG5V:1356 0.0289777 +rASIG5V/1050 X46/X28/D0:neg ASIG5V:307 0.445714 +rASIG5V/1051 X46/X28/D0:neg ASIG5V:305 0.445714 +lASIG5V/1052 ASIG5V:2377 ASIG5V:303 185.343f +rASIG5V/1053 ASIG5V:2377 ASIG5V:1340 0.0160599 +rASIG5V/1054 X46/X28/D0:neg ASIG5V:303 0.445714 +rASIG5V/1055 X46/X28/D0:neg ASIG5V:301 0.445714 +lASIG5V/1056 ASIG5V:2375 ASIG5V:299 257.868f +rASIG5V/1057 ASIG5V:2375 ASIG5V:1324 0.0223443 +rASIG5V/1058 X46/X28/D0:neg ASIG5V:299 0.445714 +rASIG5V/1059 X46/X28/D0:neg ASIG5V:297 0.445714 +rASIG5V/1060 ASIG5V:295 X46/X28/D0:neg 0.445714 +lASIG5V/1061 ASIG5V:2373 ASIG5V:1308 265.926f +rASIG5V/1062 ASIG5V:2373 ASIG5V:293 0.0230425 +rASIG5V/1063 ASIG5V:293 X46/X28/D0:neg 0.445714 +rASIG5V/1064 ASIG5V:291 X46/X28/D0:neg 0.445714 +lASIG5V/1065 ASIG5V:2371 ASIG5V:1292 193.401f +rASIG5V/1066 ASIG5V:2371 ASIG5V:289 0.0167582 +rASIG5V/1067 ASIG5V:289 X46/X28/D0:neg 0.445714 +rASIG5V/1068 ASIG5V:287 X46/X28/D0:neg 0.445714 +lASIG5V/1069 ASIG5V:2369 ASIG5V:1276 322.335f +rASIG5V/1070 ASIG5V:2369 ASIG5V:285 0.0279303 +rASIG5V/1071 ASIG5V:285 X46/X28/D0:neg 0.445714 +rASIG5V/1072 ASIG5V:283 X46/X28/D0:neg 0.445714 +rASIG5V/1073 ASIG5V:281 X46/X28/D0:neg 0.445714 +lASIG5V/1074 ASIG5V:2367 X46/X28/D0:neg 402.919f +rASIG5V/1075 ASIG5V:2367 ASIG5V:281 0.230481 +lASIG5V/1076 ASIG5V:2365 ASIG5V:309 406.948f +rASIG5V/1077 ASIG5V:2365 ASIG5V:275 0.035262 +rASIG5V/1078 X46/X28/D0:neg ASIG5V:275 0.445714 +lASIG5V/1079 ASIG5V:2363 ASIG5V:1356 72.5254f +rASIG5V/1080 ASIG5V:2363 ASIG5V:273 0.00628432 +rASIG5V/1081 X46/X28/D0:neg ASIG5V:273 0.445714 +lASIG5V/1082 ASIG5V:2361 ASIG5V:305 406.948f +rASIG5V/1083 ASIG5V:2361 ASIG5V:271 0.035262 +rASIG5V/1084 X46/X28/D0:neg ASIG5V:271 0.445714 +lASIG5V/1085 ASIG5V:2359 ASIG5V:1340 16.1167f +rASIG5V/1086 ASIG5V:2359 ASIG5V:269 0.00139652 +rASIG5V/1087 X46/X28/D0:neg ASIG5V:269 0.445714 +lASIG5V/1088 ASIG5V:2357 ASIG5V:301 402.919f +rASIG5V/1089 ASIG5V:2357 ASIG5V:267 0.0349129 +rASIG5V/1090 X46/X28/D0:neg ASIG5V:267 0.445714 +lASIG5V/1091 ASIG5V:2355 ASIG5V:1324 145.051f +rASIG5V/1092 ASIG5V:2355 ASIG5V:265 0.0125686 +rASIG5V/1093 X46/X28/D0:neg ASIG5V:265 0.445714 +lASIG5V/1094 ASIG5V:2353 ASIG5V:297 402.919f +rASIG5V/1095 ASIG5V:2353 ASIG5V:263 0.0349129 +rASIG5V/1096 X46/X28/D0:neg ASIG5V:263 0.445714 +lASIG5V/1097 ASIG5V:2351 ASIG5V:295 402.919f +rASIG5V/1098 ASIG5V:2351 ASIG5V:261 0.0349129 +rASIG5V/1099 ASIG5V:261 X46/X28/D0:neg 0.445714 +lASIG5V/1100 ASIG5V:2349 ASIG5V:293 402.919f +rASIG5V/1101 ASIG5V:2349 ASIG5V:259 0.0349129 +rASIG5V/1102 ASIG5V:259 X46/X28/D0:neg 0.445714 +lASIG5V/1103 ASIG5V:2347 ASIG5V:291 201.459f +rASIG5V/1104 ASIG5V:2347 ASIG5V:257 0.0174565 +rASIG5V/1105 ASIG5V:257 X46/X28/D0:neg 0.445714 +lASIG5V/1106 ASIG5V:2345 ASIG5V:289 402.919f +rASIG5V/1107 ASIG5V:2345 ASIG5V:255 0.0349129 +rASIG5V/1108 ASIG5V:255 X46/X28/D0:neg 0.445714 +lASIG5V/1109 ASIG5V:2343 ASIG5V:287 402.919f +rASIG5V/1110 ASIG5V:2343 ASIG5V:253 0.0349129 +rASIG5V/1111 ASIG5V:253 X46/X28/D0:neg 0.445714 +lASIG5V/1112 ASIG5V:2341 ASIG5V:285 402.919f +rASIG5V/1113 ASIG5V:2341 ASIG5V:251 0.0349129 +rASIG5V/1114 ASIG5V:251 X46/X28/D0:neg 0.445714 +lASIG5V/1115 ASIG5V:2339 ASIG5V:249 354.568f +rASIG5V/1116 ASIG5V:2339 ASIG5V:1260 0.0307234 +lASIG5V/1117 ASIG5V:2337 ASIG5V:283 402.919f +rASIG5V/1118 ASIG5V:2337 ASIG5V:249 0.0349129 +rASIG5V/1119 ASIG5V:249 X46/X28/D0:neg 0.445714 +lASIG5V/1120 ASIG5V:2335 ASIG5V:241 406.948f +rASIG5V/1121 ASIG5V:2335 ASIG5V:309 0.035262 +lASIG5V/1122 ASIG5V:2333 ASIG5V:1372 326.364f +rASIG5V/1123 ASIG5V:2333 ASIG5V:241 0.0282795 +rASIG5V/1124 X46/X28/D0:neg ASIG5V:241 0.445714 +lASIG5V/1125 ASIG5V:2331 ASIG5V:239 406.948f +rASIG5V/1126 ASIG5V:2331 ASIG5V:307 0.035262 +lASIG5V/1127 ASIG5V:2329 ASIG5V:275 406.948f +rASIG5V/1128 ASIG5V:2329 ASIG5V:239 0.035262 +rASIG5V/1129 X46/X28/D0:neg ASIG5V:239 0.445714 +lASIG5V/1130 ASIG5V:2327 ASIG5V:237 406.948f +rASIG5V/1131 ASIG5V:2327 ASIG5V:305 0.035262 +lASIG5V/1132 ASIG5V:2325 ASIG5V:273 406.948f +rASIG5V/1133 ASIG5V:2325 ASIG5V:237 0.035262 +rASIG5V/1134 X46/X28/D0:neg ASIG5V:237 0.445714 +lASIG5V/1135 ASIG5V:2323 ASIG5V:235 402.919f +rASIG5V/1136 ASIG5V:2323 ASIG5V:303 0.0349129 +lASIG5V/1137 ASIG5V:2321 ASIG5V:271 406.948f +rASIG5V/1138 ASIG5V:2321 ASIG5V:235 0.035262 +rASIG5V/1139 X46/X28/D0:neg ASIG5V:235 0.445714 +lASIG5V/1140 ASIG5V:2319 ASIG5V:233 201.459f +rASIG5V/1141 ASIG5V:2319 ASIG5V:301 0.0174565 +lASIG5V/1142 ASIG5V:2317 ASIG5V:269 604.378f +rASIG5V/1143 ASIG5V:2317 ASIG5V:233 0.0523694 +rASIG5V/1144 X46/X28/D0:neg ASIG5V:233 0.445714 +lASIG5V/1145 ASIG5V:2315 ASIG5V:231 402.919f +rASIG5V/1146 ASIG5V:2315 ASIG5V:299 0.0349129 +lASIG5V/1147 ASIG5V:2313 ASIG5V:267 402.919f +rASIG5V/1148 ASIG5V:2313 ASIG5V:231 0.0349129 +rASIG5V/1149 X46/X28/D0:neg ASIG5V:231 0.445714 +lASIG5V/1150 ASIG5V:2311 ASIG5V:229 402.919f +rASIG5V/1151 ASIG5V:2311 ASIG5V:297 0.0349129 +lASIG5V/1152 ASIG5V:2309 ASIG5V:265 402.919f +rASIG5V/1153 ASIG5V:2309 ASIG5V:229 0.0349129 +rASIG5V/1154 X46/X28/D0:neg ASIG5V:229 0.445714 +lASIG5V/1155 ASIG5V:2307 ASIG5V:227 402.919f +rASIG5V/1156 ASIG5V:2307 ASIG5V:295 0.0349129 +lASIG5V/1157 ASIG5V:2305 ASIG5V:263 402.919f +rASIG5V/1158 ASIG5V:2305 ASIG5V:227 0.0349129 +rASIG5V/1159 ASIG5V:227 X46/X28/D0:neg 0.445714 +lASIG5V/1160 ASIG5V:2303 ASIG5V:225 136.992f +rASIG5V/1161 ASIG5V:2303 ASIG5V:1308 0.0118704 +lASIG5V/1162 ASIG5V:2301 ASIG5V:261 402.919f +rASIG5V/1163 ASIG5V:2301 ASIG5V:225 0.0349129 +rASIG5V/1164 ASIG5V:225 X46/X28/D0:neg 0.445714 +lASIG5V/1165 ASIG5V:2299 ASIG5V:223 402.919f +rASIG5V/1166 ASIG5V:2299 ASIG5V:291 0.0349129 +lASIG5V/1167 ASIG5V:2297 ASIG5V:259 402.919f +rASIG5V/1168 ASIG5V:2297 ASIG5V:223 0.0349129 +rASIG5V/1169 ASIG5V:223 X46/X28/D0:neg 0.445714 +lASIG5V/1170 ASIG5V:2295 ASIG5V:221 8.05837f +rASIG5V/1171 ASIG5V:2295 ASIG5V:1292 0.000698258 +lASIG5V/1172 ASIG5V:2293 ASIG5V:257 604.378f +rASIG5V/1173 ASIG5V:2293 ASIG5V:221 0.0523694 +rASIG5V/1174 ASIG5V:221 X46/X28/D0:neg 0.445714 +lASIG5V/1175 ASIG5V:2291 ASIG5V:219 402.919f +rASIG5V/1176 ASIG5V:2291 ASIG5V:287 0.0349129 +lASIG5V/1177 ASIG5V:2289 ASIG5V:255 402.919f +rASIG5V/1178 ASIG5V:2289 ASIG5V:219 0.0349129 +rASIG5V/1179 ASIG5V:219 X46/X28/D0:neg 0.445714 +lASIG5V/1180 ASIG5V:2287 ASIG5V:217 80.5837f +rASIG5V/1181 ASIG5V:2287 ASIG5V:1276 0.00698258 +lASIG5V/1182 ASIG5V:2285 ASIG5V:253 402.919f +rASIG5V/1183 ASIG5V:2285 ASIG5V:217 0.0349129 +rASIG5V/1184 ASIG5V:217 X46/X28/D0:neg 0.445714 +lASIG5V/1185 ASIG5V:2283 ASIG5V:215 402.919f +rASIG5V/1186 ASIG5V:2283 ASIG5V:283 0.0349129 +lASIG5V/1187 ASIG5V:2281 ASIG5V:251 402.919f +rASIG5V/1188 ASIG5V:2281 ASIG5V:215 0.0349129 +rASIG5V/1189 ASIG5V:215 X46/X28/D0:neg 0.445714 +lASIG5V/1190 ASIG5V:2279 ASIG5V:213 402.919f +rASIG5V/1191 ASIG5V:2279 ASIG5V:281 0.0349129 +lASIG5V/1192 ASIG5V:2277 ASIG5V:1260 48.3502f +rASIG5V/1193 ASIG5V:2277 ASIG5V:213 0.00418955 +rASIG5V/1194 ASIG5V:213 X46/X28/D0:neg 0.445714 +rASIG5V/1195 X46/X27/D0:neg ASIG5V:1374 0.445714 +lASIG5V/1196 ASIG5V:2275 ASIG5V:206 539.467f +rASIG5V/1197 ASIG5V:2275 ASIG5V:1374 0.0470395 +rASIG5V/1198 X46/X27/D0:neg ASIG5V:206 0.445714 +rASIG5V/1199 X46/X27/D0:neg ASIG5V:204 0.445714 +lASIG5V/1200 ASIG5V:2273 ASIG5V:202 370.047f +rASIG5V/1201 ASIG5V:2273 ASIG5V:1358 0.0322668 +rASIG5V/1202 X46/X27/D0:neg ASIG5V:202 0.445714 +rASIG5V/1203 X46/X27/D0:neg ASIG5V:200 0.445714 +lASIG5V/1204 ASIG5V:2271 ASIG5V:198 205.087f +rASIG5V/1205 ASIG5V:2271 ASIG5V:1342 0.0178828 +rASIG5V/1206 X46/X27/D0:neg ASIG5V:198 0.445714 +rASIG5V/1207 X46/X27/D0:neg ASIG5V:196 0.445714 +lASIG5V/1208 ASIG5V:2269 ASIG5V:194 285.338f +rASIG5V/1209 ASIG5V:2269 ASIG5V:1326 0.0248804 +rASIG5V/1210 X46/X27/D0:neg ASIG5V:194 0.445714 +rASIG5V/1211 X46/X27/D0:neg ASIG5V:192 0.445714 +rASIG5V/1212 ASIG5V:190 X46/X27/D0:neg 0.445714 +lASIG5V/1213 ASIG5V:2267 ASIG5V:1310 294.255f +rASIG5V/1214 ASIG5V:2267 ASIG5V:188 0.0256579 +rASIG5V/1215 ASIG5V:188 X46/X27/D0:neg 0.445714 +rASIG5V/1216 ASIG5V:186 X46/X27/D0:neg 0.445714 +lASIG5V/1217 ASIG5V:2265 ASIG5V:1294 214.003f +rASIG5V/1218 ASIG5V:2265 ASIG5V:184 0.0186603 +rASIG5V/1219 ASIG5V:184 X46/X27/D0:neg 0.445714 +rASIG5V/1220 ASIG5V:182 X46/X27/D0:neg 0.445714 +lASIG5V/1221 ASIG5V:2263 ASIG5V:1278 356.672f +rASIG5V/1222 ASIG5V:2263 ASIG5V:180 0.0311005 +rASIG5V/1223 ASIG5V:180 X46/X27/D0:neg 0.445714 +rASIG5V/1224 ASIG5V:178 X46/X27/D0:neg 0.445714 +rASIG5V/1225 ASIG5V:176 X46/X27/D0:neg 0.445714 +lASIG5V/1226 ASIG5V:2261 X46/X27/D0:neg 445.84f +rASIG5V/1227 ASIG5V:2261 ASIG5V:176 0.23574 +lASIG5V/1228 ASIG5V:2259 ASIG5V:204 450.299f +rASIG5V/1229 ASIG5V:2259 ASIG5V:170 0.0392644 +rASIG5V/1230 X46/X27/D0:neg ASIG5V:170 0.445714 +lASIG5V/1231 ASIG5V:2257 ASIG5V:1358 80.2513f +rASIG5V/1232 ASIG5V:2257 ASIG5V:168 0.00699761 +rASIG5V/1233 X46/X27/D0:neg ASIG5V:168 0.445714 +lASIG5V/1234 ASIG5V:2255 ASIG5V:200 450.299f +rASIG5V/1235 ASIG5V:2255 ASIG5V:166 0.0392644 +rASIG5V/1236 X46/X27/D0:neg ASIG5V:166 0.445714 +lASIG5V/1237 ASIG5V:2253 ASIG5V:1342 17.8336f +rASIG5V/1238 ASIG5V:2253 ASIG5V:164 0.00155502 +rASIG5V/1239 X46/X27/D0:neg ASIG5V:164 0.445714 +lASIG5V/1240 ASIG5V:2251 ASIG5V:196 445.84f +rASIG5V/1241 ASIG5V:2251 ASIG5V:162 0.0388756 +rASIG5V/1242 X46/X27/D0:neg ASIG5V:162 0.445714 +lASIG5V/1243 ASIG5V:2249 ASIG5V:1326 160.503f +rASIG5V/1244 ASIG5V:2249 ASIG5V:160 0.0139952 +rASIG5V/1245 X46/X27/D0:neg ASIG5V:160 0.445714 +lASIG5V/1246 ASIG5V:2247 ASIG5V:192 445.84f +rASIG5V/1247 ASIG5V:2247 ASIG5V:158 0.0388756 +rASIG5V/1248 X46/X27/D0:neg ASIG5V:158 0.445714 +lASIG5V/1249 ASIG5V:2245 ASIG5V:190 445.84f +rASIG5V/1250 ASIG5V:2245 ASIG5V:156 0.0388756 +rASIG5V/1251 ASIG5V:156 X46/X27/D0:neg 0.445714 +lASIG5V/1252 ASIG5V:2243 ASIG5V:188 445.84f +rASIG5V/1253 ASIG5V:2243 ASIG5V:154 0.0388756 +rASIG5V/1254 ASIG5V:154 X46/X27/D0:neg 0.445714 +lASIG5V/1255 ASIG5V:2241 ASIG5V:186 222.92f +rASIG5V/1256 ASIG5V:2241 ASIG5V:152 0.0194378 +rASIG5V/1257 ASIG5V:152 X46/X27/D0:neg 0.445714 +lASIG5V/1258 ASIG5V:2239 ASIG5V:184 445.84f +rASIG5V/1259 ASIG5V:2239 ASIG5V:150 0.0388756 +rASIG5V/1260 ASIG5V:150 X46/X27/D0:neg 0.445714 +lASIG5V/1261 ASIG5V:2237 ASIG5V:182 445.84f +rASIG5V/1262 ASIG5V:2237 ASIG5V:148 0.0388756 +rASIG5V/1263 ASIG5V:148 X46/X27/D0:neg 0.445714 +lASIG5V/1264 ASIG5V:2235 ASIG5V:180 445.84f +rASIG5V/1265 ASIG5V:2235 ASIG5V:146 0.0388756 +rASIG5V/1266 ASIG5V:146 X46/X27/D0:neg 0.445714 +lASIG5V/1267 ASIG5V:2233 ASIG5V:144 392.339f +rASIG5V/1268 ASIG5V:2233 ASIG5V:1262 0.0342105 +lASIG5V/1269 ASIG5V:2231 ASIG5V:178 445.84f +rASIG5V/1270 ASIG5V:2231 ASIG5V:144 0.0388756 +rASIG5V/1271 ASIG5V:144 X46/X27/D0:neg 0.445714 +lASIG5V/1272 ASIG5V:2229 ASIG5V:138 450.299f +rASIG5V/1273 ASIG5V:2229 ASIG5V:206 0.0392644 +lASIG5V/1274 ASIG5V:2227 ASIG5V:138 450.299f +rASIG5V/1275 ASIG5V:2227 X46/X27/D0:neg 0.271523 +rASIG5V/1276 X46/X27/D0:neg ASIG5V:138 0.445714 +lASIG5V/1277 ASIG5V:2225 ASIG5V:136 450.299f +rASIG5V/1278 ASIG5V:2225 ASIG5V:204 0.0392644 +lASIG5V/1279 ASIG5V:2223 ASIG5V:1374 361.131f +rASIG5V/1280 ASIG5V:2223 ASIG5V:136 0.0314892 +rASIG5V/1281 X46/X27/D0:neg ASIG5V:136 0.445714 +lASIG5V/1282 ASIG5V:2221 ASIG5V:134 450.299f +rASIG5V/1283 ASIG5V:2221 ASIG5V:202 0.0392644 +lASIG5V/1284 ASIG5V:2219 ASIG5V:170 450.299f +rASIG5V/1285 ASIG5V:2219 ASIG5V:134 0.0392644 +rASIG5V/1286 X46/X27/D0:neg ASIG5V:134 0.445714 +lASIG5V/1287 ASIG5V:2217 ASIG5V:132 450.299f +rASIG5V/1288 ASIG5V:2217 ASIG5V:200 0.0392644 +lASIG5V/1289 ASIG5V:2215 ASIG5V:168 450.299f +rASIG5V/1290 ASIG5V:2215 ASIG5V:132 0.0392644 +rASIG5V/1291 X46/X27/D0:neg ASIG5V:132 0.445714 +lASIG5V/1292 ASIG5V:2213 ASIG5V:130 445.84f +rASIG5V/1293 ASIG5V:2213 ASIG5V:198 0.0388756 +lASIG5V/1294 ASIG5V:2211 ASIG5V:166 450.299f +rASIG5V/1295 ASIG5V:2211 ASIG5V:130 0.0392644 +rASIG5V/1296 X46/X27/D0:neg ASIG5V:130 0.445714 +lASIG5V/1297 ASIG5V:2209 ASIG5V:128 222.92f +rASIG5V/1298 ASIG5V:2209 ASIG5V:196 0.0194378 +lASIG5V/1299 ASIG5V:2207 ASIG5V:164 668.761f +rASIG5V/1300 ASIG5V:2207 ASIG5V:128 0.0583134 +rASIG5V/1301 X46/X27/D0:neg ASIG5V:128 0.445714 +lASIG5V/1302 ASIG5V:2205 ASIG5V:126 445.84f +rASIG5V/1303 ASIG5V:2205 ASIG5V:194 0.0388756 +lASIG5V/1304 ASIG5V:2203 ASIG5V:162 445.84f +rASIG5V/1305 ASIG5V:2203 ASIG5V:126 0.0388756 +rASIG5V/1306 X46/X27/D0:neg ASIG5V:126 0.445714 +lASIG5V/1307 ASIG5V:2201 ASIG5V:124 445.84f +rASIG5V/1308 ASIG5V:2201 ASIG5V:192 0.0388756 +lASIG5V/1309 ASIG5V:2199 ASIG5V:160 445.84f +rASIG5V/1310 ASIG5V:2199 ASIG5V:124 0.0388756 +rASIG5V/1311 X46/X27/D0:neg ASIG5V:124 0.445714 +lASIG5V/1312 ASIG5V:2197 ASIG5V:122 445.84f +rASIG5V/1313 ASIG5V:2197 ASIG5V:190 0.0388756 +lASIG5V/1314 ASIG5V:2195 ASIG5V:158 445.84f +rASIG5V/1315 ASIG5V:2195 ASIG5V:122 0.0388756 +rASIG5V/1316 ASIG5V:122 X46/X27/D0:neg 0.445714 +lASIG5V/1317 ASIG5V:2193 ASIG5V:120 151.586f +rASIG5V/1318 ASIG5V:2193 ASIG5V:1310 0.0132177 +lASIG5V/1319 ASIG5V:2191 ASIG5V:156 445.84f +rASIG5V/1320 ASIG5V:2191 ASIG5V:120 0.0388756 +rASIG5V/1321 ASIG5V:120 X46/X27/D0:neg 0.445714 +lASIG5V/1322 ASIG5V:2189 ASIG5V:118 445.84f +rASIG5V/1323 ASIG5V:2189 ASIG5V:186 0.0388756 +lASIG5V/1324 ASIG5V:2187 ASIG5V:154 445.84f +rASIG5V/1325 ASIG5V:2187 ASIG5V:118 0.0388756 +rASIG5V/1326 ASIG5V:118 X46/X27/D0:neg 0.445714 +lASIG5V/1327 ASIG5V:2185 ASIG5V:116 8.91681f +rASIG5V/1328 ASIG5V:2185 ASIG5V:1294 0.000777512 +lASIG5V/1329 ASIG5V:2183 ASIG5V:152 668.761f +rASIG5V/1330 ASIG5V:2183 ASIG5V:116 0.0583134 +rASIG5V/1331 ASIG5V:116 X46/X27/D0:neg 0.445714 +lASIG5V/1332 ASIG5V:2181 ASIG5V:114 445.84f +rASIG5V/1333 ASIG5V:2181 ASIG5V:182 0.0388756 +lASIG5V/1334 ASIG5V:2179 ASIG5V:150 445.84f +rASIG5V/1335 ASIG5V:2179 ASIG5V:114 0.0388756 +rASIG5V/1336 ASIG5V:114 X46/X27/D0:neg 0.445714 +lASIG5V/1337 ASIG5V:2177 ASIG5V:112 89.1681f +rASIG5V/1338 ASIG5V:2177 ASIG5V:1278 0.00777512 +lASIG5V/1339 ASIG5V:2175 ASIG5V:148 445.84f +rASIG5V/1340 ASIG5V:2175 ASIG5V:112 0.0388756 +rASIG5V/1341 ASIG5V:112 X46/X27/D0:neg 0.445714 +lASIG5V/1342 ASIG5V:2173 ASIG5V:110 445.84f +rASIG5V/1343 ASIG5V:2173 ASIG5V:178 0.0388756 +lASIG5V/1344 ASIG5V:2171 ASIG5V:146 445.84f +rASIG5V/1345 ASIG5V:2171 ASIG5V:110 0.0388756 +rASIG5V/1346 ASIG5V:110 X46/X27/D0:neg 0.445714 +lASIG5V/1347 ASIG5V:2169 ASIG5V:108 445.84f +rASIG5V/1348 ASIG5V:2169 ASIG5V:176 0.0388756 +lASIG5V/1349 ASIG5V:2167 ASIG5V:1262 53.5008f +rASIG5V/1350 ASIG5V:2167 ASIG5V:108 0.00466507 +rASIG5V/1351 ASIG5V:108 X46/X27/D0:neg 0.445714 +rASIG5V/1352 X46/X26/D0:neg ASIG5V:1376 0.445714 +lASIG5V/1353 ASIG5V:2165 ASIG5V:101 565.99f +rASIG5V/1354 ASIG5V:2165 ASIG5V:1376 0.0498351 +rASIG5V/1355 X46/X26/D0:neg ASIG5V:101 0.445714 +rASIG5V/1356 X46/X26/D0:neg ASIG5V:99 0.445714 +lASIG5V/1357 ASIG5V:2163 ASIG5V:97 388.241f +rASIG5V/1358 ASIG5V:2163 ASIG5V:1360 0.0341844 +rASIG5V/1359 X46/X26/D0:neg ASIG5V:97 0.445714 +rASIG5V/1360 X46/X26/D0:neg ASIG5V:95 0.445714 +lASIG5V/1361 ASIG5V:2161 ASIG5V:93 215.17f +rASIG5V/1362 ASIG5V:2161 ASIG5V:1344 0.0189456 +rASIG5V/1363 X46/X26/D0:neg ASIG5V:93 0.445714 +rASIG5V/1364 X46/X26/D0:neg ASIG5V:91 0.445714 +lASIG5V/1365 ASIG5V:2159 ASIG5V:89 299.367f +rASIG5V/1366 ASIG5V:2159 ASIG5V:1328 0.026359 +rASIG5V/1367 X46/X26/D0:neg ASIG5V:89 0.445714 +rASIG5V/1368 X46/X26/D0:neg ASIG5V:87 0.445714 +rASIG5V/1369 ASIG5V:85 X46/X26/D0:neg 0.445714 +lASIG5V/1370 ASIG5V:2157 ASIG5V:1312 308.722f +rASIG5V/1371 ASIG5V:2157 ASIG5V:83 0.0271828 +rASIG5V/1372 ASIG5V:83 X46/X26/D0:neg 0.445714 +rASIG5V/1373 ASIG5V:81 X46/X26/D0:neg 0.445714 +lASIG5V/1374 ASIG5V:2155 ASIG5V:1296 224.525f +rASIG5V/1375 ASIG5V:2155 ASIG5V:79 0.0197693 +rASIG5V/1376 ASIG5V:79 X46/X26/D0:neg 0.445714 +rASIG5V/1377 ASIG5V:77 X46/X26/D0:neg 0.445714 +lASIG5V/1378 ASIG5V:2153 ASIG5V:1280 374.209f +rASIG5V/1379 ASIG5V:2153 ASIG5V:75 0.0329488 +rASIG5V/1380 ASIG5V:75 X46/X26/D0:neg 0.445714 +rASIG5V/1381 ASIG5V:73 X46/X26/D0:neg 0.445714 +rASIG5V/1382 ASIG5V:71 X46/X26/D0:neg 0.445714 +lASIG5V/1383 ASIG5V:2151 X46/X26/D0:neg 467.761f +rASIG5V/1384 ASIG5V:2151 ASIG5V:71 0.2388 +lASIG5V/1385 ASIG5V:2149 ASIG5V:99 472.438f +rASIG5V/1386 ASIG5V:2149 ASIG5V:65 0.0415979 +rASIG5V/1387 X46/X26/D0:neg ASIG5V:65 0.445714 +lASIG5V/1388 ASIG5V:2147 ASIG5V:1360 84.1969f +rASIG5V/1389 ASIG5V:2147 ASIG5V:63 0.00741348 +rASIG5V/1390 X46/X26/D0:neg ASIG5V:63 0.445714 +lASIG5V/1391 ASIG5V:2145 ASIG5V:95 472.438f +rASIG5V/1392 ASIG5V:2145 ASIG5V:61 0.0415979 +rASIG5V/1393 X46/X26/D0:neg ASIG5V:61 0.445714 +lASIG5V/1394 ASIG5V:2143 ASIG5V:1344 18.7104f +rASIG5V/1395 ASIG5V:2143 ASIG5V:59 0.00164744 +rASIG5V/1396 X46/X26/D0:neg ASIG5V:59 0.445714 +lASIG5V/1397 ASIG5V:2141 ASIG5V:91 467.761f +rASIG5V/1398 ASIG5V:2141 ASIG5V:57 0.041186 +rASIG5V/1399 X46/X26/D0:neg ASIG5V:57 0.445714 +lASIG5V/1400 ASIG5V:2139 ASIG5V:1328 168.394f +rASIG5V/1401 ASIG5V:2139 ASIG5V:55 0.014827 +rASIG5V/1402 X46/X26/D0:neg ASIG5V:55 0.445714 +lASIG5V/1403 ASIG5V:2137 ASIG5V:87 467.761f +rASIG5V/1404 ASIG5V:2137 ASIG5V:53 0.041186 +rASIG5V/1405 X46/X26/D0:neg ASIG5V:53 0.445714 +lASIG5V/1406 ASIG5V:2135 ASIG5V:85 467.761f +rASIG5V/1407 ASIG5V:2135 ASIG5V:51 0.041186 +rASIG5V/1408 ASIG5V:51 X46/X26/D0:neg 0.445714 +lASIG5V/1409 ASIG5V:2133 ASIG5V:83 467.761f +rASIG5V/1410 ASIG5V:2133 ASIG5V:49 0.041186 +rASIG5V/1411 ASIG5V:49 X46/X26/D0:neg 0.445714 +lASIG5V/1412 ASIG5V:2131 ASIG5V:81 233.88f +rASIG5V/1413 ASIG5V:2131 ASIG5V:47 0.020593 +rASIG5V/1414 ASIG5V:47 X46/X26/D0:neg 0.445714 +lASIG5V/1415 ASIG5V:2129 ASIG5V:79 467.761f +rASIG5V/1416 ASIG5V:2129 ASIG5V:45 0.041186 +rASIG5V/1417 ASIG5V:45 X46/X26/D0:neg 0.445714 +lASIG5V/1418 ASIG5V:2127 ASIG5V:77 467.761f +rASIG5V/1419 ASIG5V:2127 ASIG5V:43 0.041186 +rASIG5V/1420 ASIG5V:43 X46/X26/D0:neg 0.445714 +lASIG5V/1421 ASIG5V:2125 ASIG5V:75 467.761f +rASIG5V/1422 ASIG5V:2125 ASIG5V:41 0.041186 +rASIG5V/1423 ASIG5V:41 X46/X26/D0:neg 0.445714 +lASIG5V/1424 ASIG5V:2123 ASIG5V:39 411.629f +rASIG5V/1425 ASIG5V:2123 ASIG5V:1264 0.0362437 +lASIG5V/1426 ASIG5V:2121 ASIG5V:73 467.761f +rASIG5V/1427 ASIG5V:2121 ASIG5V:39 0.041186 +rASIG5V/1428 ASIG5V:39 X46/X26/D0:neg 0.445714 +lASIG5V/1429 ASIG5V:2119 ASIG5V:33 472.438f +rASIG5V/1430 ASIG5V:2119 ASIG5V:101 0.0415979 +lASIG5V/1431 ASIG5V:2117 ASIG5V:33 472.438f +rASIG5V/1432 ASIG5V:2117 X46/X26/D0:neg 0.274391 +rASIG5V/1433 X46/X26/D0:neg ASIG5V:33 0.445714 +lASIG5V/1434 ASIG5V:2115 ASIG5V:31 472.438f +rASIG5V/1435 ASIG5V:2115 ASIG5V:99 0.0415979 +lASIG5V/1436 ASIG5V:2113 ASIG5V:1376 378.886f +rASIG5V/1437 ASIG5V:2113 ASIG5V:31 0.0333607 +rASIG5V/1438 X46/X26/D0:neg ASIG5V:31 0.445714 +lASIG5V/1439 ASIG5V:2111 ASIG5V:29 472.438f +rASIG5V/1440 ASIG5V:2111 ASIG5V:97 0.0415979 +lASIG5V/1441 ASIG5V:2109 ASIG5V:65 472.438f +rASIG5V/1442 ASIG5V:2109 ASIG5V:29 0.0415979 +rASIG5V/1443 X46/X26/D0:neg ASIG5V:29 0.445714 +lASIG5V/1444 ASIG5V:2107 ASIG5V:27 472.438f +rASIG5V/1445 ASIG5V:2107 ASIG5V:95 0.0415979 +lASIG5V/1446 ASIG5V:2105 ASIG5V:63 472.438f +rASIG5V/1447 ASIG5V:2105 ASIG5V:27 0.0415979 +rASIG5V/1448 X46/X26/D0:neg ASIG5V:27 0.445714 +lASIG5V/1449 ASIG5V:2103 ASIG5V:25 467.761f +rASIG5V/1450 ASIG5V:2103 ASIG5V:93 0.041186 +lASIG5V/1451 ASIG5V:2101 ASIG5V:61 472.438f +rASIG5V/1452 ASIG5V:2101 ASIG5V:25 0.0415979 +rASIG5V/1453 X46/X26/D0:neg ASIG5V:25 0.445714 +lASIG5V/1454 ASIG5V:2099 ASIG5V:23 233.88f +rASIG5V/1455 ASIG5V:2099 ASIG5V:91 0.020593 +lASIG5V/1456 ASIG5V:2097 ASIG5V:59 701.641f +rASIG5V/1457 ASIG5V:2097 ASIG5V:23 0.061779 +rASIG5V/1458 X46/X26/D0:neg ASIG5V:23 0.445714 +lASIG5V/1459 ASIG5V:2095 ASIG5V:21 467.761f +rASIG5V/1460 ASIG5V:2095 ASIG5V:89 0.041186 +lASIG5V/1461 ASIG5V:2093 ASIG5V:57 467.761f +rASIG5V/1462 ASIG5V:2093 ASIG5V:21 0.041186 +rASIG5V/1463 X46/X26/D0:neg ASIG5V:21 0.445714 +lASIG5V/1464 ASIG5V:2091 ASIG5V:19 467.761f +rASIG5V/1465 ASIG5V:2091 ASIG5V:87 0.041186 +lASIG5V/1466 ASIG5V:2089 ASIG5V:55 467.761f +rASIG5V/1467 ASIG5V:2089 ASIG5V:19 0.041186 +rASIG5V/1468 X46/X26/D0:neg ASIG5V:19 0.445714 +lASIG5V/1469 ASIG5V:2087 ASIG5V:17 467.761f +rASIG5V/1470 ASIG5V:2087 ASIG5V:85 0.041186 +lASIG5V/1471 ASIG5V:2085 ASIG5V:53 467.761f +rASIG5V/1472 ASIG5V:2085 ASIG5V:17 0.041186 +rASIG5V/1473 ASIG5V:17 X46/X26/D0:neg 0.445714 +lASIG5V/1474 ASIG5V:2083 ASIG5V:15 159.039f +rASIG5V/1475 ASIG5V:2083 ASIG5V:1312 0.0140032 +lASIG5V/1476 ASIG5V:2081 ASIG5V:51 467.761f +rASIG5V/1477 ASIG5V:2081 ASIG5V:15 0.041186 +rASIG5V/1478 ASIG5V:15 X46/X26/D0:neg 0.445714 +lASIG5V/1479 ASIG5V:2079 ASIG5V:13 467.761f +rASIG5V/1480 ASIG5V:2079 ASIG5V:81 0.041186 +lASIG5V/1481 ASIG5V:2077 ASIG5V:49 467.761f +rASIG5V/1482 ASIG5V:2077 ASIG5V:13 0.041186 +rASIG5V/1483 ASIG5V:13 X46/X26/D0:neg 0.445714 +lASIG5V/1484 ASIG5V:2075 ASIG5V:11 9.35521f +rASIG5V/1485 ASIG5V:2075 ASIG5V:1296 0.00082372 +lASIG5V/1486 ASIG5V:2073 ASIG5V:47 701.641f +rASIG5V/1487 ASIG5V:2073 ASIG5V:11 0.061779 +rASIG5V/1488 ASIG5V:11 X46/X26/D0:neg 0.445714 +lASIG5V/1489 ASIG5V:2071 ASIG5V:9 467.761f +rASIG5V/1490 ASIG5V:2071 ASIG5V:77 0.041186 +lASIG5V/1491 ASIG5V:2069 ASIG5V:45 467.761f +rASIG5V/1492 ASIG5V:2069 ASIG5V:9 0.041186 +rASIG5V/1493 ASIG5V:9 X46/X26/D0:neg 0.445714 +lASIG5V/1494 ASIG5V:2067 ASIG5V:7 93.5521f +rASIG5V/1495 ASIG5V:2067 ASIG5V:1280 0.0082372 +lASIG5V/1496 ASIG5V:2065 ASIG5V:43 467.761f +rASIG5V/1497 ASIG5V:2065 ASIG5V:7 0.041186 +rASIG5V/1498 ASIG5V:7 X46/X26/D0:neg 0.445714 +lASIG5V/1499 ASIG5V:2063 ASIG5V:5 467.761f +rASIG5V/1500 ASIG5V:2063 ASIG5V:73 0.041186 +lASIG5V/1501 ASIG5V:2061 ASIG5V:41 467.761f +rASIG5V/1502 ASIG5V:2061 ASIG5V:5 0.041186 +rASIG5V/1503 ASIG5V:5 X46/X26/D0:neg 0.445714 +lASIG5V/1504 ASIG5V:2059 ASIG5V:3 467.761f +rASIG5V/1505 ASIG5V:2059 ASIG5V:71 0.041186 +lASIG5V/1506 ASIG5V:2057 ASIG5V:1264 56.1313f +rASIG5V/1507 ASIG5V:2057 ASIG5V:3 0.00494232 +rASIG5V/1508 ASIG5V:3 X46/X26/D0:neg 0.445714 +XR0 R0:pos R0:neg rm2 r_width=2.54e-06 r_length=2.76e-07 +XR1 R1:pos R1:neg rm2 r_width=2.54e-06 r_length=2.76e-07 +XR2 R2:pos R2:neg rm2 r_width=2.54e-06 r_length=2.76e-07 +XR3 R3:pos R3:neg rm2 r_width=2.54e-06 r_length=2.76e-07 +XR4 R4:pos R4:neg rm2 r_width=2.54e-06 r_length=2.76e-07 +XR5 R5:pos R5:neg rm2 r_width=2.54e-06 r_length=2.76e-07 +XR6 R6:pos R6:neg rm2 r_width=2.54e-06 r_length=2.76e-07 +XR7 R7:pos R7:neg rm2 r_width=2.54e-06 r_length=2.76e-07 +dX27/D0 DVSS X27/D0:neg diode_nd2ps_06v0 area=4e-11 pj=8.2e-05 M=1 +dX28/D0 DVSS X28/D0:neg diode_nd2ps_06v0 area=4e-11 pj=8.2e-05 M=1 +dX29/D0 DVSS X29/D0:neg diode_nd2ps_06v0 area=4e-11 pj=8.2e-05 M=1 +dX30/D0 DVSS X30/D0:neg diode_nd2ps_06v0 area=4e-11 pj=8.2e-05 M=1 +dX46/X26/D0 DVSS X46/X26/D0:neg diode_nd2ps_06v0 area=1.5e-10 pj=0.000106 M=1 +dX46/X27/D0 DVSS X46/X27/D0:neg diode_nd2ps_06v0 area=1.5e-10 pj=0.000106 M=1 +dX46/X28/D0 DVSS X46/X28/D0:neg diode_nd2ps_06v0 area=1.5e-10 pj=0.000106 M=1 +dX46/X29/D0 DVSS X46/X29/D0:neg diode_nd2ps_06v0 area=1.5e-10 pj=0.000106 M=1 +dX46/X30/D0 X46/X30/D0:pos X46/X30/D0:neg diode_pd2nw_06v0 area=1.5e-10 pj=0.000106 M=1 +dX46/X31/D0 X46/X31/D0:pos X46/X31/D0:neg diode_pd2nw_06v0 area=1.5e-10 pj=0.000106 M=1 +dX46/X32/D0 X46/X32/D0:pos X46/X32/D0:neg diode_pd2nw_06v0 area=1.5e-10 pj=0.000106 M=1 +dX46/X33/D0 X46/X33/D0:pos X46/X33/D0:neg diode_pd2nw_06v0 area=1.5e-10 pj=0.000106 M=1 +XX48/X1/X0/C0 X48/X1/X0/C0:pos DVSS cap_nmos_06v0 c_length=1.5e-05 c_width=1.5e-05 +XX48/X1/X1/C0 X48/X1/X1/C0:pos DVSS cap_nmos_06v0 c_length=1.5e-05 c_width=1.5e-05 +XX48/X2/X0/C0 X48/X2/X0/C0:pos DVSS cap_nmos_06v0 c_length=1.5e-05 c_width=1.5e-05 +XX48/X2/X1/C0 X48/X2/X1/C0:pos DVSS cap_nmos_06v0 c_length=1.5e-05 c_width=1.5e-05 +XX49/X0/X1/X0/C0 X49/X0/X1/X0/C0:pos DVSS cap_nmos_06v0 c_length=1.5e-05 c_width=1.5e-05 +XX49/X0/X1/X1/C0 X49/X0/X1/X1/C0:pos DVSS cap_nmos_06v0 c_length=1.5e-05 c_width=1.5e-05 +XX49/X0/X2/X0/C0 X49/X0/X2/X0/C0:pos DVSS cap_nmos_06v0 c_length=1.5e-05 c_width=1.5e-05 +XX49/X0/X2/X1/C0 X49/X0/X2/X1/C0:pos DVSS cap_nmos_06v0 c_length=1.5e-05 c_width=1.5e-05 +XX49/X1/X1/X0/C0 X49/X1/X1/X0/C0:pos DVSS cap_nmos_06v0 c_length=1.5e-05 c_width=1.5e-05 +XX49/X1/X1/X1/C0 X49/X1/X1/X1/C0:pos DVSS cap_nmos_06v0 c_length=1.5e-05 c_width=1.5e-05 +XX49/X1/X2/X0/C0 X49/X1/X2/X0/C0:pos DVSS cap_nmos_06v0 c_length=1.5e-05 c_width=1.5e-05 +XX49/X1/X2/X1/C0 X49/X1/X2/X1/C0:pos DVSS cap_nmos_06v0 c_length=1.5e-05 c_width=1.5e-05 +XX50/X0/X1/X0/C0 X50/X0/X1/X0/C0:pos DVSS cap_nmos_06v0 c_length=1.5e-05 c_width=1.5e-05 +XX50/X0/X1/X1/C0 X50/X0/X1/X1/C0:pos DVSS cap_nmos_06v0 c_length=1.5e-05 c_width=1.5e-05 +XX50/X0/X2/X0/C0 X50/X0/X2/X0/C0:pos DVSS cap_nmos_06v0 c_length=1.5e-05 c_width=1.5e-05 +XX50/X0/X2/X1/C0 X50/X0/X2/X1/C0:pos DVSS cap_nmos_06v0 c_length=1.5e-05 c_width=1.5e-05 +XX50/X1/X1/X0/C0 X50/X1/X1/X0/C0:pos DVSS cap_nmos_06v0 c_length=1.5e-05 c_width=1.5e-05 +XX50/X1/X1/X1/C0 X50/X1/X1/X1/C0:pos DVSS cap_nmos_06v0 c_length=1.5e-05 c_width=1.5e-05 +XX50/X1/X2/X0/C0 X50/X1/X2/X0/C0:pos DVSS cap_nmos_06v0 c_length=1.5e-05 c_width=1.5e-05 +XX50/X1/X2/X1/C0 X50/X1/X2/X1/C0:pos DVSS cap_nmos_06v0 c_length=1.5e-05 c_width=1.5e-05 +XX51/X0/X1/X0/C0 X51/X0/X1/X0/C0:pos DVSS cap_nmos_06v0 c_length=1.5e-05 c_width=1.5e-05 +XX51/X0/X1/X1/C0 X51/X0/X1/X1/C0:pos DVSS cap_nmos_06v0 c_length=1.5e-05 c_width=1.5e-05 +XX51/X0/X2/X0/C0 X51/X0/X2/X0/C0:pos DVSS cap_nmos_06v0 c_length=1.5e-05 c_width=1.5e-05 +XX51/X0/X2/X1/C0 X51/X0/X2/X1/C0:pos DVSS cap_nmos_06v0 c_length=1.5e-05 c_width=1.5e-05 +XX51/X1/X1/X0/C0 X51/X1/X1/X0/C0:pos DVSS cap_nmos_06v0 c_length=1.5e-05 c_width=1.5e-05 +XX51/X1/X1/X1/C0 X51/X1/X1/X1/C0:pos DVSS cap_nmos_06v0 c_length=1.5e-05 c_width=1.5e-05 +XX51/X1/X2/X0/C0 X51/X1/X2/X0/C0:pos DVSS cap_nmos_06v0 c_length=1.5e-05 c_width=1.5e-05 +XX51/X1/X2/X1/C0 X51/X1/X2/X1/C0:pos DVSS cap_nmos_06v0 c_length=1.5e-05 c_width=1.5e-05 +XX52/X0/X1/X0/C0 X52/X0/X1/X0/C0:pos DVSS cap_nmos_06v0 c_length=1.5e-05 c_width=1.5e-05 +XX52/X0/X1/X1/C0 X52/X0/X1/X1/C0:pos DVSS cap_nmos_06v0 c_length=1.5e-05 c_width=1.5e-05 +XX52/X0/X2/X0/C0 X52/X0/X2/X0/C0:pos DVSS cap_nmos_06v0 c_length=1.5e-05 c_width=1.5e-05 +XX52/X0/X2/X1/C0 X52/X0/X2/X1/C0:pos DVSS cap_nmos_06v0 c_length=1.5e-05 c_width=1.5e-05 +XX52/X1/X1/X0/C0 X52/X1/X1/X0/C0:pos DVSS cap_nmos_06v0 c_length=1.5e-05 c_width=1.5e-05 +XX52/X1/X1/X1/C0 X52/X1/X1/X1/C0:pos DVSS cap_nmos_06v0 c_length=1.5e-05 c_width=1.5e-05 +XX52/X1/X2/X0/C0 X52/X1/X2/X0/C0:pos DVSS cap_nmos_06v0 c_length=1.5e-05 c_width=1.5e-05 +XX52/X1/X2/X1/C0 X52/X1/X2/X1/C0:pos DVSS cap_nmos_06v0 c_length=1.5e-05 c_width=1.5e-05 +.ends diff --git a/blocks/composite/regulated_cascoded_cmirror/xschem/Chipathon2025_pads/xschem/io_asig_5p0.sym b/blocks/composite/regulated_cascoded_cmirror/xschem/Chipathon2025_pads/xschem/io_asig_5p0.sym new file mode 100644 index 00000000..9dafc5a1 --- /dev/null +++ b/blocks/composite/regulated_cascoded_cmirror/xschem/Chipathon2025_pads/xschem/io_asig_5p0.sym @@ -0,0 +1,49 @@ +v {xschem version=3.4.7 file_version=1.2} +G {} +K {type=io +format="@spiceprefix@name @pinlist @model" +lvs_format="@spiceprefix@name @pinlist @model" +template="name=IO1 +model=gf180mcu_fd_io__asig_5p0_extracted +spiceprefix=X +" +} +V {} +S {} +E {} +L 4 70 -100 80 -120 {} +L 4 80 -120 90 -100 {} +L 4 70 -100 90 -100 {} +L 4 80 -100 80 -80 {} +L 4 80 -80 80 -60 {} +L 4 70 -60 90 -60 {} +L 4 80 -40 90 -60 {} +L 4 70 -60 80 -40 {} +L 4 70 -120 90 -120 {} +L 4 70 -40 90 -40 {} +L 4 80 -140 80 -120 {} +L 4 80 -40 80 -20 {} +L 4 20 -80 180 -80 {dash=4} +L 7 80 -160 80 -140 {} +L 7 120 -160 120 -140 {} +L 7 0 -80 20 -80 {} +L 7 180 -80 200 -80 {} +L 7 120 -20 120 0 {} +L 7 80 -20 80 0 {} +B 5 77.5 -2.5 82.5 2.5 {name=DVSS dir=inout +sim_pinnumber=1} +B 5 77.5 -162.5 82.5 -157.5 {name=DVDD dir=inout sim_pinnumber=2} +B 5 117.5 -2.5 122.5 2.5 {name=VSS dir=inout +sim_pinnumber=3} +B 5 117.5 -162.5 122.5 -157.5 {name=VDD dir=inout sim_pinnumber=4} +B 5 -2.5 -82.5 2.5 -77.5 {name=PAD dir=inout sim_pinnumber=5} +B 5 197.5 -82.5 202.5 -77.5 {name=ASIG5V dir=inout sim_pinnumber=6} +P 4 5 180 -140 20 -140 20 -20 180 -20 180 -140 {} +T {@symname} 52.5 -106 0 0 0.3 0.3 {} +T {@name} 135 -152 0 0 0.2 0.2 {} +T {DVSS} 55 -26 2 1 0.2 0.2 {} +T {DVDD} 75 -134 0 1 0.2 0.2 {} +T {VSS} 115 -26 2 1 0.2 0.2 {} +T {VDD} 135 -134 0 1 0.2 0.2 {} +T {PAD} 25 -74 0 0 0.2 0.2 {} +T {ASIG5V} 175 -74 0 1 0.2 0.2 {} diff --git a/blocks/composite/regulated_cascoded_cmirror/xschem/Chipathon2025_pads/xschem/io_bi_24t.sym b/blocks/composite/regulated_cascoded_cmirror/xschem/Chipathon2025_pads/xschem/io_bi_24t.sym new file mode 100644 index 00000000..58fa39af --- /dev/null +++ b/blocks/composite/regulated_cascoded_cmirror/xschem/Chipathon2025_pads/xschem/io_bi_24t.sym @@ -0,0 +1,108 @@ +v {xschem version=3.4.7 file_version=1.2} +G {} +K {type=io +format="@spiceprefix@name @pinlist @model" +lvs_format="@spiceprefix@name @pinlist @model" +template="name=IO1 +model=gf180mcu_fd_io__bi_24t +spiceprefix=X +" +} +V {} +S {} +E {} +L 4 70 -200 80 -220 {} +L 4 80 -220 90 -200 {} +L 4 70 -200 90 -200 {} +L 4 80 -200 80 -180 {} +L 4 80 -180 80 -160 {} +L 4 70 -60 90 -60 {} +L 4 80 -40 90 -60 {} +L 4 70 -60 80 -40 {} +L 4 70 -220 90 -220 {} +L 4 70 -40 90 -40 {} +L 4 80 -240 80 -220 {} +L 4 80 -160 80 -20 {} +L 4 80 -180 180 -180 {dash=4} +L 4 180 -200 180 -160 {} +L 4 180 -160 220 -180 {} +L 4 180 -200 220 -180 {} +L 4 220 -180 240 -180 {} +L 4 110 -165 115 -175 {} +L 4 115 -175 125 -155 {} +L 4 125 -155 135 -175 {} +L 4 135 -175 145 -155 {} +L 4 145 -155 150 -165 {} +L 4 150 -165 160 -165 {} +L 4 100 -165 110 -165 {} +L 4 160 -180 160 -165 {} +L 4 100 -190 100 -160 {} +L 4 100 -190 110 -210 {} +L 4 100 -230 100 -210 {} +L 4 80 -230 100 -230 {} +L 4 80 -30 100 -30 {} +L 4 100 -140 100 -30 {} +L 4 100 -160 110 -140 {} +L 4 100 -200 170 -200 {} +L 4 170 -200 170 -160 {} +L 4 170 -160 240 -160 {} +L 4 100 -150 160 -150 {} +L 4 160 -150 160 -140 {} +L 4 160 -140 240 -140 {} +L 4 240 -180 260 -180 {} +L 4 240 -160 260 -160 {} +L 4 240 -140 260 -140 {} +L 4 190 -220 240 -220 {} +L 4 190 -220 190 -200 {} +L 4 210 -200 240 -200 {} +L 4 210 -200 210 -190 {} +L 4 240 -220 260 -220 {} +L 4 240 -200 260 -200 {} +L 4 160 -100 160 -60 {} +L 4 120 -80 160 -60 {} +L 4 120 -80 160 -100 {} +L 4 160 -60 240 -60 {} +L 4 140 -70 140 -40 {} +L 4 140 -40 240 -40 {} +L 4 240 -40 260 -40 {} +L 4 240 -60 260 -60 {} +L 4 160 -80 240 -80 {} +L 4 240 -80 260 -80 {} +L 4 20 -120 80 -120 {dash=4} +L 4 80 -80 120 -80 {dash=4} +L 7 80 -260 80 -240 {} +L 7 120 -260 120 -240 {} +L 7 0 -120 20 -120 {} +L 7 120 -20 120 0 {} +L 7 80 -20 80 0 {} +B 5 257.5 -82.5 262.5 -77.5 {name=A dir=in sim_pinnumber=1} +B 5 257.5 -202.5 262.5 -197.5 {name=CS dir=in sim_pinnumber=2} +B 5 77.5 -262.5 82.5 -257.5 {name=DVDD dir=inout sim_pinnumber=3} +B 5 77.5 -2.5 82.5 2.5 {name=DVSS dir=inout +sim_pinnumber=4} +B 5 257.5 -222.5 262.5 -217.5 {name=IE dir=in sim_pinnumber=5} +B 5 257.5 -42.5 262.5 -37.5 {name=OE dir=in sim_pinnumber=6} +B 5 -2.5 -122.5 2.5 -117.5 {name=PAD dir=inout sim_pinnumber=7} +B 5 257.5 -142.5 262.5 -137.5 {name=PD dir=in sim_pinnumber=8} +B 5 257.5 -162.5 262.5 -157.5 {name=PU dir=in sim_pinnumber=11} +B 5 257.5 -62.5 262.5 -57.5 {name=SL dir=in sim_pinnumber=12} +B 5 117.5 -262.5 122.5 -257.5 {name=VDD dir=inout sim_pinnumber=13} +B 5 117.5 -2.5 122.5 2.5 {name=VSS dir=inout +sim_pinnumber=14} +B 5 257.5 -182.5 262.5 -177.5 {name=Y dir=out sim_pinnumber=15} +P 4 5 240 -240 20 -240 20 -20 240 -20 240 -240 {} +T {@symname} 52.5 -146 0 0 0.3 0.3 {} +T {@name} 195 -252 0 0 0.2 0.2 {} +T {DVSS} 45 -26 2 1 0.2 0.2 {} +T {DVDD} 75 -234 0 1 0.2 0.2 {} +T {VSS} 115 -26 2 1 0.2 0.2 {} +T {VDD} 135 -234 0 1 0.2 0.2 {} +T {PAD} 25 -134 0 0 0.2 0.2 {} +T {Y} 235 -194 0 1 0.2 0.2 {} +T {PU} 235 -174 0 1 0.2 0.2 {} +T {PD} 235 -154 0 1 0.2 0.2 {} +T {IE} 235 -234 0 1 0.2 0.2 {} +T {CS} 235 -214 0 1 0.2 0.2 {} +T {OE} 235 -54 0 1 0.2 0.2 {} +T {SL} 235 -74 0 1 0.2 0.2 {} +T {A} 235 -94 0 1 0.2 0.2 {} diff --git a/blocks/composite/regulated_cascoded_cmirror/xschem/Chipathon2025_pads/xschem/io_bi_t.sym b/blocks/composite/regulated_cascoded_cmirror/xschem/Chipathon2025_pads/xschem/io_bi_t.sym new file mode 100644 index 00000000..0557f7f9 --- /dev/null +++ b/blocks/composite/regulated_cascoded_cmirror/xschem/Chipathon2025_pads/xschem/io_bi_t.sym @@ -0,0 +1,117 @@ +v {xschem version=3.4.7 file_version=1.2} +G {} +K {type=io +format="@spiceprefix@name @pinlist @model" +lvs_format="@spiceprefix@name @pinlist @model" +template="name=IO1 +model=gf180mcu_fd_io__bi_t +spiceprefix=X +" +} +V {} +S {} +E {} +L 4 70 -200 80 -220 {} +L 4 80 -220 90 -200 {} +L 4 70 -200 90 -200 {} +L 4 80 -200 80 -180 {} +L 4 80 -180 80 -160 {} +L 4 70 -60 90 -60 {} +L 4 80 -40 90 -60 {} +L 4 70 -60 80 -40 {} +L 4 70 -220 90 -220 {} +L 4 70 -40 90 -40 {} +L 4 80 -240 80 -220 {} +L 4 80 -160 80 -20 {} +L 4 80 -180 180 -180 {dash=4} +L 4 180 -200 180 -160 {} +L 4 180 -160 220 -180 {} +L 4 180 -200 220 -180 {} +L 4 220 -180 240 -180 {} +L 4 110 -165 115 -175 {} +L 4 115 -175 125 -155 {} +L 4 125 -155 135 -175 {} +L 4 135 -175 145 -155 {} +L 4 145 -155 150 -165 {} +L 4 150 -165 160 -165 {} +L 4 100 -165 110 -165 {} +L 4 160 -180 160 -165 {} +L 4 100 -190 100 -160 {} +L 4 100 -190 110 -210 {} +L 4 100 -230 100 -210 {} +L 4 80 -230 100 -230 {} +L 4 80 -30 100 -30 {} +L 4 100 -140 100 -30 {} +L 4 100 -160 110 -140 {} +L 4 100 -200 170 -200 {} +L 4 170 -200 170 -160 {} +L 4 170 -160 240 -160 {} +L 4 100 -150 160 -150 {} +L 4 160 -150 160 -140 {} +L 4 160 -140 240 -140 {} +L 4 240 -180 260 -180 {} +L 4 240 -160 260 -160 {} +L 4 240 -140 260 -140 {} +L 4 190 -220 240 -220 {} +L 4 190 -220 190 -200 {} +L 4 210 -200 240 -200 {} +L 4 210 -200 210 -190 {} +L 4 240 -220 260 -220 {} +L 4 240 -200 260 -200 {} +L 4 160 -100 160 -60 {} +L 4 120 -80 160 -60 {} +L 4 120 -80 160 -100 {} +L 4 140 -120 140 -90 {} +L 4 140 -120 240 -120 {} +L 4 160 -100 240 -100 {} +L 4 160 -60 240 -60 {} +L 4 140 -70 140 -40 {} +L 4 140 -40 240 -40 {} +L 4 240 -40 260 -40 {} +L 4 240 -60 260 -60 {} +L 4 240 -120 260 -120 {} +L 4 240 -100 260 -100 {} +L 4 160 -80 240 -80 {} +L 4 240 -80 260 -80 {} +L 4 20 -120 80 -120 {dash=4} +L 4 80 -80 120 -80 {dash=4} +L 7 80 -260 80 -240 {} +L 7 120 -260 120 -240 {} +L 7 0 -120 20 -120 {} +L 7 120 -20 120 0 {} +L 7 80 -20 80 0 {} +B 5 257.5 -82.5 262.5 -77.5 {name=A dir=in sim_pinnumber=1} +B 5 257.5 -202.5 262.5 -197.5 {name=CS dir=in sim_pinnumber=2} +B 5 77.5 -262.5 82.5 -257.5 {name=DVDD dir=inout sim_pinnumber=3} +B 5 77.5 -2.5 82.5 2.5 {name=DVSS dir=inout +sim_pinnumber=4} +B 5 257.5 -222.5 262.5 -217.5 {name=IE dir=in sim_pinnumber=5} +B 5 257.5 -42.5 262.5 -37.5 {name=OE dir=in sim_pinnumber=6} +B 5 -2.5 -122.5 2.5 -117.5 {name=PAD dir=inout sim_pinnumber=7} +B 5 257.5 -142.5 262.5 -137.5 {name=PD dir=in sim_pinnumber=8} +B 5 257.5 -122.5 262.5 -117.5 {name=PDRV0 dir=in sim_pinnumber=9} +B 5 257.5 -102.5 262.5 -97.5 {name=PDRV1 dir=in sim_pinnumber=10} +B 5 257.5 -162.5 262.5 -157.5 {name=PU dir=in sim_pinnumber=11} +B 5 257.5 -62.5 262.5 -57.5 {name=SL dir=in sim_pinnumber=12} +B 5 117.5 -262.5 122.5 -257.5 {name=VDD dir=inout sim_pinnumber=13} +B 5 117.5 -2.5 122.5 2.5 {name=VSS dir=inout +sim_pinnumber=14} +B 5 257.5 -182.5 262.5 -177.5 {name=Y dir=out sim_pinnumber=15} +P 4 5 240 -240 20 -240 20 -20 240 -20 240 -240 {} +T {@symname} 52.5 -146 0 0 0.3 0.3 {} +T {@name} 195 -252 0 0 0.2 0.2 {} +T {DVSS} 45 -26 2 1 0.2 0.2 {} +T {DVDD} 75 -234 0 1 0.2 0.2 {} +T {VSS} 115 -26 2 1 0.2 0.2 {} +T {VDD} 135 -234 0 1 0.2 0.2 {} +T {PAD} 25 -134 0 0 0.2 0.2 {} +T {Y} 235 -194 0 1 0.2 0.2 {} +T {PU} 235 -174 0 1 0.2 0.2 {} +T {PD} 235 -154 0 1 0.2 0.2 {} +T {IE} 235 -234 0 1 0.2 0.2 {} +T {CS} 235 -214 0 1 0.2 0.2 {} +T {OE} 235 -54 0 1 0.2 0.2 {} +T {SL} 235 -74 0 1 0.2 0.2 {} +T {PDRV0} 235 -134 0 1 0.2 0.2 {} +T {PDRV1} 235 -114 0 1 0.2 0.2 {} +T {A} 235 -94 0 1 0.2 0.2 {} diff --git a/blocks/composite/regulated_cascoded_cmirror/xschem/Chipathon2025_pads/xschem/io_dvdd.sym b/blocks/composite/regulated_cascoded_cmirror/xschem/Chipathon2025_pads/xschem/io_dvdd.sym new file mode 100644 index 00000000..46f4d956 --- /dev/null +++ b/blocks/composite/regulated_cascoded_cmirror/xschem/Chipathon2025_pads/xschem/io_dvdd.sym @@ -0,0 +1,26 @@ +v {xschem version=3.4.7 file_version=1.2} +G {} +K {type=io +format="@spiceprefix@name @pinlist @model" +lvs_format="@spiceprefix@name @pinlist @model" +template="name=IO1 +model=gf180mcu_fd_io__dvdd +spiceprefix=X +" +} +V {} +S {} +E {} +L 7 80 -160 80 -140 {} +L 7 120 -20 120 0 {} +L 7 80 -20 80 0 {} +B 5 77.5 -162.5 82.5 -157.5 {name=DVDD dir=inout sim_pinnumber=1} +B 5 77.5 -2.5 82.5 2.5 {name=DVSS dir=inout +sim_pinnumber=2} +B 5 117.5 -2.5 122.5 2.5 {name=VSS dir=inout sim_pinnumber=3} +P 4 5 180 -140 20 -140 20 -20 180 -20 180 -140 {} +T {@symname} 52.5 -96 0 0 0.3 0.3 {} +T {@name} 135 -152 0 0 0.2 0.2 {} +T {DVSS} 55 -26 2 1 0.2 0.2 {} +T {DVDD} 75 -134 0 1 0.2 0.2 {} +T {VSS} 105 -26 2 1 0.2 0.2 {} diff --git a/blocks/composite/regulated_cascoded_cmirror/xschem/Chipathon2025_pads/xschem/io_dvss.sym b/blocks/composite/regulated_cascoded_cmirror/xschem/Chipathon2025_pads/xschem/io_dvss.sym new file mode 100644 index 00000000..4fcd9c0d --- /dev/null +++ b/blocks/composite/regulated_cascoded_cmirror/xschem/Chipathon2025_pads/xschem/io_dvss.sym @@ -0,0 +1,26 @@ +v {xschem version=3.4.7 file_version=1.2} +G {} +K {type=io +format="@spiceprefix@name @pinlist @model" +lvs_format="@spiceprefix@name @pinlist @model" +template="name=IO1 +model=gf180mcu_fd_io__dvss +spiceprefix=X +" +} +V {} +S {} +E {} +L 7 80 -160 80 -140 {} +L 7 120 -160 120 -140 {} +L 7 80 -20 80 0 {} +B 5 77.5 -162.5 82.5 -157.5 {name=DVDD dir=inout sim_pinnumber=1} +B 5 77.5 -2.5 82.5 2.5 {name=DVSS dir=inout +sim_pinnumber=2} +B 5 117.5 -162.5 122.5 -157.5 {name=VDD dir=inout sim_pinnumber=3} +P 4 5 180 -140 20 -140 20 -20 180 -20 180 -140 {} +T {@symname} 52.5 -96 0 0 0.3 0.3 {} +T {@name} 135 -152 0 0 0.2 0.2 {} +T {DVSS} 55 -26 2 1 0.2 0.2 {} +T {DVDD} 75 -134 0 1 0.2 0.2 {} +T {VDD} 135 -134 0 1 0.2 0.2 {} diff --git a/blocks/composite/regulated_cascoded_cmirror/xschem/Chipathon2025_pads/xschem/io_in_c.sym b/blocks/composite/regulated_cascoded_cmirror/xschem/Chipathon2025_pads/xschem/io_in_c.sym new file mode 100644 index 00000000..148adeba --- /dev/null +++ b/blocks/composite/regulated_cascoded_cmirror/xschem/Chipathon2025_pads/xschem/io_in_c.sym @@ -0,0 +1,80 @@ +v {xschem version=3.4.7 file_version=1.2} +G {} +K {type=io +format="@spiceprefix@name @pinlist @model" +lvs_format="@spiceprefix@name @pinlist @model" +template="name=IO1 +model=gf180mcu_fd_io__in_c +spiceprefix=X +" +} +V {} +S {} +E {} +L 4 70 -100 80 -120 {} +L 4 80 -120 90 -100 {} +L 4 70 -100 90 -100 {} +L 4 80 -100 80 -80 {} +L 4 80 -80 80 -60 {} +L 4 70 -60 90 -60 {} +L 4 80 -40 90 -60 {} +L 4 70 -60 80 -40 {} +L 4 70 -120 90 -120 {} +L 4 70 -40 90 -40 {} +L 4 80 -140 80 -120 {} +L 4 80 -40 80 -20 {} +L 4 20 -80 180 -80 {dash=4} +L 4 180 -100 180 -60 {} +L 4 180 -60 220 -80 {} +L 4 180 -100 220 -80 {} +L 4 220 -80 240 -80 {} +L 4 110 -65 115 -75 {} +L 4 115 -75 125 -55 {} +L 4 125 -55 135 -75 {} +L 4 135 -75 145 -55 {} +L 4 145 -55 150 -65 {} +L 4 150 -65 160 -65 {} +L 4 100 -65 110 -65 {} +L 4 160 -80 160 -65 {} +L 4 100 -90 100 -60 {} +L 4 100 -90 110 -110 {} +L 4 100 -130 100 -110 {} +L 4 80 -130 100 -130 {} +L 4 80 -30 100 -30 {} +L 4 100 -40 100 -30 {} +L 4 100 -60 110 -40 {} +L 4 100 -100 170 -100 {} +L 4 170 -100 170 -60 {} +L 4 170 -60 240 -60 {} +L 4 100 -50 160 -50 {} +L 4 160 -50 160 -40 {} +L 4 160 -40 240 -40 {} +L 4 240 -80 260 -80 {} +L 4 240 -60 260 -60 {} +L 4 240 -40 260 -40 {} +L 7 80 -160 80 -140 {} +L 7 120 -160 120 -140 {} +L 7 0 -80 20 -80 {} +L 7 120 -20 120 0 {} +L 7 80 -20 80 0 {} +B 5 77.5 -162.5 82.5 -157.5 {name=DVDD dir=inout sim_pinnumber=1} +B 5 77.5 -2.5 82.5 2.5 {name=DVSS dir=inout +sim_pinnumber=2} +B 5 -2.5 -82.5 2.5 -77.5 {name=PAD dir=inout sim_pinnumber=3} +B 5 257.5 -42.5 262.5 -37.5 {name=PD dir=in sim_pinnumber=4} +B 5 257.5 -62.5 262.5 -57.5 {name=PU dir=in sim_pinnumber=5} +B 5 117.5 -162.5 122.5 -157.5 {name=VDD dir=inout sim_pinnumber=6} +B 5 117.5 -2.5 122.5 2.5 {name=VSS dir=inout +sim_pinnumber=7} +B 5 257.5 -82.5 262.5 -77.5 {name=Y dir=out sim_pinnumber=8} +P 4 5 240 -140 20 -140 20 -20 240 -20 240 -140 {} +T {@symname} 132.5 -126 0 0 0.3 0.3 {} +T {@name} 195 -152 0 0 0.2 0.2 {} +T {DVSS} 55 -26 2 1 0.2 0.2 {} +T {DVDD} 75 -134 0 1 0.2 0.2 {} +T {VSS} 115 -26 2 1 0.2 0.2 {} +T {VDD} 135 -134 0 1 0.2 0.2 {} +T {PAD} 25 -94 0 0 0.2 0.2 {} +T {Y} 235 -94 0 1 0.2 0.2 {} +T {PU} 235 -74 0 1 0.2 0.2 {} +T {PD} 235 -54 0 1 0.2 0.2 {} diff --git a/blocks/composite/regulated_cascoded_cmirror/xschem/Chipathon2025_pads/xschem/io_in_s.sym b/blocks/composite/regulated_cascoded_cmirror/xschem/Chipathon2025_pads/xschem/io_in_s.sym new file mode 100644 index 00000000..d12a3654 --- /dev/null +++ b/blocks/composite/regulated_cascoded_cmirror/xschem/Chipathon2025_pads/xschem/io_in_s.sym @@ -0,0 +1,80 @@ +v {xschem version=3.4.7 file_version=1.2} +G {} +K {type=io +format="@spiceprefix@name @pinlist @model" +lvs_format="@spiceprefix@name @pinlist @model" +template="name=IO1 +model=gf180mcu_fd_io__in_s +spiceprefix=X +" +} +V {} +S {} +E {} +L 4 70 -100 80 -120 {} +L 4 80 -120 90 -100 {} +L 4 70 -100 90 -100 {} +L 4 80 -100 80 -80 {} +L 4 80 -80 80 -60 {} +L 4 70 -60 90 -60 {} +L 4 80 -40 90 -60 {} +L 4 70 -60 80 -40 {} +L 4 70 -120 90 -120 {} +L 4 70 -40 90 -40 {} +L 4 80 -140 80 -120 {} +L 4 80 -40 80 -20 {} +L 4 20 -80 180 -80 {dash=4} +L 4 180 -100 180 -60 {} +L 4 180 -60 220 -80 {} +L 4 180 -100 220 -80 {} +L 4 220 -80 240 -80 {} +L 4 110 -65 115 -75 {} +L 4 115 -75 125 -55 {} +L 4 125 -55 135 -75 {} +L 4 135 -75 145 -55 {} +L 4 145 -55 150 -65 {} +L 4 150 -65 160 -65 {} +L 4 100 -65 110 -65 {} +L 4 160 -80 160 -65 {} +L 4 100 -90 100 -60 {} +L 4 100 -90 110 -110 {} +L 4 100 -130 100 -110 {} +L 4 80 -130 100 -130 {} +L 4 80 -30 100 -30 {} +L 4 100 -40 100 -30 {} +L 4 100 -60 110 -40 {} +L 4 100 -100 170 -100 {} +L 4 170 -100 170 -60 {} +L 4 170 -60 240 -60 {} +L 4 100 -50 160 -50 {} +L 4 160 -50 160 -40 {} +L 4 160 -40 240 -40 {} +L 4 240 -80 260 -80 {} +L 4 240 -60 260 -60 {} +L 4 240 -40 260 -40 {} +L 7 80 -160 80 -140 {} +L 7 120 -160 120 -140 {} +L 7 0 -80 20 -80 {} +L 7 120 -20 120 0 {} +L 7 80 -20 80 0 {} +B 5 77.5 -162.5 82.5 -157.5 {name=DVDD dir=inout sim_pinnumber=1} +B 5 77.5 -2.5 82.5 2.5 {name=DVSS dir=inout +sim_pinnumber=2} +B 5 -2.5 -82.5 2.5 -77.5 {name=PAD dir=inout sim_pinnumber=3} +B 5 257.5 -42.5 262.5 -37.5 {name=PD dir=in sim_pinnumber=4} +B 5 257.5 -62.5 262.5 -57.5 {name=PU dir=in sim_pinnumber=5} +B 5 117.5 -162.5 122.5 -157.5 {name=VDD dir=inout sim_pinnumber=6} +B 5 117.5 -2.5 122.5 2.5 {name=VSS dir=inout +sim_pinnumber=7} +B 5 257.5 -82.5 262.5 -77.5 {name=Y dir=out sim_pinnumber=8} +P 4 5 240 -140 20 -140 20 -20 240 -20 240 -140 {} +T {@symname} 132.5 -126 0 0 0.3 0.3 {} +T {@name} 195 -152 0 0 0.2 0.2 {} +T {DVSS} 55 -26 2 1 0.2 0.2 {} +T {DVDD} 75 -134 0 1 0.2 0.2 {} +T {VSS} 115 -26 2 1 0.2 0.2 {} +T {VDD} 135 -134 0 1 0.2 0.2 {} +T {PAD} 25 -94 0 0 0.2 0.2 {} +T {Y} 235 -94 0 1 0.2 0.2 {} +T {PU} 235 -74 0 1 0.2 0.2 {} +T {PD} 235 -54 0 1 0.2 0.2 {} diff --git a/blocks/composite/regulated_cascoded_cmirror/xschem/Chipathon2025_pads/xschem/io_secondary_3p3_DC_tb.sch b/blocks/composite/regulated_cascoded_cmirror/xschem/Chipathon2025_pads/xschem/io_secondary_3p3_DC_tb.sch new file mode 100644 index 00000000..05543f82 --- /dev/null +++ b/blocks/composite/regulated_cascoded_cmirror/xschem/Chipathon2025_pads/xschem/io_secondary_3p3_DC_tb.sch @@ -0,0 +1,72 @@ +v {xschem version=3.4.7 file_version=1.2} +G {} +K {} +V {} +S {} +E {} +N 50 -140 50 -100 {lab=GND} +N 150 -140 150 -100 {lab=GND} +N 250 -140 250 -100 {lab=GND} +N 350 -140 350 -100 {lab=GND} +N 50 -240 50 -200 {lab=DVDD} +N 150 -240 150 -200 {lab=VDD} +N 250 -240 250 -200 {lab=DVSS} +N 350 -240 350 -200 {lab=VSS} +N 50 -100 350 -100 {lab=GND} +N 200 -100 200 -80 {lab=GND} +N 450 -140 450 -100 {lab=GND} +N 450 -240 450 -200 {lab=PAD} +N 350 -100 450 -100 {lab=GND} +N 520 -430 550 -430 {lab=PAD} +N 60 -430 90 -430 {lab=to_gate} +N 290 -430 320 -430 {lab=asig} +C {vsource.sym} 50 -170 0 0 {name=V1 value=3 savecurrent=false} +C {vsource.sym} 150 -170 0 0 {name=V2 value=3 savecurrent=false} +C {vsource.sym} 250 -170 0 0 {name=V3 value=0 savecurrent=false} +C {vsource.sym} 350 -170 0 0 {name=V4 value=0 savecurrent=false} +C {lab_wire.sym} 50 -240 0 0 {name=p1 sig_type=std_logic lab=DVDD} +C {lab_wire.sym} 150 -240 0 0 {name=p2 sig_type=std_logic lab=VDD} +C {gnd.sym} 200 -80 0 0 {name=l1 lab=GND} +C {lab_wire.sym} 250 -240 0 0 {name=p3 sig_type=std_logic lab=DVSS} +C {lab_wire.sym} 350 -240 0 0 {name=p4 sig_type=std_logic lab=VSS} +C {devices/code_shown.sym} 0 -660 0 0 {name=DUT only_toplevel=true +format="tcleval( @value )" +value=" +.include "/foss/designs/Chipathon2025_pads/xschem/gf180mcu_fd_io__asig_5p0_extracted.spice" +"} +C {devices/code_shown.sym} 930 -410 0 0 {name=MODELS only_toplevel=true +format="tcleval( @value )" +value=" +.include $::180MCU_MODELS/design.ngspice +.lib $::180MCU_MODELS/sm141064.ngspice typical +.lib $::180MCU_MODELS/sm141064.ngspice diode_typical +.lib $::180MCU_MODELS/sm141064.ngspice res_typical +.lib $::180MCU_MODELS/sm141064.ngspice moscap_typical +"} +C {devices/code_shown.sym} 940 -230 0 0 {name=s1 +only_toplevel=false +value=" + +.control +tran 1n 1u +plot V(PAD)+12 V(ASIG)+6 V(to_gate) +.endc +"} +C {vsource.sym} 450 -170 0 0 {name=V5 value="PWL(0 -10 500n 10 1u -10)" savecurrent=false} +C {lab_wire.sym} 450 -240 0 0 {name=p8 sig_type=std_logic lab=PAD} +C {Chipathon2025_pads/xschem/symbols/io_asig_5p0.sym} 520 -350 0 1 {name=IO1 +model=gf180mcu_fd_io__asig_5p0_extracted +spiceprefix=X +} +C {lab_wire.sym} 440 -510 0 1 {name=p10 sig_type=std_logic lab=DVDD} +C {lab_wire.sym} 440 -350 0 1 {name=p11 sig_type=std_logic lab=DVSS} +C {lab_wire.sym} 400 -510 0 0 {name=p12 sig_type=std_logic lab=VDD} +C {lab_wire.sym} 400 -350 0 0 {name=p13 sig_type=std_logic lab=VSS} +C {lab_wire.sym} 170 -350 0 0 {name=p14 sig_type=std_logic lab=VSS} +C {lab_wire.sym} 170 -510 0 0 {name=p15 sig_type=std_logic lab=VDD} +C {devices/lab_wire.sym} 60 -430 0 0 {name=p16 sig_type=std_logic lab=to_gate} +C {devices/lab_wire.sym} 310 -430 0 0 {name=p17 sig_type=std_logic lab=asig} +C {devices/lab_wire.sym} 550 -430 0 1 {name=p18 sig_type=std_logic lab=PAD} +C {Chipathon2025_pads/xschem/symbols/io_secondary_3p3/io_secondary_3p3.sym} 90 -350 0 0 {name=IO2 +spiceprefix=X +} diff --git a/blocks/composite/regulated_cascoded_cmirror/xschem/Chipathon2025_pads/xschem/io_secondary_AC_tb.sch b/blocks/composite/regulated_cascoded_cmirror/xschem/Chipathon2025_pads/xschem/io_secondary_AC_tb.sch new file mode 100644 index 00000000..b6b07bd3 --- /dev/null +++ b/blocks/composite/regulated_cascoded_cmirror/xschem/Chipathon2025_pads/xschem/io_secondary_AC_tb.sch @@ -0,0 +1,84 @@ +v {xschem version=3.4.7 file_version=1.2} +G {} +K {} +V {} +S {} +E {} +N 60 -100 60 -60 {lab=GND} +N 160 -100 160 -60 {lab=GND} +N 260 -100 260 -60 {lab=GND} +N 360 -100 360 -60 {lab=GND} +N 60 -200 60 -160 {lab=DVDD} +N 160 -200 160 -160 {lab=VDD} +N 260 -200 260 -160 {lab=DVSS} +N 360 -200 360 -160 {lab=VSS} +N 60 -60 360 -60 {lab=GND} +N 210 -60 210 -40 {lab=GND} +N 500 -60 500 -40 { +lab=GND} +N 500 -270 500 -210 { +lab=PAD} +N 500 -150 500 -120 { +lab=#net1} +N 500 -440 500 -270 {lab=PAD} +N 470 -440 500 -440 {lab=PAD} +N 10 -440 40 -440 {lab=to_gate} +N 240 -440 270 -440 {lab=asig} +C {vsource.sym} 60 -130 0 0 {name=V1 value=5 savecurrent=false} +C {vsource.sym} 160 -130 0 0 {name=V2 value=5 savecurrent=false} +C {vsource.sym} 260 -130 0 0 {name=V3 value=0 savecurrent=false} +C {vsource.sym} 360 -130 0 0 {name=V4 value=0 savecurrent=false} +C {lab_wire.sym} 60 -200 0 0 {name=p1 sig_type=std_logic lab=DVDD} +C {lab_wire.sym} 160 -200 0 0 {name=p2 sig_type=std_logic lab=VDD} +C {gnd.sym} 210 -40 0 0 {name=l1 lab=GND} +C {lab_wire.sym} 260 -200 0 0 {name=p3 sig_type=std_logic lab=DVSS} +C {lab_wire.sym} 360 -200 0 0 {name=p4 sig_type=std_logic lab=VSS} +C {devices/vsource.sym} 500 -90 0 0 {name=V5 value="DC 3 AC 1"} +C {devices/lab_wire.sym} 500 -250 0 0 {name=p5 sig_type=std_logic lab=PAD} +C {devices/gnd.sym} 500 -40 0 0 {name=l2 lab=GND} +C {devices/res.sym} 500 -180 0 0 {name=R1 +value=1k +footprint=1206 +device=resistor +m=1} +C {devices/code_shown.sym} 10 -640 0 0 {name=DUT only_toplevel=true +format="tcleval( @value )" +value=" +.include "/foss/designs/Chipathon2025_pads/xschem/gf180mcu_fd_io__asig_5p0_extracted.spice" +"} +C {devices/code_shown.sym} 610 -370 0 0 {name=MODELS only_toplevel=true +format="tcleval( @value )" +value=" +.include $::180MCU_MODELS/design.ngspice +.lib $::180MCU_MODELS/sm141064.ngspice typical +.lib $::180MCU_MODELS/sm141064.ngspice diode_typical +.lib $::180MCU_MODELS/sm141064.ngspice res_typical +.lib $::180MCU_MODELS/sm141064.ngspice moscap_typical +"} +C {devices/code_shown.sym} 620 -190 0 0 {name=s1 +only_toplevel=false +value=" +.ac dec 100 1k 100G +.save all +.control +run +display +plot PAD ASIG +plot vdb(asig) vdb(to_gate) +.endc +"} +C {Chipathon2025_pads/xschem/symbols/io_asig_5p0.sym} 470 -360 0 1 {name=IO1 +model=gf180mcu_fd_io__asig_5p0_extracted +spiceprefix=X +} +C {Chipathon2025_pads/xschem/symbols/io_secondary_5p0/io_secondary_5p0.sym} 40 -360 0 0 {name=IO2 +spiceprefix=X +} +C {lab_wire.sym} 390 -520 0 1 {name=p6 sig_type=std_logic lab=DVDD} +C {lab_wire.sym} 390 -360 0 1 {name=p7 sig_type=std_logic lab=DVSS} +C {lab_wire.sym} 350 -520 0 0 {name=p8 sig_type=std_logic lab=VDD} +C {lab_wire.sym} 350 -360 0 0 {name=p9 sig_type=std_logic lab=VSS} +C {lab_wire.sym} 120 -360 0 0 {name=p10 sig_type=std_logic lab=VSS} +C {lab_wire.sym} 120 -520 0 0 {name=p11 sig_type=std_logic lab=VDD} +C {devices/lab_wire.sym} 10 -440 0 0 {name=p12 sig_type=std_logic lab=to_gate} +C {devices/lab_wire.sym} 260 -440 0 0 {name=p13 sig_type=std_logic lab=asig} diff --git a/blocks/composite/regulated_cascoded_cmirror/xschem/Chipathon2025_pads/xschem/io_secondary_DC_tb.sch b/blocks/composite/regulated_cascoded_cmirror/xschem/Chipathon2025_pads/xschem/io_secondary_DC_tb.sch new file mode 100644 index 00000000..0db7b987 --- /dev/null +++ b/blocks/composite/regulated_cascoded_cmirror/xschem/Chipathon2025_pads/xschem/io_secondary_DC_tb.sch @@ -0,0 +1,72 @@ +v {xschem version=3.4.7 file_version=1.2} +G {} +K {} +V {} +S {} +E {} +N 50 -140 50 -100 {lab=GND} +N 150 -140 150 -100 {lab=GND} +N 250 -140 250 -100 {lab=GND} +N 350 -140 350 -100 {lab=GND} +N 50 -240 50 -200 {lab=DVDD} +N 150 -240 150 -200 {lab=VDD} +N 250 -240 250 -200 {lab=DVSS} +N 350 -240 350 -200 {lab=VSS} +N 50 -100 350 -100 {lab=GND} +N 200 -100 200 -80 {lab=GND} +N 450 -140 450 -100 {lab=GND} +N 450 -240 450 -200 {lab=PAD} +N 350 -100 450 -100 {lab=GND} +N 520 -430 550 -430 {lab=PAD} +N 60 -430 90 -430 {lab=to_gate} +N 290 -430 320 -430 {lab=asig} +C {vsource.sym} 50 -170 0 0 {name=V1 value=3 savecurrent=false} +C {vsource.sym} 150 -170 0 0 {name=V2 value=3 savecurrent=false} +C {vsource.sym} 250 -170 0 0 {name=V3 value=0 savecurrent=false} +C {vsource.sym} 350 -170 0 0 {name=V4 value=0 savecurrent=false} +C {lab_wire.sym} 50 -240 0 0 {name=p1 sig_type=std_logic lab=DVDD} +C {lab_wire.sym} 150 -240 0 0 {name=p2 sig_type=std_logic lab=VDD} +C {gnd.sym} 200 -80 0 0 {name=l1 lab=GND} +C {lab_wire.sym} 250 -240 0 0 {name=p3 sig_type=std_logic lab=DVSS} +C {lab_wire.sym} 350 -240 0 0 {name=p4 sig_type=std_logic lab=VSS} +C {devices/code_shown.sym} 0 -660 0 0 {name=DUT only_toplevel=true +format="tcleval( @value )" +value=" +.include "/foss/designs/Chipathon2025_pads/xschem/gf180mcu_fd_io__asig_5p0_extracted.spice" +"} +C {devices/code_shown.sym} 930 -410 0 0 {name=MODELS only_toplevel=true +format="tcleval( @value )" +value=" +.include $::180MCU_MODELS/design.ngspice +.lib $::180MCU_MODELS/sm141064.ngspice typical +.lib $::180MCU_MODELS/sm141064.ngspice diode_typical +.lib $::180MCU_MODELS/sm141064.ngspice res_typical +.lib $::180MCU_MODELS/sm141064.ngspice moscap_typical +"} +C {devices/code_shown.sym} 940 -230 0 0 {name=s1 +only_toplevel=false +value=" + +.control +tran 1n 1u +plot V(PAD)+12 V(ASIG)+6 V(to_gate) +.endc +"} +C {vsource.sym} 450 -170 0 0 {name=V5 value="PWL(0 -10 500n 10 1u -10)" savecurrent=false} +C {lab_wire.sym} 450 -240 0 0 {name=p8 sig_type=std_logic lab=PAD} +C {Chipathon2025_pads/xschem/symbols/io_asig_5p0.sym} 520 -350 0 1 {name=IO1 +model=gf180mcu_fd_io__asig_5p0_extracted +spiceprefix=X +} +C {Chipathon2025_pads/xschem/symbols/io_secondary_5p0/io_secondary_5p0.sym} 90 -350 0 0 {name=IO2 +spiceprefix=X +} +C {lab_wire.sym} 440 -510 0 1 {name=p10 sig_type=std_logic lab=DVDD} +C {lab_wire.sym} 440 -350 0 1 {name=p11 sig_type=std_logic lab=DVSS} +C {lab_wire.sym} 400 -510 0 0 {name=p12 sig_type=std_logic lab=VDD} +C {lab_wire.sym} 400 -350 0 0 {name=p13 sig_type=std_logic lab=VSS} +C {lab_wire.sym} 170 -350 0 0 {name=p14 sig_type=std_logic lab=VSS} +C {lab_wire.sym} 170 -510 0 0 {name=p15 sig_type=std_logic lab=VDD} +C {devices/lab_wire.sym} 60 -430 0 0 {name=p16 sig_type=std_logic lab=to_gate} +C {devices/lab_wire.sym} 310 -430 0 0 {name=p17 sig_type=std_logic lab=asig} +C {devices/lab_wire.sym} 550 -430 0 1 {name=p18 sig_type=std_logic lab=PAD} diff --git a/blocks/composite/regulated_cascoded_cmirror/xschem/Chipathon2025_pads/xschem/simulation/io_secondary_3p3_DC_tb.spice b/blocks/composite/regulated_cascoded_cmirror/xschem/Chipathon2025_pads/xschem/simulation/io_secondary_3p3_DC_tb.spice new file mode 100644 index 00000000..7ef682a8 --- /dev/null +++ b/blocks/composite/regulated_cascoded_cmirror/xschem/Chipathon2025_pads/xschem/simulation/io_secondary_3p3_DC_tb.spice @@ -0,0 +1,50 @@ +** sch_path: /foss/designs/gLayout-mahowalders/blocks/composite/regulated_cascoded_cmirror/xschem/Chipathon2025_pads/xschem/io_secondary_3p3_DC_tb.sch +**.subckt io_secondary_3p3_DC_tb +V1 DVDD GND 3 +V2 VDD GND 3 +V3 DVSS GND 0 +V4 VSS GND 0 +V5 PAD GND PWL(0 -10 500n 10 1u -10) +XIO1 DVSS DVDD VSS VDD PAD asig gf180mcu_fd_io__asig_5p0_extracted +XIO2 VDD to_gate asig VSS io_secondary_3p3 +**** begin user architecture code + +.include /foss/designs/gLayout-mahowalders/blocks/composite/regulated_cascoded_cmirror/xschem/Chipathon2025_pads/xschem/gf180mcu_fd_io.spice +.include /foss/designs/gLayout-mahowalders/blocks/composite/regulated_cascoded_cmirror/xschem/Chipathon2025_pads/xschem/gf180mcu_fd_io__asig_5p0_extracted.spice + + +.include /foss/pdks/gf180mcuD/libs.tech/ngspice/design.ngspice +.lib /foss/pdks/gf180mcuD/libs.tech/ngspice/sm141064.ngspice typical +.lib /foss/pdks/gf180mcuD/libs.tech/ngspice/sm141064.ngspice diode_typical +.lib /foss/pdks/gf180mcuD/libs.tech/ngspice/sm141064.ngspice res_typical +.lib /foss/pdks/gf180mcuD/libs.tech/ngspice/sm141064.ngspice moscap_typical + + + + +.control +tran 1n 1u +plot V(PAD)+12 V(ASIG)+6 V(to_gate) +.endc + + +**** end user architecture code +**.ends + +* expanding symbol: Chipathon2025_pads/xschem/symbols/io_secondary_3p3/io_secondary_3p3.sym # of pins=4 +** sym_path: /foss/designs/gLayout-mahowalders/blocks/composite/regulated_cascoded_cmirror/xschem/Chipathon2025_pads/xschem/symbols/io_secondary_3p3/io_secondary_3p3.sym +** sch_path: /foss/designs/gLayout-mahowalders/blocks/composite/regulated_cascoded_cmirror/xschem/Chipathon2025_pads/xschem/symbols/io_secondary_3p3/io_secondary_3p3.sch +.subckt io_secondary_3p3 VDD to_gate ASIG3V3 VSS + + +*.iopin VSS +*.iopin VDD +*.iopin to_gate +*.iopin ASIG3V3 +XR1 to_gate ASIG3V3 VDD ppolyf_u r_width=16e-6 r_length=4e-6 m=1 +D2 VSS to_gate diode_nd2ps_03v3 area='10u * 10u ' pj='2*10u + 2*10u ' m=4 +D1 to_gate VDD diode_pd2nw_03v3 area='10u * 10u ' pj='2*10u + 2*10u ' m=4 +.ends + +.GLOBAL GND +.end diff --git a/blocks/composite/regulated_cascoded_cmirror/xschem/Chipathon2025_pads/xschem/symbols/io_asig_5p0.sym b/blocks/composite/regulated_cascoded_cmirror/xschem/Chipathon2025_pads/xschem/symbols/io_asig_5p0.sym new file mode 100644 index 00000000..adf1e960 --- /dev/null +++ b/blocks/composite/regulated_cascoded_cmirror/xschem/Chipathon2025_pads/xschem/symbols/io_asig_5p0.sym @@ -0,0 +1,49 @@ +v {xschem version=3.4.7 file_version=1.2} +G {} +K {type=io +format="@spiceprefix@name @pinlist @model" +lvs_format="@spiceprefix@name @pinlist @model" +template="name=IO1 +model=gf180mcu_fd_io__asig_5p0_extracted +spiceprefix=X +" +} +V {} +S {} +E {} +L 4 70 -100 80 -120 {} +L 4 80 -120 90 -100 {} +L 4 70 -100 90 -100 {} +L 4 80 -100 80 -80 {} +L 4 80 -40 80 -20 {} +L 4 70 -40 90 -40 {} +L 4 70 -40 80 -60 {} +L 4 80 -60 90 -40 {} +L 4 70 -120 90 -120 {} +L 4 70 -60 90 -60 {} +L 4 80 -140 80 -120 {} +L 4 80 -80 80 -60 {} +L 4 20 -80 180 -80 {dash=4} +L 7 80 -160 80 -140 {} +L 7 120 -160 120 -140 {} +L 7 0 -80 20 -80 {} +L 7 180 -80 200 -80 {} +L 7 120 -20 120 0 {} +L 7 80 -20 80 0 {} +B 5 77.5 -2.5 82.5 2.5 {name=DVSS dir=inout +sim_pinnumber=1} +B 5 77.5 -162.5 82.5 -157.5 {name=DVDD dir=inout sim_pinnumber=2} +B 5 117.5 -2.5 122.5 2.5 {name=VSS dir=inout +sim_pinnumber=3} +B 5 117.5 -162.5 122.5 -157.5 {name=VDD dir=inout sim_pinnumber=4} +B 5 -2.5 -82.5 2.5 -77.5 {name=PAD dir=inout sim_pinnumber=5} +B 5 197.5 -82.5 202.5 -77.5 {name=ASIG5V dir=inout sim_pinnumber=6} +P 4 5 180 -140 20 -140 20 -20 180 -20 180 -140 {} +T {@symname} 52.5 -106 0 0 0.3 0.3 {} +T {@name} 135 -152 0 0 0.2 0.2 {} +T {DVSS} 55 -26 2 1 0.2 0.2 {} +T {DVDD} 75 -134 0 1 0.2 0.2 {} +T {VSS} 115 -26 2 1 0.2 0.2 {} +T {VDD} 135 -134 0 1 0.2 0.2 {} +T {PAD} 25 -74 0 0 0.2 0.2 {} +T {ASIG5V} 175 -74 0 1 0.2 0.2 {} diff --git a/blocks/composite/regulated_cascoded_cmirror/xschem/Chipathon2025_pads/xschem/symbols/io_bi_24t.sym b/blocks/composite/regulated_cascoded_cmirror/xschem/Chipathon2025_pads/xschem/symbols/io_bi_24t.sym new file mode 100644 index 00000000..58fa39af --- /dev/null +++ b/blocks/composite/regulated_cascoded_cmirror/xschem/Chipathon2025_pads/xschem/symbols/io_bi_24t.sym @@ -0,0 +1,108 @@ +v {xschem version=3.4.7 file_version=1.2} +G {} +K {type=io +format="@spiceprefix@name @pinlist @model" +lvs_format="@spiceprefix@name @pinlist @model" +template="name=IO1 +model=gf180mcu_fd_io__bi_24t +spiceprefix=X +" +} +V {} +S {} +E {} +L 4 70 -200 80 -220 {} +L 4 80 -220 90 -200 {} +L 4 70 -200 90 -200 {} +L 4 80 -200 80 -180 {} +L 4 80 -180 80 -160 {} +L 4 70 -60 90 -60 {} +L 4 80 -40 90 -60 {} +L 4 70 -60 80 -40 {} +L 4 70 -220 90 -220 {} +L 4 70 -40 90 -40 {} +L 4 80 -240 80 -220 {} +L 4 80 -160 80 -20 {} +L 4 80 -180 180 -180 {dash=4} +L 4 180 -200 180 -160 {} +L 4 180 -160 220 -180 {} +L 4 180 -200 220 -180 {} +L 4 220 -180 240 -180 {} +L 4 110 -165 115 -175 {} +L 4 115 -175 125 -155 {} +L 4 125 -155 135 -175 {} +L 4 135 -175 145 -155 {} +L 4 145 -155 150 -165 {} +L 4 150 -165 160 -165 {} +L 4 100 -165 110 -165 {} +L 4 160 -180 160 -165 {} +L 4 100 -190 100 -160 {} +L 4 100 -190 110 -210 {} +L 4 100 -230 100 -210 {} +L 4 80 -230 100 -230 {} +L 4 80 -30 100 -30 {} +L 4 100 -140 100 -30 {} +L 4 100 -160 110 -140 {} +L 4 100 -200 170 -200 {} +L 4 170 -200 170 -160 {} +L 4 170 -160 240 -160 {} +L 4 100 -150 160 -150 {} +L 4 160 -150 160 -140 {} +L 4 160 -140 240 -140 {} +L 4 240 -180 260 -180 {} +L 4 240 -160 260 -160 {} +L 4 240 -140 260 -140 {} +L 4 190 -220 240 -220 {} +L 4 190 -220 190 -200 {} +L 4 210 -200 240 -200 {} +L 4 210 -200 210 -190 {} +L 4 240 -220 260 -220 {} +L 4 240 -200 260 -200 {} +L 4 160 -100 160 -60 {} +L 4 120 -80 160 -60 {} +L 4 120 -80 160 -100 {} +L 4 160 -60 240 -60 {} +L 4 140 -70 140 -40 {} +L 4 140 -40 240 -40 {} +L 4 240 -40 260 -40 {} +L 4 240 -60 260 -60 {} +L 4 160 -80 240 -80 {} +L 4 240 -80 260 -80 {} +L 4 20 -120 80 -120 {dash=4} +L 4 80 -80 120 -80 {dash=4} +L 7 80 -260 80 -240 {} +L 7 120 -260 120 -240 {} +L 7 0 -120 20 -120 {} +L 7 120 -20 120 0 {} +L 7 80 -20 80 0 {} +B 5 257.5 -82.5 262.5 -77.5 {name=A dir=in sim_pinnumber=1} +B 5 257.5 -202.5 262.5 -197.5 {name=CS dir=in sim_pinnumber=2} +B 5 77.5 -262.5 82.5 -257.5 {name=DVDD dir=inout sim_pinnumber=3} +B 5 77.5 -2.5 82.5 2.5 {name=DVSS dir=inout +sim_pinnumber=4} +B 5 257.5 -222.5 262.5 -217.5 {name=IE dir=in sim_pinnumber=5} +B 5 257.5 -42.5 262.5 -37.5 {name=OE dir=in sim_pinnumber=6} +B 5 -2.5 -122.5 2.5 -117.5 {name=PAD dir=inout sim_pinnumber=7} +B 5 257.5 -142.5 262.5 -137.5 {name=PD dir=in sim_pinnumber=8} +B 5 257.5 -162.5 262.5 -157.5 {name=PU dir=in sim_pinnumber=11} +B 5 257.5 -62.5 262.5 -57.5 {name=SL dir=in sim_pinnumber=12} +B 5 117.5 -262.5 122.5 -257.5 {name=VDD dir=inout sim_pinnumber=13} +B 5 117.5 -2.5 122.5 2.5 {name=VSS dir=inout +sim_pinnumber=14} +B 5 257.5 -182.5 262.5 -177.5 {name=Y dir=out sim_pinnumber=15} +P 4 5 240 -240 20 -240 20 -20 240 -20 240 -240 {} +T {@symname} 52.5 -146 0 0 0.3 0.3 {} +T {@name} 195 -252 0 0 0.2 0.2 {} +T {DVSS} 45 -26 2 1 0.2 0.2 {} +T {DVDD} 75 -234 0 1 0.2 0.2 {} +T {VSS} 115 -26 2 1 0.2 0.2 {} +T {VDD} 135 -234 0 1 0.2 0.2 {} +T {PAD} 25 -134 0 0 0.2 0.2 {} +T {Y} 235 -194 0 1 0.2 0.2 {} +T {PU} 235 -174 0 1 0.2 0.2 {} +T {PD} 235 -154 0 1 0.2 0.2 {} +T {IE} 235 -234 0 1 0.2 0.2 {} +T {CS} 235 -214 0 1 0.2 0.2 {} +T {OE} 235 -54 0 1 0.2 0.2 {} +T {SL} 235 -74 0 1 0.2 0.2 {} +T {A} 235 -94 0 1 0.2 0.2 {} diff --git a/blocks/composite/regulated_cascoded_cmirror/xschem/Chipathon2025_pads/xschem/symbols/io_bi_t.sym b/blocks/composite/regulated_cascoded_cmirror/xschem/Chipathon2025_pads/xschem/symbols/io_bi_t.sym new file mode 100644 index 00000000..0557f7f9 --- /dev/null +++ b/blocks/composite/regulated_cascoded_cmirror/xschem/Chipathon2025_pads/xschem/symbols/io_bi_t.sym @@ -0,0 +1,117 @@ +v {xschem version=3.4.7 file_version=1.2} +G {} +K {type=io +format="@spiceprefix@name @pinlist @model" +lvs_format="@spiceprefix@name @pinlist @model" +template="name=IO1 +model=gf180mcu_fd_io__bi_t +spiceprefix=X +" +} +V {} +S {} +E {} +L 4 70 -200 80 -220 {} +L 4 80 -220 90 -200 {} +L 4 70 -200 90 -200 {} +L 4 80 -200 80 -180 {} +L 4 80 -180 80 -160 {} +L 4 70 -60 90 -60 {} +L 4 80 -40 90 -60 {} +L 4 70 -60 80 -40 {} +L 4 70 -220 90 -220 {} +L 4 70 -40 90 -40 {} +L 4 80 -240 80 -220 {} +L 4 80 -160 80 -20 {} +L 4 80 -180 180 -180 {dash=4} +L 4 180 -200 180 -160 {} +L 4 180 -160 220 -180 {} +L 4 180 -200 220 -180 {} +L 4 220 -180 240 -180 {} +L 4 110 -165 115 -175 {} +L 4 115 -175 125 -155 {} +L 4 125 -155 135 -175 {} +L 4 135 -175 145 -155 {} +L 4 145 -155 150 -165 {} +L 4 150 -165 160 -165 {} +L 4 100 -165 110 -165 {} +L 4 160 -180 160 -165 {} +L 4 100 -190 100 -160 {} +L 4 100 -190 110 -210 {} +L 4 100 -230 100 -210 {} +L 4 80 -230 100 -230 {} +L 4 80 -30 100 -30 {} +L 4 100 -140 100 -30 {} +L 4 100 -160 110 -140 {} +L 4 100 -200 170 -200 {} +L 4 170 -200 170 -160 {} +L 4 170 -160 240 -160 {} +L 4 100 -150 160 -150 {} +L 4 160 -150 160 -140 {} +L 4 160 -140 240 -140 {} +L 4 240 -180 260 -180 {} +L 4 240 -160 260 -160 {} +L 4 240 -140 260 -140 {} +L 4 190 -220 240 -220 {} +L 4 190 -220 190 -200 {} +L 4 210 -200 240 -200 {} +L 4 210 -200 210 -190 {} +L 4 240 -220 260 -220 {} +L 4 240 -200 260 -200 {} +L 4 160 -100 160 -60 {} +L 4 120 -80 160 -60 {} +L 4 120 -80 160 -100 {} +L 4 140 -120 140 -90 {} +L 4 140 -120 240 -120 {} +L 4 160 -100 240 -100 {} +L 4 160 -60 240 -60 {} +L 4 140 -70 140 -40 {} +L 4 140 -40 240 -40 {} +L 4 240 -40 260 -40 {} +L 4 240 -60 260 -60 {} +L 4 240 -120 260 -120 {} +L 4 240 -100 260 -100 {} +L 4 160 -80 240 -80 {} +L 4 240 -80 260 -80 {} +L 4 20 -120 80 -120 {dash=4} +L 4 80 -80 120 -80 {dash=4} +L 7 80 -260 80 -240 {} +L 7 120 -260 120 -240 {} +L 7 0 -120 20 -120 {} +L 7 120 -20 120 0 {} +L 7 80 -20 80 0 {} +B 5 257.5 -82.5 262.5 -77.5 {name=A dir=in sim_pinnumber=1} +B 5 257.5 -202.5 262.5 -197.5 {name=CS dir=in sim_pinnumber=2} +B 5 77.5 -262.5 82.5 -257.5 {name=DVDD dir=inout sim_pinnumber=3} +B 5 77.5 -2.5 82.5 2.5 {name=DVSS dir=inout +sim_pinnumber=4} +B 5 257.5 -222.5 262.5 -217.5 {name=IE dir=in sim_pinnumber=5} +B 5 257.5 -42.5 262.5 -37.5 {name=OE dir=in sim_pinnumber=6} +B 5 -2.5 -122.5 2.5 -117.5 {name=PAD dir=inout sim_pinnumber=7} +B 5 257.5 -142.5 262.5 -137.5 {name=PD dir=in sim_pinnumber=8} +B 5 257.5 -122.5 262.5 -117.5 {name=PDRV0 dir=in sim_pinnumber=9} +B 5 257.5 -102.5 262.5 -97.5 {name=PDRV1 dir=in sim_pinnumber=10} +B 5 257.5 -162.5 262.5 -157.5 {name=PU dir=in sim_pinnumber=11} +B 5 257.5 -62.5 262.5 -57.5 {name=SL dir=in sim_pinnumber=12} +B 5 117.5 -262.5 122.5 -257.5 {name=VDD dir=inout sim_pinnumber=13} +B 5 117.5 -2.5 122.5 2.5 {name=VSS dir=inout +sim_pinnumber=14} +B 5 257.5 -182.5 262.5 -177.5 {name=Y dir=out sim_pinnumber=15} +P 4 5 240 -240 20 -240 20 -20 240 -20 240 -240 {} +T {@symname} 52.5 -146 0 0 0.3 0.3 {} +T {@name} 195 -252 0 0 0.2 0.2 {} +T {DVSS} 45 -26 2 1 0.2 0.2 {} +T {DVDD} 75 -234 0 1 0.2 0.2 {} +T {VSS} 115 -26 2 1 0.2 0.2 {} +T {VDD} 135 -234 0 1 0.2 0.2 {} +T {PAD} 25 -134 0 0 0.2 0.2 {} +T {Y} 235 -194 0 1 0.2 0.2 {} +T {PU} 235 -174 0 1 0.2 0.2 {} +T {PD} 235 -154 0 1 0.2 0.2 {} +T {IE} 235 -234 0 1 0.2 0.2 {} +T {CS} 235 -214 0 1 0.2 0.2 {} +T {OE} 235 -54 0 1 0.2 0.2 {} +T {SL} 235 -74 0 1 0.2 0.2 {} +T {PDRV0} 235 -134 0 1 0.2 0.2 {} +T {PDRV1} 235 -114 0 1 0.2 0.2 {} +T {A} 235 -94 0 1 0.2 0.2 {} diff --git a/blocks/composite/regulated_cascoded_cmirror/xschem/Chipathon2025_pads/xschem/symbols/io_dvdd.sym b/blocks/composite/regulated_cascoded_cmirror/xschem/Chipathon2025_pads/xschem/symbols/io_dvdd.sym new file mode 100644 index 00000000..46f4d956 --- /dev/null +++ b/blocks/composite/regulated_cascoded_cmirror/xschem/Chipathon2025_pads/xschem/symbols/io_dvdd.sym @@ -0,0 +1,26 @@ +v {xschem version=3.4.7 file_version=1.2} +G {} +K {type=io +format="@spiceprefix@name @pinlist @model" +lvs_format="@spiceprefix@name @pinlist @model" +template="name=IO1 +model=gf180mcu_fd_io__dvdd +spiceprefix=X +" +} +V {} +S {} +E {} +L 7 80 -160 80 -140 {} +L 7 120 -20 120 0 {} +L 7 80 -20 80 0 {} +B 5 77.5 -162.5 82.5 -157.5 {name=DVDD dir=inout sim_pinnumber=1} +B 5 77.5 -2.5 82.5 2.5 {name=DVSS dir=inout +sim_pinnumber=2} +B 5 117.5 -2.5 122.5 2.5 {name=VSS dir=inout sim_pinnumber=3} +P 4 5 180 -140 20 -140 20 -20 180 -20 180 -140 {} +T {@symname} 52.5 -96 0 0 0.3 0.3 {} +T {@name} 135 -152 0 0 0.2 0.2 {} +T {DVSS} 55 -26 2 1 0.2 0.2 {} +T {DVDD} 75 -134 0 1 0.2 0.2 {} +T {VSS} 105 -26 2 1 0.2 0.2 {} diff --git a/blocks/composite/regulated_cascoded_cmirror/xschem/Chipathon2025_pads/xschem/symbols/io_dvss.sym b/blocks/composite/regulated_cascoded_cmirror/xschem/Chipathon2025_pads/xschem/symbols/io_dvss.sym new file mode 100644 index 00000000..4fcd9c0d --- /dev/null +++ b/blocks/composite/regulated_cascoded_cmirror/xschem/Chipathon2025_pads/xschem/symbols/io_dvss.sym @@ -0,0 +1,26 @@ +v {xschem version=3.4.7 file_version=1.2} +G {} +K {type=io +format="@spiceprefix@name @pinlist @model" +lvs_format="@spiceprefix@name @pinlist @model" +template="name=IO1 +model=gf180mcu_fd_io__dvss +spiceprefix=X +" +} +V {} +S {} +E {} +L 7 80 -160 80 -140 {} +L 7 120 -160 120 -140 {} +L 7 80 -20 80 0 {} +B 5 77.5 -162.5 82.5 -157.5 {name=DVDD dir=inout sim_pinnumber=1} +B 5 77.5 -2.5 82.5 2.5 {name=DVSS dir=inout +sim_pinnumber=2} +B 5 117.5 -162.5 122.5 -157.5 {name=VDD dir=inout sim_pinnumber=3} +P 4 5 180 -140 20 -140 20 -20 180 -20 180 -140 {} +T {@symname} 52.5 -96 0 0 0.3 0.3 {} +T {@name} 135 -152 0 0 0.2 0.2 {} +T {DVSS} 55 -26 2 1 0.2 0.2 {} +T {DVDD} 75 -134 0 1 0.2 0.2 {} +T {VDD} 135 -134 0 1 0.2 0.2 {} diff --git a/blocks/composite/regulated_cascoded_cmirror/xschem/Chipathon2025_pads/xschem/symbols/io_in_c.sym b/blocks/composite/regulated_cascoded_cmirror/xschem/Chipathon2025_pads/xschem/symbols/io_in_c.sym new file mode 100644 index 00000000..148adeba --- /dev/null +++ b/blocks/composite/regulated_cascoded_cmirror/xschem/Chipathon2025_pads/xschem/symbols/io_in_c.sym @@ -0,0 +1,80 @@ +v {xschem version=3.4.7 file_version=1.2} +G {} +K {type=io +format="@spiceprefix@name @pinlist @model" +lvs_format="@spiceprefix@name @pinlist @model" +template="name=IO1 +model=gf180mcu_fd_io__in_c +spiceprefix=X +" +} +V {} +S {} +E {} +L 4 70 -100 80 -120 {} +L 4 80 -120 90 -100 {} +L 4 70 -100 90 -100 {} +L 4 80 -100 80 -80 {} +L 4 80 -80 80 -60 {} +L 4 70 -60 90 -60 {} +L 4 80 -40 90 -60 {} +L 4 70 -60 80 -40 {} +L 4 70 -120 90 -120 {} +L 4 70 -40 90 -40 {} +L 4 80 -140 80 -120 {} +L 4 80 -40 80 -20 {} +L 4 20 -80 180 -80 {dash=4} +L 4 180 -100 180 -60 {} +L 4 180 -60 220 -80 {} +L 4 180 -100 220 -80 {} +L 4 220 -80 240 -80 {} +L 4 110 -65 115 -75 {} +L 4 115 -75 125 -55 {} +L 4 125 -55 135 -75 {} +L 4 135 -75 145 -55 {} +L 4 145 -55 150 -65 {} +L 4 150 -65 160 -65 {} +L 4 100 -65 110 -65 {} +L 4 160 -80 160 -65 {} +L 4 100 -90 100 -60 {} +L 4 100 -90 110 -110 {} +L 4 100 -130 100 -110 {} +L 4 80 -130 100 -130 {} +L 4 80 -30 100 -30 {} +L 4 100 -40 100 -30 {} +L 4 100 -60 110 -40 {} +L 4 100 -100 170 -100 {} +L 4 170 -100 170 -60 {} +L 4 170 -60 240 -60 {} +L 4 100 -50 160 -50 {} +L 4 160 -50 160 -40 {} +L 4 160 -40 240 -40 {} +L 4 240 -80 260 -80 {} +L 4 240 -60 260 -60 {} +L 4 240 -40 260 -40 {} +L 7 80 -160 80 -140 {} +L 7 120 -160 120 -140 {} +L 7 0 -80 20 -80 {} +L 7 120 -20 120 0 {} +L 7 80 -20 80 0 {} +B 5 77.5 -162.5 82.5 -157.5 {name=DVDD dir=inout sim_pinnumber=1} +B 5 77.5 -2.5 82.5 2.5 {name=DVSS dir=inout +sim_pinnumber=2} +B 5 -2.5 -82.5 2.5 -77.5 {name=PAD dir=inout sim_pinnumber=3} +B 5 257.5 -42.5 262.5 -37.5 {name=PD dir=in sim_pinnumber=4} +B 5 257.5 -62.5 262.5 -57.5 {name=PU dir=in sim_pinnumber=5} +B 5 117.5 -162.5 122.5 -157.5 {name=VDD dir=inout sim_pinnumber=6} +B 5 117.5 -2.5 122.5 2.5 {name=VSS dir=inout +sim_pinnumber=7} +B 5 257.5 -82.5 262.5 -77.5 {name=Y dir=out sim_pinnumber=8} +P 4 5 240 -140 20 -140 20 -20 240 -20 240 -140 {} +T {@symname} 132.5 -126 0 0 0.3 0.3 {} +T {@name} 195 -152 0 0 0.2 0.2 {} +T {DVSS} 55 -26 2 1 0.2 0.2 {} +T {DVDD} 75 -134 0 1 0.2 0.2 {} +T {VSS} 115 -26 2 1 0.2 0.2 {} +T {VDD} 135 -134 0 1 0.2 0.2 {} +T {PAD} 25 -94 0 0 0.2 0.2 {} +T {Y} 235 -94 0 1 0.2 0.2 {} +T {PU} 235 -74 0 1 0.2 0.2 {} +T {PD} 235 -54 0 1 0.2 0.2 {} diff --git a/blocks/composite/regulated_cascoded_cmirror/xschem/Chipathon2025_pads/xschem/symbols/io_in_s.sym b/blocks/composite/regulated_cascoded_cmirror/xschem/Chipathon2025_pads/xschem/symbols/io_in_s.sym new file mode 100644 index 00000000..d12a3654 --- /dev/null +++ b/blocks/composite/regulated_cascoded_cmirror/xschem/Chipathon2025_pads/xschem/symbols/io_in_s.sym @@ -0,0 +1,80 @@ +v {xschem version=3.4.7 file_version=1.2} +G {} +K {type=io +format="@spiceprefix@name @pinlist @model" +lvs_format="@spiceprefix@name @pinlist @model" +template="name=IO1 +model=gf180mcu_fd_io__in_s +spiceprefix=X +" +} +V {} +S {} +E {} +L 4 70 -100 80 -120 {} +L 4 80 -120 90 -100 {} +L 4 70 -100 90 -100 {} +L 4 80 -100 80 -80 {} +L 4 80 -80 80 -60 {} +L 4 70 -60 90 -60 {} +L 4 80 -40 90 -60 {} +L 4 70 -60 80 -40 {} +L 4 70 -120 90 -120 {} +L 4 70 -40 90 -40 {} +L 4 80 -140 80 -120 {} +L 4 80 -40 80 -20 {} +L 4 20 -80 180 -80 {dash=4} +L 4 180 -100 180 -60 {} +L 4 180 -60 220 -80 {} +L 4 180 -100 220 -80 {} +L 4 220 -80 240 -80 {} +L 4 110 -65 115 -75 {} +L 4 115 -75 125 -55 {} +L 4 125 -55 135 -75 {} +L 4 135 -75 145 -55 {} +L 4 145 -55 150 -65 {} +L 4 150 -65 160 -65 {} +L 4 100 -65 110 -65 {} +L 4 160 -80 160 -65 {} +L 4 100 -90 100 -60 {} +L 4 100 -90 110 -110 {} +L 4 100 -130 100 -110 {} +L 4 80 -130 100 -130 {} +L 4 80 -30 100 -30 {} +L 4 100 -40 100 -30 {} +L 4 100 -60 110 -40 {} +L 4 100 -100 170 -100 {} +L 4 170 -100 170 -60 {} +L 4 170 -60 240 -60 {} +L 4 100 -50 160 -50 {} +L 4 160 -50 160 -40 {} +L 4 160 -40 240 -40 {} +L 4 240 -80 260 -80 {} +L 4 240 -60 260 -60 {} +L 4 240 -40 260 -40 {} +L 7 80 -160 80 -140 {} +L 7 120 -160 120 -140 {} +L 7 0 -80 20 -80 {} +L 7 120 -20 120 0 {} +L 7 80 -20 80 0 {} +B 5 77.5 -162.5 82.5 -157.5 {name=DVDD dir=inout sim_pinnumber=1} +B 5 77.5 -2.5 82.5 2.5 {name=DVSS dir=inout +sim_pinnumber=2} +B 5 -2.5 -82.5 2.5 -77.5 {name=PAD dir=inout sim_pinnumber=3} +B 5 257.5 -42.5 262.5 -37.5 {name=PD dir=in sim_pinnumber=4} +B 5 257.5 -62.5 262.5 -57.5 {name=PU dir=in sim_pinnumber=5} +B 5 117.5 -162.5 122.5 -157.5 {name=VDD dir=inout sim_pinnumber=6} +B 5 117.5 -2.5 122.5 2.5 {name=VSS dir=inout +sim_pinnumber=7} +B 5 257.5 -82.5 262.5 -77.5 {name=Y dir=out sim_pinnumber=8} +P 4 5 240 -140 20 -140 20 -20 240 -20 240 -140 {} +T {@symname} 132.5 -126 0 0 0.3 0.3 {} +T {@name} 195 -152 0 0 0.2 0.2 {} +T {DVSS} 55 -26 2 1 0.2 0.2 {} +T {DVDD} 75 -134 0 1 0.2 0.2 {} +T {VSS} 115 -26 2 1 0.2 0.2 {} +T {VDD} 135 -134 0 1 0.2 0.2 {} +T {PAD} 25 -94 0 0 0.2 0.2 {} +T {Y} 235 -94 0 1 0.2 0.2 {} +T {PU} 235 -74 0 1 0.2 0.2 {} +T {PD} 235 -54 0 1 0.2 0.2 {} diff --git a/blocks/composite/regulated_cascoded_cmirror/xschem/Chipathon2025_pads/xschem/symbols/io_secondary_3p3/io_secondary_3p3.sch b/blocks/composite/regulated_cascoded_cmirror/xschem/Chipathon2025_pads/xschem/symbols/io_secondary_3p3/io_secondary_3p3.sch new file mode 100644 index 00000000..845197e6 --- /dev/null +++ b/blocks/composite/regulated_cascoded_cmirror/xschem/Chipathon2025_pads/xschem/symbols/io_secondary_3p3/io_secondary_3p3.sch @@ -0,0 +1,34 @@ +v {xschem version=3.4.7 file_version=1.2} +G {} +K {} +V {} +S {} +E {} +N 220 -120 220 -90 {lab=VDD} +N 220 -30 220 20 {lab=to_gate} +N 220 0 270 0 {lab=to_gate} +N 170 0 220 0 {lab=to_gate} +N 330 -0 380 -0 {lab=ASIG5V} +N 300 -120 300 -20 {lab=VDD} +N 220 -120 300 -120 {lab=VDD} +N 220 80 220 130 {lab=VSS} +C {symbols/ppolyf_u.sym} 300 0 1 0 {name=R1 +W=16e-6 +L=4e-6 +model=ppolyf_u +spiceprefix=X +m=1} +C {iopin.sym} 220 130 2 0 {name=p1 lab=VSS} +C {iopin.sym} 220 -120 2 0 {name=p2 lab=VDD} +C {iopin.sym} 170 0 2 0 {name=p3 lab=to_gate} +C {iopin.sym} 380 0 0 0 {name=p4 lab=ASIG3V3} +C {symbols/diode_nd2ps_03v3.sym} 220 50 2 0 {name=D2 +model=diode_nd2ps_03v3 +r_w=10u +r_l=10u +m=4} +C {symbols/diode_pd2nw_03v3.sym} 220 -60 2 0 {name=D1 +model=diode_pd2nw_03v3 +r_w=10u +r_l=10u +m=4} diff --git a/blocks/composite/regulated_cascoded_cmirror/xschem/Chipathon2025_pads/xschem/symbols/io_secondary_3p3/io_secondary_3p3.sym b/blocks/composite/regulated_cascoded_cmirror/xschem/Chipathon2025_pads/xschem/symbols/io_secondary_3p3/io_secondary_3p3.sym new file mode 100644 index 00000000..67e089d6 --- /dev/null +++ b/blocks/composite/regulated_cascoded_cmirror/xschem/Chipathon2025_pads/xschem/symbols/io_secondary_3p3/io_secondary_3p3.sym @@ -0,0 +1,47 @@ +v {xschem version=3.4.7 file_version=1.2} +G {} +K {type=subcircuit +format="@spiceprefix@name @pinlist @symname" +lvs_format="@spiceprefix@name @pinlist @symname" +template="name=IO1 +spiceprefix=X +" +} +V {} +S {} +E {} +L 4 70 -100 80 -120 {} +L 4 80 -120 90 -100 {} +L 4 70 -100 90 -100 {} +L 4 80 -100 80 -80 {} +L 4 80 -40 80 -20 {} +L 4 70 -40 90 -40 {} +L 4 70 -40 80 -60 {} +L 4 80 -60 90 -40 {} +L 4 70 -120 90 -120 {} +L 4 70 -60 90 -60 {} +L 4 80 -140 80 -120 {} +L 4 80 -80 80 -60 {} +L 4 20 -80 80 -80 {dash=4} +L 4 120 -80 125 -90 {} +L 4 125 -90 135 -70 {} +L 4 135 -70 145 -90 {} +L 4 145 -90 155 -70 {} +L 4 155 -70 160 -80 {} +L 4 160 -80 180 -80 {} +L 4 80 -80 120 -80 {} +L 7 80 -160 80 -140 {} +L 7 0 -80 20 -80 {} +L 7 180 -80 200 -80 {} +L 7 80 -20 80 0 {} +B 5 77.5 -162.5 82.5 -157.5 {name=VDD dir=inout} +B 5 -2.5 -82.5 2.5 -77.5 {name=to_gate dir=inout} +B 5 197.5 -82.5 202.5 -77.5 {name=ASIG3V3 dir=inout} +B 5 77.5 -2.5 82.5 2.5 {name=VSS dir=inout} +P 4 5 180 -140 20 -140 20 -20 180 -20 180 -140 {} +T {VDD} 75 -134 0 1 0.2 0.2 {} +T {to_gate} 25 -66 2 1 0.2 0.2 {} +T {ASIG3V3} 175 -74 0 1 0.2 0.2 {} +T {VSS} 55 -26 2 1 0.2 0.2 {} +T {@symname} 27.5 -101 0 0 0.3 0.3 {} +T {@name} 135 -152 0 0 0.2 0.2 {} diff --git a/blocks/composite/regulated_cascoded_cmirror/xschem/Chipathon2025_pads/xschem/symbols/io_secondary_5p0/io_secondary_5p0.sch b/blocks/composite/regulated_cascoded_cmirror/xschem/Chipathon2025_pads/xschem/symbols/io_secondary_5p0/io_secondary_5p0.sch new file mode 100644 index 00000000..efd48490 --- /dev/null +++ b/blocks/composite/regulated_cascoded_cmirror/xschem/Chipathon2025_pads/xschem/symbols/io_secondary_5p0/io_secondary_5p0.sch @@ -0,0 +1,34 @@ +v {xschem version=3.4.7 file_version=1.2} +G {} +K {} +V {} +S {} +E {} +N 220 -120 220 -90 {lab=VDD} +N 220 -30 220 20 {lab=to_gate} +N 220 0 270 0 {lab=to_gate} +N 170 0 220 0 {lab=to_gate} +N 330 -0 380 -0 {lab=ASIG5V} +N 300 -120 300 -20 {lab=VDD} +N 220 -120 300 -120 {lab=VDD} +N 220 80 220 130 {lab=VSS} +C {symbols/diode_pd2nw_06v0.sym} 220 -60 2 0 {name=D1 +model=diode_pd2nw_06v0 +r_w=10u +r_l=10u +m=4} +C {symbols/ppolyf_u.sym} 300 0 1 0 {name=R1 +W=16e-6 +L=4e-6 +model=ppolyf_u +spiceprefix=X +m=1} +C {iopin.sym} 220 130 2 0 {name=p1 lab=VSS} +C {iopin.sym} 220 -120 2 0 {name=p2 lab=VDD} +C {iopin.sym} 170 0 2 0 {name=p3 lab=to_gate} +C {iopin.sym} 380 0 0 0 {name=p4 lab=ASIG5V} +C {symbols/diode_nd2ps_06v0.sym} 220 50 2 0 {name=D2 +model=diode_nd2ps_06v0 +r_w=10u +r_l=10u +m=4} diff --git a/blocks/composite/regulated_cascoded_cmirror/xschem/Chipathon2025_pads/xschem/symbols/io_secondary_5p0/io_secondary_5p0.sym b/blocks/composite/regulated_cascoded_cmirror/xschem/Chipathon2025_pads/xschem/symbols/io_secondary_5p0/io_secondary_5p0.sym new file mode 100644 index 00000000..393d7357 --- /dev/null +++ b/blocks/composite/regulated_cascoded_cmirror/xschem/Chipathon2025_pads/xschem/symbols/io_secondary_5p0/io_secondary_5p0.sym @@ -0,0 +1,47 @@ +v {xschem version=3.4.7 file_version=1.2} +G {} +K {type=subcircuit +format="@spiceprefix@name @pinlist @symname" +lvs_format="@spiceprefix@name @pinlist @symname" +template="name=IO1 +spiceprefix=X +" +} +V {} +S {} +E {} +L 4 70 -100 80 -120 {} +L 4 80 -120 90 -100 {} +L 4 70 -100 90 -100 {} +L 4 80 -100 80 -80 {} +L 4 80 -40 80 -20 {} +L 4 70 -40 90 -40 {} +L 4 70 -40 80 -60 {} +L 4 80 -60 90 -40 {} +L 4 70 -120 90 -120 {} +L 4 70 -60 90 -60 {} +L 4 80 -140 80 -120 {} +L 4 80 -80 80 -60 {} +L 4 20 -80 80 -80 {dash=4} +L 4 120 -80 125 -90 {} +L 4 125 -90 135 -70 {} +L 4 135 -70 145 -90 {} +L 4 145 -90 155 -70 {} +L 4 155 -70 160 -80 {} +L 4 160 -80 180 -80 {} +L 4 80 -80 120 -80 {} +L 7 80 -160 80 -140 {} +L 7 0 -80 20 -80 {} +L 7 180 -80 200 -80 {} +L 7 80 -20 80 0 {} +B 5 77.5 -162.5 82.5 -157.5 {name=VDD dir=inout} +B 5 -2.5 -82.5 2.5 -77.5 {name=to_gate dir=inout} +B 5 197.5 -82.5 202.5 -77.5 {name=ASIG5V dir=inout} +B 5 77.5 -2.5 82.5 2.5 {name=VSS dir=inout} +P 4 5 180 -140 20 -140 20 -20 180 -20 180 -140 {} +T {VDD} 75 -134 0 1 0.2 0.2 {} +T {to_gate} 25 -66 2 1 0.2 0.2 {} +T {ASIG5V} 175 -74 0 1 0.2 0.2 {} +T {VSS} 55 -26 2 1 0.2 0.2 {} +T {@symname} 27.5 -101 0 0 0.3 0.3 {} +T {@name} 135 -152 0 0 0.2 0.2 {} diff --git a/blocks/composite/regulated_cascoded_cmirror/xschem/Chipathon2025_pads/xschem/test_tieH_L.sch b/blocks/composite/regulated_cascoded_cmirror/xschem/Chipathon2025_pads/xschem/test_tieH_L.sch new file mode 100644 index 00000000..658e2e43 --- /dev/null +++ b/blocks/composite/regulated_cascoded_cmirror/xschem/Chipathon2025_pads/xschem/test_tieH_L.sch @@ -0,0 +1,193 @@ +v {xschem version=3.4.7 file_version=1.2} +G {} +K {} +V {} +S {} +E {} +B 2 1200 -440 1790 20 {flags=graph +y1=-30.547443 +y2=20.010549 +ypos1=0 +ypos2=2 +divy=5 +subdivy=1 +unity=1 +x1=5e-09 +x2=1.05e-07 +divx=5 +subdivx=1 + + + +unitx=1 +dataset=-1 +color="5 4" +node="z_2 +z_1" +sim_type=tran +digital=0 +autoload=1 +rawfile=$netlist_dir/test_tieH_L.raw} +N 650 -130 650 -20 { +lab=G} +N 690 -70 690 -50 { +lab=G} +N 650 -70 690 -70 { +lab=G} +N 690 -100 770 -100 { +lab=Z_1} +N 690 -200 690 -160 { +lab=D} +N 690 -130 710 -130 { +lab=D} +N 710 -170 710 -130 { +lab=D} +N 690 -170 710 -170 { +lab=D} +N 690 10 690 50 { +lab=S} +N 690 -20 710 -20 { +lab=S} +N 710 -20 710 20 { +lab=S} +N 690 20 710 20 { +lab=S} +N 980 -130 980 -20 { +lab=G2} +N 1020 -200 1020 -160 { +lab=D} +N 1020 -130 1040 -130 { +lab=D} +N 1040 -170 1040 -130 { +lab=D} +N 1020 -170 1040 -170 { +lab=D} +N 1020 10 1020 50 { +lab=S} +N 1020 -20 1040 -20 { +lab=S} +N 1040 -20 1040 20 { +lab=S} +N 1020 20 1040 20 { +lab=S} +N 980 -100 1020 -100 { +lab=G2} +N 820 -350 820 -320 { +lab=#net1} +N 820 -450 820 -410 { +lab=#net2} +N 1020 -50 1130 -50 { +lab=Z_2} +N 620 -90 650 -90 { +lab=G} +N 920 -80 980 -80 { +lab=G2} +N 600 -90 620 -90 { +lab=G} +C {devices/code_shown.sym} -50 110 0 0 {name=MODELS only_toplevel=true +format="tcleval( @value )" +value=" +.include $::180MCU_MODELS/design.ngspice +.lib $::180MCU_MODELS/sm141064.ngspice typical +"} +C {devices/lab_pin.sym} 690 50 0 0 {name=l3 sig_type=std_logic lab=S} +C {devices/code_shown.sym} 140 -480 0 0 {name=NGSPICE only_toplevel=true +value=" +.option gmin=1e-15 + +vd d 0 3.3 +vs s 0 0 +vb b 0 0 +.control +save all + + +tran 1p 100n +write test_tieH_L.raw +set appendwrite + +op +write test_tieH_L.raw + +.endc +*.save all +"} +C {symbols/nfet_03v3.sym} 670 -20 0 0 {name=M1 +L=0.6u +W=0.82u +nf=1 +mult=1 +ad="'int((nf+1)/2) * W/nf * 0.18u'" +pd="'2*int((nf+1)/2) * (W/nf + 0.18u)'" +as="'int((nf+2)/2) * W/nf * 0.18u'" +ps="'2*int((nf+2)/2) * (W/nf + 0.18u)'" +nrd="'0.18u / W'" nrs="'0.18u / W'" +sa=0 sb=0 sd=0 +model=nfet_03v3 +spiceprefix=X +} +C {symbols/pfet_03v3.sym} 670 -130 0 0 {name=M2 +L=0.5u +W=1.22u +nf=1 +m=1 +ad="'int((nf+1)/2) * W/nf * 0.18u'" +pd="'2*int((nf+1)/2) * (W/nf + 0.18u)'" +as="'int((nf+2)/2) * W/nf * 0.18u'" +ps="'2*int((nf+2)/2) * (W/nf + 0.18u)'" +nrd="'0.18u / W'" nrs="'0.18u / W'" +sa=0 sb=0 sd=0 +model=pfet_03v3 +spiceprefix=X +} +C {devices/lab_pin.sym} 690 -200 0 0 {name=l5 sig_type=std_logic lab=D} +C {devices/lab_pin.sym} 770 -100 0 1 {name=l1 sig_type=std_logic lab=Z_1} +C {devices/launcher.sym} 480 -390 0 0 {name=h1 +descr="Annotate OP" +tclcommand="set show_hidden_texts 1; xschem annotate_op"} +C {devices/lab_pin.sym} 1020 50 0 0 {name=l4 sig_type=std_logic lab=S} +C {symbols/nfet_03v3.sym} 1000 -20 0 0 {name=M3 +L=0.5u +W=1.22u +nf=1 +mult=1 +ad="'int((nf+1)/2) * W/nf * 0.18u'" +pd="'2*int((nf+1)/2) * (W/nf + 0.18u)'" +as="'int((nf+2)/2) * W/nf * 0.18u'" +ps="'2*int((nf+2)/2) * (W/nf + 0.18u)'" +nrd="'0.18u / W'" nrs="'0.18u / W'" +sa=0 sb=0 sd=0 +model=nfet_03v3 +spiceprefix=X +} +C {symbols/pfet_03v3.sym} 1000 -130 0 0 {name=M4 +L=0.5u +W=1.22u +nf=1 +m=1 +ad="'int((nf+1)/2) * W/nf * 0.18u'" +pd="'2*int((nf+1)/2) * (W/nf + 0.18u)'" +as="'int((nf+2)/2) * W/nf * 0.18u'" +ps="'2*int((nf+2)/2) * (W/nf + 0.18u)'" +nrd="'0.18u / W'" nrs="'0.18u / W'" +sa=0 sb=0 sd=0 +model=pfet_03v3 +spiceprefix=X +} +C {devices/lab_pin.sym} 1020 -200 0 0 {name=l6 sig_type=std_logic lab=D} +C {devices/launcher.sym} 1255 -485 0 0 {name=h2 +descr="Click left mouse button here with control key +pressed to load/unload waveforms in graph." +tclcommand=" +xschem raw_read $netlist_dir/[file tail [file rootname [xschem get current_name]]].raw +" +} +C {devices/vsource.sym} 820 -380 0 0 {name=V1 value="pulse(0 3.3 0 20n 20n 10u 100u)" +spice_ignore=true} +C {devices/lab_pin.sym} 820 -450 0 0 {name=l9 sig_type=std_logic lab=D +spice_ignore=true} +C {devices/lab_pin.sym} 820 -320 0 0 {name=l10 sig_type=std_logic lab=S +spice_ignore=true} +C {devices/lab_pin.sym} 1130 -50 0 1 {name=l7 sig_type=std_logic lab=Z_2} +C {devices/lab_pin.sym} 600 -90 0 0 {name=l2 sig_type=std_logic lab=G} +C {devices/lab_pin.sym} 920 -80 0 0 {name=l8 sig_type=std_logic lab=G2} diff --git a/blocks/composite/regulated_cascoded_cmirror/xschem/Chipathon2025_pads/xschem/tieH.sch b/blocks/composite/regulated_cascoded_cmirror/xschem/Chipathon2025_pads/xschem/tieH.sch new file mode 100644 index 00000000..127072ee --- /dev/null +++ b/blocks/composite/regulated_cascoded_cmirror/xschem/Chipathon2025_pads/xschem/tieH.sch @@ -0,0 +1,51 @@ +v {xschem version=3.4.7 file_version=1.2} +G {} +K {} +V {} +S {} +E {} +N -40 30 -40 80 {lab=#net1} +N -40 30 0 30 {lab=#net1} +N 0 30 0 50 {lab=#net1} +N 0 -50 0 30 {lab=#net1} +N 40 -20 40 10 {lab=TIEH} +N 40 10 100 10 {lab=TIEH} +N 40 -110 40 -80 {lab=VDD} +N 40 -50 50 -50 {lab=VDD} +N 50 -110 50 -50 {lab=VDD} +N 40 -110 50 -110 {lab=VDD} +N 0 80 10 80 {lab=VSS} +N 10 80 10 130 {lab=VSS} +N 0 130 10 130 {lab=VSS} +N 0 110 0 130 {lab=VSS} +C {symbols/pfet_05v0.sym} 20 -50 0 0 {name=M1 +L=0.55u +W=2u +nf=1 +m=1 +ad="'int((nf+1)/2) * W/nf * 0.18u'" +pd="'2*int((nf+1)/2) * (W/nf + 0.18u)'" +as="'int((nf+2)/2) * W/nf * 0.18u'" +ps="'2*int((nf+2)/2) * (W/nf + 0.18u)'" +nrd="'0.18u / W'" nrs="'0.18u / W'" +sa=0 sb=0 sd=0 +model=pfet_05v0 +spiceprefix=X +} +C {symbols/nfet_05v0.sym} -20 80 0 0 {name=M2 +L=0.70u +W=1u +nf=1 +m=1 +ad="'int((nf+1)/2) * W/nf * 0.18u'" +pd="'2*int((nf+1)/2) * (W/nf + 0.18u)'" +as="'int((nf+2)/2) * W/nf * 0.18u'" +ps="'2*int((nf+2)/2) * (W/nf + 0.18u)'" +nrd="'0.18u / W'" nrs="'0.18u / W'" +sa=0 sb=0 sd=0 +model=nfet_05v0 +spiceprefix=X +} +C {iopin.sym} 0 130 2 0 {name=p1 lab=VSS} +C {iopin.sym} 50 -110 0 0 {name=p2 lab=VDD} +C {iopin.sym} 100 10 0 0 {name=p3 lab=TIEH} diff --git a/blocks/composite/regulated_cascoded_cmirror/xschem/Chipathon2025_pads/xschem/tieH.sym b/blocks/composite/regulated_cascoded_cmirror/xschem/Chipathon2025_pads/xschem/tieH.sym new file mode 100644 index 00000000..b98137b8 --- /dev/null +++ b/blocks/composite/regulated_cascoded_cmirror/xschem/Chipathon2025_pads/xschem/tieH.sym @@ -0,0 +1,25 @@ +v {xschem version=3.4.7 file_version=1.2} +G {} +K {type=subcircuit +format="@name @pinlist @symname" +template="name=x1" +} +V {} +S {} +E {} +L 4 0 -50 0 0 {} +L 4 -10 -30 0 -50 {} +L 4 -10 -30 10 -30 {} +L 4 0 -50 10 -30 {} +L 7 -70 -80 -50 -80 {} +L 7 0 -100 0 -80 {} +L 7 0 30 0 50 {} +B 5 -72.5 -82.5 -67.5 -77.5 {name=TIEH dir=inout} +B 5 -2.5 -102.5 2.5 -97.5 {name=VDD dir=inout} +B 5 -2.5 47.5 2.5 52.5 {name=VSS dir=inout} +P 4 5 40 -100 -70 -100 -70 50 40 50 40 -100 {} +T {TIEH} -45 -76 2 1 0.2 0.2 {} +T {@symname} -44 -46 1 0 0.3 0.3 {} +T {@name} 5 -122 0 0 0.2 0.2 {} +T {VDD} 15 -74 0 1 0.2 0.2 {} +T {VSS} -5 24 2 1 0.2 0.2 {} diff --git a/blocks/composite/regulated_cascoded_cmirror/xschem/Chipathon2025_pads/xschem/tieL.sch b/blocks/composite/regulated_cascoded_cmirror/xschem/Chipathon2025_pads/xschem/tieL.sch new file mode 100644 index 00000000..4d201573 --- /dev/null +++ b/blocks/composite/regulated_cascoded_cmirror/xschem/Chipathon2025_pads/xschem/tieL.sch @@ -0,0 +1,51 @@ +v {xschem version=3.4.7 file_version=1.2} +G {} +K {} +V {} +S {} +E {} +N 0 30 0 80 {lab=#net1} +N 40 30 40 50 {lab=TIEL} +N -40 -60 -40 -10 {lab=#net1} +N 40 30 100 30 {lab=TIEL} +N 0 -120 0 -90 {lab=VDD} +N 0 -60 10 -60 {lab=VDD} +N 10 -120 10 -60 {lab=VDD} +N 0 -120 10 -120 {lab=VDD} +N 40 80 50 80 {lab=VSS} +N 50 80 50 130 {lab=VSS} +N 40 130 50 130 {lab=VSS} +N 40 110 40 130 {lab=VSS} +N 0 -30 0 30 {lab=#net1} +N -40 -10 0 -10 {lab=#net1} +C {symbols/pfet_05v0.sym} -20 -60 0 0 {name=M3 +L=0.55u +W=2u +nf=1 +m=1 +ad="'int((nf+1)/2) * W/nf * 0.18u'" +pd="'2*int((nf+1)/2) * (W/nf + 0.18u)'" +as="'int((nf+2)/2) * W/nf * 0.18u'" +ps="'2*int((nf+2)/2) * (W/nf + 0.18u)'" +nrd="'0.18u / W'" nrs="'0.18u / W'" +sa=0 sb=0 sd=0 +model=pfet_05v0 +spiceprefix=X +} +C {symbols/nfet_05v0.sym} 20 80 0 0 {name=M4 +L=0.70u +W=1u +nf=1 +m=1 +ad="'int((nf+1)/2) * W/nf * 0.18u'" +pd="'2*int((nf+1)/2) * (W/nf + 0.18u)'" +as="'int((nf+2)/2) * W/nf * 0.18u'" +ps="'2*int((nf+2)/2) * (W/nf + 0.18u)'" +nrd="'0.18u / W'" nrs="'0.18u / W'" +sa=0 sb=0 sd=0 +model=nfet_05v0 +spiceprefix=X +} +C {iopin.sym} 40 130 2 0 {name=p4 lab=VSS} +C {iopin.sym} 10 -120 0 0 {name=p5 lab=VDD} +C {iopin.sym} 100 30 0 0 {name=p6 lab=TIEL} diff --git a/blocks/composite/regulated_cascoded_cmirror/xschem/Chipathon2025_pads/xschem/tieL.sym b/blocks/composite/regulated_cascoded_cmirror/xschem/Chipathon2025_pads/xschem/tieL.sym new file mode 100644 index 00000000..5a299236 --- /dev/null +++ b/blocks/composite/regulated_cascoded_cmirror/xschem/Chipathon2025_pads/xschem/tieL.sym @@ -0,0 +1,25 @@ +v {xschem version=3.4.7 file_version=1.2} +G {} +K {type=subcircuit +format="@name @pinlist @symname" +template="name=x1" +} +V {} +S {} +E {} +L 4 0 -30 0 20 {} +L 4 0 20 10 0 {} +L 4 -10 0 10 0 {} +L 4 -10 0 0 20 {} +L 7 0 -80 0 -60 {} +L 7 -70 50 -50 50 {} +L 7 0 50 0 70 {} +B 5 -2.5 -82.5 2.5 -77.5 {name=VDD dir=inout} +B 5 -72.5 47.5 -67.5 52.5 {name=TIEL dir=inout} +B 5 -2.5 67.5 2.5 72.5 {name=VSS dir=inout} +P 4 5 40 -80 -70 -80 -70 70 40 70 40 -80 {} +T {@symname} -34 -66 1 0 0.3 0.3 {} +T {@name} 5 -102 0 0 0.2 0.2 {} +T {VDD} 15 -54 0 1 0.2 0.2 {} +T {TIEL} -45 54 2 1 0.2 0.2 {} +T {VSS} -5 44 2 1 0.2 0.2 {} diff --git a/blocks/composite/regulated_cascoded_cmirror/xschem/Figure2_ibas_1u.png b/blocks/composite/regulated_cascoded_cmirror/xschem/Figure2_ibas_1u.png new file mode 100644 index 00000000..9b382795 Binary files /dev/null and b/blocks/composite/regulated_cascoded_cmirror/xschem/Figure2_ibas_1u.png differ diff --git a/blocks/composite/regulated_cascoded_cmirror/xschem/Figure_ibas_1u.png b/blocks/composite/regulated_cascoded_cmirror/xschem/Figure_ibas_1u.png new file mode 100644 index 00000000..a460d58b Binary files /dev/null and b/blocks/composite/regulated_cascoded_cmirror/xschem/Figure_ibas_1u.png differ diff --git a/blocks/composite/regulated_cascoded_cmirror/xschem/LVS/int_top_lvs.gds b/blocks/composite/regulated_cascoded_cmirror/xschem/LVS/int_top_lvs.gds new file mode 100644 index 00000000..42de3c92 Binary files /dev/null and b/blocks/composite/regulated_cascoded_cmirror/xschem/LVS/int_top_lvs.gds differ diff --git a/blocks/composite/regulated_cascoded_cmirror/xschem/LVS/int_top_lvs.sch b/blocks/composite/regulated_cascoded_cmirror/xschem/LVS/int_top_lvs.sch new file mode 100644 index 00000000..a673912a --- /dev/null +++ b/blocks/composite/regulated_cascoded_cmirror/xschem/LVS/int_top_lvs.sch @@ -0,0 +1,94 @@ +v {xschem version=3.4.7 file_version=1.2} +G {} +K {} +V {} +S {} +E {} +N 640 -410 970 -410 {lab=ENA} +N 1210 -220 1210 -210 {lab=VSS} +N 1210 -470 1210 -440 {lab=VDD} +N 730 -370 970 -370 {lab=VIN_INT} +N 850 -320 970 -320 {lab=VBIAS_INT} +N 320 -1180 500 -1180 {lab=PU} +N 590 -1130 850 -1130 {lab=PD} +N 380 -1160 380 -1150 {lab=PD} +N 320 -1160 380 -1160 {lab=PD} +N 780 -1140 780 -1100 {lab=VSS} +N 920 -1000 920 -980 {lab=VSS} +N 920 -1180 920 -1150 {lab=VDD} +N 780 -1310 780 -1290 {lab=VDD} +N 1210 -210 1210 -190 {lab=VSS} +N -110 -870 50 -870 {lab=VIN} +N -100 -620 60 -620 {lab=VBIAS} +N 250 -870 380 -870 {lab=VIN} +N 260 -620 370 -620 {lab=VBIAS} +N 140 -1200 320 -1200 {lab=EN} +N 1410 -390 1500 -390 {lab=VCM_OUT} +N 1500 -410 1500 -390 {lab=VCM_OUT} +N 1500 -410 1570 -410 {lab=VCM_OUT} +N 1410 -370 1570 -370 {lab=BCM_OUT} +N 1410 -350 1500 -350 {lab=CCM_OUT} +N 1500 -350 1500 -330 {lab=CCM_OUT} +N 1500 -330 1570 -330 {lab=CCM_OUT} +N 10 -280 90 -280 {lab=VDD} +N 270 -280 360 -280 {lab=VSS} +N 380 -1290 380 -1200 {lab=EN} +N 580 -1290 610 -1290 {lab=ENA} +N 320 -1200 380 -1200 {lab=EN} +N 500 -1160 710 -1160 {lab=PU} +N 500 -1180 500 -1160 {lab=PU} +N 380 -1130 590 -1130 {lab=PD} +N 380 -1150 380 -1130 {lab=PD} +N 1410 -410 1480 -410 {lab=VIN_OUT} +N 1480 -440 1480 -410 {lab=VIN_OUT} +N 1480 -440 1570 -440 {lab=VIN_OUT} +N 60 -620 260 -620 {lab=VBIAS} +N 50 -870 250 -870 {lab=VIN} +N 380 -870 420 -870 {lab=VIN} +N 370 -620 420 -620 {lab=VBIAS} +N 620 -870 660 -870 {lab=VIN_INT} +N 620 -620 730 -620 {lab=VBIAS_INT} +C {title.sym} 190 -90 0 0 {name=l1 author="Quentin Halbach and Sapta"} +C {ipin.sym} 140 -1200 0 0 {name=p120 lab=EN} +C {lab_pin.sym} 920 -1180 2 1 {name=p108 lab=VDD} +C {lab_pin.sym} 780 -1310 2 1 {name=p111 lab=VDD} +C {lab_pin.sym} 920 -980 2 1 {name=p164 lab=VSS} +C {iopin.sym} 90 -280 0 0 {name=p92 lab=VDD} +C {iopin.sym} 360 -280 0 0 {name=p51 lab=VSS} +C {Chipathon2025_pads/xschem/tieH.sym} 920 -1050 0 0 {name=x2} +C {Chipathon2025_pads/xschem/tieL.sym} 780 -1210 0 0 {name=x3} +C {lab_pin.sym} 610 -1290 0 1 {name=p1 lab=ENA} +C {lab_pin.sym} 780 -1100 2 1 {name=p2 lab=VSS} +C {lab_pin.sym} 1210 -470 2 1 {name=p3 lab=VDD} +C {lab_pin.sym} 1210 -190 2 1 {name=p4 lab=VSS} +C {lab_pin.sym} 640 -410 2 1 {name=p5 lab=ENA} +C {ipin.sym} -110 -870 0 0 {name=p6 lab=VIN} +C {ipin.sym} -100 -620 0 0 {name=p7 lab=VBIAS} +C {lab_pin.sym} 660 -870 0 1 {name=p8 lab=VIN_INT} +C {lab_pin.sym} 730 -620 0 1 {name=p9 lab=VBIAS_INT} +C {lab_pin.sym} 730 -370 2 1 {name=p10 lab=VIN_INT} +C {lab_pin.sym} 850 -320 2 1 {name=p11 lab=VBIAS_INT} +C {opin.sym} 1570 -410 0 0 {name=p24 lab=VCM_OUT} +C {opin.sym} 1570 -370 0 0 {name=p20 lab=BCM_OUT} +C {opin.sym} 1570 -330 0 0 {name=p28 lab=CCM_OUT} +C {lab_pin.sym} 10 -280 2 1 {name=p41 lab=VDD} +C {lab_pin.sym} 270 -280 2 1 {name=p43 lab=VSS} +C {Chipathon2025_pads/xschem/symbols/io_secondary_5p0/io_secondary_5p0.sym} 580 -1210 0 1 {name=IO8 +spiceprefix=X +} +C {lab_pin.sym} 500 -1370 2 1 {name=p49 lab=VDD} +C {lab_pin.sym} 500 -1210 2 1 {name=p50 lab=VSS} +C {opin.sym} 1570 -440 0 0 {name=p54 lab=VIN_OUT} +C {top_level.sym} 1210 -330 0 0 {name=x1} +C {Chipathon2025_pads/xschem/symbols/io_secondary_5p0/io_secondary_5p0.sym} 620 -790 0 1 {name=IO1 +spiceprefix=X +} +C {lab_pin.sym} 540 -950 2 1 {name=p12 lab=VDD} +C {lab_pin.sym} 540 -790 2 1 {name=p13 lab=VSS} +C {Chipathon2025_pads/xschem/symbols/io_secondary_5p0/io_secondary_5p0.sym} 620 -540 0 1 {name=IO2 +spiceprefix=X +} +C {lab_pin.sym} 540 -700 2 1 {name=p14 lab=VDD} +C {lab_pin.sym} 540 -540 2 1 {name=p15 lab=VSS} +C {ipin.sym} 320 -1180 0 0 {name=p16 lab=PU} +C {ipin.sym} 320 -1160 0 0 {name=p17 lab=PD} diff --git a/blocks/composite/regulated_cascoded_cmirror/xschem/LVS/int_top_lvs.spice b/blocks/composite/regulated_cascoded_cmirror/xschem/LVS/int_top_lvs.spice new file mode 100644 index 00000000..3f435c5a --- /dev/null +++ b/blocks/composite/regulated_cascoded_cmirror/xschem/LVS/int_top_lvs.spice @@ -0,0 +1,220 @@ +** sch_path: /foss/designs/gLayout-mahowalders/blocks/composite/regulated_cascoded_cmirror/xschem/int_top_lvs.sch +.SUBCKT TOP EN VDD VSS VIN VBIAS VCM_OUT BCM_OUT CCM_OUT VIN_OUT PU PD +*.ipin EN +*.iopin VDD +*.iopin VSS +*.ipin VIN +*.ipin VBIAS +*.opin VCM_OUT +*.opin BCM_OUT +*.opin CCM_OUT +*.opin VIN_OUT +*.ipin PU +*.ipin PD +x2 PD VDD VSS tieH +x3 VDD PU VSS tieL +XIO8 VDD ENA EN VSS io_secondary_5p0 +x1 VDD ENA VIN_INT VCM_OUT BCM_OUT CCM_OUT VBIAS_INT VSS VIN_OUT top_level +XIO1 VDD VIN_INT VIN VSS io_secondary_5p0 +XIO2 VDD VBIAS_INT VBIAS VSS io_secondary_5p0 +**.ends + +* expanding symbol: Chipathon2025_pads/xschem/tieH.sym # of pins=3 +** sym_path: /foss/designs/gLayout-mahowalders/blocks/composite/regulated_cascoded_cmirror/xschem/Chipathon2025_pads/xschem/tieH.sym +** sch_path: /foss/designs/gLayout-mahowalders/blocks/composite/regulated_cascoded_cmirror/xschem/Chipathon2025_pads/xschem/tieH.sch +.subckt tieH TIEH VDD VSS +*.iopin VSS +*.iopin VDD +*.iopin TIEH +XM1 TIEH net1 VDD VDD pfet_05v0 L=0.55u W=2u nf=1 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=1 +XM2 net1 net1 VSS VSS nfet_05v0 L=0.70u W=1u nf=1 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=1 +.ends + + +* expanding symbol: Chipathon2025_pads/xschem/tieL.sym # of pins=3 +** sym_path: /foss/designs/gLayout-mahowalders/blocks/composite/regulated_cascoded_cmirror/xschem/Chipathon2025_pads/xschem/tieL.sym +** sch_path: /foss/designs/gLayout-mahowalders/blocks/composite/regulated_cascoded_cmirror/xschem/Chipathon2025_pads/xschem/tieL.sch +.subckt tieL VDD TIEL VSS +*.iopin VSS +*.iopin VDD +*.iopin TIEL +XM3 net1 net1 VDD VDD pfet_05v0 L=0.55u W=2u nf=1 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=1 +XM4 TIEL net1 VSS VSS nfet_05v0 L=0.70u W=1u nf=1 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=1 +.ends + + +* expanding symbol: Chipathon2025_pads/xschem/symbols/io_secondary_5p0/io_secondary_5p0.sym # of pins=4 +** sym_path: /foss/designs/gLayout-mahowalders/blocks/composite/regulated_cascoded_cmirror/xschem/Chipathon2025_pads/xschem/symbols/io_secondary_5p0/io_secondary_5p0.sym +** sch_path: /foss/designs/gLayout-mahowalders/blocks/composite/regulated_cascoded_cmirror/xschem/Chipathon2025_pads/xschem/symbols/io_secondary_5p0/io_secondary_5p0.sch +.subckt io_secondary_5p0 VDD to_gate ASIG5V VSS + + +*.iopin VSS +*.iopin VDD +*.iopin to_gate +*.iopin ASIG5V +D1 to_gate VDD diode_pd2nw_06v0 area='10u * 10u ' pj='2*10u + 2*10u ' m=4 +XR1 to_gate ASIG5V VDD ppolyf_u r_width=16e-6 r_length=4e-6 m=1 +D2 VSS to_gate diode_nd2ps_06v0 area='10u * 10u ' pj='2*10u + 2*10u ' m=4 +.ends + + +* expanding symbol: top_level.sym # of pins=9 +** sym_path: /foss/designs/gLayout-mahowalders/blocks/composite/regulated_cascoded_cmirror/xschem/top_level.sym +** sch_path: /foss/designs/gLayout-mahowalders/blocks/composite/regulated_cascoded_cmirror/xschem/top_level.sch +.subckt top_level VDD EN V_IN V_OUT_VCM V_OUT_BCM V_OUT_CCM V_AUX_CCM VSS V_OUT_VIN +*.iopin VSS +*.ipin V_AUX_CCM +*.iopin VDD +*.opin V_OUT_VCM +*.opin V_OUT_BCM +*.opin V_OUT_CCM +*.ipin V_IN +*.ipin EN +*.opin V_OUT_VIN +XM1 net1 net1 VDD VDD pfet_03v3 L=2.0u W=10.0u nf=1 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=1 +XM2 V_IN V_IN net1 VDD pfet_03v3 L=2.0u W=10.0u nf=1 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=1 +XM3 net2 net1 VDD VDD pfet_03v3 L=2.0u W=10.0u nf=1 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=1 +XM4 net3 V_IN net2 VDD pfet_03v3 L=2.0u W=10.0u nf=1 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=1 +XM5 net7 net1 VDD VDD pfet_03v3 L=2.0u W=10.0u nf=1 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=1 +XM6 net4 V_IN net7 VDD pfet_03v3 L=2.0u W=10.0u nf=1 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=1 +XM7 net6 net1 VDD VDD pfet_03v3 L=2.0u W=10.0u nf=1 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=1 +XM8 net5 V_IN net6 VDD pfet_03v3 L=2.0u W=10.0u nf=1 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=1 +XM14 net1 EN VDD VDD pfet_03v3 L=2.0u W=10.0u nf=1 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=1 +XM18 net1 EN VDD VDD pfet_03v3 L=2.0u W=10.0u nf=1 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=1 +XM15 net1 EN VDD VDD pfet_03v3 L=2.0u W=10.0u nf=1 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=1 +x1 net3 V_OUT_VCM VSS vanilla_cm +x2 V_OUT_BCM net4 VSS biased_cm +x3 V_OUT_CCM net8 net5 VSS cascode_cm +x4 VDD EN V_AUX_CCM net8 VSS bias +XM9 net9 net1 VDD VDD pfet_03v3 L=2.0u W=10.0u nf=1 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=1 +XM10 V_OUT_VIN V_IN net9 VDD pfet_03v3 L=2.0u W=10.0u nf=1 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=1 +XM11 net1 EN VDD VDD pfet_03v3 L=2.0u W=10.0u nf=1 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=1 +XM12 VDD VDD VDD VDD pfet_03v3 L=2.0u W=10.0u nf=1 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=6 +.ends + + +* expanding symbol: vanilla_cm.sym # of pins=3 +** sym_path: /foss/designs/gLayout-mahowalders/blocks/composite/regulated_cascoded_cmirror/xschem/vanilla_cm.sym +** sch_path: /foss/designs/gLayout-mahowalders/blocks/composite/regulated_cascoded_cmirror/xschem/vanilla_cm.sch +.subckt vanilla_cm v_in v_out vss +*.ipin v_in +*.iopin vss +*.opin v_out +XM1 v_out v_in vss vss nfet_03v3 L=1u W=4u nf=1 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=1 +XM2 v_in v_in vss vss nfet_03v3 L=1u W=4u nf=1 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=1 +XM3 vss vss vss vss nfet_03v3 L=1u W=4u nf=1 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=2 +.ends + + +* expanding symbol: biased_cm.sym # of pins=3 +** sym_path: /foss/designs/gLayout-mahowalders/blocks/composite/regulated_cascoded_cmirror/xschem/biased_cm.sym +** sch_path: /foss/designs/gLayout-mahowalders/blocks/composite/regulated_cascoded_cmirror/xschem/biased_cm.sch +.subckt biased_cm v_out v_in vss +*.ipin v_in +*.iopin vss +*.opin v_out +XM3 net2 net1 vss vss nfet_03v3 L=1u W=4u nf=1 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=1 +XM4 net1 net1 vss vss nfet_03v3 L=1u W=4u nf=1 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=1 +XM5 v_out v_in net2 vss nfet_03v3 L=1u W=4u nf=1 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=1 +XM6 v_in v_in net1 vss nfet_03v3 L=1u W=4u nf=1 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=1 +XM1 vss vss vss vss nfet_03v3 L=1u W=4u nf=1 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=4 +.ends + + +* expanding symbol: cascode_cm.sym # of pins=4 +** sym_path: /foss/designs/gLayout-mahowalders/blocks/composite/regulated_cascoded_cmirror/xschem/cascode_cm.sym +** sch_path: /foss/designs/gLayout-mahowalders/blocks/composite/regulated_cascoded_cmirror/xschem/cascode_cm.sch +.subckt cascode_cm v_out v_aux v_in vss +*.ipin v_in +*.iopin vss +*.ipin v_aux +*.opin v_out +XM10 v_aux net1 vss vss nfet_03v3 L=1u W=8u nf=2 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=1 +XM8 v_in v_aux net1 vss nfet_03v3 L=1u W=8u nf=2 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=1 +XM11 net1 v_in vss vss nfet_03v3 L=1u W=8u nf=2 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=1 +XM12 v_aux net2 vss vss nfet_03v3 L=1u W=8u nf=2 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=1 +XM13 net2 v_in vss vss nfet_03v3 L=1u W=8u nf=2 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=1 +XM14 v_out v_aux net2 vss nfet_03v3 L=1u W=8u nf=2 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=1 +XM1 vss vss vss vss nfet_03v3 L=1u W=4u nf=1 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=6 +.ends + + +* expanding symbol: bias.sym # of pins=5 +** sym_path: /foss/designs/gLayout-mahowalders/blocks/composite/regulated_cascoded_cmirror/xschem/bias.sym +** sch_path: /foss/designs/gLayout-mahowalders/blocks/composite/regulated_cascoded_cmirror/xschem/bias.sch +.subckt bias VDD ENA bias_in bias_out vss +*.iopin vss +*.iopin VDD +*.ipin ENA +*.ipin bias_in +*.opin bias_out +XM11 net1 net1 VDD VDD pfet_03v3 L=2.0u W=100.0u nf=10 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=1 +XM12 bias_in bias_in net1 VDD pfet_03v3 L=2.0u W=100.0u nf=10 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=1 +XM16 net1 ENA VDD VDD pfet_03v3 L=2.0u W=10.0u nf=1 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=1 +XM17 net2 net1 VDD VDD pfet_03v3 L=2.0u W=10.0u nf=1 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=1 +XM19 net3 bias_in net2 VDD pfet_03v3 L=2.0u W=10.0u nf=1 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=1 +XM9 net4 net4 VDD VDD pfet_03v3 L=2.0u W=100.0u nf=10 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=1 +XM10 net5 net5 net4 VDD pfet_03v3 L=2.0u W=100.0u nf=10 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=1 +XM13 net4 ENA VDD VDD pfet_03v3 L=2.0u W=10.0u nf=1 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=1 +XM20 net6 net4 VDD VDD pfet_03v3 L=2.0u W=10.0u nf=1 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=1 +XM21 bias_out net5 net6 VDD pfet_03v3 L=2.0u W=10.0u nf=10 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=1 +XM22 net8 net7 vss vss nfet_03v3 L=1u W=8u nf=1 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=1 +XM23 net7 net7 vss vss nfet_03v3 L=1u W=80u nf=10 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=1 +XM24 net5 net3 net8 vss nfet_03v3 L=1u W=8u nf=1 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=1 +XM25 net3 net3 net7 vss nfet_03v3 L=1u W=80u nf=10 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=1 +XM1 VDD VDD VDD VDD pfet_03v3 L=2.0u W=10.0u nf=1 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=12 +XM2 vss vss vss vss nfet_03v3 L=1u W=8u nf=1 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=4 +.ends + +.end diff --git a/blocks/composite/regulated_cascoded_cmirror/xschem/LVS/simulation/int_top_lvs.spice b/blocks/composite/regulated_cascoded_cmirror/xschem/LVS/simulation/int_top_lvs.spice new file mode 100644 index 00000000..1ca9d075 --- /dev/null +++ b/blocks/composite/regulated_cascoded_cmirror/xschem/LVS/simulation/int_top_lvs.spice @@ -0,0 +1,220 @@ +** sch_path: /foss/designs/gLayout-mahowalders/blocks/composite/regulated_cascoded_cmirror/xschem/LVS/int_top_lvs.sch +**.subckt int_top_lvs EN VDD VSS VIN VBIAS VCM_OUT BCM_OUT CCM_OUT VIN_OUT PU PD +*.ipin EN +*.iopin VDD +*.iopin VSS +*.ipin VIN +*.ipin VBIAS +*.opin VCM_OUT +*.opin BCM_OUT +*.opin CCM_OUT +*.opin VIN_OUT +*.ipin PU +*.ipin PD +x2 PD VDD VSS tieH +x3 VDD PU VSS tieL +XIO8 VDD ENA EN VSS io_secondary_5p0 +x1 VDD ENA VIN_INT VCM_OUT BCM_OUT CCM_OUT VBIAS_INT VSS VIN_OUT top_level +XIO1 VDD VIN_INT VIN VSS io_secondary_5p0 +XIO2 VDD VBIAS_INT VBIAS VSS io_secondary_5p0 +**.ends + +* expanding symbol: Chipathon2025_pads/xschem/tieH.sym # of pins=3 +** sym_path: /foss/designs/gLayout-mahowalders/blocks/composite/regulated_cascoded_cmirror/xschem/Chipathon2025_pads/xschem/tieH.sym +** sch_path: /foss/designs/gLayout-mahowalders/blocks/composite/regulated_cascoded_cmirror/xschem/Chipathon2025_pads/xschem/tieH.sch +.subckt tieH TIEH VDD VSS +*.iopin VSS +*.iopin VDD +*.iopin TIEH +XM1 TIEH net1 VDD VDD pfet_05v0 L=0.55u W=2u nf=1 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=1 +XM2 net1 net1 VSS VSS nfet_05v0 L=0.70u W=1u nf=1 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=1 +.ends + + +* expanding symbol: Chipathon2025_pads/xschem/tieL.sym # of pins=3 +** sym_path: /foss/designs/gLayout-mahowalders/blocks/composite/regulated_cascoded_cmirror/xschem/Chipathon2025_pads/xschem/tieL.sym +** sch_path: /foss/designs/gLayout-mahowalders/blocks/composite/regulated_cascoded_cmirror/xschem/Chipathon2025_pads/xschem/tieL.sch +.subckt tieL VDD TIEL VSS +*.iopin VSS +*.iopin VDD +*.iopin TIEL +XM3 net1 net1 VDD VDD pfet_05v0 L=0.55u W=2u nf=1 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=1 +XM4 TIEL net1 VSS VSS nfet_05v0 L=0.70u W=1u nf=1 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=1 +.ends + + +* expanding symbol: Chipathon2025_pads/xschem/symbols/io_secondary_5p0/io_secondary_5p0.sym # of pins=4 +** sym_path: /foss/designs/gLayout-mahowalders/blocks/composite/regulated_cascoded_cmirror/xschem/Chipathon2025_pads/xschem/symbols/io_secondary_5p0/io_secondary_5p0.sym +** sch_path: /foss/designs/gLayout-mahowalders/blocks/composite/regulated_cascoded_cmirror/xschem/Chipathon2025_pads/xschem/symbols/io_secondary_5p0/io_secondary_5p0.sch +.subckt io_secondary_5p0 VDD to_gate ASIG5V VSS + + +*.iopin VSS +*.iopin VDD +*.iopin to_gate +*.iopin ASIG5V +D1 to_gate VDD diode_pd2nw_06v0 area='10u * 10u ' pj='2*10u + 2*10u ' m=4 +XR1 to_gate ASIG5V VDD ppolyf_u r_width=16e-6 r_length=4e-6 m=1 +D2 VSS to_gate diode_nd2ps_06v0 area='10u * 10u ' pj='2*10u + 2*10u ' m=4 +.ends + + +* expanding symbol: top_level.sym # of pins=9 +** sym_path: /foss/designs/gLayout-mahowalders/blocks/composite/regulated_cascoded_cmirror/xschem/top_level.sym +** sch_path: /foss/designs/gLayout-mahowalders/blocks/composite/regulated_cascoded_cmirror/xschem/top_level.sch +.subckt top_level VDD EN V_IN V_OUT_VCM V_OUT_BCM V_OUT_CCM V_AUX_CCM VSS V_OUT_VIN +*.iopin VSS +*.ipin V_AUX_CCM +*.iopin VDD +*.opin V_OUT_VCM +*.opin V_OUT_BCM +*.opin V_OUT_CCM +*.ipin V_IN +*.ipin EN +*.opin V_OUT_VIN +XM1 net1 net1 VDD VDD pfet_03v3 L=2.0u W=10.0u nf=1 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=1 +XM2 V_IN V_IN net1 VDD pfet_03v3 L=2.0u W=10.0u nf=1 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=1 +XM3 net2 net1 VDD VDD pfet_03v3 L=2.0u W=10.0u nf=1 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=1 +XM4 net3 V_IN net2 VDD pfet_03v3 L=2.0u W=10.0u nf=1 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=1 +XM5 net7 net1 VDD VDD pfet_03v3 L=2.0u W=10.0u nf=1 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=1 +XM6 net4 V_IN net7 VDD pfet_03v3 L=2.0u W=10.0u nf=1 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=1 +XM7 net6 net1 VDD VDD pfet_03v3 L=2.0u W=10.0u nf=1 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=1 +XM8 net5 V_IN net6 VDD pfet_03v3 L=2.0u W=10.0u nf=1 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=1 +XM14 net1 EN VDD VDD pfet_03v3 L=2.0u W=10.0u nf=1 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=1 +XM18 net1 EN VDD VDD pfet_03v3 L=2.0u W=10.0u nf=1 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=1 +XM15 net1 EN VDD VDD pfet_03v3 L=2.0u W=10.0u nf=1 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=1 +x1 net3 V_OUT_VCM VSS vanilla_cm +x2 V_OUT_BCM net4 VSS biased_cm +x3 V_OUT_CCM net8 net5 VSS cascode_cm +x4 VDD EN V_AUX_CCM net8 VSS bias +XM9 net9 net1 VDD VDD pfet_03v3 L=2.0u W=10.0u nf=1 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=1 +XM10 V_OUT_VIN V_IN net9 VDD pfet_03v3 L=2.0u W=10.0u nf=1 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=1 +XM11 net1 EN VDD VDD pfet_03v3 L=2.0u W=10.0u nf=1 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=1 +XM12 VDD VDD VDD VDD pfet_03v3 L=2.0u W=10.0u nf=1 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=6 +.ends + + +* expanding symbol: vanilla_cm.sym # of pins=3 +** sym_path: /foss/designs/gLayout-mahowalders/blocks/composite/regulated_cascoded_cmirror/xschem/vanilla_cm.sym +** sch_path: /foss/designs/gLayout-mahowalders/blocks/composite/regulated_cascoded_cmirror/xschem/vanilla_cm.sch +.subckt vanilla_cm v_in v_out vss +*.ipin v_in +*.iopin vss +*.opin v_out +XM1 v_out v_in vss vss nfet_03v3 L=1u W=4u nf=1 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=1 +XM2 v_in v_in vss vss nfet_03v3 L=1u W=4u nf=1 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=1 +XM3 vss vss vss vss nfet_03v3 L=1u W=4u nf=1 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=2 +.ends + + +* expanding symbol: biased_cm.sym # of pins=3 +** sym_path: /foss/designs/gLayout-mahowalders/blocks/composite/regulated_cascoded_cmirror/xschem/biased_cm.sym +** sch_path: /foss/designs/gLayout-mahowalders/blocks/composite/regulated_cascoded_cmirror/xschem/biased_cm.sch +.subckt biased_cm v_out v_in vss +*.ipin v_in +*.iopin vss +*.opin v_out +XM3 net2 net1 vss vss nfet_03v3 L=1u W=4u nf=1 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=1 +XM4 net1 net1 vss vss nfet_03v3 L=1u W=4u nf=1 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=1 +XM5 v_out v_in net2 vss nfet_03v3 L=1u W=4u nf=1 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=1 +XM6 v_in v_in net1 vss nfet_03v3 L=1u W=4u nf=1 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=1 +XM1 vss vss vss vss nfet_03v3 L=1u W=4u nf=1 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=4 +.ends + + +* expanding symbol: cascode_cm.sym # of pins=4 +** sym_path: /foss/designs/gLayout-mahowalders/blocks/composite/regulated_cascoded_cmirror/xschem/cascode_cm.sym +** sch_path: /foss/designs/gLayout-mahowalders/blocks/composite/regulated_cascoded_cmirror/xschem/cascode_cm.sch +.subckt cascode_cm v_out v_aux v_in vss +*.ipin v_in +*.iopin vss +*.ipin v_aux +*.opin v_out +XM10 v_aux net1 vss vss nfet_03v3 L=1u W=8u nf=2 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=1 +XM8 v_in v_aux net1 vss nfet_03v3 L=1u W=8u nf=2 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=1 +XM11 net1 v_in vss vss nfet_03v3 L=1u W=8u nf=2 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=1 +XM12 v_aux net2 vss vss nfet_03v3 L=1u W=8u nf=2 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=1 +XM13 net2 v_in vss vss nfet_03v3 L=1u W=8u nf=2 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=1 +XM14 v_out v_aux net2 vss nfet_03v3 L=1u W=8u nf=2 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=1 +XM1 vss vss vss vss nfet_03v3 L=1u W=4u nf=1 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=6 +.ends + + +* expanding symbol: bias.sym # of pins=5 +** sym_path: /foss/designs/gLayout-mahowalders/blocks/composite/regulated_cascoded_cmirror/xschem/bias.sym +** sch_path: /foss/designs/gLayout-mahowalders/blocks/composite/regulated_cascoded_cmirror/xschem/bias.sch +.subckt bias VDD ENA bias_in bias_out vss +*.iopin vss +*.iopin VDD +*.ipin ENA +*.ipin bias_in +*.opin bias_out +XM11 net1 net1 VDD VDD pfet_03v3 L=2.0u W=100.0u nf=10 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=1 +XM12 bias_in bias_in net1 VDD pfet_03v3 L=2.0u W=100.0u nf=10 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=1 +XM16 net1 ENA VDD VDD pfet_03v3 L=2.0u W=10.0u nf=1 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=1 +XM17 net2 net1 VDD VDD pfet_03v3 L=2.0u W=10.0u nf=1 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=1 +XM19 net3 bias_in net2 VDD pfet_03v3 L=2.0u W=10.0u nf=1 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=1 +XM9 net4 net4 VDD VDD pfet_03v3 L=2.0u W=100.0u nf=10 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=1 +XM10 net5 net5 net4 VDD pfet_03v3 L=2.0u W=100.0u nf=10 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=1 +XM13 net4 ENA VDD VDD pfet_03v3 L=2.0u W=10.0u nf=1 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=1 +XM20 net6 net4 VDD VDD pfet_03v3 L=2.0u W=10.0u nf=1 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=1 +XM21 bias_out net5 net6 VDD pfet_03v3 L=2.0u W=10.0u nf=10 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=1 +XM22 net8 net7 vss vss nfet_03v3 L=1u W=8u nf=1 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=1 +XM23 net7 net7 vss vss nfet_03v3 L=1u W=80u nf=10 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=1 +XM24 net5 net3 net8 vss nfet_03v3 L=1u W=8u nf=1 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=1 +XM25 net3 net3 net7 vss nfet_03v3 L=1u W=80u nf=10 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=1 +XM1 VDD VDD VDD VDD pfet_03v3 L=2.0u W=10.0u nf=1 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=12 +XM2 vss vss vss vss nfet_03v3 L=1u W=8u nf=1 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=4 +.ends + +.end diff --git a/blocks/composite/regulated_cascoded_cmirror/xschem/README.md b/blocks/composite/regulated_cascoded_cmirror/xschem/README.md new file mode 100644 index 00000000..593458bc --- /dev/null +++ b/blocks/composite/regulated_cascoded_cmirror/xschem/README.md @@ -0,0 +1,3 @@ +## gLayout-mahowalders + +> 🚧 **Under Construction** diff --git a/blocks/composite/regulated_cascoded_cmirror/xschem/bias.sch b/blocks/composite/regulated_cascoded_cmirror/xschem/bias.sch new file mode 100644 index 00000000..84fc96e3 --- /dev/null +++ b/blocks/composite/regulated_cascoded_cmirror/xschem/bias.sch @@ -0,0 +1,363 @@ +v {xschem version=3.4.7 file_version=1.2} +G {} +K {} +V {} +S {} +E {} +N -370 -210 -370 -150 {lab=#net1} +N -330 -120 -190 -120 {lab=bias_in} +N -330 -240 -190 -240 {lab=#net1} +N -150 -210 -150 -150 {lab=#net2} +N -370 -180 -280 -180 {lab=#net1} +N -280 -120 -280 -60 {lab=bias_in} +N -260 -260 -260 -240 {lab=#net1} +N -260 -240 -260 -190 {lab=#net1} +N -260 -190 -260 -180 {lab=#net1} +N -280 -180 -260 -180 {lab=#net1} +N -370 -340 -370 -270 {lab=VDD} +N -260 -340 -260 -320 {lab=VDD} +N -150 -340 -150 -270 {lab=VDD} +N -330 -290 -300 -290 {lab=ENA} +N -370 -90 -370 -60 {lab=bias_in} +N -150 -90 -150 -70 {lab=#net3} +N 160 -210 160 -150 {lab=#net4} +N 200 -120 340 -120 {lab=#net5} +N 200 -240 340 -240 {lab=#net4} +N 380 -210 380 -150 {lab=#net6} +N 160 -180 250 -180 {lab=#net4} +N 250 -120 250 -60 {lab=#net5} +N 270 -260 270 -240 {lab=#net4} +N 270 -240 270 -190 {lab=#net4} +N 270 -190 270 -180 {lab=#net4} +N 250 -180 270 -180 {lab=#net4} +N 160 -340 160 -270 {lab=VDD} +N 270 -340 270 -320 {lab=VDD} +N 200 -290 230 -290 {lab=ENA} +N 160 -90 160 -60 {lab=#net5} +N 380 -90 380 -70 {lab=bias_out} +N 80 420 80 440 {lab=vss} +N 80 350 120 350 {lab=vss} +N 120 350 120 400 {lab=vss} +N 80 400 120 400 {lab=vss} +N 0 350 40 350 {lab=#net7} +N -60 300 -60 320 {lab=#net7} +N -60 300 0 300 {lab=#net7} +N 0 300 0 350 {lab=#net7} +N -60 180 -60 300 {lab=#net7} +N -60 390 -60 440 {lab=vss} +N -120 350 -60 350 {lab=vss} +N -120 350 -120 390 {lab=vss} +N -120 390 -60 390 {lab=vss} +N 80 230 80 320 {lab=#net8} +N 80 380 80 400 {lab=vss} +N -20 350 0 350 {lab=#net7} +N -60 380 -60 390 {lab=vss} +N 80 400 80 420 {lab=vss} +N -60 440 80 440 {lab=vss} +N 80 200 80 230 {lab=#net8} +N 80 110 120 110 {lab=vss} +N 120 110 120 160 {lab=vss} +N 0 110 40 110 {lab=#net3} +N -60 60 -60 80 {lab=#net3} +N -60 60 0 60 {lab=#net3} +N 0 60 0 110 {lab=#net3} +N -120 110 -60 110 {lab=vss} +N -120 110 -120 150 {lab=vss} +N 80 140 80 160 {lab=#net8} +N -20 110 0 110 {lab=#net3} +N -60 140 -60 150 {lab=#net7} +N -60 50 -60 60 {lab=#net3} +N -60 150 -60 180 {lab=#net7} +N 80 160 80 200 {lab=#net8} +N 80 50 80 80 {lab=#net5} +N -120 20 -100 20 {lab=#net3} +N 120 160 120 350 {lab=vss} +N -120 150 -120 350 {lab=vss} +N -160 440 -60 440 {lab=vss} +N -60 20 -60 50 {lab=#net3} +N -100 20 -60 20 {lab=#net3} +N 80 10 90 10 {lab=#net5} +N 80 10 80 50 {lab=#net5} +N -460 -390 380 -390 {lab=VDD} +N 380 -390 380 -270 {lab=VDD} +N 270 -390 270 -340 {lab=VDD} +N 160 -390 160 -340 {lab=VDD} +N -150 -390 -150 -340 {lab=VDD} +N -370 -390 -370 -340 {lab=VDD} +N -260 -390 -260 -340 {lab=VDD} +N -600 -390 -580 -390 {lab=VDD} +N -580 -330 200 -330 {lab=ENA} +N 200 -330 200 -290 {lab=ENA} +N -330 -330 -330 -290 {lab=ENA} +N -620 -40 -370 -40 {lab=bias_in} +N -370 -60 -370 -40 {lab=bias_in} +N -370 -40 -280 -40 {lab=bias_in} +N -280 -60 -280 -40 {lab=bias_in} +N -150 -70 -150 20 {lab=#net3} +N -150 20 -120 20 {lab=#net3} +N 160 -60 160 10 {lab=#net5} +N 90 10 160 10 {lab=#net5} +N 160 -60 250 -60 {lab=#net5} +N 380 -30 490 -30 {lab=bias_out} +N 380 -70 380 -30 {lab=bias_out} +N -560 440 -160 440 {lab=vss} +N 490 -390 490 -360 {lab=VDD} +N 380 -390 490 -390 {lab=VDD} +N 450 -390 450 -330 {lab=VDD} +N 490 -300 520 -300 {lab=VDD} +N 520 -390 520 -300 {lab=VDD} +N 490 -390 520 -390 {lab=VDD} +N 490 -330 520 -330 {lab=VDD} +N 230 380 230 440 {lab=vss} +N 80 440 230 440 {lab=vss} +N 190 350 190 440 {lab=vss} +N 230 320 270 320 {lab=vss} +N 270 320 270 440 {lab=vss} +N 230 440 270 440 {lab=vss} +N 230 350 270 350 {lab=vss} +C {symbols/pfet_03v3.sym} -350 -240 0 1 {name=M11 +L=2.0u +W=100.0u +nf=10 +m=1 +ad="'int((nf+1)/2) * W/nf * 0.18u'" +pd="'2*int((nf+1)/2) * (W/nf + 0.18u)'" +as="'int((nf+2)/2) * W/nf * 0.18u'" +ps="'2*int((nf+2)/2) * (W/nf + 0.18u)'" +nrd="'0.18u / W'" nrs="'0.18u / W'" +sa=0 sb=0 sd=0 +model=pfet_03v3 +spiceprefix=X +} +C {symbols/pfet_03v3.sym} -350 -120 0 1 {name=M12 +L=2.0u +W=100.0u +nf=10 +m=1 +ad="'int((nf+1)/2) * W/nf * 0.18u'" +pd="'2*int((nf+1)/2) * (W/nf + 0.18u)'" +as="'int((nf+2)/2) * W/nf * 0.18u'" +ps="'2*int((nf+2)/2) * (W/nf + 0.18u)'" +nrd="'0.18u / W'" nrs="'0.18u / W'" +sa=0 sb=0 sd=0 +model=pfet_03v3 +spiceprefix=X +} +C {symbols/pfet_03v3.sym} -280 -290 0 0 {name=M16 +L=2.0u +W=10.0u +nf=1 +m=1 +ad="'int((nf+1)/2) * W/nf * 0.18u'" +pd="'2*int((nf+1)/2) * (W/nf + 0.18u)'" +as="'int((nf+2)/2) * W/nf * 0.18u'" +ps="'2*int((nf+2)/2) * (W/nf + 0.18u)'" +nrd="'0.18u / W'" nrs="'0.18u / W'" +sa=0 sb=0 sd=0 +model=pfet_03v3 +spiceprefix=X +} +C {symbols/pfet_03v3.sym} -170 -240 0 0 {name=M17 +L=2.0u +W=10.0u +nf=1 +m=1 +ad="'int((nf+1)/2) * W/nf * 0.18u'" +pd="'2*int((nf+1)/2) * (W/nf + 0.18u)'" +as="'int((nf+2)/2) * W/nf * 0.18u'" +ps="'2*int((nf+2)/2) * (W/nf + 0.18u)'" +nrd="'0.18u / W'" nrs="'0.18u / W'" +sa=0 sb=0 sd=0 +model=pfet_03v3 +spiceprefix=X +} +C {symbols/pfet_03v3.sym} -170 -120 0 0 {name=M19 +L=2.0u +W=10.0u +nf=1 +m=1 +ad="'int((nf+1)/2) * W/nf * 0.18u'" +pd="'2*int((nf+1)/2) * (W/nf + 0.18u)'" +as="'int((nf+2)/2) * W/nf * 0.18u'" +ps="'2*int((nf+2)/2) * (W/nf + 0.18u)'" +nrd="'0.18u / W'" nrs="'0.18u / W'" +sa=0 sb=0 sd=0 +model=pfet_03v3 +spiceprefix=X +} +C {lab_pin.sym} -370 -240 0 0 {name=p25 sig_type=std_logic lab=VDD} +C {lab_pin.sym} -370 -120 0 0 {name=p26 sig_type=std_logic lab=VDD} +C {lab_pin.sym} -150 -240 2 0 {name=p27 sig_type=std_logic lab=VDD} +C {lab_pin.sym} -150 -120 2 0 {name=p28 sig_type=std_logic lab=VDD} +C {lab_pin.sym} -260 -290 2 0 {name=p29 sig_type=std_logic lab=VDD} +C {symbols/pfet_03v3.sym} 180 -240 0 1 {name=M9 +L=2.0u +W=100.0u +nf=10 +m=1 +ad="'int((nf+1)/2) * W/nf * 0.18u'" +pd="'2*int((nf+1)/2) * (W/nf + 0.18u)'" +as="'int((nf+2)/2) * W/nf * 0.18u'" +ps="'2*int((nf+2)/2) * (W/nf + 0.18u)'" +nrd="'0.18u / W'" nrs="'0.18u / W'" +sa=0 sb=0 sd=0 +model=pfet_03v3 +spiceprefix=X +} +C {symbols/pfet_03v3.sym} 180 -120 0 1 {name=M10 +L=2.0u +W=100.0u +nf=10 +m=1 +ad="'int((nf+1)/2) * W/nf * 0.18u'" +pd="'2*int((nf+1)/2) * (W/nf + 0.18u)'" +as="'int((nf+2)/2) * W/nf * 0.18u'" +ps="'2*int((nf+2)/2) * (W/nf + 0.18u)'" +nrd="'0.18u / W'" nrs="'0.18u / W'" +sa=0 sb=0 sd=0 +model=pfet_03v3 +spiceprefix=X +} +C {symbols/pfet_03v3.sym} 250 -290 0 0 {name=M13 +L=2.0u +W=10.0u +nf=1 +m=1 +ad="'int((nf+1)/2) * W/nf * 0.18u'" +pd="'2*int((nf+1)/2) * (W/nf + 0.18u)'" +as="'int((nf+2)/2) * W/nf * 0.18u'" +ps="'2*int((nf+2)/2) * (W/nf + 0.18u)'" +nrd="'0.18u / W'" nrs="'0.18u / W'" +sa=0 sb=0 sd=0 +model=pfet_03v3 +spiceprefix=X +} +C {symbols/pfet_03v3.sym} 360 -240 0 0 {name=M20 +L=2.0u +W=10.0u +nf=1 +m=1 +ad="'int((nf+1)/2) * W/nf * 0.18u'" +pd="'2*int((nf+1)/2) * (W/nf + 0.18u)'" +as="'int((nf+2)/2) * W/nf * 0.18u'" +ps="'2*int((nf+2)/2) * (W/nf + 0.18u)'" +nrd="'0.18u / W'" nrs="'0.18u / W'" +sa=0 sb=0 sd=0 +model=pfet_03v3 +spiceprefix=X +} +C {symbols/pfet_03v3.sym} 360 -120 0 0 {name=M21 +L=2.0u +W=10.0u +nf=10 +m=1 +ad="'int((nf+1)/2) * W/nf * 0.18u'" +pd="'2*int((nf+1)/2) * (W/nf + 0.18u)'" +as="'int((nf+2)/2) * W/nf * 0.18u'" +ps="'2*int((nf+2)/2) * (W/nf + 0.18u)'" +nrd="'0.18u / W'" nrs="'0.18u / W'" +sa=0 sb=0 sd=0 +model=pfet_03v3 +spiceprefix=X +} +C {lab_pin.sym} 160 -240 0 0 {name=p30 sig_type=std_logic lab=VDD} +C {lab_pin.sym} 160 -120 0 0 {name=p31 sig_type=std_logic lab=VDD} +C {lab_pin.sym} 380 -240 2 0 {name=p32 sig_type=std_logic lab=VDD} +C {lab_pin.sym} 380 -120 2 0 {name=p33 sig_type=std_logic lab=VDD} +C {lab_pin.sym} 270 -290 2 0 {name=p34 sig_type=std_logic lab=VDD} +C {symbols/nfet_03v3.sym} 60 350 0 0 {name=M22 +L=1u +W=8u +nf=1 +m=1 +ad="'int((nf+1)/2) * W/nf * 0.18u'" +pd="'2*int((nf+1)/2) * (W/nf + 0.18u)'" +as="'int((nf+2)/2) * W/nf * 0.18u'" +ps="'2*int((nf+2)/2) * (W/nf + 0.18u)'" +nrd="'0.18u / W'" nrs="'0.18u / W'" +sa=0 sb=0 sd=0 +model=nfet_03v3 +spiceprefix=X +} +C {symbols/nfet_03v3.sym} -40 350 0 1 {name=M23 +L=1u +W=80u +nf=10 +m=1 +ad="'int((nf+1)/2) * W/nf * 0.18u'" +pd="'2*int((nf+1)/2) * (W/nf + 0.18u)'" +as="'int((nf+2)/2) * W/nf * 0.18u'" +ps="'2*int((nf+2)/2) * (W/nf + 0.18u)'" +nrd="'0.18u / W'" nrs="'0.18u / W'" +sa=0 sb=0 sd=0 +model=nfet_03v3 +spiceprefix=X +} +C {symbols/nfet_03v3.sym} 60 110 0 0 {name=M24 +L=1u +W=8u +nf=1 +m=1 +ad="'int((nf+1)/2) * W/nf * 0.18u'" +pd="'2*int((nf+1)/2) * (W/nf + 0.18u)'" +as="'int((nf+2)/2) * W/nf * 0.18u'" +ps="'2*int((nf+2)/2) * (W/nf + 0.18u)'" +nrd="'0.18u / W'" nrs="'0.18u / W'" +sa=0 sb=0 sd=0 +model=nfet_03v3 +spiceprefix=X +} +C {symbols/nfet_03v3.sym} -40 110 0 1 {name=M25 +L=1u +W=80u +nf=10 +m=1 +ad="'int((nf+1)/2) * W/nf * 0.18u'" +pd="'2*int((nf+1)/2) * (W/nf + 0.18u)'" +as="'int((nf+2)/2) * W/nf * 0.18u'" +ps="'2*int((nf+2)/2) * (W/nf + 0.18u)'" +nrd="'0.18u / W'" nrs="'0.18u / W'" +sa=0 sb=0 sd=0 +model=nfet_03v3 +spiceprefix=X +} +C {iopin.sym} -560 440 2 0 {name=p36 lab=vss +} +C {iopin.sym} -600 -390 2 0 {name=p1 lab=VDD +} +C {ipin.sym} -580 -330 0 0 {name=p2 lab=ENA +} +C {ipin.sym} -620 -40 0 0 {name=p3 lab=bias_in +} +C {opin.sym} 490 -30 0 0 {name=p4 lab=bias_out +} +C {lab_pin.sym} -580 -390 2 0 {name=p5 sig_type=std_logic lab=VDD} +C {lab_pin.sym} -460 -390 0 0 {name=p6 sig_type=std_logic lab=VDD} +C {symbols/pfet_03v3.sym} 470 -330 0 0 {name=M1 +L=2.0u +W=10.0u +nf=1 +m=12 +ad="'int((nf+1)/2) * W/nf * 0.18u'" +pd="'2*int((nf+1)/2) * (W/nf + 0.18u)'" +as="'int((nf+2)/2) * W/nf * 0.18u'" +ps="'2*int((nf+2)/2) * (W/nf + 0.18u)'" +nrd="'0.18u / W'" nrs="'0.18u / W'" +sa=0 sb=0 sd=0 +model=pfet_03v3 +spiceprefix=X +} +C {symbols/nfet_03v3.sym} 210 350 0 0 {name=M2 +L=1u +W=8u +nf=1 +m=4 +ad="'int((nf+1)/2) * W/nf * 0.18u'" +pd="'2*int((nf+1)/2) * (W/nf + 0.18u)'" +as="'int((nf+2)/2) * W/nf * 0.18u'" +ps="'2*int((nf+2)/2) * (W/nf + 0.18u)'" +nrd="'0.18u / W'" nrs="'0.18u / W'" +sa=0 sb=0 sd=0 +model=nfet_03v3 +spiceprefix=X +} diff --git a/blocks/composite/regulated_cascoded_cmirror/xschem/bias.sym b/blocks/composite/regulated_cascoded_cmirror/xschem/bias.sym new file mode 100644 index 00000000..ac164a01 --- /dev/null +++ b/blocks/composite/regulated_cascoded_cmirror/xschem/bias.sym @@ -0,0 +1,48 @@ +v {xschem version=3.4.7 file_version=1.2} +G {} +K {type=subcircuit +format="@name @pinlist @symname" +template="name=x1" +} +V {} +S {} +E {} +L 4 -120 -60 -100 -60 {} +L 4 -120 -40 -100 -40 {} +L 4 100 -40 120 -40 {} +L 4 -100 -40 -50 -40 {} +L 4 -50 -40 -50 -20 {} +L 4 -50 -40 -50 -10 {} +L 4 -50 -10 -30 -10 {} +L 4 -30 -10 -30 10 {} +L 4 -50 10 -30 10 {} +L 4 -50 10 -50 30 {} +L 4 -50 -40 0 -40 {} +L 4 -20 -10 -20 10 {} +L 4 -20 0 0 0 {} +L 4 0 -40 0 0 {} +L 4 50 -40 50 -20 {} +L 4 50 -40 50 -10 {} +L 4 30 -10 50 -10 {} +L 4 30 -10 30 10 {} +L 4 30 10 50 10 {} +L 4 50 10 50 30 {} +L 4 20 -10 20 10 {} +L 4 0 0 20 0 {} +L 4 50 -40 100 -40 {} +L 4 -50 30 50 30 {} +L 7 0 -70 0 -50 {} +L 7 0 30 0 50 {} +B 4 -110 -70 110 50 {fill=False} +B 5 -2.5 -72.5 2.5 -67.5 {name=VDD dir=inout} +B 5 -122.5 -62.5 -117.5 -57.5 {name=ENA dir=in} +B 5 -122.5 -42.5 -117.5 -37.5 {name=bias_in dir=in} +B 5 117.5 -42.5 122.5 -37.5 {name=bias_out dir=out} +B 5 -2.5 47.5 2.5 52.5 {name=vss dir=inout} +T {@symname} 14 -66 0 0 0.3 0.3 {} +T {@name} 65 -92 0 0 0.2 0.2 {} +T {VDD} -5 -64 0 1 0.2 0.2 {} +T {ENA} -95 -64 0 0 0.2 0.2 {} +T {bias_in} -95 -34 0 0 0.2 0.2 {} +T {bias_out} 105 -24 0 1 0.2 0.2 {} +T {vss} 5 44 2 1 0.2 0.2 {} diff --git a/blocks/composite/regulated_cascoded_cmirror/xschem/biased_cm.sch b/blocks/composite/regulated_cascoded_cmirror/xschem/biased_cm.sch new file mode 100644 index 00000000..f14c03f1 --- /dev/null +++ b/blocks/composite/regulated_cascoded_cmirror/xschem/biased_cm.sch @@ -0,0 +1,131 @@ +v {xschem version=3.4.7 file_version=1.2} +G {} +K {} +V {} +S {} +E {} +N 320 -60 320 -40 {lab=vss} +N 320 -130 360 -130 {lab=vss} +N 360 -130 360 -80 {lab=vss} +N 320 -80 360 -80 {lab=vss} +N 240 -130 280 -130 {lab=#net1} +N 180 -180 180 -160 {lab=#net1} +N 180 -180 240 -180 {lab=#net1} +N 240 -180 240 -130 {lab=#net1} +N 180 -300 180 -180 {lab=#net1} +N 180 -90 180 -40 {lab=vss} +N 120 -130 180 -130 {lab=vss} +N 120 -130 120 -90 {lab=vss} +N 120 -90 180 -90 {lab=vss} +N 320 -250 320 -160 {lab=#net2} +N 320 -100 320 -80 {lab=vss} +N 220 -130 240 -130 {lab=#net1} +N 180 -100 180 -90 {lab=vss} +N 320 -80 320 -60 {lab=vss} +N 180 -40 320 -40 {lab=vss} +N 320 -280 320 -250 {lab=#net2} +N 320 -370 360 -370 {lab=vss} +N 360 -370 360 -320 {lab=vss} +N 240 -370 280 -370 {lab=v_in} +N 180 -420 180 -400 {lab=v_in} +N 180 -420 240 -420 {lab=v_in} +N 240 -420 240 -370 {lab=v_in} +N 120 -370 180 -370 {lab=vss} +N 120 -370 120 -330 {lab=vss} +N 320 -340 320 -320 {lab=#net2} +N 220 -370 240 -370 {lab=v_in} +N 180 -340 180 -330 {lab=#net1} +N 180 -430 180 -420 {lab=v_in} +N 180 -330 180 -300 {lab=#net1} +N 320 -320 320 -280 {lab=#net2} +N 320 -430 320 -400 {lab=v_out} +N 120 -460 140 -460 {lab=v_in} +N 360 -320 360 -130 {lab=vss} +N 120 -330 120 -130 {lab=vss} +N 80 -40 180 -40 {lab=vss} +N 180 -460 180 -430 {lab=v_in} +N 140 -460 180 -460 {lab=v_in} +N 320 -470 330 -470 {lab=v_out} +N 320 -470 320 -430 {lab=v_out} +N 450 -100 450 -40 {lab=vss} +N 320 -40 450 -40 {lab=vss} +N 410 -130 410 -40 {lab=vss} +N 450 -160 490 -160 {lab=vss} +N 490 -160 490 -40 {lab=vss} +N 450 -40 490 -40 {lab=vss} +N 450 -130 490 -130 {lab=vss} +C {symbols/nfet_03v3.sym} 300 -130 0 0 {name=M3 +L=1u +W=4u +nf=1 +m=1 +ad="'int((nf+1)/2) * W/nf * 0.18u'" +pd="'2*int((nf+1)/2) * (W/nf + 0.18u)'" +as="'int((nf+2)/2) * W/nf * 0.18u'" +ps="'2*int((nf+2)/2) * (W/nf + 0.18u)'" +nrd="'0.18u / W'" nrs="'0.18u / W'" +sa=0 sb=0 sd=0 +model=nfet_03v3 +spiceprefix=X +} +C {symbols/nfet_03v3.sym} 200 -130 0 1 {name=M4 +L=1u +W=4u +nf=1 +m=1 +ad="'int((nf+1)/2) * W/nf * 0.18u'" +pd="'2*int((nf+1)/2) * (W/nf + 0.18u)'" +as="'int((nf+2)/2) * W/nf * 0.18u'" +ps="'2*int((nf+2)/2) * (W/nf + 0.18u)'" +nrd="'0.18u / W'" nrs="'0.18u / W'" +sa=0 sb=0 sd=0 +model=nfet_03v3 +spiceprefix=X +} +C {symbols/nfet_03v3.sym} 300 -370 0 0 {name=M5 +L=1u +W=4u +nf=1 +m=1 +ad="'int((nf+1)/2) * W/nf * 0.18u'" +pd="'2*int((nf+1)/2) * (W/nf + 0.18u)'" +as="'int((nf+2)/2) * W/nf * 0.18u'" +ps="'2*int((nf+2)/2) * (W/nf + 0.18u)'" +nrd="'0.18u / W'" nrs="'0.18u / W'" +sa=0 sb=0 sd=0 +model=nfet_03v3 +spiceprefix=X +} +C {symbols/nfet_03v3.sym} 200 -370 0 1 {name=M6 +L=1u +W=4u +nf=1 +m=1 +ad="'int((nf+1)/2) * W/nf * 0.18u'" +pd="'2*int((nf+1)/2) * (W/nf + 0.18u)'" +as="'int((nf+2)/2) * W/nf * 0.18u'" +ps="'2*int((nf+2)/2) * (W/nf + 0.18u)'" +nrd="'0.18u / W'" nrs="'0.18u / W'" +sa=0 sb=0 sd=0 +model=nfet_03v3 +spiceprefix=X +} +C {ipin.sym} 120 -460 0 0 {name=p1 lab=v_in +} +C {iopin.sym} 80 -40 2 0 {name=p3 lab=vss +} +C {opin.sym} 330 -470 0 0 {name=p4 lab=v_out} +C {symbols/nfet_03v3.sym} 430 -130 0 0 {name=M1 +L=1u +W=4u +nf=1 +m=4 +ad="'int((nf+1)/2) * W/nf * 0.18u'" +pd="'2*int((nf+1)/2) * (W/nf + 0.18u)'" +as="'int((nf+2)/2) * W/nf * 0.18u'" +ps="'2*int((nf+2)/2) * (W/nf + 0.18u)'" +nrd="'0.18u / W'" nrs="'0.18u / W'" +sa=0 sb=0 sd=0 +model=nfet_03v3 +spiceprefix=X +} diff --git a/blocks/composite/regulated_cascoded_cmirror/xschem/biased_cm.sym b/blocks/composite/regulated_cascoded_cmirror/xschem/biased_cm.sym new file mode 100644 index 00000000..df0161b1 --- /dev/null +++ b/blocks/composite/regulated_cascoded_cmirror/xschem/biased_cm.sym @@ -0,0 +1,42 @@ +v {xschem version=3.4.7 file_version=1.2} +G {} +K {type=subcircuit +format="@name @pinlist @symname" +template="name=x1" +} +V {} +S {} +E {} +L 4 100 -40 120 -40 {} +L 4 -120 -40 -100 -40 {} +L 4 -100 -40 -50 -40 {} +L 4 -50 -40 -50 -20 {} +L 4 -50 -40 -50 -10 {} +L 4 -50 -10 -30 -10 {} +L 4 -30 -10 -30 10 {} +L 4 -50 10 -30 10 {} +L 4 -50 10 -50 30 {} +L 4 -50 -40 0 -40 {} +L 4 -20 -10 -20 10 {} +L 4 -20 0 0 0 {} +L 4 0 -40 0 0 {} +L 4 50 -40 50 -20 {} +L 4 50 -40 50 -10 {} +L 4 30 -10 50 -10 {} +L 4 30 -10 30 10 {} +L 4 30 10 50 10 {} +L 4 50 10 50 30 {} +L 4 20 -10 20 10 {} +L 4 0 0 20 0 {} +L 4 50 -40 100 -40 {} +L 4 -50 30 50 30 {} +L 7 0 30 0 50 {} +B 4 -110 -70 110 50 {fill=False} +B 5 117.5 -42.5 122.5 -37.5 {name=v_out dir=out} +B 5 -122.5 -42.5 -117.5 -37.5 {name=v_in dir=in} +B 5 -2.5 47.5 2.5 52.5 {name=vss dir=inout} +T {@symname} -38.5 -66 0 0 0.3 0.3 {} +T {@name} 65 -92 0 0 0.2 0.2 {} +T {v_out} 95 -34 0 1 0.2 0.2 {} +T {v_in} -95 -34 0 0 0.2 0.2 {} +T {vss} 4 25 1 1 0.2 0.2 {} diff --git a/blocks/composite/regulated_cascoded_cmirror/xschem/cascode_cm.sch b/blocks/composite/regulated_cascoded_cmirror/xschem/cascode_cm.sch new file mode 100644 index 00000000..b06b1185 --- /dev/null +++ b/blocks/composite/regulated_cascoded_cmirror/xschem/cascode_cm.sch @@ -0,0 +1,183 @@ +v {xschem version=3.4.7 file_version=1.2} +G {} +K {} +V {} +S {} +E {} +N 170 -190 170 -70 {lab=vss} +N 230 -260 270 -260 {lab=#net1} +N 170 -610 170 -590 {lab=v_aux} +N 110 -260 170 -260 {lab=vss} +N 110 -260 110 -220 {lab=vss} +N 210 -260 230 -260 {lab=#net1} +N 170 -230 170 -220 {lab=vss} +N 170 -620 170 -610 {lab=v_aux} +N 170 -220 170 -190 {lab=vss} +N 170 -360 340 -360 {lab=v_aux} +N 170 -360 170 -290 {lab=v_aux} +N 380 -330 380 -170 {lab=#net1} +N 270 -260 380 -260 {lab=#net1} +N 170 -510 170 -360 {lab=v_aux} +N 380 -110 380 -70 {lab=vss} +N 170 -70 380 -70 {lab=vss} +N 870 -430 870 -310 {lab=v_aux} +N 770 -240 810 -240 {lab=#net2} +N 870 -240 930 -240 {lab=vss} +N 810 -240 830 -240 {lab=#net2} +N 870 -280 870 -270 {lab=v_aux} +N 870 -310 870 -280 {lab=v_aux} +N 870 -210 870 -140 {lab=vss} +N 660 -330 660 -170 {lab=#net2} +N 660 -240 770 -240 {lab=#net2} +N 660 -430 660 -390 {lab=v_out} +N 660 -110 660 -70 {lab=vss} +N 700 -360 870 -360 {lab=v_aux} +N 420 -140 620 -140 {lab=v_in} +N 380 -600 380 -390 {lab=v_in} +N 380 -440 510 -440 {lab=v_in} +N 510 -440 510 -140 {lab=v_in} +N 870 -610 870 -430 {lab=v_aux} +N 200 -610 870 -610 {lab=v_aux} +N 170 -610 200 -610 {lab=v_aux} +N 170 -590 170 -510 {lab=v_aux} +N 380 -690 380 -600 {lab=v_in} +N 170 -710 170 -620 {lab=v_aux} +N 380 -710 380 -690 {lab=v_in} +N 870 -140 870 -70 {lab=vss} +N 660 -70 870 -70 {lab=vss} +N 370 -70 660 -70 {lab=vss} +N 870 -70 930 -70 {lab=vss} +N 380 -360 400 -360 {lab=vss} +N 350 -140 380 -140 {lab=vss} +N 350 -140 350 -70 {lab=vss} +N 660 -140 690 -140 {lab=vss} +N 690 -140 690 -70 {lab=vss} +N 620 -360 660 -360 {lab=vss} +N 930 -240 930 -70 {lab=vss} +N 110 -220 170 -220 {lab=vss} +N 320 -740 340 -740 {lab=v_in} +N 110 -740 130 -740 {lab=v_aux} +N 400 -360 440 -360 {lab=vss} +N 440 -360 440 -70 {lab=vss} +N 570 -360 620 -360 {lab=vss} +N 570 -360 570 -80 {lab=vss} +N 570 -80 570 -70 {lab=vss} +N 130 -740 170 -740 {lab=v_aux} +N 170 -740 170 -720 {lab=v_aux} +N 170 -720 170 -710 {lab=v_aux} +N 380 -740 380 -710 {lab=v_in} +N 340 -740 380 -740 {lab=v_in} +N 660 -770 880 -770 {lab=v_out} +N 660 -770 660 -430 {lab=v_out} +N 1040 -90 1040 -70 {lab=vss} +N 930 -70 1040 -70 {lab=vss} +N 1000 -120 1000 -70 {lab=vss} +N 1040 -150 1070 -150 {lab=vss} +N 1070 -150 1070 -70 {lab=vss} +N 1040 -70 1070 -70 {lab=vss} +N 1040 -120 1070 -120 {lab=vss} +C {symbols/nfet_03v3.sym} 190 -260 0 1 {name=M10 +L=1u +W=8u +nf=2 +m=1 +ad="'int((nf+1)/2) * W/nf * 0.18u'" +pd="'2*int((nf+1)/2) * (W/nf + 0.18u)'" +as="'int((nf+2)/2) * W/nf * 0.18u'" +ps="'2*int((nf+2)/2) * (W/nf + 0.18u)'" +nrd="'0.18u / W'" nrs="'0.18u / W'" +sa=0 sb=0 sd=0 +model=nfet_03v3 +spiceprefix=X +} +C {symbols/nfet_03v3.sym} 360 -360 0 0 {name=M8 +L=1u +W=8u +nf=2 +m=1 +ad="'int((nf+1)/2) * W/nf * 0.18u'" +pd="'2*int((nf+1)/2) * (W/nf + 0.18u)'" +as="'int((nf+2)/2) * W/nf * 0.18u'" +ps="'2*int((nf+2)/2) * (W/nf + 0.18u)'" +nrd="'0.18u / W'" nrs="'0.18u / W'" +sa=0 sb=0 sd=0 +model=nfet_03v3 +spiceprefix=X +} +C {symbols/nfet_03v3.sym} 400 -140 0 1 {name=M11 +L=1u +W=8u +nf=2 +m=1 +ad="'int((nf+1)/2) * W/nf * 0.18u'" +pd="'2*int((nf+1)/2) * (W/nf + 0.18u)'" +as="'int((nf+2)/2) * W/nf * 0.18u'" +ps="'2*int((nf+2)/2) * (W/nf + 0.18u)'" +nrd="'0.18u / W'" nrs="'0.18u / W'" +sa=0 sb=0 sd=0 +model=nfet_03v3 +spiceprefix=X +} +C {symbols/nfet_03v3.sym} 850 -240 0 0 {name=M12 +L=1u +W=8u +nf=2 +m=1 +ad="'int((nf+1)/2) * W/nf * 0.18u'" +pd="'2*int((nf+1)/2) * (W/nf + 0.18u)'" +as="'int((nf+2)/2) * W/nf * 0.18u'" +ps="'2*int((nf+2)/2) * (W/nf + 0.18u)'" +nrd="'0.18u / W'" nrs="'0.18u / W'" +sa=0 sb=0 sd=0 +model=nfet_03v3 +spiceprefix=X +} +C {symbols/nfet_03v3.sym} 640 -140 0 0 {name=M13 +L=1u +W=8u +nf=2 +m=1 +ad="'int((nf+1)/2) * W/nf * 0.18u'" +pd="'2*int((nf+1)/2) * (W/nf + 0.18u)'" +as="'int((nf+2)/2) * W/nf * 0.18u'" +ps="'2*int((nf+2)/2) * (W/nf + 0.18u)'" +nrd="'0.18u / W'" nrs="'0.18u / W'" +sa=0 sb=0 sd=0 +model=nfet_03v3 +spiceprefix=X +} +C {symbols/nfet_03v3.sym} 680 -360 0 1 {name=M14 +L=1u +W=8u +nf=2 +m=1 +ad="'int((nf+1)/2) * W/nf * 0.18u'" +pd="'2*int((nf+1)/2) * (W/nf + 0.18u)'" +as="'int((nf+2)/2) * W/nf * 0.18u'" +ps="'2*int((nf+2)/2) * (W/nf + 0.18u)'" +nrd="'0.18u / W'" nrs="'0.18u / W'" +sa=0 sb=0 sd=0 +model=nfet_03v3 +spiceprefix=X +} +C {ipin.sym} 320 -740 0 0 {name=p1 lab=v_in +} +C {iopin.sym} 510 -70 1 0 {name=p3 lab=vss +} +C {ipin.sym} 110 -740 0 0 {name=p4 lab=v_aux +} +C {opin.sym} 880 -770 0 0 {name=p5 lab=v_out} +C {symbols/nfet_03v3.sym} 1020 -120 0 0 {name=M1 +L=1u +W=4u +nf=1 +m=6 +ad="'int((nf+1)/2) * W/nf * 0.18u'" +pd="'2*int((nf+1)/2) * (W/nf + 0.18u)'" +as="'int((nf+2)/2) * W/nf * 0.18u'" +ps="'2*int((nf+2)/2) * (W/nf + 0.18u)'" +nrd="'0.18u / W'" nrs="'0.18u / W'" +sa=0 sb=0 sd=0 +model=nfet_03v3 +spiceprefix=X +} diff --git a/blocks/composite/regulated_cascoded_cmirror/xschem/cascode_cm.sym b/blocks/composite/regulated_cascoded_cmirror/xschem/cascode_cm.sym new file mode 100644 index 00000000..4407c3e8 --- /dev/null +++ b/blocks/composite/regulated_cascoded_cmirror/xschem/cascode_cm.sym @@ -0,0 +1,45 @@ +v {xschem version=3.4.7 file_version=1.2} +G {} +K {type=subcircuit +format="@name @pinlist @symname" +template="name=x1" +} +V {} +S {} +E {} +L 4 100 -40 120 -40 {} +L 4 -120 0 -100 0 {} +L 4 -120 -40 -100 -40 {} +L 4 -100 -40 -50 -40 {} +L 4 -50 -40 -50 -20 {} +L 4 -50 -40 -50 -10 {} +L 4 -50 -10 -30 -10 {} +L 4 -30 -10 -30 10 {} +L 4 -50 10 -30 10 {} +L 4 -50 10 -50 30 {} +L 4 -50 -40 0 -40 {} +L 4 -20 -10 -20 10 {} +L 4 -20 0 0 0 {} +L 4 0 -40 0 0 {} +L 4 50 -40 50 -20 {} +L 4 50 -40 50 -10 {} +L 4 30 -10 50 -10 {} +L 4 30 -10 30 10 {} +L 4 30 10 50 10 {} +L 4 50 10 50 30 {} +L 4 20 -10 20 10 {} +L 4 0 0 20 0 {} +L 4 50 -40 100 -40 {} +L 4 -50 30 50 30 {} +L 7 0 30 0 50 {} +B 4 -110 -70 110 50 {fill=False} +B 5 117.5 -42.5 122.5 -37.5 {name=v_out dir=out} +B 5 -122.5 -2.5 -117.5 2.5 {name=v_aux dir=in} +B 5 -122.5 -42.5 -117.5 -37.5 {name=v_in dir=in} +B 5 -2.5 47.5 2.5 52.5 {name=vss dir=inout} +T {@symname} -33 -66 0 0 0.3 0.3 {} +T {@name} 65 -92 0 0 0.2 0.2 {} +T {v_out} 95 -34 0 1 0.2 0.2 {} +T {v_aux} -95 -4 0 0 0.2 0.2 {} +T {v_in} -95 -34 0 0 0.2 0.2 {} +T {vss} 4 25 1 1 0.2 0.2 {} diff --git a/blocks/composite/regulated_cascoded_cmirror/xschem/chip_top.sch b/blocks/composite/regulated_cascoded_cmirror/xschem/chip_top.sch new file mode 100644 index 00000000..4af3eccd --- /dev/null +++ b/blocks/composite/regulated_cascoded_cmirror/xschem/chip_top.sch @@ -0,0 +1,656 @@ +v {xschem version=3.4.7 file_version=1.2} +G {} +K {} +V {} +S {} +E {} +N -510 -380 -510 -340 {lab=VDD} +N -510 -280 -510 -270 {lab=#net1} +N -60 -110 50 -110 {lab=VSS} +N -20 -140 -20 -110 {lab=VSS} +N 50 -140 50 -110 {lab=VSS} +N -30 -300 40 -300 {lab=VDD} +N -0 -330 0 -300 {lab=VDD} +N -510 -190 -440 -190 {lab=GND} +N -440 -210 -440 -190 {lab=GND} +N -440 -410 -440 -270 {lab=ENABLE} +N 160 -240 580 -240 {lab=#net2} +N 160 -210 490 -210 {lab=#net3} +N 160 -180 410 -180 {lab=#net4} +N -440 -190 -350 -190 {lab=GND} +N -350 -210 -350 -190 {lab=GND} +N -350 -190 -290 -190 {lab=GND} +N -290 -210 -290 -190 {lab=GND} +N -290 -300 -290 -270 {lab=BIAS} +N -350 -290 -350 -270 {lab=IN} +N -160 -220 -140 -220 {lab=IN} +N -160 -180 -140 -180 {lab=BIAS} +N -510 -210 -510 -190 {lab=GND} +N -570 -290 -570 -270 {lab=VSS} +N -570 -210 -570 -190 {lab=GND} +N -570 -190 -510 -190 {lab=GND} +N 240 -270 660 -270 {lab=#net5} +N 160 -270 240 -270 {lab=#net5} +C {vsource.sym} 580 -150 0 0 {name=v_vanilla value=1.65} +C {gnd.sym} 580 -120 0 0 {name=l15 lab=GND +value=" +.options savecurrents +.param temp=27 +.control +set wr_singlescale +set noaskquit +*set appendwrite +set hcopypscolor=1 + +save all +op +*write tb_vcm.raw +* --- Run vanilla sweep --- +dc v_vanilla 0 3.3 0.1 +let i_vanilla = -i(v_vanilla) +wrdata vanilla.txt i_vanilla +*write tb_vcm.raw +* --- Run biased sweep --- +reset +*write tb_bcm.raw +dc v_biased 0 3.3 0.1 +let i_biased = -i(v_biased) +wrdata biased.txt i_biased +*write tb_bcm.raw +* --- Run cascode sweep --- +reset +*write tb_ccm.raw +dc v_cascode 0 3.3 0.1 +let i_cascode = -i(v_cascode) +wrdata cascode.txt i_cascode +*write tb_ccm.raw +.endc +"} +C {vsource.sym} 490 -120 0 0 {name=v_biased value=1.65} +C {gnd.sym} 490 -90 0 0 {name=l4 lab=GND +value=" +.options savecurrents +.param temp=27 +.control +set wr_singlescale +set noaskquit +*set appendwrite +set hcopypscolor=1 + +save all +op +*write tb_vcm.raw +* --- Run vanilla sweep --- +dc v_vanilla 0 3.3 0.1 +let i_vanilla = -i(v_vanilla) +wrdata vanilla.txt i_vanilla +*write tb_vcm.raw +* --- Run biased sweep --- +reset +*write tb_bcm.raw +dc v_biased 0 3.3 0.1 +let i_biased = -i(v_biased) +wrdata biased.txt i_biased +*write tb_bcm.raw +* --- Run cascode sweep --- +reset +*write tb_ccm.raw +dc v_cascode 0 3.3 0.1 +let i_cascode = -i(v_cascode) +wrdata cascode.txt i_cascode +*write tb_ccm.raw +.endc +"} +C {vsource.sym} 410 -90 0 0 {name=v_cascode value=1.65} +C {gnd.sym} 410 -60 0 0 {name=l5 lab=GND +value=" +.options savecurrents +.param temp=27 +.control +set wr_singlescale +set noaskquit +*set appendwrite +set hcopypscolor=1 + +save all +op +*write tb_vcm.raw +* --- Run vanilla sweep --- +dc v_vanilla 0 3.3 0.1 +let i_vanilla = -i(v_vanilla) +wrdata vanilla.txt i_vanilla +*write tb_vcm.raw +* --- Run biased sweep --- +reset +*write tb_bcm.raw +dc v_biased 0 3.3 0.1 +let i_biased = -i(v_biased) +wrdata biased.txt i_biased +*write tb_bcm.raw +* --- Run cascode sweep --- +reset +*write tb_ccm.raw +dc v_cascode 0 3.3 0.1 +let i_cascode = -i(v_cascode) +wrdata cascode.txt i_cascode +*write tb_ccm.raw +.endc +"} +C {res.sym} 580 -210 0 0 {name=R3 +footprint=1206 +device=resistor +m=1} +C {res.sym} 490 -180 0 0 {name=R5 +footprint=1206 +device=resistor +m=1} +C {res.sym} 410 -150 0 0 {name=R6 +footprint=1206 +device=resistor +m=1} +C {vsource.sym} -510 -240 0 0 {name=V1 value=3.3} +C {gnd.sym} -400 -190 0 0 {name=l10 lab=GND +value=" +.options savecurrents +.param temp=27 +.control +set wr_singlescale +set noaskquit +*set appendwrite +set hcopypscolor=1 + +save all +op +*write tb_vcm.raw +* --- Run vanilla sweep --- +dc v_vanilla 0 3.3 0.1 +let i_vanilla = -i(v_vanilla) +wrdata vanilla.txt i_vanilla +*write tb_vcm.raw +* --- Run biased sweep --- +reset +*write tb_bcm.raw +dc v_biased 0 3.3 0.1 +let i_biased = -i(v_biased) +wrdata biased.txt i_biased +*write tb_bcm.raw +* --- Run cascode sweep --- +reset +*write tb_ccm.raw +dc v_cascode 0 3.3 0.1 +let i_cascode = -i(v_cascode) +wrdata cascode.txt i_cascode +*write tb_ccm.raw +.endc +"} +C {res.sym} -510 -310 0 0 {name=R4 +footprint=1206 +device=resistor +m=1} +C {vdd.sym} -510 -380 0 0 {name=l8 lab=VDD +value=" +.options savecurrents +.param temp=27 +.control +set wr_singlescale +set noaskquit +*set appendwrite +set hcopypscolor=1 + +save all +op +*write tb_vcm.raw +* --- Run vanilla sweep --- +dc v_vanilla 0 3.3 0.1 +let i_vanilla = -i(v_vanilla) +wrdata vanilla.txt i_vanilla +*write tb_vcm.raw +* --- Run biased sweep --- +reset +*write tb_bcm.raw +dc v_biased 0 3.3 0.1 +let i_biased = -i(v_biased) +wrdata biased.txt i_biased +*write tb_bcm.raw +* --- Run cascode sweep --- +reset +*write tb_ccm.raw +dc v_cascode 0 3.3 0.1 +let i_cascode = -i(v_cascode) +wrdata cascode.txt i_cascode +*write tb_ccm.raw +.endc +"} +C {devices/code_shown.sym} -850 180 0 0 {name=MODELS only_toplevel=true +format="tcleval( @value )" +value=" +.include /foss/designs/gLayout-mahowalders/blocks/composite/regulated_cascoded_cmirror/xschem/Chipathon2025_pads/xschem/gf180mcu_fd_io.spice +.include /foss/designs/gLayout-mahowalders/blocks/composite/regulated_cascoded_cmirror/xschem/Chipathon2025_pads/xschem/gf180mcu_fd_io__asig_5p0_extracted.spice +.include $::180MCU_MODELS/design.ngspice +.lib $::180MCU_MODELS/sm141064.ngspice typical +.lib $::180MCU_MODELS/sm141064.ngspice diode_typical +.lib $::180MCU_MODELS/sm141064.ngspice res_typical +.lib $::180MCU_MODELS/sm141064.ngspice moscap_typical +" +} +C {code_shown.sym} -900 -490 0 0 {name=code only_toplevel=false +value=" +*.options savecurrents +.save i(v_vanilla) i(v_biased) i(v_cascode) +.param temp=27 +.control +set wr_singlescale +set noaskquit +*set appendwrite +set hcopypscolor=1 + +op +*write tb_vcm.raw +* --- Run vanilla sweep --- +dc v_vanilla 0 3.3 0.05 +let i_vanilla = -i(v_vanilla) +wrdata vanilla.txt i_vanilla +*write tb_vcm.raw +destroy $curplot +* --- Run biased sweep --- +reset +*write tb_bcm.raw +dc v_biased 0 3.3 0.05 +let i_biased = -i(v_biased) +wrdata biased.txt i_biased +*write tb_bcm.raw +destroy $curplot +* --- Run cascode sweep --- +reset +*write tb_ccm.raw +dc v_cascode 0 3.3 0.05 +let i_cascode = -i(v_cascode) +wrdata cascode.txt i_cascode +*write tb_ccm.raw +destroy $curplot +.endc +" +} +C {int_top_tb.sym} 10 -220 0 0 {name=x1 +value=" +.options savecurrents +.param temp=27 +.control +set wr_singlescale +set noaskquit +*set appendwrite +set hcopypscolor=1 + +save all +op +*write tb_vcm.raw +* --- Run vanilla sweep --- +dc v_vanilla 0 3.3 0.1 +let i_vanilla = -i(v_vanilla) +wrdata vanilla.txt i_vanilla +*write tb_vcm.raw +* --- Run biased sweep --- +reset +*write tb_bcm.raw +dc v_biased 0 3.3 0.1 +let i_biased = -i(v_biased) +wrdata biased.txt i_biased +*write tb_bcm.raw +* --- Run cascode sweep --- +reset +*write tb_ccm.raw +dc v_cascode 0 3.3 0.1 +let i_cascode = -i(v_cascode) +wrdata cascode.txt i_cascode +*write tb_ccm.raw +.endc +"} +C {lab_wire.sym} -570 -290 0 0 {name=p1 sig_type=std_logic lab=VSS +value=" +.options savecurrents +.param temp=27 +.control +set wr_singlescale +set noaskquit +*set appendwrite +set hcopypscolor=1 + +save all +op +*write tb_vcm.raw +* --- Run vanilla sweep --- +dc v_vanilla 0 3.3 0.1 +let i_vanilla = -i(v_vanilla) +wrdata vanilla.txt i_vanilla +*write tb_vcm.raw +* --- Run biased sweep --- +reset +*write tb_bcm.raw +dc v_biased 0 3.3 0.1 +let i_biased = -i(v_biased) +wrdata biased.txt i_biased +*write tb_bcm.raw +* --- Run cascode sweep --- +reset +*write tb_ccm.raw +dc v_cascode 0 3.3 0.1 +let i_cascode = -i(v_cascode) +wrdata cascode.txt i_cascode +*write tb_ccm.raw +.endc +"} +C {lab_wire.sym} -60 -110 0 0 {name=p2 sig_type=std_logic lab=VSS +value=" +.options savecurrents +.param temp=27 +.control +set wr_singlescale +set noaskquit +*set appendwrite +set hcopypscolor=1 + +save all +op +*write tb_vcm.raw +* --- Run vanilla sweep --- +dc v_vanilla 0 3.3 0.1 +let i_vanilla = -i(v_vanilla) +wrdata vanilla.txt i_vanilla +*write tb_vcm.raw +* --- Run biased sweep --- +reset +*write tb_bcm.raw +dc v_biased 0 3.3 0.1 +let i_biased = -i(v_biased) +wrdata biased.txt i_biased +*write tb_bcm.raw +* --- Run cascode sweep --- +reset +*write tb_ccm.raw +dc v_cascode 0 3.3 0.1 +let i_cascode = -i(v_cascode) +wrdata cascode.txt i_cascode +*write tb_ccm.raw +.endc +"} +C {vdd.sym} 0 -330 0 0 {name=l1 lab=VDD +value=" +.options savecurrents +.param temp=27 +.control +set wr_singlescale +set noaskquit +*set appendwrite +set hcopypscolor=1 + +save all +op +*write tb_vcm.raw +* --- Run vanilla sweep --- +dc v_vanilla 0 3.3 0.1 +let i_vanilla = -i(v_vanilla) +wrdata vanilla.txt i_vanilla +*write tb_vcm.raw +* --- Run biased sweep --- +reset +*write tb_bcm.raw +dc v_biased 0 3.3 0.1 +let i_biased = -i(v_biased) +wrdata biased.txt i_biased +*write tb_bcm.raw +* --- Run cascode sweep --- +reset +*write tb_ccm.raw +dc v_cascode 0 3.3 0.1 +let i_cascode = -i(v_cascode) +wrdata cascode.txt i_cascode +*write tb_ccm.raw +.endc +"} +C {vsource.sym} -440 -240 0 0 {name=V2 value=3.3} +C {lab_wire.sym} -440 -410 2 0 {name=p3 sig_type=std_logic lab=ENABLE +value=" +.options savecurrents +.param temp=27 +.control +set wr_singlescale +set noaskquit +*set appendwrite +set hcopypscolor=1 + +save all +op +*write tb_vcm.raw +* --- Run vanilla sweep --- +dc v_vanilla 0 3.3 0.1 +let i_vanilla = -i(v_vanilla) +wrdata vanilla.txt i_vanilla +*write tb_vcm.raw +* --- Run biased sweep --- +reset +*write tb_bcm.raw +dc v_biased 0 3.3 0.1 +let i_biased = -i(v_biased) +wrdata biased.txt i_biased +*write tb_bcm.raw +* --- Run cascode sweep --- +reset +*write tb_ccm.raw +dc v_cascode 0 3.3 0.1 +let i_cascode = -i(v_cascode) +wrdata cascode.txt i_cascode +*write tb_ccm.raw +.endc +"} +C {lab_wire.sym} -140 -260 0 0 {name=p4 sig_type=std_logic lab=ENABLE +value=" +.options savecurrents +.param temp=27 +.control +set wr_singlescale +set noaskquit +*set appendwrite +set hcopypscolor=1 + +save all +op +*write tb_vcm.raw +* --- Run vanilla sweep --- +dc v_vanilla 0 3.3 0.1 +let i_vanilla = -i(v_vanilla) +wrdata vanilla.txt i_vanilla +*write tb_vcm.raw +* --- Run biased sweep --- +reset +*write tb_bcm.raw +dc v_biased 0 3.3 0.1 +let i_biased = -i(v_biased) +wrdata biased.txt i_biased +*write tb_bcm.raw +* --- Run cascode sweep --- +reset +*write tb_ccm.raw +dc v_cascode 0 3.3 0.1 +let i_cascode = -i(v_cascode) +wrdata cascode.txt i_cascode +*write tb_ccm.raw +.endc +"} +C {isource.sym} -350 -240 0 0 {name=Iin value="10u"} +C {isource.sym} -290 -240 0 0 {name=I_aux value=1u} +C {lab_wire.sym} -350 -290 0 0 {name=p5 sig_type=std_logic lab=IN +value=" +.options savecurrents +.param temp=27 +.control +set wr_singlescale +set noaskquit +*set appendwrite +set hcopypscolor=1 + +save all +op +*write tb_vcm.raw +* --- Run vanilla sweep --- +dc v_vanilla 0 3.3 0.1 +let i_vanilla = -i(v_vanilla) +wrdata vanilla.txt i_vanilla +*write tb_vcm.raw +* --- Run biased sweep --- +reset +*write tb_bcm.raw +dc v_biased 0 3.3 0.1 +let i_biased = -i(v_biased) +wrdata biased.txt i_biased +*write tb_bcm.raw +* --- Run cascode sweep --- +reset +*write tb_ccm.raw +dc v_cascode 0 3.3 0.1 +let i_cascode = -i(v_cascode) +wrdata cascode.txt i_cascode +*write tb_ccm.raw +.endc +"} +C {lab_wire.sym} -290 -300 2 0 {name=p6 sig_type=std_logic lab=BIAS +value=" +.options savecurrents +.param temp=27 +.control +set wr_singlescale +set noaskquit +*set appendwrite +set hcopypscolor=1 + +save all +op +*write tb_vcm.raw +* --- Run vanilla sweep --- +dc v_vanilla 0 3.3 0.1 +let i_vanilla = -i(v_vanilla) +wrdata vanilla.txt i_vanilla +*write tb_vcm.raw +* --- Run biased sweep --- +reset +*write tb_bcm.raw +dc v_biased 0 3.3 0.1 +let i_biased = -i(v_biased) +wrdata biased.txt i_biased +*write tb_bcm.raw +* --- Run cascode sweep --- +reset +*write tb_ccm.raw +dc v_cascode 0 3.3 0.1 +let i_cascode = -i(v_cascode) +wrdata cascode.txt i_cascode +*write tb_ccm.raw +.endc +"} +C {lab_wire.sym} -160 -220 0 0 {name=p7 sig_type=std_logic lab=IN +value=" +.options savecurrents +.param temp=27 +.control +set wr_singlescale +set noaskquit +*set appendwrite +set hcopypscolor=1 + +save all +op +*write tb_vcm.raw +* --- Run vanilla sweep --- +dc v_vanilla 0 3.3 0.1 +let i_vanilla = -i(v_vanilla) +wrdata vanilla.txt i_vanilla +*write tb_vcm.raw +* --- Run biased sweep --- +reset +*write tb_bcm.raw +dc v_biased 0 3.3 0.1 +let i_biased = -i(v_biased) +wrdata biased.txt i_biased +*write tb_bcm.raw +* --- Run cascode sweep --- +reset +*write tb_ccm.raw +dc v_cascode 0 3.3 0.1 +let i_cascode = -i(v_cascode) +wrdata cascode.txt i_cascode +*write tb_ccm.raw +.endc +"} +C {lab_wire.sym} -160 -180 0 0 {name=p8 sig_type=std_logic lab=BIAS +value=" +.options savecurrents +.param temp=27 +.control +set wr_singlescale +set noaskquit +*set appendwrite +set hcopypscolor=1 + +save all +op +*write tb_vcm.raw +* --- Run vanilla sweep --- +dc v_vanilla 0 3.3 0.1 +let i_vanilla = -i(v_vanilla) +wrdata vanilla.txt i_vanilla +*write tb_vcm.raw +* --- Run biased sweep --- +reset +*write tb_bcm.raw +dc v_biased 0 3.3 0.1 +let i_biased = -i(v_biased) +wrdata biased.txt i_biased +*write tb_bcm.raw +* --- Run cascode sweep --- +reset +*write tb_ccm.raw +dc v_cascode 0 3.3 0.1 +let i_cascode = -i(v_cascode) +wrdata cascode.txt i_cascode +*write tb_ccm.raw +.endc +"} +C {vsource.sym} -570 -240 0 0 {name=V3 value=0} +C {vsource.sym} 660 -180 0 0 {name=v_in value=1.65} +C {gnd.sym} 660 -150 0 0 {name=l2 lab=GND +value=" +.options savecurrents +.param temp=27 +.control +set wr_singlescale +set noaskquit +*set appendwrite +set hcopypscolor=1 + +save all +op +*write tb_vcm.raw +* --- Run vanilla sweep --- +dc v_vanilla 0 3.3 0.1 +let i_vanilla = -i(v_vanilla) +wrdata vanilla.txt i_vanilla +*write tb_vcm.raw +* --- Run biased sweep --- +reset +*write tb_bcm.raw +dc v_biased 0 3.3 0.1 +let i_biased = -i(v_biased) +wrdata biased.txt i_biased +*write tb_bcm.raw +* --- Run cascode sweep --- +reset +*write tb_ccm.raw +dc v_cascode 0 3.3 0.1 +let i_cascode = -i(v_cascode) +wrdata cascode.txt i_cascode +*write tb_ccm.raw +.endc +"} +C {res.sym} 660 -240 0 0 {name=R1 +footprint=1206 +device=resistor +m=1} diff --git a/blocks/composite/regulated_cascoded_cmirror/xschem/int_top_tb.sch b/blocks/composite/regulated_cascoded_cmirror/xschem/int_top_tb.sch new file mode 100644 index 00000000..ff3bdd89 --- /dev/null +++ b/blocks/composite/regulated_cascoded_cmirror/xschem/int_top_tb.sch @@ -0,0 +1,192 @@ +v {xschem version=3.4.7 file_version=1.2} +G {} +K {} +V {} +S {} +E {} +N 640 -410 970 -410 {lab=ENA} +N 1210 -220 1210 -210 {lab=VSS} +N 1210 -470 1210 -440 {lab=VDD} +N 730 -370 970 -370 {lab=VIN_INT} +N 850 -320 970 -320 {lab=VBIAS_INT} +N 320 -1180 500 -1180 {lab=#net1} +N 590 -1130 850 -1130 {lab=#net2} +N 380 -1160 380 -1150 {lab=#net2} +N 320 -1160 380 -1160 {lab=#net2} +N 780 -1140 780 -1100 {lab=VSS} +N 920 -1000 920 -980 {lab=VSS} +N 920 -1180 920 -1150 {lab=VDD} +N 780 -1310 780 -1290 {lab=VDD} +N 1210 -210 1210 -190 {lab=VSS} +N -110 -870 50 -870 {lab=VIN} +N -100 -620 60 -620 {lab=VBIAS} +N 250 -870 380 -870 {lab=#net3} +N 260 -620 370 -620 {lab=#net4} +N -120 -1200 60 -1200 {lab=EN} +N 1180 -1080 1220 -1080 {lab=#net5} +N 1210 -820 1250 -820 {lab=BCM_OUT_INT} +N 1220 -600 1250 -600 {lab=CCM_OUT_INT} +N 1410 -390 1500 -390 {lab=VCM_OUT_INT} +N 1500 -410 1500 -390 {lab=VCM_OUT_INT} +N 1500 -410 1570 -410 {lab=VCM_OUT_INT} +N 1410 -370 1570 -370 {lab=BCM_OUT_INT} +N 1410 -350 1500 -350 {lab=CCM_OUT_INT} +N 1500 -350 1500 -330 {lab=CCM_OUT_INT} +N 1500 -330 1570 -330 {lab=CCM_OUT_INT} +N 1420 -1080 1910 -1080 {lab=VCM_OUT} +N 1450 -600 1570 -600 {lab=BCM_OUT} +N 1450 -820 1910 -820 {lab=CCM_OUT} +N 1300 -1180 1300 -1160 {lab=VDD} +N 1340 -1180 1340 -1160 {lab=DVDD} +N 1300 -1000 1300 -980 {lab=VSS} +N 1340 -1000 1340 -980 {lab=DVSS} +N 1330 -930 1330 -900 {lab=VDD} +N 1370 -930 1370 -900 {lab=DVDD} +N 1330 -740 1330 -730 {lab=VSS} +N 1370 -740 1370 -730 {lab=DVSS} +N 1330 -710 1330 -680 {lab=VDD} +N 1370 -710 1370 -680 {lab=#net6} +N 1370 -520 1370 -500 {lab=DVSS} +N 1330 -520 1330 -500 {lab=VSS} +N 10 -340 90 -340 {lab=DVDD} +N 10 -280 90 -280 {lab=VDD} +N 270 -340 360 -340 {lab=DVSS} +N 270 -280 360 -280 {lab=VSS} +N 380 -1290 380 -1200 {lab=#net7} +N 580 -1290 610 -1290 {lab=ENA} +N 320 -1200 380 -1200 {lab=#net7} +N 500 -1160 710 -1160 {lab=#net1} +N 500 -1180 500 -1160 {lab=#net1} +N 380 -1130 590 -1130 {lab=#net2} +N 380 -1150 380 -1130 {lab=#net2} +N 1410 -410 1480 -410 {lab=VIN_OUT_INT} +N 1480 -440 1480 -410 {lab=VIN_OUT_INT} +N 1480 -440 1570 -440 {lab=VIN_OUT_INT} +N 1200 -1340 1230 -1340 {lab=VIN_OUT_INT} +N 1430 -1340 1550 -1340 {lab=VIN_OUT} +N 1310 -1450 1310 -1420 {lab=VDD} +N 1350 -1450 1350 -1420 {lab=DVDD} +N 1350 -1260 1350 -1240 {lab=DVSS} +N 1310 -1260 1310 -1240 {lab=VSS} +C {title.sym} 190 -90 0 0 {name=l1 author="Quentin Halbach and Sapta"} +C {lab_pin.sym} 140 -1280 0 0 {name=p105 lab=DVDD} +C {lab_pin.sym} 140 -1120 0 0 {name=p106 lab=DVSS} +C {lab_pin.sym} 180 -1280 0 1 {name=p109 lab=VDD} +C {lab_pin.sym} 180 -1120 0 1 {name=p110 lab=VSS} +C {ipin.sym} -120 -1200 0 0 {name=p120 lab=EN} +C {lab_pin.sym} 920 -1180 2 1 {name=p108 lab=VDD} +C {lab_pin.sym} 780 -1310 2 1 {name=p111 lab=VDD} +C {lab_pin.sym} 920 -980 2 1 {name=p164 lab=VSS} +C {iopin.sym} 90 -280 0 0 {name=p92 lab=VDD} +C {iopin.sym} 90 -340 0 0 {name=p181 lab=DVDD} +C {symbols/rm3.sym} 90 -310 2 0 {name=R1 +W=1e-6 +L=1e-6 +model=rm3 +spiceprefix=X +m=1} +C {iopin.sym} 360 -340 0 0 {name=p182 lab=DVSS} +C {iopin.sym} 360 -280 0 0 {name=p51 lab=VSS} +C {symbols/rm3.sym} 360 -310 2 0 {name=R2 +W=1e-6 +L=1e-6 +model=rm3 +spiceprefix=X +m=1} +C {Chipathon2025_pads/xschem/io_in_c.sym} 60 -1120 0 0 {name=IO6 +model=gf180mcu_fd_io__in_c +spiceprefix=X +} +C {Chipathon2025_pads/xschem/tieH.sym} 920 -1050 0 0 {name=x2} +C {Chipathon2025_pads/xschem/tieL.sym} 780 -1210 0 0 {name=x3} +C {lab_pin.sym} 610 -1290 0 1 {name=p1 lab=ENA} +C {lab_pin.sym} 780 -1100 2 1 {name=p2 lab=VSS} +C {lab_pin.sym} 1210 -470 2 1 {name=p3 lab=VDD} +C {lab_pin.sym} 1210 -190 2 1 {name=p4 lab=VSS} +C {lab_pin.sym} 640 -410 2 1 {name=p5 lab=ENA} +C {ipin.sym} -110 -870 0 0 {name=p6 lab=VIN} +C {ipin.sym} -100 -620 0 0 {name=p7 lab=VBIAS} +C {lab_pin.sym} 580 -870 0 1 {name=p8 lab=VIN_INT} +C {lab_pin.sym} 570 -620 0 1 {name=p9 lab=VBIAS_INT} +C {lab_pin.sym} 730 -370 2 1 {name=p10 lab=VIN_INT} +C {lab_pin.sym} 850 -320 2 1 {name=p11 lab=VBIAS_INT} +C {lab_pin.sym} 130 -790 0 0 {name=p12 lab=DVSS} +C {lab_pin.sym} 140 -540 0 0 {name=p13 lab=DVSS} +C {lab_pin.sym} 170 -790 0 1 {name=p14 lab=VSS} +C {lab_pin.sym} 180 -540 0 1 {name=p15 lab=VSS} +C {lab_pin.sym} 130 -950 0 0 {name=p16 lab=DVDD} +C {lab_pin.sym} 140 -700 0 0 {name=p17 lab=DVDD} +C {lab_pin.sym} 170 -950 0 1 {name=p18 lab=VDD} +C {lab_pin.sym} 180 -700 0 1 {name=p19 lab=VDD} +C {lab_pin.sym} 1210 -820 2 1 {name=p21 lab=BCM_OUT_INT} +C {lab_pin.sym} 1040 -1220 2 1 {name=p22 lab=VCM_OUT_INT} +C {lab_pin.sym} 1220 -600 2 1 {name=p23 lab=CCM_OUT_INT} +C {opin.sym} 1910 -1080 0 0 {name=p24 lab=VCM_OUT} +C {lab_pin.sym} 1570 -370 0 1 {name=p25 lab=BCM_OUT_INT} +C {lab_pin.sym} 1570 -410 0 1 {name=p26 lab=VCM_OUT_INT} +C {lab_pin.sym} 1570 -330 0 1 {name=p27 lab=CCM_OUT_INT} +C {opin.sym} 1570 -600 0 0 {name=p20 lab=BCM_OUT} +C {opin.sym} 1910 -820 0 0 {name=p28 lab=CCM_OUT} +C {lab_pin.sym} 1330 -930 2 1 {name=p29 lab=VDD} +C {lab_pin.sym} 1300 -1180 2 1 {name=p30 lab=VDD} +C {lab_pin.sym} 1330 -710 2 1 {name=p31 lab=VDD} +C {lab_pin.sym} 1300 -980 2 1 {name=p32 lab=VSS} +C {lab_pin.sym} 1330 -730 2 1 {name=p33 lab=VSS} +C {lab_pin.sym} 1330 -500 2 1 {name=p34 lab=VSS} +C {lab_pin.sym} 1340 -1180 2 0 {name=p35 lab=DVDD} +C {lab_pin.sym} 1370 -930 2 0 {name=p36 lab=DVDD} +C {lab_pin.sym} 1370 -710 2 0 {name=p37 lab=DVDD} +C {lab_pin.sym} 1370 -500 2 0 {name=p38 lab=DVSS} +C {lab_pin.sym} 1370 -730 2 0 {name=p39 lab=DVSS} +C {lab_pin.sym} 1340 -980 2 0 {name=p40 lab=DVSS} +C {lab_pin.sym} 10 -280 2 1 {name=p41 lab=VDD} +C {lab_pin.sym} 10 -340 0 0 {name=p42 lab=DVDD} +C {lab_pin.sym} 270 -280 2 1 {name=p43 lab=VSS} +C {lab_pin.sym} 270 -340 0 0 {name=p44 lab=DVSS} +C {Chipathon2025_pads/xschem/io_asig_5p0.sym} 50 -790 0 0 {name=IO1 +model=gf180mcu_fd_io__asig_5p0_extracted +spiceprefix=X +} +C {Chipathon2025_pads/xschem/io_asig_5p0.sym} 60 -540 0 0 {name=IO2 +model=gf180mcu_fd_io__asig_5p0_extracted +spiceprefix=X +} +C {Chipathon2025_pads/xschem/io_asig_5p0.sym} 1220 -1000 0 0 {name=IO3 +model=gf180mcu_fd_io__asig_5p0_extracted +spiceprefix=X +} +C {Chipathon2025_pads/xschem/io_asig_5p0.sym} 1250 -740 0 0 {name=IO4 +model=gf180mcu_fd_io__asig_5p0_extracted +spiceprefix=X +} +C {Chipathon2025_pads/xschem/io_asig_5p0.sym} 1250 -520 0 0 {name=IO5 +model=gf180mcu_fd_io__asig_5p0_extracted +spiceprefix=X +} +C {lab_pin.sym} 500 -950 2 1 {name=p45 lab=VDD} +C {lab_pin.sym} 500 -790 2 1 {name=p46 lab=VSS} +C {lab_pin.sym} 490 -700 2 1 {name=p47 lab=VDD} +C {lab_pin.sym} 490 -540 2 1 {name=p48 lab=VSS} +C {Chipathon2025_pads/xschem/symbols/io_secondary_5p0/io_secondary_5p0.sym} 580 -790 0 1 {name=IO9 +spiceprefix=X +} +C {Chipathon2025_pads/xschem/symbols/io_secondary_5p0/io_secondary_5p0.sym} 570 -540 0 1 {name=IO7 +spiceprefix=X +} +C {Chipathon2025_pads/xschem/symbols/io_secondary_5p0/io_secondary_5p0.sym} 580 -1210 0 1 {name=IO8 +spiceprefix=X +} +C {lab_pin.sym} 500 -1370 2 1 {name=p49 lab=VDD} +C {lab_pin.sym} 500 -1210 2 1 {name=p50 lab=VSS} +C {lab_pin.sym} 1570 -440 0 1 {name=p52 lab=VIN_OUT_INT} +C {lab_pin.sym} 1200 -1340 2 1 {name=p53 lab=VIN_OUT_INT} +C {opin.sym} 1550 -1340 0 0 {name=p54 lab=VIN_OUT} +C {lab_pin.sym} 1310 -1450 2 1 {name=p55 lab=VDD} +C {lab_pin.sym} 1310 -1240 2 1 {name=p56 lab=VSS} +C {lab_pin.sym} 1350 -1450 2 0 {name=p57 lab=DVDD} +C {lab_pin.sym} 1350 -1240 2 0 {name=p58 lab=DVSS} +C {Chipathon2025_pads/xschem/io_asig_5p0.sym} 1230 -1260 0 0 {name=IO11 +model=gf180mcu_fd_io__asig_5p0_extracted +spiceprefix=X +} +C {top_level.sym} 1210 -330 0 0 {name=x4} diff --git a/blocks/composite/regulated_cascoded_cmirror/xschem/int_top_tb.sym b/blocks/composite/regulated_cascoded_cmirror/xschem/int_top_tb.sym new file mode 100644 index 00000000..445d5225 --- /dev/null +++ b/blocks/composite/regulated_cascoded_cmirror/xschem/int_top_tb.sym @@ -0,0 +1,45 @@ +v {xschem version=3.4.7 file_version=1.2} +G {} +K {type=subcircuit +format="@name @pinlist @symname" +template="name=x1" +} +V {} +S {} +E {} +L 4 130 -20 150 -20 {} +L 4 -150 -40 -130 -40 {} +L 4 130 10 150 10 {} +L 4 130 40 150 40 {} +L 4 -150 0 -130 0 {} +L 4 -150 40 -130 40 {} +L 4 130 -50 150 -50 {} +L 7 -30 60 -30 80 {} +L 7 -40 -80 -40 -60 {} +L 7 30 -80 30 -60 {} +L 7 40 60 40 80 {} +B 5 147.5 -22.5 152.5 -17.5 {name=VCM_OUT dir=out} +B 5 -152.5 -42.5 -147.5 -37.5 {name=EN dir=in} +B 5 147.5 7.5 152.5 12.5 {name=BCM_OUT dir=out} +B 5 147.5 37.5 152.5 42.5 {name=CCM_OUT dir=out} +B 5 -152.5 -2.5 -147.5 2.5 {name=VIN dir=in} +B 5 -32.5 77.5 -27.5 82.5 {name=DVSS dir=inout} +B 5 -42.5 -82.5 -37.5 -77.5 {name=DVDD dir=inout} +B 5 27.5 -82.5 32.5 -77.5 {name=VDD dir=inout} +B 5 37.5 77.5 42.5 82.5 {name=VSS dir=inout} +B 5 -152.5 37.5 -147.5 42.5 {name=VBIAS dir=in} +B 5 147.5 -52.5 152.5 -47.5 {name=VIN_OUT dir=out} +P 4 5 130 -70 -130 -70 -130 70 130 70 130 -70 {} +T {@symname} -63 -6 0 0 0.3 0.3 {} +T {@name} 135 -82 0 0 0.2 0.2 {} +T {VCM_OUT} 125 -24 0 1 0.2 0.2 {} +T {EN} -125 -44 0 0 0.2 0.2 {} +T {BCM_OUT} 125 6 0 1 0.2 0.2 {} +T {CCM_OUT} 125 36 0 1 0.2 0.2 {} +T {VIN} -125 -4 0 0 0.2 0.2 {} +T {DVSS} -26 55 1 1 0.2 0.2 {} +T {DVDD} -44 -55 3 1 0.2 0.2 {} +T {VDD} 26 -55 3 1 0.2 0.2 {} +T {VSS} 44 55 1 1 0.2 0.2 {} +T {VBIAS} -125 36 0 0 0.2 0.2 {} +T {VIN_OUT} 125 -54 0 1 0.2 0.2 {} diff --git a/blocks/composite/regulated_cascoded_cmirror/xschem/simulation/bias.spice b/blocks/composite/regulated_cascoded_cmirror/xschem/simulation/bias.spice new file mode 100644 index 00000000..b58ced0b --- /dev/null +++ b/blocks/composite/regulated_cascoded_cmirror/xschem/simulation/bias.spice @@ -0,0 +1,37 @@ +** sch_path: /foss/designs/gLayout-mahowalders/blocks/composite/regulated_cascoded_cmirror/xschem/bias.sch +**.subckt bias VDD ENA bias_in bias_out vss +*.iopin vss +*.iopin VDD +*.ipin ENA +*.ipin bias_in +*.opin bias_out +XM11 net1 net1 VDD VDD pfet_03v3 L=2.0u W=100.0u nf=10 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=1 +XM12 bias_in bias_in net1 VDD pfet_03v3 L=2.0u W=100.0u nf=10 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=1 +XM16 net1 ENA VDD VDD pfet_03v3 L=2.0u W=10.0u nf=1 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=1 +XM17 net2 net1 VDD VDD pfet_03v3 L=2.0u W=10.0u nf=1 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=1 +XM19 net3 bias_in net2 VDD pfet_03v3 L=2.0u W=10.0u nf=1 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=1 +XM9 net4 net4 VDD VDD pfet_03v3 L=2.0u W=100.0u nf=10 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=1 +XM10 net5 net5 net4 VDD pfet_03v3 L=2.0u W=100.0u nf=10 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=1 +XM13 net4 ENA VDD VDD pfet_03v3 L=2.0u W=10.0u nf=1 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=1 +XM20 net6 net4 VDD VDD pfet_03v3 L=2.0u W=10.0u nf=1 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=1 +XM21 bias_out net5 net6 VDD pfet_03v3 L=2.0u W=10.0u nf=10 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=1 +XM22 net8 net7 vss vss nfet_03v3 L=1u W=8u nf=1 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=1 +XM23 net7 net7 vss vss nfet_03v3 L=1u W=80u nf=10 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=1 +XM24 net5 net3 net8 vss nfet_03v3 L=1u W=8u nf=1 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=1 +XM25 net3 net3 net7 vss nfet_03v3 L=1u W=80u nf=10 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=1 +**.ends +.end diff --git a/blocks/composite/regulated_cascoded_cmirror/xschem/simulation/biased.txt b/blocks/composite/regulated_cascoded_cmirror/xschem/simulation/biased.txt new file mode 100644 index 00000000..af3db35f --- /dev/null +++ b/blocks/composite/regulated_cascoded_cmirror/xschem/simulation/biased.txt @@ -0,0 +1,67 @@ + 0.00000000e+00 -1.20612118e-11 + 5.00000000e-02 3.38914759e-06 + 1.00000000e-01 6.06682285e-06 + 1.50000000e-01 7.99481540e-06 + 2.00000000e-01 9.15235788e-06 + 2.50000000e-01 9.65090203e-06 + 3.00000000e-01 9.82100609e-06 + 3.50000000e-01 9.89489510e-06 + 4.00000000e-01 9.93840553e-06 + 4.50000000e-01 9.96772647e-06 + 5.00000000e-01 9.98662838e-06 + 5.50000000e-01 9.99568869e-06 + 6.00000000e-01 9.99845562e-06 + 6.50000000e-01 9.99926273e-06 + 7.00000000e-01 9.99968435e-06 + 7.50000000e-01 9.99996381e-06 + 8.00000000e-01 1.00001848e-05 + 8.50000000e-01 1.00003754e-05 + 9.00000000e-01 1.00005439e-05 + 9.50000000e-01 1.00006988e-05 + 1.00000000e+00 1.00008448e-05 + 1.05000000e+00 1.00009821e-05 + 1.10000000e+00 1.00011142e-05 + 1.15000000e+00 1.00012395e-05 + 1.20000000e+00 1.00013620e-05 + 1.25000000e+00 1.00014787e-05 + 1.30000000e+00 1.00015939e-05 + 1.35000000e+00 1.00017060e-05 + 1.40000000e+00 1.00018184e-05 + 1.45000000e+00 1.00019248e-05 + 1.50000000e+00 1.00020302e-05 + 1.55000000e+00 1.00021376e-05 + 1.60000000e+00 1.00022397e-05 + 1.65000000e+00 1.00023415e-05 + 1.70000000e+00 1.00024433e-05 + 1.75000000e+00 1.00025418e-05 + 1.80000000e+00 1.00026423e-05 + 1.85000000e+00 1.00027413e-05 + 1.90000000e+00 1.00028404e-05 + 1.95000000e+00 1.00029441e-05 + 2.00000000e+00 1.00030521e-05 + 2.05000000e+00 1.00031659e-05 + 2.10000000e+00 1.00032883e-05 + 2.15000000e+00 1.00034270e-05 + 2.20000000e+00 1.00035798e-05 + 2.25000000e+00 1.00037686e-05 + 2.30000000e+00 1.00039903e-05 + 2.35000000e+00 1.00042601e-05 + 2.40000000e+00 1.00045967e-05 + 2.45000000e+00 1.00050165e-05 + 2.50000000e+00 1.00055359e-05 + 2.55000000e+00 1.00061865e-05 + 2.60000000e+00 1.00069868e-05 + 2.65000000e+00 1.00079734e-05 + 2.70000000e+00 1.00091816e-05 + 2.75000000e+00 1.00106474e-05 + 2.80000000e+00 1.00124205e-05 + 2.85000000e+00 1.00145516e-05 + 2.90000000e+00 1.00170908e-05 + 2.95000000e+00 1.00200908e-05 + 3.00000000e+00 1.00236169e-05 + 3.05000000e+00 1.00277370e-05 + 3.10000000e+00 1.00325242e-05 + 3.15000000e+00 1.00380514e-05 + 3.20000000e+00 1.00443946e-05 + 3.25000000e+00 1.00516408e-05 + 3.30000000e+00 1.00598814e-05 diff --git a/blocks/composite/regulated_cascoded_cmirror/xschem/simulation/cascode.txt b/blocks/composite/regulated_cascoded_cmirror/xschem/simulation/cascode.txt new file mode 100644 index 00000000..c2394263 --- /dev/null +++ b/blocks/composite/regulated_cascoded_cmirror/xschem/simulation/cascode.txt @@ -0,0 +1,67 @@ + 0.00000000e+00 -1.19468780e-11 + 5.00000000e-02 3.73676380e-06 + 1.00000000e-01 6.56190344e-06 + 1.50000000e-01 8.41161964e-06 + 2.00000000e-01 9.30548503e-06 + 2.50000000e-01 9.59004677e-06 + 3.00000000e-01 9.69014273e-06 + 3.50000000e-01 9.74512095e-06 + 4.00000000e-01 9.78423907e-06 + 4.50000000e-01 9.81567562e-06 + 5.00000000e-01 9.84258909e-06 + 5.50000000e-01 9.86646809e-06 + 6.00000000e-01 9.88811634e-06 + 6.50000000e-01 9.90798302e-06 + 7.00000000e-01 9.92629712e-06 + 7.50000000e-01 9.94311480e-06 + 8.00000000e-01 9.95831816e-06 + 8.50000000e-01 9.97158706e-06 + 9.00000000e-01 9.98239027e-06 + 9.50000000e-01 9.99007236e-06 + 1.00000000e+00 9.99425242e-06 + 1.05000000e+00 9.99571722e-06 + 1.10000000e+00 9.99618597e-06 + 1.15000000e+00 9.99638822e-06 + 1.20000000e+00 9.99652047e-06 + 1.25000000e+00 9.99662790e-06 + 1.30000000e+00 9.99672183e-06 + 1.35000000e+00 9.99680889e-06 + 1.40000000e+00 9.99688728e-06 + 1.45000000e+00 9.99696475e-06 + 1.50000000e+00 9.99703867e-06 + 1.55000000e+00 9.99710536e-06 + 1.60000000e+00 9.99717631e-06 + 1.65000000e+00 9.99724566e-06 + 1.70000000e+00 9.99730766e-06 + 1.75000000e+00 9.99736676e-06 + 1.80000000e+00 9.99742877e-06 + 1.85000000e+00 9.99749487e-06 + 1.90000000e+00 9.99755642e-06 + 1.95000000e+00 9.99761828e-06 + 2.00000000e+00 9.99767469e-06 + 2.05000000e+00 9.99773622e-06 + 2.10000000e+00 9.99778834e-06 + 2.15000000e+00 9.99785208e-06 + 2.20000000e+00 9.99791276e-06 + 2.25000000e+00 9.99796443e-06 + 2.30000000e+00 9.99802735e-06 + 2.35000000e+00 9.99808828e-06 + 2.40000000e+00 9.99814361e-06 + 2.45000000e+00 9.99821843e-06 + 2.50000000e+00 9.99829255e-06 + 2.55000000e+00 9.99836912e-06 + 2.60000000e+00 9.99845944e-06 + 2.65000000e+00 9.99858007e-06 + 2.70000000e+00 9.99872902e-06 + 2.75000000e+00 9.99890145e-06 + 2.80000000e+00 9.99912960e-06 + 2.85000000e+00 9.99941228e-06 + 2.90000000e+00 9.99977268e-06 + 2.95000000e+00 1.00002406e-05 + 3.00000000e+00 1.00008295e-05 + 3.05000000e+00 1.00015581e-05 + 3.10000000e+00 1.00024797e-05 + 3.15000000e+00 1.00036078e-05 + 3.20000000e+00 1.00049823e-05 + 3.25000000e+00 1.00066705e-05 + 3.30000000e+00 1.00086950e-05 diff --git a/blocks/composite/regulated_cascoded_cmirror/xschem/simulation/int_top_lvs.spice b/blocks/composite/regulated_cascoded_cmirror/xschem/simulation/int_top_lvs.spice new file mode 100644 index 00000000..d1cdf886 --- /dev/null +++ b/blocks/composite/regulated_cascoded_cmirror/xschem/simulation/int_top_lvs.spice @@ -0,0 +1,220 @@ +** sch_path: /foss/designs/gLayout-mahowalders/blocks/composite/regulated_cascoded_cmirror/xschem/int_top_lvs.sch +**.subckt int_top_lvs EN VDD VSS VIN VBIAS VCM_OUT BCM_OUT CCM_OUT VIN_OUT PU PD +*.ipin EN +*.iopin VDD +*.iopin VSS +*.ipin VIN +*.ipin VBIAS +*.opin VCM_OUT +*.opin BCM_OUT +*.opin CCM_OUT +*.opin VIN_OUT +*.ipin PU +*.ipin PD +x2 PD VDD VSS tieH +x3 VDD PU VSS tieL +XIO8 VDD ENA EN VSS io_secondary_5p0 +x1 VDD ENA VIN_INT VCM_OUT BCM_OUT CCM_OUT VBIAS_INT VSS VIN_OUT top_level +XIO1 VDD VIN_INT VIN VSS io_secondary_5p0 +XIO2 VDD VBIAS_INT VBIAS VSS io_secondary_5p0 +**.ends + +* expanding symbol: Chipathon2025_pads/xschem/tieH.sym # of pins=3 +** sym_path: /foss/designs/gLayout-mahowalders/blocks/composite/regulated_cascoded_cmirror/xschem/Chipathon2025_pads/xschem/tieH.sym +** sch_path: /foss/designs/gLayout-mahowalders/blocks/composite/regulated_cascoded_cmirror/xschem/Chipathon2025_pads/xschem/tieH.sch +.subckt tieH TIEH VDD VSS +*.iopin VSS +*.iopin VDD +*.iopin TIEH +XM1 TIEH net1 VDD VDD pfet_06v0 L=0.55u W=2u nf=1 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=1 +XM2 net1 net1 VSS VSS nfet_06v0 L=0.70u W=1u nf=1 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=1 +.ends + + +* expanding symbol: Chipathon2025_pads/xschem/tieL.sym # of pins=3 +** sym_path: /foss/designs/gLayout-mahowalders/blocks/composite/regulated_cascoded_cmirror/xschem/Chipathon2025_pads/xschem/tieL.sym +** sch_path: /foss/designs/gLayout-mahowalders/blocks/composite/regulated_cascoded_cmirror/xschem/Chipathon2025_pads/xschem/tieL.sch +.subckt tieL VDD TIEL VSS +*.iopin VSS +*.iopin VDD +*.iopin TIEL +XM3 net1 net1 VDD VDD pfet_06v0 L=0.55u W=2u nf=1 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=1 +XM4 TIEL net1 VSS VSS nfet_06v0 L=0.70u W=1u nf=1 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=1 +.ends + + +* expanding symbol: Chipathon2025_pads/xschem/symbols/io_secondary_5p0/io_secondary_5p0.sym # of pins=4 +** sym_path: /foss/designs/gLayout-mahowalders/blocks/composite/regulated_cascoded_cmirror/xschem/Chipathon2025_pads/xschem/symbols/io_secondary_5p0/io_secondary_5p0.sym +** sch_path: /foss/designs/gLayout-mahowalders/blocks/composite/regulated_cascoded_cmirror/xschem/Chipathon2025_pads/xschem/symbols/io_secondary_5p0/io_secondary_5p0.sch +.subckt io_secondary_5p0 VDD to_gate ASIG5V VSS + + +*.iopin VSS +*.iopin VDD +*.iopin to_gate +*.iopin ASIG5V +D1 to_gate VDD diode_pd2nw_06v0 area='10u * 10u ' pj='2*10u + 2*10u ' m=4 +XR1 to_gate ASIG5V VDD ppolyf_u r_width=16e-6 r_length=4e-6 m=1 +D2 VSS to_gate diode_nd2ps_06v0 area='10u * 10u ' pj='2*10u + 2*10u ' m=4 +.ends + + +* expanding symbol: top_level.sym # of pins=9 +** sym_path: /foss/designs/gLayout-mahowalders/blocks/composite/regulated_cascoded_cmirror/xschem/top_level.sym +** sch_path: /foss/designs/gLayout-mahowalders/blocks/composite/regulated_cascoded_cmirror/xschem/top_level.sch +.subckt top_level VDD EN V_IN V_OUT_VCM V_OUT_BCM V_OUT_CCM V_AUX_CCM VSS V_OUT_VIN +*.iopin VSS +*.ipin V_AUX_CCM +*.iopin VDD +*.opin V_OUT_VCM +*.opin V_OUT_BCM +*.opin V_OUT_CCM +*.ipin V_IN +*.ipin EN +*.opin V_OUT_VIN +XM1 net1 net1 VDD VDD pfet_03v3 L=2.0u W=10.0u nf=1 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=1 +XM2 V_IN V_IN net1 VDD pfet_03v3 L=2.0u W=10.0u nf=1 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=1 +XM3 net2 net1 VDD VDD pfet_03v3 L=2.0u W=10.0u nf=1 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=1 +XM4 net3 V_IN net2 VDD pfet_03v3 L=2.0u W=10.0u nf=1 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=1 +XM5 net7 net1 VDD VDD pfet_03v3 L=2.0u W=10.0u nf=1 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=1 +XM6 net4 V_IN net7 VDD pfet_03v3 L=2.0u W=10.0u nf=1 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=1 +XM7 net6 net1 VDD VDD pfet_03v3 L=2.0u W=10.0u nf=1 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=1 +XM8 net5 V_IN net6 VDD pfet_03v3 L=2.0u W=10.0u nf=1 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=1 +XM14 net1 EN VDD VDD pfet_03v3 L=2.0u W=10.0u nf=1 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=1 +XM18 net1 EN VDD VDD pfet_03v3 L=2.0u W=10.0u nf=1 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=1 +XM15 net1 EN VDD VDD pfet_03v3 L=2.0u W=10.0u nf=1 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=1 +x1 net3 V_OUT_VCM VSS vanilla_cm +x2 V_OUT_BCM net4 VSS biased_cm +x3 V_OUT_CCM net8 net5 VSS cascode_cm +x4 VDD EN V_AUX_CCM net8 VSS bias +XM9 net9 net1 VDD VDD pfet_03v3 L=2.0u W=10.0u nf=1 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=1 +XM10 V_OUT_VIN V_IN net9 VDD pfet_03v3 L=2.0u W=10.0u nf=1 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=1 +XM11 net1 EN VDD VDD pfet_03v3 L=2.0u W=10.0u nf=1 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=1 +XM12 VDD VDD VDD VDD pfet_03v3 L=2.0u W=10.0u nf=1 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=6 +.ends + + +* expanding symbol: vanilla_cm.sym # of pins=3 +** sym_path: /foss/designs/gLayout-mahowalders/blocks/composite/regulated_cascoded_cmirror/xschem/vanilla_cm.sym +** sch_path: /foss/designs/gLayout-mahowalders/blocks/composite/regulated_cascoded_cmirror/xschem/vanilla_cm.sch +.subckt vanilla_cm v_in v_out vss +*.ipin v_in +*.iopin vss +*.opin v_out +XM1 v_out v_in vss vss nfet_03v3 L=1u W=4u nf=1 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=1 +XM2 v_in v_in vss vss nfet_03v3 L=1u W=4u nf=1 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=1 +XM3 vss vss vss vss nfet_03v3 L=1u W=4u nf=1 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=2 +.ends + + +* expanding symbol: biased_cm.sym # of pins=3 +** sym_path: /foss/designs/gLayout-mahowalders/blocks/composite/regulated_cascoded_cmirror/xschem/biased_cm.sym +** sch_path: /foss/designs/gLayout-mahowalders/blocks/composite/regulated_cascoded_cmirror/xschem/biased_cm.sch +.subckt biased_cm v_out v_in vss +*.ipin v_in +*.iopin vss +*.opin v_out +XM3 net2 net1 vss vss nfet_03v3 L=1u W=4u nf=1 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=1 +XM4 net1 net1 vss vss nfet_03v3 L=1u W=4u nf=1 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=1 +XM5 v_out v_in net2 vss nfet_03v3 L=1u W=4u nf=1 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=1 +XM6 v_in v_in net1 vss nfet_03v3 L=1u W=4u nf=1 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=1 +XM1 vss vss vss vss nfet_03v3 L=1u W=4u nf=1 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=4 +.ends + + +* expanding symbol: cascode_cm.sym # of pins=4 +** sym_path: /foss/designs/gLayout-mahowalders/blocks/composite/regulated_cascoded_cmirror/xschem/cascode_cm.sym +** sch_path: /foss/designs/gLayout-mahowalders/blocks/composite/regulated_cascoded_cmirror/xschem/cascode_cm.sch +.subckt cascode_cm v_out v_aux v_in vss +*.ipin v_in +*.iopin vss +*.ipin v_aux +*.opin v_out +XM10 v_aux net1 vss vss nfet_03v3 L=1u W=8u nf=2 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=1 +XM8 v_in v_aux net1 vss nfet_03v3 L=1u W=8u nf=2 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=1 +XM11 net1 v_in vss vss nfet_03v3 L=1u W=8u nf=2 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=1 +XM12 v_aux net2 vss vss nfet_03v3 L=1u W=8u nf=2 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=1 +XM13 net2 v_in vss vss nfet_03v3 L=1u W=8u nf=2 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=1 +XM14 v_out v_aux net2 vss nfet_03v3 L=1u W=8u nf=2 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=1 +XM1 vss vss vss vss nfet_03v3 L=1u W=4u nf=1 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=6 +.ends + + +* expanding symbol: bias.sym # of pins=5 +** sym_path: /foss/designs/gLayout-mahowalders/blocks/composite/regulated_cascoded_cmirror/xschem/bias.sym +** sch_path: /foss/designs/gLayout-mahowalders/blocks/composite/regulated_cascoded_cmirror/xschem/bias.sch +.subckt bias VDD ENA bias_in bias_out vss +*.iopin vss +*.iopin VDD +*.ipin ENA +*.ipin bias_in +*.opin bias_out +XM11 net1 net1 VDD VDD pfet_03v3 L=2.0u W=100.0u nf=10 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=1 +XM12 bias_in bias_in net1 VDD pfet_03v3 L=2.0u W=100.0u nf=10 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=1 +XM16 net1 ENA VDD VDD pfet_03v3 L=2.0u W=10.0u nf=1 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=1 +XM17 net2 net1 VDD VDD pfet_03v3 L=2.0u W=10.0u nf=1 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=1 +XM19 net3 bias_in net2 VDD pfet_03v3 L=2.0u W=10.0u nf=1 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=1 +XM9 net4 net4 VDD VDD pfet_03v3 L=2.0u W=100.0u nf=10 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=1 +XM10 net5 net5 net4 VDD pfet_03v3 L=2.0u W=100.0u nf=10 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=1 +XM13 net4 ENA VDD VDD pfet_03v3 L=2.0u W=10.0u nf=1 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=1 +XM20 net6 net4 VDD VDD pfet_03v3 L=2.0u W=10.0u nf=1 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=1 +XM21 bias_out net5 net6 VDD pfet_03v3 L=2.0u W=10.0u nf=10 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=1 +XM22 net8 net7 vss vss nfet_03v3 L=1u W=8u nf=1 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=1 +XM23 net7 net7 vss vss nfet_03v3 L=1u W=80u nf=10 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=1 +XM24 net5 net3 net8 vss nfet_03v3 L=1u W=8u nf=1 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=1 +XM25 net3 net3 net7 vss nfet_03v3 L=1u W=80u nf=10 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=1 +XM1 VDD VDD VDD VDD pfet_03v3 L=2.0u W=10.0u nf=1 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=12 +XM2 vss vss vss vss nfet_03v3 L=1u W=8u nf=1 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=4 +.ends + +.end diff --git a/blocks/composite/regulated_cascoded_cmirror/xschem/simulation/vanilla.txt b/blocks/composite/regulated_cascoded_cmirror/xschem/simulation/vanilla.txt new file mode 100644 index 00000000..ca0ca878 --- /dev/null +++ b/blocks/composite/regulated_cascoded_cmirror/xschem/simulation/vanilla.txt @@ -0,0 +1,67 @@ + 0.00000000e+00 -1.18401964e-11 + 5.00000000e-02 4.03040083e-06 + 1.00000000e-01 6.93219569e-06 + 1.50000000e-01 8.68130901e-06 + 2.00000000e-01 9.41408477e-06 + 2.50000000e-01 9.62853110e-06 + 3.00000000e-01 9.71191053e-06 + 3.50000000e-01 9.76180953e-06 + 4.00000000e-01 9.79890387e-06 + 4.50000000e-01 9.82947590e-06 + 5.00000000e-01 9.85611290e-06 + 5.50000000e-01 9.88011491e-06 + 6.00000000e-01 9.90222462e-06 + 6.50000000e-01 9.92290700e-06 + 7.00000000e-01 9.94247262e-06 + 7.50000000e-01 9.96114181e-06 + 8.00000000e-01 9.97907190e-06 + 8.50000000e-01 9.99638415e-06 + 9.00000000e-01 1.00131744e-05 + 9.50000000e-01 1.00295108e-05 + 1.00000000e+00 1.00454575e-05 + 1.05000000e+00 1.00610576e-05 + 1.10000000e+00 1.00763526e-05 + 1.15000000e+00 1.00913799e-05 + 1.20000000e+00 1.01061630e-05 + 1.25000000e+00 1.01207261e-05 + 1.30000000e+00 1.01350900e-05 + 1.35000000e+00 1.01492736e-05 + 1.40000000e+00 1.01632938e-05 + 1.45000000e+00 1.01771618e-05 + 1.50000000e+00 1.01908938e-05 + 1.55000000e+00 1.02044962e-05 + 1.60000000e+00 1.02179874e-05 + 1.65000000e+00 1.02313670e-05 + 1.70000000e+00 1.02446529e-05 + 1.75000000e+00 1.02578564e-05 + 1.80000000e+00 1.02709926e-05 + 1.85000000e+00 1.02840642e-05 + 1.90000000e+00 1.02970939e-05 + 1.95000000e+00 1.03100844e-05 + 2.00000000e+00 1.03230715e-05 + 2.05000000e+00 1.03360725e-05 + 2.10000000e+00 1.03490966e-05 + 2.15000000e+00 1.03621864e-05 + 2.20000000e+00 1.03753651e-05 + 2.25000000e+00 1.03886698e-05 + 2.30000000e+00 1.04021480e-05 + 2.35000000e+00 1.04158384e-05 + 2.40000000e+00 1.04297856e-05 + 2.45000000e+00 1.04440448e-05 + 2.50000000e+00 1.04586917e-05 + 2.55000000e+00 1.04737694e-05 + 2.60000000e+00 1.04893666e-05 + 2.65000000e+00 1.05055629e-05 + 2.70000000e+00 1.05224402e-05 + 2.75000000e+00 1.05400906e-05 + 2.80000000e+00 1.05586151e-05 + 2.85000000e+00 1.05781206e-05 + 2.90000000e+00 1.05987213e-05 + 2.95000000e+00 1.06205251e-05 + 3.00000000e+00 1.06436707e-05 + 3.05000000e+00 1.06682871e-05 + 3.10000000e+00 1.06945266e-05 + 3.15000000e+00 1.07225201e-05 + 3.20000000e+00 1.07524374e-05 + 3.25000000e+00 1.07844241e-05 + 3.30000000e+00 1.08186792e-05 diff --git a/blocks/composite/regulated_cascoded_cmirror/xschem/top_level.sch b/blocks/composite/regulated_cascoded_cmirror/xschem/top_level.sch new file mode 100644 index 00000000..cbd06544 --- /dev/null +++ b/blocks/composite/regulated_cascoded_cmirror/xschem/top_level.sch @@ -0,0 +1,336 @@ +v {xschem version=3.4.7 file_version=1.2} +G {} +K {} +V {} +S {} +E {} +N -20 -910 0 -910 {lab=VDD} +N 510 -910 510 -740 {lab=VDD} +N 740 -910 740 -740 {lab=VDD} +N 630 -910 630 -850 {lab=VDD} +N 550 -710 700 -710 {lab=#net1} +N 630 -790 630 -710 {lab=#net1} +N 550 -590 700 -590 {lab=V_IN} +N 510 -680 510 -620 {lab=#net1} +N 740 -680 740 -620 {lab=#net2} +N 630 -710 630 -650 {lab=#net1} +N 510 -650 630 -650 {lab=#net1} +N 1010 -910 1010 -740 {lab=VDD} +N 870 -910 870 -850 {lab=VDD} +N 1120 -910 1120 -850 {lab=VDD} +N 740 -560 740 -470 {lab=#net3} +N 980 -470 2020 -470 {lab=V_OUT_VCM} +N 1010 -560 1010 -340 {lab=#net4} +N 1250 -340 2030 -340 {lab=V_OUT_BCM} +N 1350 -560 1350 -240 {lab=#net5} +N 1350 -910 1350 -740 {lab=VDD} +N 1350 -680 1350 -620 {lab=#net6} +N 630 -760 1310 -760 {lab=#net1} +N 1310 -760 1310 -710 {lab=#net1} +N 910 -710 970 -710 {lab=#net1} +N 910 -760 910 -710 {lab=#net1} +N 1010 -680 1010 -620 {lab=#net7} +N 870 -790 870 -760 {lab=#net1} +N 1120 -790 1120 -760 {lab=#net1} +N 1080 -880 1080 -820 {lab=EN} +N -20 -880 1080 -880 {lab=EN} +N 550 -820 590 -820 {lab=EN} +N 550 -880 550 -820 {lab=EN} +N 790 -820 830 -820 {lab=EN} +N 790 -880 790 -820 {lab=EN} +N 1310 -650 1310 -590 {lab=V_IN} +N 660 -650 660 -590 {lab=V_IN} +N 660 -650 1310 -650 {lab=V_IN} +N 920 -590 970 -590 {lab=V_IN} +N 920 -650 920 -590 {lab=V_IN} +N 1590 -240 2040 -240 {lab=V_OUT_CCM} +N 620 -200 1350 -200 {lab=#net8} +N 1120 -910 1350 -910 {lab=VDD} +N 1010 -910 1120 -910 {lab=VDD} +N 870 -910 1010 -910 {lab=VDD} +N 740 -910 870 -910 {lab=VDD} +N 630 -910 740 -910 {lab=VDD} +N 510 -910 630 -910 {lab=VDD} +N 160 -910 510 -910 {lab=VDD} +N 1470 -150 1470 -70 {lab=VSS} +N 1130 -250 1130 -70 {lab=VSS} +N 860 -380 860 -70 {lab=VSS} +N -20 -520 510 -520 {lab=V_IN} +N 510 -520 630 -520 {lab=V_IN} +N 630 -590 630 -520 {lab=V_IN} +N 510 -560 510 -520 {lab=V_IN} +N -30 -50 1470 -50 {lab=VSS} +N 1470 -70 1470 -50 {lab=VSS} +N 1130 -70 1130 -50 {lab=VSS} +N 860 -70 860 -50 {lab=VSS} +N 500 -110 500 -50 {lab=VSS} +N 340 -200 380 -200 {lab=V_AUX_CCM} +N 330 -220 380 -220 {lab=EN} +N 330 -880 330 -220 {lab=EN} +N -10 -200 340 -200 {lab=V_AUX_CCM} +N 500 -260 500 -230 {lab=VDD} +N 1610 -910 1610 -740 {lab=VDD} +N 1610 -680 1610 -620 {lab=#net9} +N 1570 -760 1570 -710 {lab=#net1} +N 1570 -650 1570 -590 {lab=V_IN} +N 1300 -760 1570 -760 {lab=#net1} +N 1310 -650 1570 -650 {lab=V_IN} +N 1350 -910 1610 -910 {lab=VDD} +N 1470 -790 1470 -760 {lab=#net1} +N 1470 -910 1470 -850 {lab=VDD} +N 1080 -880 1430 -880 {lab=EN} +N 1430 -880 1430 -820 {lab=EN} +N 1610 -560 2020 -560 {lab=V_OUT_VIN} +N 1610 -910 1710 -910 {lab=VDD} +N 1710 -910 1710 -870 {lab=VDD} +N 1670 -910 1670 -840 {lab=VDD} +N 1710 -810 1730 -810 {lab=VDD} +N 1730 -910 1730 -810 {lab=VDD} +N 1710 -910 1730 -910 {lab=VDD} +N 1710 -840 1730 -840 {lab=VDD} +C {iopin.sym} -30 -50 2 0 {name=p1 lab=VSS +} +C {ipin.sym} -10 -200 0 0 {name=p3 lab=V_AUX_CCM +} +C {iopin.sym} -20 -910 2 0 {name=p4 lab=VDD +} +C {opin.sym} 2020 -470 0 0 {name=p5 lab=V_OUT_VCM} +C {opin.sym} 2030 -340 0 0 {name=p6 lab=V_OUT_BCM} +C {opin.sym} 2040 -240 0 0 {name=p7 lab=V_OUT_CCM} +C {ipin.sym} -20 -520 0 0 {name=p9 lab=V_IN +} +C {symbols/pfet_03v3.sym} 530 -710 0 1 {name=M1 +L=2.0u +W=10.0u +nf=1 +m=1 +ad="'int((nf+1)/2) * W/nf * 0.18u'" +pd="'2*int((nf+1)/2) * (W/nf + 0.18u)'" +as="'int((nf+2)/2) * W/nf * 0.18u'" +ps="'2*int((nf+2)/2) * (W/nf + 0.18u)'" +nrd="'0.18u / W'" nrs="'0.18u / W'" +sa=0 sb=0 sd=0 +model=pfet_03v3 +spiceprefix=X +} +C {symbols/pfet_03v3.sym} 530 -590 0 1 {name=M2 +L=2.0u +W=10.0u +nf=1 +m=1 +ad="'int((nf+1)/2) * W/nf * 0.18u'" +pd="'2*int((nf+1)/2) * (W/nf + 0.18u)'" +as="'int((nf+2)/2) * W/nf * 0.18u'" +ps="'2*int((nf+2)/2) * (W/nf + 0.18u)'" +nrd="'0.18u / W'" nrs="'0.18u / W'" +sa=0 sb=0 sd=0 +model=pfet_03v3 +spiceprefix=X +} +C {symbols/pfet_03v3.sym} 720 -710 0 0 {name=M3 +L=2.0u +W=10.0u +nf=1 +m=1 +ad="'int((nf+1)/2) * W/nf * 0.18u'" +pd="'2*int((nf+1)/2) * (W/nf + 0.18u)'" +as="'int((nf+2)/2) * W/nf * 0.18u'" +ps="'2*int((nf+2)/2) * (W/nf + 0.18u)'" +nrd="'0.18u / W'" nrs="'0.18u / W'" +sa=0 sb=0 sd=0 +model=pfet_03v3 +spiceprefix=X +} +C {symbols/pfet_03v3.sym} 720 -590 0 0 {name=M4 +L=2.0u +W=10.0u +nf=1 +m=1 +ad="'int((nf+1)/2) * W/nf * 0.18u'" +pd="'2*int((nf+1)/2) * (W/nf + 0.18u)'" +as="'int((nf+2)/2) * W/nf * 0.18u'" +ps="'2*int((nf+2)/2) * (W/nf + 0.18u)'" +nrd="'0.18u / W'" nrs="'0.18u / W'" +sa=0 sb=0 sd=0 +model=pfet_03v3 +spiceprefix=X +} +C {symbols/pfet_03v3.sym} 990 -710 0 0 {name=M5 +L=2.0u +W=10.0u +nf=1 +m=1 +ad="'int((nf+1)/2) * W/nf * 0.18u'" +pd="'2*int((nf+1)/2) * (W/nf + 0.18u)'" +as="'int((nf+2)/2) * W/nf * 0.18u'" +ps="'2*int((nf+2)/2) * (W/nf + 0.18u)'" +nrd="'0.18u / W'" nrs="'0.18u / W'" +sa=0 sb=0 sd=0 +model=pfet_03v3 +spiceprefix=X +} +C {symbols/pfet_03v3.sym} 990 -590 0 0 {name=M6 +L=2.0u +W=10.0u +nf=1 +m=1 +ad="'int((nf+1)/2) * W/nf * 0.18u'" +pd="'2*int((nf+1)/2) * (W/nf + 0.18u)'" +as="'int((nf+2)/2) * W/nf * 0.18u'" +ps="'2*int((nf+2)/2) * (W/nf + 0.18u)'" +nrd="'0.18u / W'" nrs="'0.18u / W'" +sa=0 sb=0 sd=0 +model=pfet_03v3 +spiceprefix=X +} +C {symbols/pfet_03v3.sym} 1330 -710 0 0 {name=M7 +L=2.0u +W=10.0u +nf=1 +m=1 +ad="'int((nf+1)/2) * W/nf * 0.18u'" +pd="'2*int((nf+1)/2) * (W/nf + 0.18u)'" +as="'int((nf+2)/2) * W/nf * 0.18u'" +ps="'2*int((nf+2)/2) * (W/nf + 0.18u)'" +nrd="'0.18u / W'" nrs="'0.18u / W'" +sa=0 sb=0 sd=0 +model=pfet_03v3 +spiceprefix=X +} +C {symbols/pfet_03v3.sym} 1330 -590 0 0 {name=M8 +L=2.0u +W=10.0u +nf=1 +m=1 +ad="'int((nf+1)/2) * W/nf * 0.18u'" +pd="'2*int((nf+1)/2) * (W/nf + 0.18u)'" +as="'int((nf+2)/2) * W/nf * 0.18u'" +ps="'2*int((nf+2)/2) * (W/nf + 0.18u)'" +nrd="'0.18u / W'" nrs="'0.18u / W'" +sa=0 sb=0 sd=0 +model=pfet_03v3 +spiceprefix=X +} +C {symbols/pfet_03v3.sym} 850 -820 0 0 {name=M14 +L=2.0u +W=10.0u +nf=1 +m=1 +ad="'int((nf+1)/2) * W/nf * 0.18u'" +pd="'2*int((nf+1)/2) * (W/nf + 0.18u)'" +as="'int((nf+2)/2) * W/nf * 0.18u'" +ps="'2*int((nf+2)/2) * (W/nf + 0.18u)'" +nrd="'0.18u / W'" nrs="'0.18u / W'" +sa=0 sb=0 sd=0 +model=pfet_03v3 +spiceprefix=X +} +C {symbols/pfet_03v3.sym} 610 -820 0 0 {name=M18 +L=2.0u +W=10.0u +nf=1 +m=1 +ad="'int((nf+1)/2) * W/nf * 0.18u'" +pd="'2*int((nf+1)/2) * (W/nf + 0.18u)'" +as="'int((nf+2)/2) * W/nf * 0.18u'" +ps="'2*int((nf+2)/2) * (W/nf + 0.18u)'" +nrd="'0.18u / W'" nrs="'0.18u / W'" +sa=0 sb=0 sd=0 +model=pfet_03v3 +spiceprefix=X +} +C {lab_pin.sym} 0 -910 2 0 {name=p10 sig_type=std_logic lab=VDD} +C {lab_pin.sym} 160 -910 0 0 {name=p11 sig_type=std_logic lab=VDD} +C {ipin.sym} -20 -880 0 0 {name=p12 lab=EN +} +C {symbols/pfet_03v3.sym} 1100 -820 0 0 {name=M15 +L=2.0u +W=10.0u +nf=1 +m=1 +ad="'int((nf+1)/2) * W/nf * 0.18u'" +pd="'2*int((nf+1)/2) * (W/nf + 0.18u)'" +as="'int((nf+2)/2) * W/nf * 0.18u'" +ps="'2*int((nf+2)/2) * (W/nf + 0.18u)'" +nrd="'0.18u / W'" nrs="'0.18u / W'" +sa=0 sb=0 sd=0 +model=pfet_03v3 +spiceprefix=X +} +C {lab_pin.sym} 630 -820 2 0 {name=p2 sig_type=std_logic lab=VDD} +C {lab_pin.sym} 870 -820 2 0 {name=p8 sig_type=std_logic lab=VDD} +C {lab_pin.sym} 1120 -820 2 0 {name=p13 sig_type=std_logic lab=VDD} +C {lab_pin.sym} 1010 -710 2 0 {name=p14 sig_type=std_logic lab=VDD} +C {lab_pin.sym} 740 -710 2 0 {name=p15 sig_type=std_logic lab=VDD} +C {lab_pin.sym} 510 -710 0 0 {name=p16 sig_type=std_logic lab=VDD} +C {lab_pin.sym} 510 -590 0 0 {name=p17 sig_type=std_logic lab=VDD} +C {lab_pin.sym} 740 -590 2 0 {name=p18 sig_type=std_logic lab=VDD} +C {lab_pin.sym} 1010 -590 2 0 {name=p19 sig_type=std_logic lab=VDD} +C {lab_pin.sym} 1350 -710 2 0 {name=p20 sig_type=std_logic lab=VDD} +C {lab_pin.sym} 1350 -590 2 0 {name=p21 sig_type=std_logic lab=VDD} +C {vanilla_cm.sym} 860 -430 0 0 {name=x1} +C {biased_cm.sym} 1130 -300 0 0 {name=x2} +C {cascode_cm.sym} 1470 -200 0 0 {name=x3} +C {bias.sym} 500 -160 0 0 {name=x4} +C {lab_pin.sym} 500 -260 0 0 {name=p22 sig_type=std_logic lab=VDD} +C {symbols/pfet_03v3.sym} 1590 -710 0 0 {name=M9 +L=2.0u +W=10.0u +nf=1 +m=1 +ad="'int((nf+1)/2) * W/nf * 0.18u'" +pd="'2*int((nf+1)/2) * (W/nf + 0.18u)'" +as="'int((nf+2)/2) * W/nf * 0.18u'" +ps="'2*int((nf+2)/2) * (W/nf + 0.18u)'" +nrd="'0.18u / W'" nrs="'0.18u / W'" +sa=0 sb=0 sd=0 +model=pfet_03v3 +spiceprefix=X +} +C {symbols/pfet_03v3.sym} 1590 -590 0 0 {name=M10 +L=2.0u +W=10.0u +nf=1 +m=1 +ad="'int((nf+1)/2) * W/nf * 0.18u'" +pd="'2*int((nf+1)/2) * (W/nf + 0.18u)'" +as="'int((nf+2)/2) * W/nf * 0.18u'" +ps="'2*int((nf+2)/2) * (W/nf + 0.18u)'" +nrd="'0.18u / W'" nrs="'0.18u / W'" +sa=0 sb=0 sd=0 +model=pfet_03v3 +spiceprefix=X +} +C {lab_pin.sym} 1610 -710 2 0 {name=p23 sig_type=std_logic lab=VDD} +C {lab_pin.sym} 1610 -590 2 0 {name=p24 sig_type=std_logic lab=VDD} +C {symbols/pfet_03v3.sym} 1450 -820 0 0 {name=M11 +L=2.0u +W=10.0u +nf=1 +m=1 +ad="'int((nf+1)/2) * W/nf * 0.18u'" +pd="'2*int((nf+1)/2) * (W/nf + 0.18u)'" +as="'int((nf+2)/2) * W/nf * 0.18u'" +ps="'2*int((nf+2)/2) * (W/nf + 0.18u)'" +nrd="'0.18u / W'" nrs="'0.18u / W'" +sa=0 sb=0 sd=0 +model=pfet_03v3 +spiceprefix=X +} +C {opin.sym} 2020 -560 0 0 {name=p25 lab=V_OUT_VIN +} +C {lab_pin.sym} 1470 -820 2 0 {name=p26 sig_type=std_logic lab=VDD} +C {symbols/pfet_03v3.sym} 1690 -840 0 0 {name=M12 +L=2.0u +W=10.0u +nf=1 +m=6 +ad="'int((nf+1)/2) * W/nf * 0.18u'" +pd="'2*int((nf+1)/2) * (W/nf + 0.18u)'" +as="'int((nf+2)/2) * W/nf * 0.18u'" +ps="'2*int((nf+2)/2) * (W/nf + 0.18u)'" +nrd="'0.18u / W'" nrs="'0.18u / W'" +sa=0 sb=0 sd=0 +model=pfet_03v3 +spiceprefix=X +} diff --git a/blocks/composite/regulated_cascoded_cmirror/xschem/top_level.sym b/blocks/composite/regulated_cascoded_cmirror/xschem/top_level.sym new file mode 100644 index 00000000..ebc794c7 --- /dev/null +++ b/blocks/composite/regulated_cascoded_cmirror/xschem/top_level.sym @@ -0,0 +1,88 @@ +v {xschem version=3.4.7 file_version=1.2} +G {} +K {type=subcircuit +format="@name @pinlist @symname" +template="name=x1" +} +V {} +S {} +E {} +L 4 -240 -80 -220 -80 {} +L 4 -240 -40 -220 -40 {} +L 4 180 -60 200 -60 {} +L 4 180 -40 200 -40 {} +L 4 180 -20 200 -20 {} +L 4 -240 10 -220 10 {} +L 4 -100 20 -100 100 {} +L 4 -70 20 -70 100 {} +L 4 -40 20 -40 100 {} +L 4 -40 -40 -40 -10 {} +L 4 -100 100 -40 100 {} +L 4 -70 -20 -70 -10 {} +L 4 -160 -60 -40 -60 {} +L 4 -40 -60 -40 -40 {} +L 4 100 20 100 100 {} +L 4 40 100 100 100 {} +L 4 70 20 70 100 {} +L 4 40 20 40 100 {} +L 4 40 -40 40 -10 {} +L 4 70 -20 70 -10 {} +L 4 40 -60 40 -40 {} +L 4 40 -60 110 -60 {} +L 4 70 -40 110 -40 {} +L 4 70 -40 70 -20 {} +L 4 100 -20 100 -10 {} +L 4 100 -20 110 -20 {} +L 4 -70 -40 -70 -20 {} +L 4 -170 -40 -70 -40 {} +L 4 -100 -20 -100 -10 {} +L 4 -170 -20 -100 -20 {} +L 4 -170 -60 -160 -60 {} +L 4 -170 -60 -170 -20 {} +L 4 -190 -40 -170 -40 {} +L 4 -240 -110 -240 110 {} +L 4 200 -110 200 110 {} +L 4 -240 -110 200 -110 {} +L 4 -240 110 200 110 {} +L 4 180 -80 200 -80 {} +L 7 0 -110 0 -90 {} +L 7 0 90 0 110 {} +B 5 -2.5 -112.5 2.5 -107.5 {name=VDD dir=inout} +B 5 -242.5 -82.5 -237.5 -77.5 {name=EN dir=in} +B 5 -242.5 -42.5 -237.5 -37.5 {name=V_IN dir=in} +B 5 197.5 -62.5 202.5 -57.5 {name=V_OUT_VCM dir=out} +B 5 197.5 -42.5 202.5 -37.5 {name=V_OUT_BCM dir=out} +B 5 197.5 -22.5 202.5 -17.5 {name=V_OUT_CCM dir=out} +B 5 -242.5 7.5 -237.5 12.5 {name=V_AUX_CCM dir=in} +B 5 -2.5 107.5 2.5 112.5 {name=VSS dir=inout} +B 5 197.5 -82.5 202.5 -77.5 {name=V_OUT_VIN dir=out} +A 4 -100 0 10 270 360 {} +A 4 -100 10 10 270 360 {} +A 4 -70 0 10 270 360 {} +A 4 -70 10 10 270 360 {} +A 4 -40 0 10 270 360 {} +A 4 -40 10 10 270 360 {} +A 4 100 0 10 270 360 {} +A 4 100 10 10 270 360 {} +A 4 70 0 10 270 360 {} +A 4 70 10 10 270 360 {} +A 4 40 0 10 270 360 {} +A 4 40 10 10 270 360 {} +T {@symname} -228.5 -136 0 0 0.3 0.3 {} +T {@name} 155 -142 0 0 0.2 0.2 {} +T {VDD} -4 -85 3 1 0.2 0.2 {} +T {EN} -215 -84 0 0 0.2 0.2 {} +T {V_IN} -215 -44 0 0 0.2 0.2 {} +T {V_OUT_VCM} 175 -64 0 1 0.2 0.2 {} +T {V_OUT_BCM} 175 -44 0 1 0.2 0.2 {} +T {V_OUT_CCM} 175 -24 0 1 0.2 0.2 {} +T {V_AUX_CCM} -215 6 0 0 0.2 0.2 {} +T {VSS} 4 85 1 1 0.2 0.2 {} +T {3} -100 20 0 0 0.4 0.4 {} +T {2} -70 20 0 0 0.4 0.4 {} +T {1} -40 20 0 0 0.4 0.4 {} +T {3} 100 20 0 0 0.4 0.4 {} +T {2} 70 20 0 0 0.4 0.4 {} +T {1} 40 20 0 0 0.4 0.4 {} +T {V_OUT_VCM} 175 -64 0 1 0.2 0.2 {} +T {V_OUT_VIN} 175 -84 0 1 0.2 0.2 {} diff --git a/blocks/composite/regulated_cascoded_cmirror/xschem/vanilla_cm.sch b/blocks/composite/regulated_cascoded_cmirror/xschem/vanilla_cm.sch new file mode 100644 index 00000000..1e463242 --- /dev/null +++ b/blocks/composite/regulated_cascoded_cmirror/xschem/vanilla_cm.sch @@ -0,0 +1,85 @@ +v {xschem version=3.4.7 file_version=1.2} +G {} +K {} +V {} +S {} +E {} +N 300 -50 300 -30 {lab=vss} +N 300 -120 340 -120 {lab=vss} +N 340 -120 340 -70 {lab=vss} +N 300 -70 340 -70 {lab=vss} +N 220 -120 260 -120 {lab=v_in} +N 160 -170 160 -150 {lab=v_in} +N 160 -170 220 -170 {lab=v_in} +N 220 -170 220 -120 {lab=v_in} +N 160 -290 160 -170 {lab=v_in} +N 160 -80 160 -30 {lab=vss} +N 100 -120 160 -120 {lab=vss} +N 100 -120 100 -80 {lab=vss} +N 100 -80 160 -80 {lab=vss} +N 300 -240 300 -150 {lab=v_out} +N 300 -90 300 -70 {lab=vss} +N 200 -120 220 -120 {lab=v_in} +N 160 -90 160 -80 {lab=vss} +N 300 -70 300 -50 {lab=vss} +N 160 -30 300 -30 {lab=vss} +N 300 -270 300 -240 {lab=v_out} +N 110 -290 130 -290 {lab=v_in} +N 130 -290 160 -290 {lab=v_in} +N 60 -30 160 -30 {lab=vss} +N 300 -290 320 -290 {lab=v_out} +N 300 -290 300 -270 {lab=v_out} +N 440 -90 440 -30 {lab=vss} +N 300 -30 440 -30 {lab=vss} +N 400 -120 400 -30 {lab=vss} +N 440 -150 470 -150 {lab=vss} +N 470 -150 470 -30 {lab=vss} +N 440 -30 470 -30 {lab=vss} +N 440 -120 470 -120 {lab=vss} +C {symbols/nfet_03v3.sym} 280 -120 0 0 {name=M1 +L=1u +W=4u +nf=1 +m=1 +ad="'int((nf+1)/2) * W/nf * 0.18u'" +pd="'2*int((nf+1)/2) * (W/nf + 0.18u)'" +as="'int((nf+2)/2) * W/nf * 0.18u'" +ps="'2*int((nf+2)/2) * (W/nf + 0.18u)'" +nrd="'0.18u / W'" nrs="'0.18u / W'" +sa=0 sb=0 sd=0 +model=nfet_03v3 +spiceprefix=X +} +C {symbols/nfet_03v3.sym} 180 -120 0 1 {name=M2 +L=1u +W=4u +nf=1 +m=1 +ad="'int((nf+1)/2) * W/nf * 0.18u'" +pd="'2*int((nf+1)/2) * (W/nf + 0.18u)'" +as="'int((nf+2)/2) * W/nf * 0.18u'" +ps="'2*int((nf+2)/2) * (W/nf + 0.18u)'" +nrd="'0.18u / W'" nrs="'0.18u / W'" +sa=0 sb=0 sd=0 +model=nfet_03v3 +spiceprefix=X +} +C {ipin.sym} 110 -290 0 0 {name=p1 lab=v_in +} +C {iopin.sym} 60 -30 2 0 {name=p3 lab=vss +} +C {opin.sym} 320 -290 0 0 {name=p4 lab=v_out} +C {symbols/nfet_03v3.sym} 420 -120 0 0 {name=M3 +L=1u +W=4u +nf=1 +m=2 +ad="'int((nf+1)/2) * W/nf * 0.18u'" +pd="'2*int((nf+1)/2) * (W/nf + 0.18u)'" +as="'int((nf+2)/2) * W/nf * 0.18u'" +ps="'2*int((nf+2)/2) * (W/nf + 0.18u)'" +nrd="'0.18u / W'" nrs="'0.18u / W'" +sa=0 sb=0 sd=0 +model=nfet_03v3 +spiceprefix=X +} diff --git a/blocks/composite/regulated_cascoded_cmirror/xschem/vanilla_cm.sym b/blocks/composite/regulated_cascoded_cmirror/xschem/vanilla_cm.sym new file mode 100644 index 00000000..a54648f2 --- /dev/null +++ b/blocks/composite/regulated_cascoded_cmirror/xschem/vanilla_cm.sym @@ -0,0 +1,42 @@ +v {xschem version=3.4.7 file_version=1.2} +G {} +K {type=subcircuit +format="@name @pinlist @symname" +template="name=x1" +} +V {} +S {} +E {} +L 4 -120 -40 -100 -40 {} +L 4 100 -40 120 -40 {} +L 4 -100 -40 -50 -40 {} +L 4 -50 -40 -50 -20 {} +L 4 -50 -40 -50 -10 {} +L 4 -50 -10 -30 -10 {} +L 4 -30 -10 -30 10 {} +L 4 -50 10 -30 10 {} +L 4 -50 10 -50 30 {} +L 4 -50 -40 0 -40 {} +L 4 -20 -10 -20 10 {} +L 4 -20 0 0 0 {} +L 4 0 -40 0 0 {} +L 4 50 -40 50 -20 {} +L 4 50 -40 50 -10 {} +L 4 30 -10 50 -10 {} +L 4 30 -10 30 10 {} +L 4 30 10 50 10 {} +L 4 50 10 50 30 {} +L 4 20 -10 20 10 {} +L 4 0 0 20 0 {} +L 4 50 -40 100 -40 {} +L 4 -50 30 50 30 {} +L 7 0 30 0 50 {} +B 4 -110 -70 110 50 {fill=False} +B 5 -122.5 -42.5 -117.5 -37.5 {name=v_in dir=in} +B 5 117.5 -42.5 122.5 -37.5 {name=v_out dir=out} +B 5 -2.5 47.5 2.5 52.5 {name=vss dir=inout} +T {@symname} -53 -66 0 0 0.3 0.3 {} +T {@name} 65 -92 0 0 0.2 0.2 {} +T {v_in} -95 -34 0 0 0.2 0.2 {} +T {v_out} 95 -34 0 1 0.2 0.2 {} +T {vss} 4 25 1 1 0.2 0.2 {} diff --git a/blocks/composite/regulated_cascoded_cmirror/xschem/xschemrc b/blocks/composite/regulated_cascoded_cmirror/xschem/xschemrc new file mode 100644 index 00000000..9f4b09b7 --- /dev/null +++ b/blocks/composite/regulated_cascoded_cmirror/xschem/xschemrc @@ -0,0 +1,7 @@ +# Source the PDK xschemrc file +if {![info exists PDK]} { +source $env(PDK_ROOT)/$env(PDK)/libs.tech/xschem/xschemrc +} + +# Add current directory to xschem library path +append XSCHEM_LIBRARY_PATH :[file dirname [info script]] diff --git a/blocks/composite/regulated_cascoded_cmirror/zoom_plot.py b/blocks/composite/regulated_cascoded_cmirror/zoom_plot.py new file mode 100644 index 00000000..d9613dd2 --- /dev/null +++ b/blocks/composite/regulated_cascoded_cmirror/zoom_plot.py @@ -0,0 +1,62 @@ +import numpy as np +import matplotlib.pyplot as plt +from matplotlib.patches import Rectangle, ConnectionPatch +from mpl_toolkits.axes_grid1 import make_axes_locatable + +path = "xschem/simulation/" + +# Load the saved sweeps +v1, i1 = np.loadtxt(path + '/vanilla.txt', unpack=True) +v2, i2 = np.loadtxt(path + '/biased.txt', unpack=True) +v3, i3 = np.loadtxt(path + '/cascode.txt', unpack=True) + +fig, ax = plt.subplots() + +# Main plot +ax.plot(v1, i1, label="Vanilla") +ax.plot(v2, i2, label="Biased") +ax.plot(v3, i3, label="Cascode") + +ax.set_xlabel("V_out (V)") +ax.set_ylabel("I_out (A)") +ax.set_title("I-V Curves of Different Current Mirrors") +ax.legend() +ax.grid(True) + +# --- Side zoom panel (outside the main axes) --- +divider = make_axes_locatable(ax) +ax_zoom = divider.append_axes("right", size="50%", pad=0.6) + +# Zoomed x-range +x1, x2 = 0.0, 0.9 +# Fixed y-range +y_lo, y_hi = 0.4e-6, 1.2e-6 + +if y_lo > y_hi: + y_lo, y_hi = y_hi, y_lo + +# Plot zoomed data +ax_zoom.plot(v1, i1, label="Vanilla") +ax_zoom.plot(v2, i2, label="Biased") +ax_zoom.plot(v3, i3, label="Cascode") +ax_zoom.set_xlim(x1, x2) +ax_zoom.set_ylim(y_lo, y_hi) +ax_zoom.grid(True) +ax_zoom.set_xlabel("V_out (V)") +ax_zoom.set_ylabel("I_out (A)") +ax_zoom.set_title("Zoom: early V_out", fontsize=10) + +# Rectangle to indicate zoomed region on main plot +rect = Rectangle((x1, y_lo), x2 - x1, y_hi - y_lo, + fill=False, linestyle="--", linewidth=1, edgecolor="red", zorder=10) +ax.add_patch(rect) + +# Optional connectors +for xy_main, xy_zoom in [((x1, y_hi), (x1, y_hi)), ((x2, y_lo), (x2, y_lo))]: + con = ConnectionPatch(xyA=xy_zoom, coordsA=ax_zoom.transData, + xyB=xy_main, coordsB=ax.transData, + linestyle="--", linewidth=0.6, color="red") + fig.add_artist(con) + +plt.tight_layout() +plt.show()