"
+ ]
+ },
+ "metadata": {},
+ "output_type": "display_data"
+ },
+ {
+ "name": "stderr",
+ "output_type": "stream",
+ "text": [
+ "/headless/conda-env/miniconda3/envs/GLdev/lib/python3.10/site-packages/gdsfactory/show.py:40: UserWarning: Unnamed cells, 8 in 'combined_stage1_stage2'\n",
+ " gdspath = component.write_gds(\n",
+ "\u001b[32m2025-07-12 07:22:48.239\u001b[0m | \u001b[33m\u001b[1mWARNING \u001b[0m | \u001b[36mgdsfactory.klive\u001b[0m:\u001b[36mshow\u001b[0m:\u001b[36m57\u001b[0m - \u001b[33m\u001b[1mklive didn't send data, closing\u001b[0m\n"
+ ]
+ }
+ ],
+ "source": [
+ "# Cell 9: Final Routing\n",
+ "from gdsfactory import Component, components as c\n",
+ "def combine_stage1_stage2(stage1: Component, stage2: Component) -> Component:\n",
+ " top = Component(\"combined_stage1_stage2\")\n",
+ " ref1 = top << stage1\n",
+ " ref2 = top << stage2\n",
+ "\n",
+ " spacing = 30\n",
+ " w1 = stage1.bbox[1][0] - stage1.bbox[0][0]\n",
+ " ref2.movex(w1 + spacing)\n",
+ "\n",
+ " trace_width = 0.5\n",
+ " metal_layer = (68, 20)\n",
+ "\n",
+ " # RoutingL I1 (Stage 1 output) to C1 (top of MIM1 in Stage 2)\n",
+ " try:\n",
+ " p1 = ref1.ports[\"I1\"].center # Stage 1 current mirror output\n",
+ "\n",
+ " # Find top port of MIM1 (C1) in stage 2\n",
+ " c1_top_candidates = [p for p in ref2.ports.values() if \"top\" in p.name.lower()]\n",
+ " if not c1_top_candidates:\n",
+ " raise ValueError(\"No top port found on C1 in stage 2.\")\n",
+ " p2 = c1_top_candidates[0].center # Assume first match is correct\n",
+ "\n",
+ " # Horizontal segment\n",
+ " h = c.rectangle(size=(abs(p1[0] - p2[0]), trace_width), layer=metal_layer)\n",
+ " h_ref = top << h\n",
+ " h_ref.move((min(p1[0], p2[0]), p1[1] - trace_width / 2))\n",
+ "\n",
+ " # Vertical segment\n",
+ " v = c.rectangle(size=(trace_width, abs(p1[1] - p2[1])), layer=metal_layer)\n",
+ " v_ref = top << v\n",
+ " v_ref.move((p2[0] - trace_width / 2, min(p1[1], p2[1])))\n",
+ "\n",
+ " print(f\"Connected I1 to {c1_top_candidates[0].name}\")\n",
+ "\n",
+ " except Exception as e:\n",
+ " print(f\"\")\n",
+ "\n",
+ " # RoutingL Vout+ PAD (Stage 2) to PMOS DRAIN (Stage 1)\n",
+ " try:\n",
+ " # Stage 2: external Vout+ pad\n",
+ " vp2 = ref2.ports[\"Vout+_pad\"].center\n",
+ "\n",
+ " # Stage 1: internal PMOS drain (from differential pair)\n",
+ " vp1 = ref1.ports[\"Vout+\"].center\n",
+ "\n",
+ " # Horizontal segment\n",
+ " h = c.rectangle(size=(abs(vp1[0] - vp2[0]), trace_width), layer=metal_layer)\n",
+ " h_ref = top << h\n",
+ " h_ref.move((min(vp1[0], vp2[0]), vp1[1] - trace_width / 2))\n",
+ "\n",
+ " # Vertical segment if needed\n",
+ " if vp1[1] != vp2[1]:\n",
+ " v = c.rectangle(size=(trace_width, abs(vp1[1] - vp2[1])), layer=metal_layer)\n",
+ " v_ref = top << v\n",
+ " v_ref.move((vp2[0] - trace_width / 2, min(vp1[1], vp2[1])))\n",
+ "\n",
+ " print(\"Connected Vout+ pad (stage2) → PMOS drain (stage1)\")\n",
+ "\n",
+ " except Exception as e:\n",
+ " print(f\"\")\n",
+ "\n",
+ " return top\n",
+ "\n",
+ "# Combine and display to klayout\n",
+ "combined = combine_stage1_stage2(stage1=top1, stage2=top2)\n",
+ "display_component(combined, scale=3)\n",
+ "combined.write_gds(\"combine.gds\")\n",
+ "display_gds(\"combine.gds\")\n",
+ "combined.show()"
+ ]
+ },
+ {
+ "cell_type": "code",
+ "execution_count": null,
+ "id": "1e0d9ce0-e63b-4ac7-b13a-0381455ea78b",
+ "metadata": {},
+ "outputs": [],
+ "source": []
+ }
+ ],
+ "metadata": {
+ "kernelspec": {
+ "display_name": "Python 3 (ipykernel)",
+ "language": "python",
+ "name": "python3"
+ },
+ "language_info": {
+ "codemirror_mode": {
+ "name": "ipython",
+ "version": 3
+ },
+ "file_extension": ".py",
+ "mimetype": "text/x-python",
+ "name": "python",
+ "nbconvert_exporter": "python",
+ "pygments_lexer": "ipython3",
+ "version": "3.10.18"
+ }
+ },
+ "nbformat": 4,
+ "nbformat_minor": 5
+}
diff --git a/blocks/composite/OpAmp Challenge-GenYZTeam/JupyterNotebook/test2.txt b/blocks/composite/OpAmp Challenge-GenYZTeam/JupyterNotebook/test2.txt
new file mode 100644
index 00000000..8b137891
--- /dev/null
+++ b/blocks/composite/OpAmp Challenge-GenYZTeam/JupyterNotebook/test2.txt
@@ -0,0 +1 @@
+
diff --git a/blocks/composite/OpAmp Challenge-GenYZTeam/NGSPICE/opamp_design.asc b/blocks/composite/OpAmp Challenge-GenYZTeam/NGSPICE/opamp_design.asc
new file mode 100644
index 00000000..2566f77a
--- /dev/null
+++ b/blocks/composite/OpAmp Challenge-GenYZTeam/NGSPICE/opamp_design.asc
@@ -0,0 +1,224 @@
+Version 4.1
+SHEET 1 3356 1268
+WIRE 768 -480 480 -480
+WIRE 768 -448 768 -480
+WIRE 480 -400 480 -480
+WIRE 480 -400 368 -400
+WIRE 592 -400 480 -400
+WIRE 368 -320 368 -400
+WIRE 432 -320 368 -320
+WIRE 592 -320 592 -400
+WIRE 624 -320 592 -320
+WIRE 368 -304 368 -320
+WIRE 592 -304 592 -320
+WIRE 432 -256 432 -320
+WIRE 432 -256 368 -256
+WIRE 624 -256 624 -320
+WIRE 624 -256 592 -256
+WIRE 320 -224 288 -224
+WIRE 288 -192 288 -224
+WIRE 544 -192 544 -224
+WIRE 544 -192 288 -192
+WIRE 288 -128 288 -192
+WIRE 368 -128 368 -208
+WIRE 368 -128 288 -128
+WIRE 592 -128 592 -208
+WIRE 624 -128 592 -128
+WIRE 928 -128 624 -128
+WIRE 368 -112 368 -128
+WIRE 400 -112 368 -112
+WIRE 400 -48 400 -112
+WIRE 624 -48 624 -128
+WIRE 512 0 400 0
+WIRE 624 0 512 0
+WIRE 512 16 512 0
+WIRE 352 32 256 32
+WIRE 112 80 32 80
+WIRE 576 80 576 32
+WIRE 752 80 576 80
+WIRE 112 96 112 80
+WIRE 256 96 256 32
+WIRE 752 96 752 80
+WIRE 32 112 32 80
+WIRE 400 176 400 48
+WIRE 624 176 624 48
+WIRE 624 176 400 176
+WIRE 400 192 400 176
+WIRE 112 224 112 176
+WIRE 112 224 32 224
+WIRE 112 240 112 224
+WIRE 448 240 400 240
+WIRE 32 272 32 224
+WIRE 352 272 32 272
+WIRE 160 288 112 288
+WIRE 32 320 32 272
+WIRE 64 320 32 320
+WIRE 256 320 256 176
+WIRE 752 320 752 176
+WIRE 112 352 112 336
+WIRE 160 352 160 288
+WIRE 160 352 112 352
+WIRE 400 368 400 288
+WIRE 448 368 448 240
+WIRE 448 368 400 368
+WIRE 112 384 112 352
+WIRE 256 448 256 400
+WIRE 400 448 400 368
+WIRE 752 448 752 400
+WIRE 560 544 256 544
+WIRE 928 544 560 544
+WIRE 560 560 560 544
+WIRE 928 608 928 544
+WIRE 560 720 560 640
+WIRE 560 720 352 720
+WIRE 256 736 256 544
+WIRE 560 784 560 720
+WIRE 560 784 512 784
+WIRE 560 816 560 784
+WIRE 576 816 560 816
+WIRE 352 832 352 720
+WIRE 832 832 624 832
+WIRE 928 832 928 688
+WIRE 928 832 896 832
+WIRE 992 832 928 832
+WIRE 512 864 512 784
+WIRE 576 864 512 864
+WIRE 176 880 112 880
+WIRE 256 880 256 816
+WIRE 256 880 240 880
+WIRE 288 880 256 880
+WIRE 352 992 352 928
+WIRE 576 1088 576 912
+WIRE 576 1088 480 1088
+WIRE 928 1088 928 832
+WIRE 480 1120 480 1088
+WIRE 480 1248 480 1184
+WIRE 576 1248 576 1168
+WIRE 928 1248 928 1168
+WIRE 928 1248 576 1248
+FLAG 32 112 0
+FLAG 112 384 0
+FLAG 256 448 0
+FLAG 400 448 0
+FLAG 512 16 0
+FLAG 752 448 0
+FLAG 768 -368 0
+FLAG 928 -128 outfinal
+FLAG 256 32 in
+FLAG 112 880 outfinal
+FLAG 352 992 0
+FLAG 992 832 0
+FLAG 480 1088 outamp
+FLAG 480 1248 0
+DATAFLAG 640 80 "$-V(outfinal)"
+DATAFLAG 768 -128 ""
+DATAFLAG 672 832 ""
+DATAFLAG 464 720 ""
+DATAFLAG 560 752 ""
+DATAFLAG 576 928 ""
+SYMBOL current 112 96 R0
+WINDOW 123 0 0 Left 0
+WINDOW 39 0 0 Left 0
+SYMATTR InstName I1
+SYMATTR Value 50µ
+SYMBOL voltage 256 304 R0
+WINDOW 123 0 0 Left 0
+WINDOW 39 0 0 Left 0
+SYMATTR InstName V1
+SYMATTR Value 1.2
+SYMBOL voltage 256 80 R0
+WINDOW 123 24 124 Left 2
+WINDOW 39 0 0 Left 0
+SYMATTR Value2 AC 1
+SYMATTR InstName V2
+SYMATTR Value SINE(0 15m 1k)
+SYMBOL voltage 752 80 R0
+WINDOW 123 0 0 Left 0
+WINDOW 39 0 0 Left 0
+SYMATTR InstName V3
+SYMATTR Value SINE(0 15m 1k 0 0 180)
+SYMBOL voltage 752 304 R0
+WINDOW 123 0 0 Left 0
+WINDOW 39 0 0 Left 0
+SYMATTR InstName V4
+SYMATTR Value 1.2
+SYMBOL voltage 768 -464 R0
+WINDOW 123 0 0 Left 0
+WINDOW 39 0 0 Left 0
+SYMATTR InstName V5
+SYMATTR Value 1.8
+SYMBOL INV\\cmosn 576 -48 R0
+SYMATTR InstName M3
+SYMATTR Value2 l=1u w=9u
+SYMBOL INV\\cmosn 352 -48 R0
+SYMATTR InstName M4
+SYMATTR Value2 l=1u w=9u
+SYMBOL INV\\cmosn 352 192 R0
+SYMATTR InstName M2
+SYMATTR Value2 l=1u w=6u
+SYMBOL INV\\cmosn 64 240 R0
+SYMATTR InstName M1
+SYMATTR Value2 l=1u w=6u
+SYMBOL INV\\cmosp 544 -304 R0
+SYMATTR InstName M5
+SYMATTR Value2 l=1u w=48u
+SYMBOL INV\\cmosp 320 -304 R0
+SYMATTR InstName M6
+SYMATTR Value2 l=1u w=48u
+SYMBOL cap 240 864 R90
+WINDOW 0 0 32 VBottom 2
+WINDOW 3 32 32 VTop 2
+SYMATTR InstName C1
+SYMATTR Value 100µ
+SYMBOL npn 288 832 R0
+SYMATTR InstName Q1
+SYMATTR Value DI_MMBT3904
+SYMBOL INV\\cmosp 624 912 R180
+SYMATTR InstName M7
+SYMATTR Value2 l=1u w=48u
+SYMBOL current 256 736 R0
+WINDOW 123 0 0 Left 0
+WINDOW 39 0 0 Left 0
+SYMATTR InstName I2
+SYMATTR Value 1µ
+SYMBOL current 560 560 R0
+WINDOW 123 0 0 Left 0
+WINDOW 39 0 0 Left 0
+SYMATTR InstName I3
+SYMATTR Value 170µ
+SYMBOL cap 896 816 R90
+WINDOW 0 0 32 VBottom 2
+WINDOW 3 32 32 VTop 2
+SYMATTR InstName C2
+SYMATTR Value 100µ
+SYMBOL current 576 1088 R0
+WINDOW 123 0 0 Left 0
+WINDOW 39 0 0 Left 0
+SYMATTR InstName I4
+SYMATTR Value 30µ
+SYMBOL voltage 928 592 R0
+WINDOW 123 0 0 Left 0
+WINDOW 39 0 0 Left 0
+SYMATTR InstName V7
+SYMATTR Value 1.8
+SYMBOL voltage 928 1072 R0
+WINDOW 123 0 0 Left 0
+WINDOW 39 0 0 Left 0
+SYMATTR InstName V6
+SYMATTR Value 1.8
+SYMBOL cap 464 1120 R0
+SYMATTR InstName C3
+SYMATTR Value 5p
+TEXT 944 296 Left 2 ;.op
+TEXT 944 320 Left 2 ;.tran 10m
+TEXT 944 344 Left 2 !.ac dec 100 10 100000000
+TEXT 1176 -248 Left 2 !.MODEL CMOSN NMOS ( LEVEL = 49\n+VERSION = 3.1 TNOM = 27 TOX = 4.1E-9\n+XJ = 1E-7 NCH = 2.3549E17 VTH0 = 0.3662473\n+K1 = 0.5864999 K2 = 1.127266E-3 K3 = 1E-3\n+K3B = 0.0294061 W0 = 1E-7 NLX = 1.630684E-7\n+DVT0W = 0 DVT1W = 0 DVT2W = 0\n+DVT0 = 1.2064649 DVT1 = 0.4215486 DVT2 = 0.0197749\n+U0 = 273.8094484 UA = -1.40499E-9 UB = 2.408323E-18\n+UC = 6.504826E-11 VSAT = 1.355009E5 A0 = 2\n+AGS = 0.4449958 B0 = 1.901075E-7 B1 = 4.99995E-6\n+KETA = -0.0164863 A1 = 3.868769E-4 A2 = 0.4640272\n+RDSW = 123.3376355 PRWG = 0.5 PRWB = -0.197728\n+WR = 1 WINT = 0 LINT = 1.690044E-8\n+XL = 0 XW = -1E-8 DWG = -4.728719E-9\n+DWB = -2.452411E-9 VOFF = -0.0948017 NFACTOR = 2.1860065\n+CIT = 0 CDSC = 2.4E-4 CDSCD = 0\n+CDSCB = 0 ETA0 = 2.230928E-3 ETAB = 6.028975E-5\n+DSUB = 0.0145467 PCLM = 1.3822069 PDIBLC1 = 0.1762787\n+PDIBLC2 = 1.66653E-3 PDIBLCB = -0.1 DROUT = 0.7694691\n+PSCBE1 = 8.91287E9 PSCBE2 = 7.349607E-9 PVAG = 1.685917E-3\n+DELTA = 0.01 RSH = 6.7 MOBMOD = 1\n+PRT = 0 UTE = -1.5 KT1 = -0.11\n+KT1L = 0 KT2 = 0.022 UA1 = 4.31E-9\n+UB1 = -7.61E-18 UC1 = -5.6E-11 AT = 3.3E4\n+WL = 0 WLN = 1 WW = 0\n+WWN = 1 WWL = 0 LL = 0\n+LLN = 1 LW = 0 LWN = 1\n+LWL = 0 CAPMOD = 2 XPART = 0.5\n+CGDO = 8.23E-10 CGSO = 8.23E-10 CGBO = 1E-12\n+CJ = 9.466429E-4 PB = 0.8 MJ = 0.3820266\n+CJSW = 2.608154E-10 PBSW = 0.8 MJSW = 0.102322\n+CJSWG = 3.3E-10 PBSWG = 0.8 MJSWG = 0.102322\n+CF = 0 PVTH0 = -2.199373E-3 PRDSW = -0.9368961\n+PK2 = 1.593254E-3 WKETA = -2.880976E-3 LKETA = 7.165078E-3\n+PU0 = 6.777519 PUA = 5.505418E-12 PUB = 8.84133E-25\n+PVSAT = 2.006286E3 PETA0 = 1.003159E-4 PKETA = -6.759277E-3\n+NOIMOD=2.0E+00 NOIA=1.3182567385564E+19\n+NOIB=144543.977074592 NOIC=-1.24515784572817E-12 EF=0.92 EM=41000000 )
+TEXT 2216 -248 Left 2 !.MODEL CMOSP PMOS ( LEVEL = 49\n+VERSION = 3.1 TNOM = 27 TOX = 4.1E-9\n+XJ = 1E-7 NCH = 4.1589E17 VTH0 = -0.3906012\n+K1 = 0.5341312 K2 = 0.0395326 K3 = 0\n+K3B = 7.4916211 W0 = 1E-6 NLX = 1.194072E-7\n+DVT0W = 0 DVT1W = 0 DVT2W = 0\n+DVT0 = 0.5060555 DVT1 = 0.2423835 DVT2 = 0.1\n+U0 = 115.6894042 UA = 1.573746E-9 UB = 1.874308E-21\n+UC = -1E-10 VSAT = 1.130982E5 A0 = 1.9976555\n+AGS = 0.4186945 B0 = 1.949178E-7 B1 = 6.422908E-7\n+KETA = 0.0166345 A1 = 0.4749146 A2 = 0.300003\n+RDSW = 198.321294 PRWG = 0.5 PRWB = -0.4986647\n+WR = 1 WINT = 0 LINT = 2.94454E-8\n+XL = 0 XW = -1E-8 DWG = -2.798724E-8\n+DWB = -4.83797E-10 VOFF = -0.095236 NFACTOR = 2\n+CIT = 0 CDSC = 2.4E-4 CDSCD = 0\n+CDSCB = 0 ETA0 = 1.035504E-3 ETAB = -4.358398E-4\n+DSUB = 1.816555E-3 PCLM = 1.3299898 PDIBLC1 = 1.766563E-3\n+PDIBLC2 = 7.728395E-7 PDIBLCB = -1E-3 DROUT = 1.011891E-3\n+PSCBE1 = 4.872184E10 PSCBE2 = 5E-10 PVAG = 0.0209921\n+DELTA = 0.01 RSH = 7.7 MOBMOD = 1\n+PRT = 0 UTE = -1.5 KT1 = -0.11\n+KT1L = 0 KT2 = 0.022 UA1 = 4.31E-9\n+UB1 = -7.61E-18 UC1 = -5.6E-11 AT = 3.3E4\n+WL = 0 WLN = 1 WW = 0\n+WWN = 1 WWL = 0 LL = 0\n+LLN = 1 LW = 0 LWN = 1\n+LWL = 0 CAPMOD = 2 XPART = 0.5\n+CGDO = 6.35E-10 CGSO = 6.35E-10 CGBO = 1E-12\n+CJ = 1.144521E-3 PB = 0.8468686 MJ = 0.4099522\n+CJSW = 2.490749E-10 PBSW = 0.8769118 MJSW = 0.3478565\n+CJSWG = 4.22E-10 PBSWG = 0.8769118 MJSWG = 0.3478565\n+CF = 0 PVTH0 = 2.302018E-3 PRDSW = 9.0575312\n+PK2 = 1.821914E-3 WKETA = 0.0222457 LKETA = -1.495872E-3\n+PU0 = -1.5580645 PUA = -6.36889E-11 PUB = 1E-21\n+PVSAT = 49.8420442 PETA0 = 2.827793E-5 PKETA = -2.536564E-3 \n+ NOIMOD=2.0E+00 NOIA=3.57456993317604E+18 NOIB=2500\n+ NOIC=2.61260020285845E-11 EF=1.1388 EM=41000000 )
+TEXT 80 -224 Left 2 ;Differential Pair
+TEXT -8 424 Left 2 ;Tail current source
+TEXT 752 80 Left 2 ;in_inverted
+TEXT 1176 864 Left 2 !.MODEL DI_MMBT3904 NPN (IS=48.3f NF=1.00 BF=410 VAF=114\n+ IKF=0.121 ISE=13.1p NE=2.00 BR=4.00 NR=1.00\n+ VAR=24.0 IKR=0.300 RE=2.63 RB=10.5 RC=1.05\n+ XTB=1.5 CJE=9.67p VJE=1.10 MJE=0.500 CJC=8.70p VJC=0.300\n+ MJC=0.300 TF=440p TR=74.7n EG=1.12 )
+TEXT 32 1040 Left 2 ;Folded Cascode (PMOS + NPN)
+TEXT 32 1072 Left 2 ;CS Config
+TEXT 8 -504 Left 2 ;STAGE 1
+TEXT 24 552 Left 2 ;STAGE 2
diff --git a/blocks/composite/OpAmp Challenge-GenYZTeam/NGSPICE/opampchallenge.cir b/blocks/composite/OpAmp Challenge-GenYZTeam/NGSPICE/opampchallenge.cir
new file mode 100644
index 00000000..55638310
--- /dev/null
+++ b/blocks/composite/OpAmp Challenge-GenYZTeam/NGSPICE/opampchallenge.cir
@@ -0,0 +1,115 @@
+* Differential Amplifier with Folded Cascode Output Stage
+
+* ======================= INPUT SOURCES ===========================
+V5 N001 0 DC 1.8
+V6 0 N012 DC 1.8
+V7 N008 0 DC 1.8
+
+* ======================= DC OFFSET FOR INPUT ===========================
+V1 N006 0 DC 1.2
+V4 N007 0 DC 1.2
+
+* Tail Current Source
+I1 N005 0 DC 50u
+
+* Folded Cascode Bias Currents
+I2 N008 N011 DC 1u
+I3 N008 N009 DC 170u
+I4 outamp N012 DC 30u
+
+* ======================= TRANSISTOR CORE ==========================
+M4 N002 in N004 0 CMOSN L=1u W=9u
+M3 outfinal N003 N004 0 CMOSN L=1u W=9u
+M1 N005 N005 0 0 CMOSN L=1u W=6u
+M2 N004 N005 0 0 CMOSN L=1u W=6u
+
+M5 N001 N002 outfinal N001 CMOSP L=1u W=48u
+M6 N001 N002 N002 N001 CMOSP L=1u W=48u
+
+Q1 N009 N011 0 0 DI_MMBT3904
+M7 outamp N010 N009 N009 CMOSP L=1u W=48u
+
+* ======================= PASSIVE COMPONENTS =======================
+C1 N011 outfinal 10u
+C2 0 N010 10u
+C3 outamp 0 5p
+R1 N010 N009 100Meg
+R2 N010 outamp 100Meg
+Rload outfinal 0 10k
+
+* ======================= TRANSISTOR MODELS ========================
+* BJT NPN
+.model DI_MMBT3904 NPN(IS=48.3f NF=1.00 BF=410 VAF=114
++ IKF=0.121 ISE=13.1p NE=2.00 BR=4.00 NR=1.00
++ VAR=24.0 IKR=0.300 RE=2.63 RB=10.5 RC=1.05
++ XTB=1.5 CJE=9.67p VJE=1.10 MJE=0.500 CJC=8.70p VJC=0.300
++ MJC=0.300 TF=440p TR=74.7n EG=1.12)
+
+* MOSFET N TYPE
+.model CMOSN NMOS (LEVEL=49
++VERSION=3.1 TNOM=27 TOX=4.1n XJ=0.1u NCH=2.3549E17 VTH0=0.3662473
++K1=0.5864999 K2=1.127266E-3 K3=1E-3 K3B=0.0294061 W0=0.1u NLX=1.630684E-7
++DVT0=1.2064649 DVT1=0.4215486 DVT2=0.0197749 U0=273.8094484 UA=-1.40499E-9 UB=2.408323E-18
++UC=6.504826E-11 VSAT=1.355009E5 A0=2 AGS=0.4449958 B0=1.901075E-7 B1=4.99995E-6
++KETA=-0.0164863 A1=3.868769E-4 A2=0.4640272 RDSW=123.3376355 PRWG=0.5 PRWB=-0.197728
++WR=1 WINT=0 LINT=1.690044E-8 DWG=-4.728719E-9 DWB=-2.452411E-9
++VOFF=-0.0948017 NFACTOR=2.1860065 CIT=0 CDSC=2.4E-4 ETA0=2.230928E-3 ETAB=6.028975E-5
++DSUB=0.0145467 PCLM=1.3822069 PDIBLC1=0.1762787 PDIBLC2=1.66653E-3 PDIBLCB=-0.1 DROUT=0.7694691
++PSCBE1=8.91287E9 PSCBE2=7.349607E-9 PVAG=1.685917E-3 DELTA=0.01 RSH=6.7
++MOBMOD=1 UTE=-1.5 KT1=-0.11 KT2=0.022 UA1=4.31E-9 UB1=-7.61E-18 UC1=-5.6E-11 AT=3.3E4
++WL=0 WLN=1 WW=0 WWN=1 WWL=0 LL=0 LLN=1 LW=0 LWN=1
++CAPMOD=2 XPART=0.5 CGDO=8.23E-10 CGSO=8.23E-10 CGBO=1E-12
++CJ=9.466429E-4 PB=0.8 MJ=0.3820266 CJSW=2.608154E-10 PBSW=0.8 MJSW=0.102322
++CJSWG=3.3E-10 PBSWG=0.8 MJSWG=0.102322
++CF=0 PVTH0=-2.199373E-3 PRDSW=-0.9368961
++PK2=1.593254E-3 WKETA=-2.880976E-3 LKETA=7.165078E-3
++PU0=6.777519 PUA=5.505418E-12 PUB=8.84133E-25
++PVSAT=2.006286E3 PETA0=1.003159E-4 PKETA=-6.759277E-3
++NOIMOD=2 NOIA=1.3182567385564E+19 NOIB=144543.977074592 NOIC=-1.24515784572817E-12 EF=0.92 EM=41000000)
+
+* MOSFET P TYPE
+.model CMOSP PMOS (LEVEL=49
++VERSION=3.1 TNOM=27 TOX=4.1n XJ=0.1u NCH=4.1589E17 VTH0=-0.3906012
++K1=0.5341312 K2=0.0395326 K3=0 K3B=7.4916211 W0=1E-6 NLX=1.194072E-7
++DVT0=0.5060555 DVT1=0.2423835 DVT2=0.1 U0=115.6894042 UA=1.573746E-9 UB=1.874308E-21
++UC=-1E-10 VSAT=1.130982E5 A0=1.9976555 AGS=0.4186945 B0=1.949178E-7 B1=6.422908E-7
++KETA=0.0166345 A1=0.4749146 A2=0.300003 RDSW=198.321294 PRWG=0.5 PRWB=-0.4986647
++WR=1 WINT=0 LINT=2.94454E-8 DWG=-2.798724E-8 DWB=-4.83797E-10
++VOFF=-0.095236 NFACTOR=2 CIT=0 CDSC=2.4E-4 ETA0=1.035504E-3 ETAB=-4.358398E-4
++DSUB=1.816555E-3 PCLM=1.3299898 PDIBLC1=1.766563E-3 PDIBLC2=7.728395E-7 PDIBLCB=-1E-3
++DROUT=1.011891E-3 PSCBE1=4.872184E10 PSCBE2=5E-10 PVAG=0.0209921 DELTA=0.01 RSH=7.7
++MOBMOD=1 UTE=-1.5 KT1=-0.11 KT2=0.022 UA1=4.31E-9 UB1=-7.61E-18 UC1=-5.6E-11 AT=3.3E4
++WL=0 WLN=1 WW=0 WWN=1 WWL=0 LL=0 LLN=1 LW=0 LWN=1
++CAPMOD=2 XPART=0.5 CGDO=6.35E-10 CGSO=6.35E-10 CGBO=1E-12
++CJ=1.144521E-3 PB=0.8468686 MJ=0.4099522 CJSW=2.490749E-10 PBSW=0.8769118 MJSW=0.3478565
++CJSWG=4.22E-10 PBSWG=0.8769118 MJSWG=0.3478565
++CF=0 PVTH0=2.302018E-3 PRDSW=9.0575312
++PK2=1.821914E-3 WKETA=0.0222457 LKETA=-1.495872E-3
++PU0=-1.5580645 PUA=-6.36889E-11 PUB=1E-21
++PVSAT=49.8420442 PETA0=2.827793E-5 PKETA=-2.536564E-3
++NOIMOD=2 NOIA=3.57456993317604E+18 NOIB=2500 NOIC=2.61260020285845E-11 EF=1.1388 EM=41000000)
+
+* ======================= AC SOURCE (Balanced Diff Pair) ==========
+* Reversed input polarity to fix output swing direction
+V2 in N006 SIN(0 15m 1k) AC -1
+V3 N003 N007 SIN(0 15m 1k) AC 1
+* Note. You can change this as input / testcase
+
+* ======================= SIMULATION CONTROL ========================
+.control
+set units=degrees
+
+* Estimated total power
+.print tran "Estimated total power :" (1u+51u+170u+30u)*v(N001)
+
+* === AC ANALYSIS ===
+ac dec 100 10 100Meg
+plot db(v(outamp)/(v(in)-v(N003)))
+plot phase(v(outamp)/(v(in)-v(N003)))
+
+* === TRANSIENT SWING ===
+tran 0.1u 5m
+plot v(outamp)
+.endc
+
+.end
diff --git a/blocks/composite/OpAmp Challenge-GenYZTeam/NGSPICE/test.txt b/blocks/composite/OpAmp Challenge-GenYZTeam/NGSPICE/test.txt
new file mode 100644
index 00000000..8b137891
--- /dev/null
+++ b/blocks/composite/OpAmp Challenge-GenYZTeam/NGSPICE/test.txt
@@ -0,0 +1 @@
+
diff --git a/blocks/composite/OpAmp Challenge-GenYZTeam/ReadMe.md b/blocks/composite/OpAmp Challenge-GenYZTeam/ReadMe.md
new file mode 100644
index 00000000..ca13252f
--- /dev/null
+++ b/blocks/composite/OpAmp Challenge-GenYZTeam/ReadMe.md
@@ -0,0 +1,130 @@
+# OPAMP Design Challenge
+
+## GenYZ Team
+*This is the copy of our [OpAmp Design Challenge from Github repository](https://github.com/aurxdeqo/GenYZ-GlayoutChallenge). However, you can also access our design in this repo.*
+
+## Op Amp Design Using LTSpice
+MODELS OR COMPONENTS USED
+- NPN: DI_MMBT3904
+- NMOS: CMOSN technology: 180nm
+- PMOS: CMOSP technology: 180nm
+- Capacitor 5pF for Load, Capacitor 10uF for Coupling
+
+Objective:
+Build an OpAmp using any suitable architecture with the GF180 PDK with the following baseline specifications at a 5pF Capacitive Load:
+- Supply Voltage: 1.8V
+- DC Gain: >70 dB
+- CMRR: >85 dB
+- Phase Margin: >45 degrees
+- Power Dissipation: <500 µW
+- Unity Gain Bandwidth: >10 MHz
+- Output Swing: >1.0 Vpp
+
+Our design have the design of 2 STAGE AMPLIFIER :
+
+ 
+
+Figure 1. Operational Amplifier Design Using LTSpice
+
+
+
+ 
+ 
+
+
+ Figure 2. Bode Plot for AC Simulatiom
+ Figure 3. Vout in Transient Mode for Output Swing
+
+
+
+ 
+ 
+
+
+ Figure 4. DC Operating Point (1)
+ Figure 5. Vout DC Operating Point (2)
+
+
+
+
+---
+## Layout Design Using Jupyter Notebook
+
+- Gitclone this repo
+ ```bash
+ git clone https://github.com/aurxdeqo/gLayout-genyz-team.git'
+- Go to the folder
+ ```bash
+ cd gLayout-genyz-team/JupyterNotebook
+- Start and run Jupyter notebook
+ ```bash
+ jupyter notebook
+- search for [Layout](JupyterNotebook/opamp_challenge_final.ipynb) on jupyter notebook file, and run the file
+
+- When u run the .ipynb file, you should see the display as below.
+
+ 
+
+Figure 6. Display on Jupyter Notebook
+
+- When you open the generated .gds file after running the .ipynb file, you should see the display as below.
+
+ 
+
+Figure 7. Display on K-Layout
+
+---
+## Testbench Using NGspice
+*Note about the Specification Checking*: *Ngspice simulation still fulfill the below specification, but different from our original design in LTSPICE. The issue might be due to differences in MOSFET models, as some parameters defined in LTspice may be undefined or incompatible in Ngspice. We showed you expected result from LTSPICE above already. You can see Ngspice simulation by the step above.*
+- Gitclone this repo
+ ```bash
+ git clone https://github.com/aurxdeqo/gLayout-genyz-team.git'
+
+- Go to the folder
+ ```bash
+ cd gLayout-genyz-team/NGSpice
+
+- Download and run [testbench](NGSPICE/opampchallenge.cir) on ngspice
+ ```bash
+ # on ngspice terminal
+ ngspice opampchallange.cir
+
+- After running the .cir file, you should see some plots, showing you the parameter given for the specs. You can see Gain DC, Phase Margin (Phase at 0dB Gain + 180deg), Unity Gain Bandwith/Frequency from Bodeplot Magnitude and Phase. You can also see the Output swing from the plot .tran simulation.
+
+---
+## Manual Testbench for CMRR and Power Consumption
+- CMRR can be observed as follow (manually)
+ Update input sources for differential mode and common mode in LT SPICE
+ (1) Open opamp_design.asc file for LTSPICE in the NgSPICE folder
+ (2) Make sure you have the library TSMC 180 for 180nm Technology
+ Download the following files (*Credits from Sanjay Vihdyadharan on Youtube)
+ https://sanjayvidhyadharan.in/Downloads
+ (a) tsmc018.lib
+ (b) cmosn.asy
+ (c) cmosp.asy
+ export it in your LTSPICE to use the component models.
+
+- For Differential Input, we used it as a testbench here (VIN AC +1 and -1). Adiff +/- 93.88dB
+
+
+ 
+
+Figure 8. CMRR Simulation (1)
+
+- For Common mode, use the same AC 1 0 (same amplitude and same phase for VIN AC). You will get Acommon-mode is +/- 10dB
+
+
+ 
+
+Figure 9. CMRR Simulation (2)
+
+- As result you can count that CMRR = 20*log(Adiff/Acomm) = Adiff(dB) - Acomm(dB) = +/- 84/85 dB
+
+- Power consumption
+ Since the I and VDD is constant, the power consumption (I1+I2+I3+I4)*VDD = 451.8 uW (under 500uW). You can see from the circuit.
+
+---
+## Problems and Suggestion
+1. We still struggle to optimize the placement for routing the components
+2. Opamp we designed might use different model which doesnt exists in glayout lib. We spent time to make the Pcell of component we needed too.
+3. Simulation for testbench using Ngspice prone of errors, couldn't print 2 of the parameter we wanted. We simulated it manually
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+