upload ovm_demo_v3

Author: RedFlag2017

ovm_demo_v3/00_src/and2.v

@@ -0,0 +1,15 @@
+module and2 (
+  output reg Y,
+  input A, B,
+  input clk,
+  input rst);
+
+always @(posedge clk or negedge rst)
+begin
+	if(rst==1)
+		Y <= 0;
+	else
+		Y= A&B;
+end
+
+endmodule

ovm_demo_v3/03_st/00_bench/agent/and_agent/and_agent.sv

@@ -0,0 +1,45 @@
+class and_agent extends ovm_component;
+  
+  `ovm_component_utils(and_agent);
+  virtual and_if and_vif;
+  function new(string name, ovm_component parent);
+    super.new(name, parent);
+  endfunction
+
+  function void build();
+    ovm_report_info("build", "");
+    
+  endfunction
+
+  function void connect();
+    ovm_report_info("connect", "");
+  endfunction
+
+  function void end_of_elaboration();
+    ovm_report_info("end_of_elaboration", "");
+  endfunction
+
+  function void start_of_simulation();
+    ovm_report_info("start_of_simulation", "");
+  endfunction
+
+  task run();
+    ovm_report_info("run", "");
+
+  endtask
+
+  function void extract();
+    ovm_report_info("extract", "");
+  endfunction
+
+  function void check();
+    ovm_report_info("check", "");
+  endfunction
+
+  function void report();
+    ovm_report_info("report", "");
+  endfunction	
+  
+
+	
+endclass

ovm_demo_v3/03_st/00_bench/agent/and_agent/and_agent.svh

@@ -0,0 +1,2 @@
+`include "../00_bench/agent/and_agent/and_if.sv"  
+`include "../00_bench/agent/and_agent/and_agent.sv"

ovm_demo_v3/03_st/00_bench/agent/and_agent/and_if.sv

@@ -0,0 +1,32 @@
+interface and_if();
+	logic rst;
+	logic clk;
+	logic A;
+	logic B;
+	logic Y;
+parameter U_DLY = 1ps;	
+	
+	initial begin
+		if(rst==1)
+		begin
+			A<=0;
+			B<=0;
+		end	
+		else 
+			gen_AB();
+		
+	end
+		
+	task gen_AB();
+  	automatic int stim_num=100;
+  	
+  	while(stim_num>0) begin
+  		@(posedge clk)
+  		A<=#U_DLY $random();
+  		B<=#U_DLY $random();
+  		stim_num--;
+  	end
+  endtask: gen_AB
+			
+	
+endinterface:and_if

ovm_demo_v3/03_st/00_bench/clk_rst/clock_gen.sv

@@ -0,0 +1,35 @@
+// ~~~~~~~~ ~~~~~~~~ ~~~~~~~~ ~~~~~~~~ ~~~~~~~~ ~~~~~~~~
+// ~ --
+// ~ Published by:   www.asic-digital-design.com
+// ~ --
+// ~ Description: This is clock generator model.
+// ~ --
+// ~~~~~~~~ ~~~~~~~~ ~~~~~~~~ ~~~~~~~~ ~~~~~~~~ ~~~~~~~~
+//`timescale 1ps/1ps
+module clock_gen ( clk, arst );
+  output clk;
+  input  arst;
+
+  parameter param_time_end_of_sim   = 1000000;
+  parameter param_clock_half_period = 50;
+  reg clk_i;
+
+  // clock generation
+  initial begin
+    {clk_i} <= 1'b0;
+    #(param_time_end_of_sim) $finish;
+  end
+  //end initial
+
+  always @(*)
+  begin
+  	if(arst==1)
+  	   {clk_i} <= 1'b0;
+  	else
+  		#(param_clock_half_period) {clk_i} <= ~(clk_i);
+  end
+
+  // outputs --
+  assign {clk}=clk_i;
+  //--
+endmodule

ovm_demo_v3/03_st/00_bench/clk_rst/reset_gen.sv

@@ -0,0 +1,26 @@
+// ~~~~~~~~ ~~~~~~~~ ~~~~~~~~ ~~~~~~~~ ~~~~~~~~ ~~~~~~~~
+// ~ --
+// ~ Published by:   www.asic-digital-design.com
+// ~ --
+// ~ Description: This is reset generator model.
+// ~ --
+// ~~~~~~~~ ~~~~~~~~ ~~~~~~~~ ~~~~~~~~ ~~~~~~~~ ~~~~~~~~
+//`timescale 1ps/1ps
+module reset_gen ( arst );
+  output arst;
+
+  parameter param_reset_delay = 25;
+  
+  reg arst_i;
+
+  // reset generation
+  initial begin
+                          {arst_i}<=1'b1;
+    #(param_reset_delay)  {arst_i}<=1'b0;
+  end
+  //end initial
+
+  // outputs --
+  assign {arst}=arst_i;
+  //--
+endmodule

ovm_demo_v3/03_st/00_bench/harness.sv

@@ -0,0 +1,43 @@
+import ovm_pkg::*;
+`timescale 1ps/1ps
+`include "../00_bench/clk_rst/reset_gen.sv"
+`include "../00_bench/clk_rst/clock_gen.sv"
+
+`include "ovm_macros.svh"
+
+`include "../00_bench/agent/and_agent/and_agent.svh"
+
+module harness();
+`include "../00_bench/testbench/tb.svh"
+`include "../03_testcase/tc.svh"
+
+//output logic Clock; 
+
+//logic arst;
+and_if u_and_vif();
+
+reset_gen  u_reset_gen(u_and_vif.rst);
+clock_gen #(.param_time_end_of_sim(10000),.param_clock_half_period(50)) u_clock_gen( u_and_vif.clk, u_and_vif.rst );
+
+initial begin
+	$display("greetting from harness");
+	fork
+//		print_signal();
+
+	join_none
+	run_test();
+	$display("hahahhahh");
+//	run_test();
+end
+
+
+and2 duv(
+  .Y(u_and_vif.Y),
+  .A(u_and_vif.A),
+  .B(u_and_vif.B),
+  .clk(u_and_vif.clk),
+  .rst(u_and_vif.rst)
+  );
+
+endmodule
+

ovm_demo_v3/03_st/00_bench/testbench/tb.sv

@@ -0,0 +1,52 @@
+class tb extends ovm_component;
+  
+  `ovm_component_utils(tb);
+  
+  and_agent o_and_agent;
+  virtual and_if and_vif;
+  
+  
+  function new(string name, ovm_component parent);
+    super.new(name, parent);
+  endfunction
+
+  function void build();
+    ovm_report_info("build", "");
+    o_and_agent = new("o_and_agent",this);
+    this.and_vif = o_and_agent.and_vif;
+  endfunction
+
+  function void connect();
+    ovm_report_info("connect", "");
+  endfunction
+
+  function void end_of_elaboration();
+    ovm_report_info("end_of_elaboration", "");
+  endfunction
+
+  function void start_of_simulation();
+    ovm_report_info("start_of_simulation", "");
+  endfunction
+
+  task run();
+    ovm_report_info("run", "");
+
+  endtask
+
+  function void extract();
+    ovm_report_info("extract", "");
+  endfunction
+
+  function void check();
+    ovm_report_info("check", "");
+  endfunction
+
+  function void report();
+    ovm_report_info("report", "");
+  endfunction	
+  
+  function void tb_func();
+  	ovm_report_info("tb_func", "hello");
+  endfunction: tb_func
+	
+endclass

ovm_demo_v3/03_st/00_bench/testbench/tb.svh

@@ -0,0 +1 @@
+`include "../00_bench/testbench/tb.sv"

ovm_demo_v3/03_st/02_script/rtl.f

@@ -0,0 +1,3 @@
+../../00_src/and2.v
+
+../00_bench/harness.sv 

ovm_demo_v3/03_st/02_script/run.bat

@@ -0,0 +1,9 @@
+::¹Ø±Õ»ØÏÔ
+::@ECHO OFF
+::ÉèÖÃÈí¼þ·¾¶
+
+
+
+vsim -c -do sim.do
+
+pause

ovm_demo_v3/03_st/02_script/sim.do

@@ -0,0 +1,13 @@
+set TEST_NAME tc01
+
+vlib ../10_sim/work
+vmap work ../10_sim/work
+vlog -L mtiAvm -L mtiOvm -L mtiUvm -L mtiUPF  -f rtl.f ../00_bench/harness.sv
+vsim  -novopt work.harness +OVM_TESTNAME=$TEST_NAME 
+
+   
+add wave sim:/harness/u_and_vif/*     
+add wave sim:/harness/duv/* 
+view structure  
+view signals 
+run -all

ovm_demo_v3/03_st/03_testcase/tc.svh

@@ -0,0 +1 @@
+`include "../03_testcase/tc01/tc01.sv"

ovm_demo_v3/03_st/03_testcase/tc01/tc01.sv

@@ -0,0 +1,48 @@
+class tc01 extends ovm_test;
+  
+  `ovm_component_utils(tc01);
+  tb o_tb;
+  
+  function new(string name, ovm_component parent);
+    super.new(name, parent);
+  endfunction
+
+  function void build();
+    ovm_report_info("build", "");
+    o_tb = new("o_tb",this);
+    o_tb.and_vif = harness.u_and_vif;
+  endfunction
+
+  function void connect();
+    ovm_report_info("connect", "");
+  endfunction
+
+  function void end_of_elaboration();
+    ovm_report_info("end_of_elaboration", "");
+  endfunction
+
+  function void start_of_simulation();
+    ovm_report_info("start_of_simulation", "");
+  endfunction
+
+  task run();
+    ovm_report_info("tc01", "start");
+		o_tb.tb_func();
+    #10000ps;
+    global_stop_request();
+    ovm_report_info("tc01", "finish");
+  endtask
+
+  function void extract();
+    ovm_report_info("extract", "");
+  endfunction
+
+  function void check();
+    ovm_report_info("check", "");
+  endfunction
+
+  function void report();
+    ovm_report_info("report", "");
+  endfunction	
+	
+endclass