allow clippy lints

Author: zeegomo

blake2/src/as_bytes.rs

@@ -8,6 +8,7 @@
 use core::mem;
 use core::slice;
 
+#[allow(clippy::missing_safety_doc)]
 pub unsafe trait Safe {}
 
 pub trait AsBytes {

blake2/src/simd.rs

@@ -15,6 +15,7 @@ pub use self::simdty::{u32x4, u64x4};
 pub trait Vector4<T>: Copy {
     fn gather(src: &[T], i0: usize, i1: usize, i2: usize, i3: usize) -> Self;
 
+    #[allow(clippy::wrong_self_convention)]
     fn from_le(self) -> Self;
     fn to_le(self) -> Self;
 

sha1/src/compress/soft.rs

@@ -201,6 +201,7 @@ fn sha1_digest_block_u32(state: &mut [u32; 5], block: &[u32; 16]) {
     let mut w1 = [block[4], block[5], block[6], block[7]];
     let mut w2 = [block[8], block[9], block[10], block[11]];
     let mut w3 = [block[12], block[13], block[14], block[15]];
+    #[allow(clippy::needless_late_init)]
     let mut w4;
 
     let mut h0 = [state[0], state[1], state[2], state[3]];

sha1/src/compress/x86.rs

@@ -52,6 +52,7 @@ unsafe fn digest_blocks(state: &mut [u32; 5], blocks: &[[u8; 64]]) {
         let mut w1 = _mm_shuffle_epi8(_mm_loadu_si128(block_ptr.offset(1)), MASK);
         let mut w2 = _mm_shuffle_epi8(_mm_loadu_si128(block_ptr.offset(2)), MASK);
         let mut w3 = _mm_shuffle_epi8(_mm_loadu_si128(block_ptr.offset(3)), MASK);
+        #[allow(clippy::needless_late_init)]
         let mut w4;
 
         let mut h0 = state_abcd;

whirlpool/src/lib.rs

@@ -126,6 +126,8 @@ impl WhirlpoolCore {
     }
 }
 
+// derivable impl does not inline
+#[allow(clippy::derivable_impls)]
 impl Default for WhirlpoolCore {
     #[inline]
     fn default() -> Self {