Alpha channel, top.v rewrite, new panel

Author: Subserial

alpha_blend.v

@@ -2,18 +2,27 @@
 
 module alpha_blend (
   input  clk,
-  input  [23:0] colorTop, colorBot,
-  input  [7:0]  alphaTop,
-  input  valid,
-  output ready,
-  output [23:0] colorOut);
+  input     [23:0] colorTop, colorBot,
+  input     [7:0]  alphaTop,
+  input            valid,
+  input            ack,
+  output reg       validOut,
+  output           ready,
+  output reg [23:0] colorOut
+);
 
-  localparam STATE_WAIT = 2'b0;
-  localparam STATE_MULT = 2'b1;
-  localparam STATE_ADD = 2'b2;
-  reg [1:0] state, nextState;
+  localparam STATE_WAIT = 2'b00;
+  localparam STATE_MULT = 2'b01;
+  localparam STATE_ADD = 2'b10;
+  reg [1:0] state=STATE_WAIT, nextState;
 
-  assign ready = (nextState == STATE_WAIT);
+  
+  wire [15:0] redSum, greenSum, blueSum;
+  
+  assign ready = (state == STATE_WAIT);
+  assign redSum = (redTop + redBot + 15'h00FF);
+  assign greenSum = (greenTop + greenBot + 15'h00FF);
+  assign blueSum = (blueTop + blueBot + 15'h00FF);
 
   always @(*) begin
     case (state)
@@ -22,7 +31,7 @@ module alpha_blend (
     end
     STATE_MULT: nextState = STATE_ADD;
     STATE_ADD: nextState = STATE_WAIT;
-    default: nextState = state_WAIT;
+    default: nextState = STATE_WAIT;
     endcase
   end
 
@@ -34,7 +43,8 @@ module alpha_blend (
 
   always @(posedge clk) begin
     state <= nextState;
-    ready <= 0;
+    if (ack)
+      validOut <= 0;
     case (state)
     STATE_WAIT: begin
       case (nextState)
@@ -54,15 +64,15 @@ module alpha_blend (
       redTop <= redTop * alpha;
       greenTop <= greenTop * alpha;
       blueTop <= blueTop * alpha;
-      redBot <= redBot * (255 - alpha);
-      greenBot <= greenBot * (255 - alpha);
-      blueBot <= blueBot * (255 - alpha);
+      redBot <= redBot * (16'hFF - {8'h00, alpha});
+      greenBot <= greenBot * (16'hFF - {8'h00, alpha});
+      blueBot <= blueBot * (16'hFF - {8'h00, alpha});
     end
     STATE_ADD: begin
-      colorOut[23:16] <= (redTop + redBot + 15'h00FF)[15:8];
-      colorOut[15:8] <= (greenTop + greenBot + 15'h00FF)[15:8];
-      colorOut[7:0] <= (blueTop + blueBot + 15'h00FF)[15:8];
-      ready <= 1;
+      colorOut[23:16] <= redSum[15:8];
+      colorOut[15:8] <= greenSum[15:8];
+      colorOut[7:0] <= blueSum[15:8];
+      validOut <= 1;
     end
     default: begin end
     endcase

coord.v

@@ -0,0 +1,8 @@
+module coord (
+  input  [9:0] index,
+  output [9:0] x,
+  output [9:0] y);
+  
+  assign x = {3'h0, index[9:3]};
+  assign y = {7'h00, (index[3] ? ~index[2:0] : index[2:0])};
+endmodule // coord

panel_bg.v

@@ -1,23 +1,39 @@
 `default_nettype none
 
 module panel_bg (
-  input        clk,
-  input        valid,
-  input  [9:0] index,
-  output       ready,
-  output [7:0] red, blue, green,
-  output [7:0] alpha,
-  output [1:0] blend
+  input            clk,
+  input            valid,
+  input            tick,
+  input      [9:0] x, y,
+  input            ack,
+  output reg       validOut,
+  output           ready,
+  output reg [7:0] red, green, blue,
+  output reg [7:0] alpha
 );
-
-  wire [9:0] true_index;
-  assign true_index = {index[9:3], (index[3] ? ~index[2:0] : index[2:0])};
-
-  assign red = {5'h00, true_index[2:0]};
-  assign blue = {5'h00, true_index[5:3]};
-  assign green = {5'h00, true_index[8:6]};
-  assign alpha = 8'hFF;
-  assign blend = 2'h0;
-  assign ready = valid;
+  
+  reg [10:0] offset = 0;
+  wire [9:0] x_pos, y_pos;
+  
+  assign x_pos = x;
+  assign y_pos = y + {6'h00, offset[4:1]};
+  
+  assign ready = 1;
+  
+  always @(posedge clk) begin
+    if (ack)
+      validOut <= 0;
+    if (valid) begin
+      if (tick) begin
+        offset <= offset + 1;
+      end else begin
+        red <= {5'h00, x_pos[2:0]};
+        green <= {2'h0, x_pos[7:3], 1'b0};
+        blue <= 8'h00;
+        alpha <= 8'hFF;
+        validOut <= 1;
+      end
+    end
+  end
 
 endmodule // panel_bg

panel_cube.v

@@ -0,0 +1,50 @@
+`default_nettype none
+
+module panel_cube (
+  input            clk,
+  input            valid,
+  input            tick,
+  input      [9:0] x, y,
+  input            ack,
+  output reg       validOut,
+  output           ready,
+  output reg [7:0] red, blue, green,
+  output reg [7:0] alpha
+);
+  
+  reg [9:0] offset = 0;
+  wire [9:0] x_pos, y_pos;
+  
+  assign x_pos = x + offset;
+  assign y_pos = y;
+  
+  wire [2:0] x_pos_off;
+  assign x_pos_off = x_pos[2:0] - 3'd2;
+  
+  assign ready = 1;
+  
+  always @(posedge clk) begin
+    if (ack)
+      validOut <= 0;
+    if (valid) begin
+      if (tick) begin
+        offset <= offset + 1;
+      end else begin
+        validOut <= 1;
+        if (x_pos[2:0] > 1 && x_pos[2:0] < 6
+            && y_pos[2:0] > 1 && y_pos[2:0] < 6) begin
+          red <= 0;
+          green <= 0;
+          blue <= 8'h3F;
+          alpha <= {x_pos_off[1:0], 6'h3F};
+        end else begin
+          red <= 0;
+          green <= 0;
+          blue <= 0;
+          alpha <= 0;
+        end
+      end
+    end
+  end
+
+endmodule // panel_cube

pixel_driver.v

@@ -14,7 +14,7 @@ module pixel_driver
     parameter CNT_COLOR=24,
     parameter RESET_VERIFY=800) (
   input        clk,
-  input  [7:0] red, blue, green,
+  input  [7:0] red, green, blue,
   input        reset,
   input        valid,
   output       ready,
@@ -25,7 +25,7 @@ module pixel_driver
   localparam TIMING_FAILURE = (RESET_VERIFY <= TCK_RESET);
 
   localparam CNT_BITS = $clog2(CNT_COLOR);
-  localparam TCK_BITS = $clog2(TCK_RESET);
+  localparam TCK_BITS = 32;
 
   // pixel buffer storage
   reg [22:0] stored;
@@ -37,16 +37,11 @@ module pixel_driver
 
   // State machine init
   localparam STATE_WAIT=0, STATE_RESET=1, STATE_COLOR=2;
-  reg  [1:0] state=STATE_WAIT;
-  reg  [1:0] nextState;
+  reg  [1:0] state=STATE_WAIT, nextState;
 
-  // output signals determined by zero states
   assign ready = (state == STATE_WAIT);
   assign clk_out = ~(tick_on == 0);
 
-  wire next_ready;
-  assign next_ready = (count == 0 && tick == 1);
-  
   // STATE_WAIT: No command received.
   // STATE_COLOR: Consume stored buffer and translate to PWM output.
   // STATE_RESET: Hold clock low for a while to indicate new output chain.
@@ -62,7 +57,7 @@ module pixel_driver
           nextState = STATE_WAIT;
       end
       STATE_RESET,STATE_COLOR: begin
-        if (next_ready)
+        if (count == 0 && tick == 1)
           nextState = STATE_WAIT;
         else
           nextState = state;