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simulation_RAM1.mem
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19 lines (19 loc) · 1.44 KB
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// memory data file (do not edit the following line - required for mem load use)
// instance=/tb_project_v2/uut/M2_unit/dual_port_RAM_inst1/altsyncram_component/mem_data
// format=mti addressradix=d dataradix=h version=1.0 wordsperline=8
0: 00002289 0000002b 00000000 00000000 00000000 00000000 00000000 00000000
8: 0000231d fffffe32 00000000 00000000 00000000 00000000 00000000 00000000
16: 000023f2 fffffe79 00000000 00000000 00000000 00000000 00000000 00000000
24: 00002494 000000f4 00000000 00000000 00000000 00000000 00000000 00000000
32: 000024ad 00000000 00000000 00000000 00000000 00000000 00000000 00000000
40: 00002439 00000000 00000000 00000000 00000000 00000000 00000000 00000000
48: 00002387 00000000 00000000 00000000 00000000 00000000 00000000 00000000
56: 00002306 00000000 00000000 00000000 00000000 00000000 00000000 00000000
64: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
72: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
80: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
88: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
96: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
104: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
112: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
120: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000