How to implement batch processing for NAND/AND/OR logic gates?

[black6816]

I would like to inquire about methods for batch processing NAND, AND, and OR logic gates. Could you provide guidance or implementation approaches for handling these gates in bulk operations?

[cgouert]

We have an example that demonstrates distributing a large batch of NAND gates across multiple GPUs (see lines 85-99 for instance for submitting multiple gates to a GPU); in a similar way to the original cuFHE, gates are evaluated on a per-stream basis; at a high-level, each GPU can be evaluate N gates in parallel where N is the number of streaming multiprocessors in the specific card. Additionally, if you are looking for a higher level batched API, nuFHE gate operations can process multiple ciphertexts automatically.

[black6816]

In this file redcufhe_bootstrap_gpu.cu line 504~556, the kernel can evaluate 1 gate. Can these kernels evaluate multi gates, like XnorBootstrap<<<batchsize, 512>>>() ?

[cgouert]

The bootstrap kernels only support single gate evaluations; they could be modified to support multiple gates per kernel, but you may not see any throughput gains relative to the current strategy.