Skip to content

Commit 989fc3e

Browse files
committed
Reverted workaround from 6aedc46.
1 parent ef8b83e commit 989fc3e

File tree

5 files changed

+9
-7
lines changed

5 files changed

+9
-7
lines changed

.github/workflows/Simulate.yml

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -307,9 +307,11 @@ jobs:
307307
}
308308
309309
if {$::osvvm::ToolName eq "GHDL"} {
310+
SetExtendedAnalyzeOptions {-frelaxed -Wno-specs -Wno-elaboration}
310311
SetExtendedSimulateOptions {-frelaxed -Wno-specs -Wno-binding}
311312
}
312313
if {$::osvvm::ToolName eq "NVC"} {
314+
SetExtendedAnalyzeOptions {--relaxed}
313315
}
314316
315317
build ../../tb/RunAllTests.pro

regression.tcl

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -31,7 +31,7 @@ source ../lib/OSVVM-Scripts/StartUp.tcl
3131
build ../lib/OsvvmLibraries.pro
3232

3333
if {$::osvvm::ToolName eq "GHDL"} {
34-
SetExtendedAnalyzeOptions {-frelaxed -Wno-specs -Wno-elaboration}
34+
SetExtendedAnalyzeOptions {-frelaxed -Wno-specs -Wno-elaboration}
3535
SetExtendedSimulateOptions {-frelaxed -Wno-specs -Wno-binding}
3636
}
3737

src/arith/arith_cca.vhdl

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -102,7 +102,7 @@ architecture rtl of arith_cca is
102102

103103
begin
104104
genRCA: if not CCA generate
105-
assert false
105+
assert true -- false WORAROUND for OSVVM 2025.02
106106
report "Using standard RCA for small "&integer'image(N)&"-bit adder."
107107
severity note;
108108
s <= std_logic_vector(unsigned(a)+unsigned(b)+(0 to 0 => c));

src/arith/xilinx/arith_cca_xilinx.vhdl

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -101,7 +101,7 @@ architecture rtl of arith_cca is
101101

102102
begin
103103
genRCA: if not CCA generate
104-
assert false
104+
assert true -- false WORAROUND for OSVVM 2025.02
105105
report "Using standard RCA for small "&integer'image(N)&"-bit adder."
106106
severity note;
107107
s <= std_logic_vector(unsigned(a)+unsigned(b)+(0 to 0 => c));

tb/arith/div/arith_div_Simple.vhdl

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -100,8 +100,8 @@ begin
100100
WaitForClock(Clock);
101101
wait for 1 ns;
102102
Start <= '0';
103-
A <= (A'range => '-'); -- (others => '-'); WORKAROUND: NVC 1.18.2 Linux
104-
D <= (D'range => '-'); -- (others => '-');
103+
A <= (others => '-');
104+
D <= (others => '-');
105105
done := (others => false);
106106

107107
loop
@@ -136,8 +136,8 @@ begin
136136

137137
begin
138138
Start <= '0';
139-
A <= (A'range => '-'); -- (others => '-'); WORKAROUND: NVC 1.18.2 Linux
140-
D <= (D'range => '-'); -- (others => '-');
139+
A <= (others => '-');
140+
D <= (others => '-');
141141

142142
-- Initialize Random
143143
Random.InitSeed(Random'instance_name);

0 commit comments

Comments
 (0)