2024.2 Release

Author: ryanvergel

General/DFX/Embedded_IOB_inside_RM/constraints/io.xdc

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+#
+# Copyright (C) 2024, Advanced Micro Devices, Inc. All rights reserved.
+# SPDX-License-Identifier: X11
+#
+
+set_property PACKAGE_PIN BF33 [get_ports [list {IOBUF_IO_IO[0]}]]
+set_property IOSTANDARD SSTL12 [get_ports [list {IOBUF_IO_IO[0]}]]
+
+set_property PACKAGE_PIN BF29 [get_ports [list {GPIO_0_tri_o[0]}]]
+set_property IOSTANDARD SSTL12 [get_ports [list {GPIO_0_tri_o[0]}]]

General/DFX/Embedded_IOB_inside_RM/constraints/io_child_0_impl_1.xdc

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+#
+# Copyright (C) 2024, Advanced Micro Devices, Inc. All rights reserved.
+# SPDX-License-Identifier: X11
+#
+
+set_property PACKAGE_PIN BF33 [get_ports [list {IOBUF_IO_IO[0]}]]
+set_property IOSTANDARD SSTL12 [get_ports [list {IOBUF_IO_IO[0]}]]
+

General/DFX/Embedded_IOB_inside_RM/constraints/pblocks.xdc

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+#
+# Copyright (C) 2024, Advanced Micro Devices, Inc. All rights reserved.
+# SPDX-License-Identifier: X11
+#
+
+create_pblock pblock_rp1
+add_cells_to_pblock [get_pblocks pblock_rp1] [get_cells -quiet [list design_1_i/rp1]]
+resize_pblock [get_pblocks pblock_rp1] -add {CLOCKREGION_X3Y1:CLOCKREGION_X3Y2}
+resize_pblock [get_pblocks pblock_rp1] -add {CLOCKREGION_X4Y0}
+set_property SNAPPING_MODE ON [get_pblocks pblock_rp1]
+
+
+

General/DFX/Embedded_IOB_inside_RM/images/IO_BUFFER_TYPE.png

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+<table class="sphinxhide" width="100%">
+ <tr width="100%">
+    <td align="center"><img src="https://github.com/Xilinx/Image-Collateral/blob/main/xilinx-logo.png?raw=true" width="30%"/><h1>Versal™ Adaptive SoC DFX Tutorials</h1>
+    <a href="https://www.amd.com/en/products/software/adaptive-socs-and-fpgas/vivado.html">See Vivado™ Development Environment on amd.com</a>
+    </td>
+ </tr>
+</table>
+
+# Embedded IO Buffers inside Reconfigurable Partition
+
+***Version: AMD Vivado&trade; 2024.2***
+
+## Introduction
+
+This design demonstrates the methodology to adopt in an AMD Vivado&trade; IPI based DFX flow to instantiate Input/Output Buffers inside the reconfigurable partition. In the DFX flow, if a reconfigurable pblock includes an IO bank, the corresponding IO buffers must be located logically inside the corresponding reconfigurable module hieararchy. By default, Vivado flow infers IOBs at the top level. This tutorial demonstrates the method using Utility Buffer IP in IPI to instantiate IOBs inside the reconfigurable module.  
+
+This tutorial demoes the following :
+1. Instantiation of IOBs inside a reconfigurable module block design using the Utility Buffer IP.
+2. Use RTL attribute "IO_BUFFER_TYPE NONE" on the top port to convey the Vivado flow to not to infer IOBs at the top level.
+3. Create and apply a constraint set for child implementation, which is different from constraint set used for parent implementation.
+
+## Design Flow
+
+Follow the design flow from tutorial "1RP_AXI_GPIO_in_RP_Interface_INI" to become familiar with the IPI based DFX design flow using the block design container feature. This is the same flow used for this tutorial. 
+
+### IPI
+
+- As shown in the IPI diagram below, this is a design with one reconfigurable partition. Note that there are two AXI GPIOs in RP1 for demo purpose. axi_gpio_0 is connected to a utility buffer which is configured as "IOBUF", whereas axi_gpio_1 is directly taken as output port of design. This is to demo that for the latter, an OBUF is infered at the top level by the tool, where as for the former, an IOBUF is instantiated inside the reconfigurable module. 
+
+<p align="center">
+  <img src="./images/top_bd.png?raw=true" alt="top bd"/>
+</p>
+
+- Here is the IP customization of Utility Buffer. For this design, it is configured as an IOBUF. 
+
+<p align="center">
+  <img src="./images/utility_buffer.png?raw=true" alt="utility buffer"/>
+</p>
+
+
+### IO_BUFFER_TYPE RTL Attribute
+- Apply the IO_BUFFER_TYPE attribute on any top-level port to instruct the tool to use buffers. Add the property with a value "NONE" to disable automatic inference of buffers at the top. More details about this attribute are provided in [Vivado Design Suite User Guide: Synthesis (UG901)](https://docs.xilinx.com/access/sources/dita/topic?Doc_Version=2023.2%20English&url=ug901-vivado-synthesis&resourceid=fbp1697798409980.html). In this design, set the property to NONE for the top port that already has buffer instantiated inside the module.
+
+<p align="center">
+  <img src="./images/IO_BUFFER_TYPE.png?raw=true" alt="IO_BUFFER_TYPE"/>
+</p>
+
+
+### Schematic
+
+- Here is the schematic of the two IOBs used in the design. The infered IOB is at the top, whereas the utility buffer instantiated IOBUF is inside the reconfigurable partition. 
+<p align="center">
+  <img src="./images/schematic.png?raw=true" alt="schematic"/>
+</p>
+
+### IOB Device View
+- The following figure shows that the physical location of the IOB inside reconfigurable module should be inside the corresponding pblock, whereas the top level static IO buffer can be located anywhere outside the reconfigurable partition. 
+
+<p align="center">
+  <img src="./images/iob_device_view.png?raw=true" alt="iob_device_view"/>
+</p>
+
+### Different Constraints set for Child Implementation
+
+- The Vivado DFX flow supports applying different constraint sets for different implementations. In this example, constraint set constrs_1 has the floorplanning constraints and IOB constraints. In the DFX flow, the child implementation is initiated from the output DCP from the parent implementation where each reconfigurable partition is blackboxed. While blackboxing the reconfigurable partition, the corresponding embedded IOBs are lost from netlist, thereby its constraints are removed as well. Hence, you must reapply PACKAGE_PIN and IOSTANDARD constraints for any embedded IOBs inside each RM for child implementation runs. This is achieved by creating a new constraints set "constrs_2" and applying it for the child implementation.  
+
+
+<p align="center">
+  <img src="./images/child_impl_constraints.png?raw=true" alt="child implementation constraints"/>
+</p>
+
+- Ensure the new constraints set is manually applied to the child implementation by enabling it in the child implementation properties window.
+
+<p align="center">
+  <img src="./images/constrs_2_child_impl.png?raw=true" alt="constrs_2_child_impl"/>
+</p>
+
+- Observe that the Design Runs window is also updated to confirm that parent and child implementations each use different constraints sets.
+
+<p align="center">
+  <img src="./images/design_runs_window.png?raw=true" alt="design_runs_window"/>
+</p>
+
+
+
+<hr class="sphinxhide"></hr>
+
+<p class="sphinxhide" align="center"><sub>Copyright © 2020–2024 Advanced Micro Devices, Inc.</sub></p>
+
+<p class="sphinxhide" align="center"><sup><a href="https://www.amd.com/en/corporate/copyright">Terms and Conditions</a></sup></p>

General/DFX/Embedded_IOB_inside_RM/images/child_impl_constraints.png

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+#
+# Copyright (C) 2024, Advanced Micro Devices, Inc. All rights reserved.
+# SPDX-License-Identifier: X11
+#
+
+cd scripts
+vivado -mode tcl -source run_all.tcl

General/DFX/Embedded_IOB_inside_RM/images/constrs_2_child_impl.png

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+#
+# Copyright (C) 2024, Advanced Micro Devices, Inc. All rights reserved.
+# SPDX-License-Identifier: X11
+#
+
+#Creating a hierarchy for rp1 and rp2
+group_bd_cells rp1 [get_bd_cells util_ds_buf_0] [get_bd_cells axi_gpio_0] [get_bd_cells axi_gpio_1]
+#Creating a hierarchy for static region
+group_bd_cells static_region [get_bd_cells clk_wizard_0] [get_bd_cells proc_sys_reset_0] [get_bd_cells smartconnect_0] [get_bd_cells versal_cips_0] [get_bd_cells proc_sys_reset_0] [get_bd_cells dfx_decoupler_0] [get_bd_cells axi_noc_0]
+regenerate_bd_layout
+validate_bd_design
+save_bd_design
+
+set curdesign [current_bd_design]
+create_bd_design -cell [get_bd_cells /rp1] rp1rm1
+current_bd_design $curdesign
+set new_cell [create_bd_cell -type container -reference rp1rm1 rp1_temp]
+replace_bd_cell [get_bd_cells /rp1] $new_cell
+delete_bd_objs  [get_bd_cells /rp1]
+set_property name rp1 $new_cell
+current_bd_design [get_bd_designs rp1rm1]
+update_compile_order -fileset sources_1
+validate_bd_design
+save_bd_design
+
+
+current_bd_design [get_bd_designs design_1]
+validate_bd_design
+save_bd_design
+
+

General/DFX/Embedded_IOB_inside_RM/images/design_runs_window.png

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+#
+# Copyright (C) 2024, Advanced Micro Devices, Inc. All rights reserved.
+# SPDX-License-Identifier: X11
+#
+
+set curdesign [current_bd_design]
+create_bd_design -boundary_from_container [get_bd_cells /rp1] rp1rm2
+current_bd_design $curdesign
+set_property -dict [list CONFIG.LIST_SYNTH_BD {rp1rm1.bd:rp1rm2.bd} CONFIG.LIST_SIM_BD {rp1rm1.bd:rp1rm2.bd}] [get_bd_cells /rp1]
+current_bd_design [get_bd_designs rp1rm2]
+update_compile_order -fileset sources_1
+regenerate_bd_layout
+#Creating IPs of RP1RM2
+create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 axi_gpio_0
+create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 smartconnect_0
+create_bd_cell -type ip -vlnv xilinx.com:ip:util_ds_buf:2.2 util_ds_buf_0
+set_property -dict [list CONFIG.C_BUF_TYPE {IOBUF}] [get_bd_cells util_ds_buf_0]
+set_property -dict [list CONFIG.C_GPIO_WIDTH {1} CONFIG.C_GPIO2_WIDTH {1} CONFIG.C_IS_DUAL {1} CONFIG.C_ALL_OUTPUTS {1} CONFIG.C_ALL_OUTPUTS_2 {1}] [get_bd_cells axi_gpio_0]
+#Connecting RM Ports to IPs
+connect_bd_intf_net [get_bd_intf_ports S_AXI] [get_bd_intf_pins smartconnect_0/S00_AXI]
+connect_bd_intf_net [get_bd_intf_ports S_AXI1] [get_bd_intf_pins smartconnect_0/S01_AXI]
+connect_bd_net [get_bd_ports s_axi_aclk] [get_bd_pins smartconnect_0/aclk]
+connect_bd_net [get_bd_ports s_axi_aclk] [get_bd_pins axi_gpio_0/s_axi_aclk]
+connect_bd_net [get_bd_ports s_axi_aresetn] [get_bd_pins smartconnect_0/aresetn]
+connect_bd_net [get_bd_ports s_axi_aresetn] [get_bd_pins axi_gpio_0/s_axi_aresetn]
+connect_bd_intf_net [get_bd_intf_pins smartconnect_0/M00_AXI] [get_bd_intf_pins axi_gpio_0/S_AXI]
+connect_bd_net [get_bd_ports IOBUF_IO_IO] [get_bd_pins util_ds_buf_0/IOBUF_IO_IO]
+connect_bd_net [get_bd_pins axi_gpio_0/gpio_io_o] [get_bd_pins util_ds_buf_0/IOBUF_IO_I]
+connect_bd_intf_net [get_bd_intf_ports GPIO_0] [get_bd_intf_pins axi_gpio_0/GPIO2]
+
+regenerate_bd_layout
+#Assign address
+
+assign_bd_address
+set_property offset 0x80010000 [get_bd_addr_segs {S_AXI/SEG_axi_gpio_0_Reg}]
+set_property offset 0x80030000 [get_bd_addr_segs {S_AXI1/SEG_axi_gpio_0_Reg}]
+validate_bd_design
+save_bd_design