@@ -62,10 +62,10 @@ typedef struct {
6262 tu_edpt_stream_t rx ;
6363
6464 uint8_t tx_ff_buf [CFG_TUH_CDC_TX_BUFSIZE ];
65- CFG_TUSB_MEM_ALIGN uint8_t tx_ep_buf [CFG_TUH_CDC_TX_EPSIZE ];
65+ CFG_TUH_MEM_ALIGN uint8_t tx_ep_buf [CFG_TUH_CDC_TX_EPSIZE ];
6666
6767 uint8_t rx_ff_buf [CFG_TUH_CDC_TX_BUFSIZE ];
68- CFG_TUSB_MEM_ALIGN uint8_t rx_ep_buf [CFG_TUH_CDC_TX_EPSIZE ];
68+ CFG_TUH_MEM_ALIGN uint8_t rx_ep_buf [CFG_TUH_CDC_TX_EPSIZE ];
6969 } stream ;
7070
7171} cdch_interface_t ;
@@ -74,7 +74,7 @@ typedef struct {
7474// INTERNAL OBJECT & FUNCTION DECLARATION
7575//--------------------------------------------------------------------+
7676
77- CFG_TUSB_MEM_SECTION
77+ CFG_TUH_MEM_SECTION
7878static cdch_interface_t cdch_data [CFG_TUH_CDC ];
7979
8080static inline cdch_interface_t * get_itf (uint8_t idx )
@@ -323,7 +323,8 @@ bool tuh_cdc_set_control_line_state(uint8_t idx, uint16_t line_state, tuh_xfer_c
323323 .user_data = user_data
324324 };
325325
326- return tuh_control_xfer (& xfer );
326+ TU_ASSERT (tuh_control_xfer (& xfer ));
327+ return true;
327328}
328329
329330bool tuh_cdc_set_line_coding (uint8_t idx , cdc_line_coding_t const * line_coding , tuh_xfer_cb_t complete_cb , uintptr_t user_data )
@@ -363,7 +364,8 @@ bool tuh_cdc_set_line_coding(uint8_t idx, cdc_line_coding_t const* line_coding,
363364 .user_data = user_data
364365 };
365366
366- return tuh_control_xfer (& xfer );
367+ TU_ASSERT (tuh_control_xfer (& xfer ));
368+ return true;
367369}
368370
369371//--------------------------------------------------------------------+
@@ -543,32 +545,36 @@ static void process_cdc_config(tuh_xfer_t* xfer)
543545 uintptr_t const state = xfer -> user_data ;
544546 uint8_t const itf_num = (uint8_t ) tu_le16toh (xfer -> setup -> wIndex );
545547 uint8_t const idx = tuh_cdc_itf_get_index (xfer -> daddr , itf_num );
546- TU_ASSERT (idx != TUSB_INDEX_INVALID_8 , );
548+ cdch_interface_t * p_cdc = get_itf (idx );
549+ TU_ASSERT (p_cdc , );
547550
548551 switch (state )
549552 {
550553 case CONFIG_SET_CONTROL_LINE_STATE :
551- #if CFG_TUH_CDC_LINE_CONTROL_ON_ENUM
552- TU_ASSERT ( tuh_cdc_set_control_line_state (idx , CFG_TUH_CDC_LINE_CONTROL_ON_ENUM , process_cdc_config , CONFIG_SET_LINE_CODING ), );
553- break ;
554- #endif
555- TU_ATTR_FALLTHROUGH ;
554+ #if CFG_TUH_CDC_LINE_CONTROL_ON_ENUM
555+ if (p_cdc -> acm_capability .support_line_request )
556+ {
557+ TU_ASSERT ( tuh_cdc_set_control_line_state (idx , CFG_TUH_CDC_LINE_CONTROL_ON_ENUM , process_cdc_config , CONFIG_SET_LINE_CODING ), );
558+ break ;
559+ }
560+ #endif
561+ TU_ATTR_FALLTHROUGH ;
556562
557563 case CONFIG_SET_LINE_CODING :
558- #ifdef CFG_TUH_CDC_LINE_CODING_ON_ENUM
559- {
560- cdc_line_coding_t line_coding = CFG_TUH_CDC_LINE_CODING_ON_ENUM ;
561- TU_ASSERT ( tuh_cdc_set_line_coding (idx , & line_coding , process_cdc_config , CONFIG_COMPLETE ), );
562- break ;
563- }
564- #endif
565- TU_ATTR_FALLTHROUGH ;
564+ #ifdef CFG_TUH_CDC_LINE_CODING_ON_ENUM
565+ if (p_cdc -> acm_capability .support_line_request )
566+ {
567+ cdc_line_coding_t line_coding = CFG_TUH_CDC_LINE_CODING_ON_ENUM ;
568+ TU_ASSERT ( tuh_cdc_set_line_coding (idx , & line_coding , process_cdc_config , CONFIG_COMPLETE ), );
569+ break ;
570+ }
571+ #endif
572+ TU_ATTR_FALLTHROUGH ;
566573
567574 case CONFIG_COMPLETE :
568575 if (tuh_cdc_mount_cb ) tuh_cdc_mount_cb (idx );
569576
570577 // Prepare for incoming data
571- cdch_interface_t * p_cdc = get_itf (idx );
572578 tu_edpt_stream_read_xfer (& p_cdc -> stream .rx );
573579
574580 // notify usbh that driver enumeration is complete
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