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MIPS has a branch delay slot which means that we can't just design something where we return the next processor state naively from a function with no other side effects. Branch delay means that the next instruction after a jump or branch will be executed regardless of whether the branch is taken or not taken.
The text was updated successfully, but these errors were encountered:
MIPS has a branch delay slot which means that we can't just design something where we return the next processor state naively from a function with no other side effects. Branch delay means that the next instruction after a jump or branch will be executed regardless of whether the branch is taken or not taken.
The text was updated successfully, but these errors were encountered: