More clang-tidy fixes (pytorch#92944)

Pull Request resolved: pytorch#92944
Approved by: https://github.com/Skylion007

Author: cyyever

aten/src/ATen/EmptyTensor.cpp

@@ -242,8 +242,7 @@ TensorBase empty_cpu(
     c10::optional<Device> device_opt,
     c10::optional<bool> pin_memory_opt,
     c10::optional<c10::MemoryFormat> memory_format_opt) {
-  auto device = device_or_default(device_opt);
-  TORCH_INTERNAL_ASSERT_DEBUG_ONLY(device.type() == DeviceType::CPU);
+  TORCH_INTERNAL_ASSERT_DEBUG_ONLY(device_or_default(device_opt).type() == DeviceType::CPU);
   TORCH_INTERNAL_ASSERT_DEBUG_ONLY(layout_or_default(layout_opt) == Layout::Strided);
 
   auto pin_memory = pinned_memory_or_default(pin_memory_opt);
@@ -277,8 +276,7 @@ TensorBase empty_strided_cpu(
     c10::optional<Layout> layout_opt,
     c10::optional<Device> device_opt,
     c10::optional<bool> pin_memory_opt) {
-  auto device = device_or_default(device_opt);
-  TORCH_INTERNAL_ASSERT_DEBUG_ONLY(device.type() == DeviceType::CPU);
+  TORCH_INTERNAL_ASSERT_DEBUG_ONLY(device_or_default(device_opt).type() == DeviceType::CPU);
   TORCH_INTERNAL_ASSERT_DEBUG_ONLY(layout_or_default(layout_opt) == Layout::Strided);
 
   auto pin_memory = pinned_memory_or_default(pin_memory_opt);
@@ -335,8 +333,7 @@ TensorBase empty_meta(
   c10::optional<bool> pin_memory_opt,
   c10::optional<c10::MemoryFormat> memory_format_opt
 ) {
-  auto device = device_or_default(device_opt);
-  TORCH_INTERNAL_ASSERT_DEBUG_ONLY(device.type() == DeviceType::Meta);
+  TORCH_INTERNAL_ASSERT_DEBUG_ONLY(device_or_default(device_opt).type() == DeviceType::Meta);
   // NB: because there is no SparseMeta (yet), non-strided layout is
   // exerciseable
   TORCH_CHECK_NOT_IMPLEMENTED(
@@ -388,8 +385,7 @@ TensorBase empty_strided_meta(
     c10::optional<Layout> layout_opt,
     c10::optional<Device> device_opt,
     c10::optional<bool> pin_memory_opt) {
-  auto device = device_or_default(device_opt);
-  TORCH_INTERNAL_ASSERT_DEBUG_ONLY(device.type() == DeviceType::Meta);
+  TORCH_INTERNAL_ASSERT_DEBUG_ONLY(device_or_default(device_opt).type() == DeviceType::Meta);
   TORCH_INTERNAL_ASSERT_DEBUG_ONLY(layout_or_default(layout_opt) == Layout::Strided);
 
   auto dtype = dtype_or_default(dtype_opt);
@@ -424,8 +420,7 @@ TensorBase empty_strided_symint_meta(
     c10::optional<Layout> layout_opt,
     c10::optional<Device> device_opt,
     c10::optional<bool> pin_memory_opt) {
-  auto device = device_or_default(device_opt);
-  TORCH_INTERNAL_ASSERT_DEBUG_ONLY(device.type() == DeviceType::Meta);
+  TORCH_INTERNAL_ASSERT_DEBUG_ONLY(device_or_default(device_opt).type() == DeviceType::Meta);
   TORCH_INTERNAL_ASSERT_DEBUG_ONLY(layout_or_default(layout_opt) == Layout::Strided);
 
   auto dtype = dtype_or_default(dtype_opt);

aten/src/ATen/FunctionalizeFallbackKernel.cpp

@@ -128,7 +128,7 @@ const at::Tensor & resize__functionalization(c10::DispatchKeySet dispatchKeySet,
   // Case 1: arguments are not functional tensors, so we no-op and redispatch.
   if (!at::functionalization::impl::isFunctionalTensor(self)) {
      at::AutoDispatchSkipFunctionalize guard;
-     at::Tensor tmp_output = self_.resize_(size, memory_format);
+     self_.resize_(size, memory_format);
      return self;
   }
 

aten/src/ATen/PythonTorchFunctionTLS.cpp

@@ -12,7 +12,7 @@ void PythonTorchFunctionTLS::push_onto_stack(std::shared_ptr<SafePyObject> mode)
 
 const std::shared_ptr<SafePyObject> PythonTorchFunctionTLS::pop_stack() {
   TORCH_CHECK(pythonTorchFunctionState.stack_.size() > 0, "trying to pop from empty mode stack");
-  const auto out = pythonTorchFunctionState.stack_.back();
+  auto out = pythonTorchFunctionState.stack_.back();
   pythonTorchFunctionState.stack_.pop_back();
   return out;
 }

aten/src/ATen/TensorIterator.cpp

@@ -69,8 +69,8 @@ static OptionalTensorRef make_otr(const TensorBase &tensor) {
 namespace internal {
 
 OpaqueOptionalTensorRef::OpaqueOptionalTensorRef() {
-  static_assert(alignof(OptionalTensorRef) == alignof(TensorBase), "");
-  static_assert(sizeof(OptionalTensorRef) == sizeof(TensorBase), "");
+  static_assert(alignof(OptionalTensorRef) == alignof(TensorBase));
+  static_assert(sizeof(OptionalTensorRef) == sizeof(TensorBase));
   new (data_.data()) OptionalTensorRef();
 }
 

aten/src/ATen/core/VariableFallbackKernel.cpp

@@ -19,12 +19,7 @@
 // TODO This whole file should be deleted and replaced with the mechanism
 //      described in https://github.com/pytorch/pytorch/issues/29548
 
-using c10::OperatorHandle;
 using c10::Stack;
-using c10::DispatchKey;
-using c10::DispatchKeySet;
-using c10::Dispatcher;
-using c10::KernelFunction;
 
 namespace {
 

aten/src/ATen/functorch/DynamicLayer.cpp

@@ -253,10 +253,10 @@ int64_t initAndPushDynamicLayer(
   const auto& dynamicLayerStack = dynamicLayerStackAccessor();
   const auto layerId = 1 + dynamicLayerStack.size();
   DynamicLayer new_layer(transform_type, layerId, batch_size, randomness, prev_grad_mode, prev_fwd_grad_mode, functionalize_add_back_views);
-  pushDynamicLayer(std::move(new_layer));
-
   // NB: this function should be called while holding the GIL to avoid races
   new_layer.interpreter().set_is_alive(true);
+  pushDynamicLayer(std::move(new_layer));
+
 
   if (transform_type == TransformType::Grad) {
     TORCH_INTERNAL_ASSERT(prev_grad_mode.has_value());

aten/src/ATen/native/Convolution.cpp

@@ -1164,9 +1164,6 @@ at::Tensor convolution_overrideable(
     const Tensor& input, const Tensor& weight, const c10::optional<Tensor>& bias_opt,
     IntArrayRef stride, IntArrayRef padding, IntArrayRef dilation,
     bool transposed, IntArrayRef output_padding, int64_t groups) {
-  // See [Note: hacky wrapper removal for optional tensor]
-  c10::MaybeOwned<Tensor> bias_maybe_owned = at::borrow_from_optional_tensor(bias_opt);
-
   TORCH_CHECK_NOT_IMPLEMENTED(false, "convolution_overrideable not implemented. You are likely triggering this with tensor backend other than CPU/CUDA/MKLDNN, if this is intended, please use TORCH_LIBRARY_IMPL to override this function ");
 }
 

aten/src/ATen/native/TensorConversions.cpp

@@ -1097,7 +1097,7 @@ Tensor sparse_compressed_to_flipped(
   // performance.
   const auto batch_nnz_offset = [&]() -> Tensor {
     const auto wrapped_nnz = at::tensor({nnz}, compressed_indices.options());
-    const auto offset = wrapped_nnz
+    auto offset = wrapped_nnz
       .expand({batch_numel_nonzero})
       .cumsum(-1).sub_(wrapped_nnz)
       .reshape(batch_sizes_nonempty);
@@ -1152,7 +1152,7 @@ Tensor sparse_compressed_to_flipped(
   // To CSC/BSC inputs these indices will appear "transposed".
   const auto is_transposed_indices = layout == at::kSparseCsc || layout == at::kSparseBsc;
   const auto coo_indices_2d_transposed = [&]() -> Tensor {
-    const auto coo_indices_2d = _convert_indices_from_csr_to_coo(
+    auto coo_indices_2d = _convert_indices_from_csr_to_coo(
         compressed_indices_2d,
         plain_indices_2d,
         is_out_int32,
@@ -1415,7 +1415,7 @@ void _csr_to_block_csr_cpu_kernel(
   // value lives within them. Otherwise they're not.
 
   // Allocate pointers for all possible column blocks plus 1
-  std::vector<T*> blocks(n_col / C + 1, (T*)0);
+  std::vector<T*> blocks(n_col / C + 1, nullptr);
 
   assert(n_row % R == 0);
   assert(n_col % C == 0);

aten/src/ATen/native/mkl/SparseCsrLinearAlgebra.cpp

@@ -53,7 +53,7 @@ static constexpr ScalarType TORCH_INT_TYPE = at::kInt;
 
 class SparseCsrMKLInterface {
  private:
-  sparse_matrix_t A = 0;
+  sparse_matrix_t A{nullptr};
   matrix_descr desc;
 
  public:

aten/src/ATen/native/quantized/cpu/ReduceOps.cpp

@@ -200,7 +200,7 @@ inline bool is_std_inner_dim_fast_path(
   auto all_dims = std::vector<int64_t>(self.dim());
   std::iota(all_dims.begin(), all_dims.end(), 0);
   dims = dims.empty() ? all_dims : dims;
-  bool is_unbiased = unbiased.has_value() ? unbiased.value() : 0;
+  bool is_unbiased = unbiased.has_value() ? unbiased.value() : false;
   int64_t num_ele = 1;
   for (auto d : dims) {
     num_ele *= self.size(d);

aten/src/ATen/native/quantized/cpu/UpSampleNearest3d.cpp

@@ -215,9 +215,6 @@ Tensor _upsample_nearest3d_quantized_cpu(
   }
 }
 
-using at::native::upsample::compute_output_size;
-using at::native::upsample::get_scale_value;
-
 Tensor upsample_nearest3d_quantized_cpu(
     const Tensor& input,
     IntArrayRef osize,

aten/src/ATen/native/quantized/cpu/qnnpack/src/q8dwconv/mp8x25-sse2-per-channel.c

@@ -418,7 +418,6 @@ void pytorch_q8dwconv_ukernel_mp8x25_per_channel__sse2(
         _mm_storeu_si128((__m128i*)outacc, vacc_lo);
         outacc += 4;
         _mm_storeu_si128((__m128i*)outacc, vacc_hi);
-        outacc += 4;
       }
     }
     {
@@ -806,7 +805,6 @@ void pytorch_q8dwconv_ukernel_mp8x25_per_channel__sse2(
         _mm_storeu_si128((__m128i*)outacc, vacc_lo);
         outacc += 4;
         _mm_storeu_si128((__m128i*)outacc, vacc_hi);
-        outacc += 4;
       }
     }
     {
@@ -1043,7 +1041,6 @@ void pytorch_q8dwconv_ukernel_mp8x25_per_channel__sse2(
         vacc_lo = _mm_add_epi32(vacc_lo, _mm_loadu_si128((__m128i*)outacc));
         vacc_hi =
             _mm_add_epi32(vacc_hi, _mm_loadu_si128((__m128i*)(outacc + 4)));
-        outacc += 8;
 
         const __m128 vmultiplier_lo =
             _mm_loadu_ps(&quantization_params->sse2.requantization_scales[channels - c]);