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Merge branch 'amaranth-lang:main' into main
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.env.toolchain

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AMARANTH_USE_YOSYS=builtin
2+
YOSYS=yowasp-yosys
3+
NEXTPNR_ICE40=yowasp-nextpnr-ice40
4+
ICEPACK=yowasp-icepack
5+
NEXTPNR_ECP5=yowasp-nextpnr-ecp5
6+
ECPPACK=yowasp-ecppack

.git_archival.txt

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node: $Format:%H$
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node-date: $Format:%cI$
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describe-name: $Format:%(describe:tags=true,match=*[0-9]*)$
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ref-names: $Format:%D$

.gitattributes

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.git_archival.txt export-subst

.github/workflows/main.yml

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@@ -1,16 +1,60 @@
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on: [push, pull_request]
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on:
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push:
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pull_request:
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schedule:
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- cron: '0 0 * * *' # test daily against git HEAD of dependencies
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27
name: CI
38
jobs:
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410
test:
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runs-on: ubuntu-latest
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strategy:
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matrix:
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python-version:
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- '3.8'
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- '3.9'
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- '3.10'
18+
- '3.11'
19+
- 'pypy-3.8'
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- 'pypy-3.9'
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# this version range needs to be synchronized with the one in pyproject.toml
22+
amaranth-version:
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- '0.4'
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- 'git'
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allow-failure:
26+
- true
27+
- false
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exclude: # all of these are inverted (this is unfortunately the best way to do this)
29+
- amaranth-version: '0.4'
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allow-failure: false
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- amaranth-version: 'git'
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allow-failure: true
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continue-on-error: '${{ matrix.allow-failure }}'
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name: "test (${{ matrix.python-version }}, ${{ matrix.amaranth-version }}${{ matrix.allow-failure == 'false' && ', required' || '' }})"
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steps:
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- name: Check out source code
8-
uses: actions/checkout@v2
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uses: actions/checkout@v3
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- name: Set up Python
10-
uses: actions/setup-python@v2
11-
- name: Install dependencies
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uses: actions/setup-python@v4
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with:
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python-version: ${{ matrix.python-version }}
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- name: Install Amaranth release
43+
if: ${{ matrix.amaranth-version != 'git' }}
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run: |
13-
pip install wheel
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- name: Test
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pip install 'amaranth[builtin-yosys] ==${{ matrix.amaranth-version }}'
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- name: Install Amaranth from git
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if: ${{ matrix.amaranth-version == 'git' }}
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run: |
16-
python setup.py test
49+
pip install 'amaranth[builtin-yosys] @ git+https://github.com/amaranth-lang/amaranth.git'
50+
- name: Run tests
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run: |
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python -m unittest discover -t . -s amaranth_boards -p '*.py'
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54+
required: # group all required workflows into one to avoid reconfiguring this in Actions settings
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needs:
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- test
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if: ${{ always() && !contains(needs.*.result, 'cancelled') }}
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runs-on: ubuntu-latest
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steps:
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- run: ${{ contains(needs.*.result, 'failure') && 'false' || 'true' }}

.gitignore

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# Python
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*.pyc
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/*.egg-info
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/.eggs
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__pycache__/
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*.egg-info
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/dist
65

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# pdm
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/.pdm-plugins
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/.pdm-python
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/.venv
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/pdm.lock
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# misc user-created
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/build

LICENSE.txt

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1-
Copyright (C) 2019-2021 Amaranth HDL contributors
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Copyright (C) 2019-2023 Amaranth HDL contributors
22

33
Redistribution and use in source and binary forms, with or without modification,
44
are permitted provided that the following conditions are met:

amaranth_boards/__init__.py

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@@ -1,9 +1,7 @@
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try:
2-
try:
3-
from importlib import metadata as importlib_metadata # py3.8+ stdlib
4-
except ImportError:
5-
import importlib_metadata # py3.7- shim
2+
from importlib import metadata as importlib_metadata
63
__version__ = importlib_metadata.version(__package__)
4+
del importlib_metadata
75
except ImportError:
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# No importlib_metadata. This shouldn't normally happen, but some people prefer not installing
97
# packages via pip at all, instead using PYTHONPATH directly or copying the package files into

amaranth_boards/alchitry_au.py

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import shutil
44

55
from amaranth.build import *
6-
from amaranth.vendor.xilinx_7series import *
6+
from amaranth.vendor import XilinxPlatform
77
from .resources import *
88

99

@@ -20,7 +20,7 @@ def find_loader():
2020
return (loader_prgm, bridge_bin)
2121

2222

23-
class AlchitryAuPlatform(Xilinx7SeriesPlatform):
23+
class AlchitryAuPlatform(XilinxPlatform):
2424
device = "XC7A35T" # Artix 7 33K LEs
2525
package = "FTG256"
2626
speed = "1"

amaranth_boards/arrow_deca.py

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import subprocess
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44
from amaranth.build import *
5-
from amaranth.vendor.intel import *
5+
from amaranth.vendor import IntelPlatform
66
from .resources import *
77

88

amaranth_boards/arty_a7.py

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@@ -1,15 +1,16 @@
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import os
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import subprocess
3+
import unittest
34

45
from amaranth.build import *
5-
from amaranth.vendor.xilinx_7series import *
6+
from amaranth.vendor import XilinxPlatform
67
from .resources import *
78

89

910
__all__ = ["ArtyA7_35Platform", "ArtyA7_100Platform"]
1011

1112

12-
class _ArtyA7Platform(Xilinx7SeriesPlatform):
13+
class _ArtyA7Platform(XilinxPlatform):
1314
package = "csg324"
1415
speed = "1L"
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default_clk = "clk100"
@@ -225,6 +226,12 @@ class ArtyA7_100Platform(_ArtyA7Platform):
225226
device = "xc7a100ti"
226227

227228

229+
class TestCase(unittest.TestCase):
230+
def test_smoke(self):
231+
from .test.blinky import Blinky
232+
ArtyA7_35Platform().build(Blinky(), do_build=False)
233+
234+
228235
if __name__ == "__main__":
229236
from .test.blinky import *
230237
ArtyA7_35Platform().build(Blinky(), do_program=True)

amaranth_boards/arty_s7.py

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import subprocess
44

55
from amaranth.build import *
6-
from amaranth.vendor.xilinx_7series import *
6+
from amaranth.vendor import XilinxPlatform
77
from .resources import *
88

99

1010
__all__ = ["ArtyS7_25Platform", "ArtyS7_50Platform"]
1111

1212

13-
class _ArtyS7Platform(Xilinx7SeriesPlatform):
13+
class _ArtyS7Platform(XilinxPlatform):
1414
package = "csga324"
1515
speed = "1"
1616
default_clk = "clk100"

amaranth_boards/arty_z7.py

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@@ -2,14 +2,14 @@
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import subprocess
33

44
from amaranth.build import *
5-
from amaranth.vendor.xilinx_7series import *
5+
from amaranth.vendor import XilinxPlatform
66
from .resources import *
77

88

99
__all__ = ["ArtyZ720Platform"]
1010

1111

12-
class ArtyZ720Platform(Xilinx7SeriesPlatform):
12+
class ArtyZ720Platform(XilinxPlatform):
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device = "xc7z020"
1414
package = "clg400"
1515
speed = "1"

amaranth_boards/atlys.py

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import textwrap
33

44
from amaranth.build import *
5-
from amaranth.vendor.xilinx_spartan_3_6 import *
5+
from amaranth.vendor import XilinxPlatform
66
from .resources import *
77

88

99
__all__ = ["AtlysPlatform"]
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1111

12-
class AtlysPlatform(XilinxSpartan6Platform):
12+
class AtlysPlatform(XilinxPlatform):
1313
"""Platform file for Digilent Atlys Spartan 6 board.
1414
https://reference.digilentinc.com/reference/programmable-logic/atlys/start"""
1515

amaranth_boards/blackice.py

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import subprocess
33

44
from amaranth.build import *
5-
from amaranth.vendor.lattice_ice40 import *
5+
from amaranth.vendor import LatticeICE40Platform
66
from .resources import *
77

88

amaranth_boards/blackice_ii.py

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import subprocess
33

44
from amaranth.build import *
5-
from amaranth.vendor.lattice_ice40 import *
5+
from amaranth.vendor import LatticeICE40Platform
66
from .resources import *
77

88

@@ -35,7 +35,7 @@ class BlackIceIIPlatform(LatticeICE40Platform):
3535
),
3636

3737
SRAMResource(0,
38-
cs_n="136", oe_n="29", we_n="120",
38+
cs_n="23", oe_n="29", we_n="120",
3939
a="137 138 139 141 142 42 43 44 73 74 75 76 115 116 117 118 119 78",
4040
d="136 135 134 130 125 124 122 121 62 61 60 56 55 48 47 45",
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dm_n="24 28",

amaranth_boards/chameleon96.py

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@@ -3,7 +3,7 @@
33

44
from amaranth import *
55
from amaranth.build import *
6-
from amaranth.vendor.intel import *
6+
from amaranth.vendor import IntelPlatform
77
from .resources import *
88

99

amaranth_boards/cmod_a7.py

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import os
2+
import subprocess
3+
4+
from amaranth.build import *
5+
from amaranth.vendor import XilinxPlatform
6+
from .resources import *
7+
8+
"""
9+
Example Usage:
10+
platform = CModA7_35Platform(toolchain="Symbiflow")
11+
platform.build(Top(), do_program=True)
12+
13+
Supported programmer:
14+
openocd
15+
"""
16+
17+
__all__ = ["CmodA7_15Platform", "CmodA7_35Platform"]
18+
19+
20+
class _CmodA7Platform(XilinxPlatform):
21+
package = "cpg236"
22+
speed = "1"
23+
default_clk = "clk12"
24+
resources = [
25+
Resource("clk12", 0, Pins("L17", dir="i"),
26+
Clock(12e6), Attrs(IOSTANDARD="LVCMOS33")),
27+
28+
*LEDResources(pins="A17 C16", attrs=Attrs(IOSTANDARD="LVCMOS33")),
29+
30+
RGBLEDResource(0, r="C17", g="B16", b="B17", invert=True,
31+
attrs=Attrs(IOSTANDARD="LVCMOS33")),
32+
33+
*ButtonResources(pins="A18 B18", attrs=Attrs(IOSTANDARD="LVCMOS33")),
34+
35+
UARTResource(0,
36+
rx="J17", tx="J18",
37+
attrs=Attrs(IOSTANDARD="LVCMOS33")
38+
),
39+
40+
*SPIFlashResources(0,
41+
cs_n="K19", clk="E19", copi="D19", cipo="D18", wp_n="G18",
42+
hold_n="F18",
43+
attrs=Attrs(IOSTANDARD="LVCMOS33")
44+
),
45+
46+
SRAMResource(0,
47+
cs_n="N19", oe_n="P19", we_n="R19",
48+
a="M18 M19 K17 N17 P17 P18 R18 W19 U19 V19 W18 T17 T18 U17 U18 V16 W16 W17 V15",
49+
d="W15 W13 W14 U15 U16 V13 V14 U14"),
50+
51+
# One-wire interface to crypto authentication device
52+
# May not be populated on the board
53+
Resource("atsha204a", 0, Pins("D17", dir="io"),
54+
Attrs(IOSTANDARD="LVCMOS33"))
55+
]
56+
connectors = [
57+
Connector("pmod", 0, "G17 G19 N18 L18 - - H17 H19 J19 K18 - -"), # JA
58+
59+
# Pin 24/25 are VCC and GND
60+
# Pin 15/16 are analog (XADC)
61+
Connector("gpio", 0,
62+
"""
63+
M3 L3 A16 K3 C15 H1 A15 B15 A14 J3 J1 K2
64+
L1 L2 - - M1 N3 P3 M2 N1 N2 P1 -
65+
- R3 T3 R2 T1 T2 U1 W2 V2 W3 V3 W5
66+
V4 U4 V5 W4 U5 U2 W6 U3 U7 W7 U8 V8
67+
"""),
68+
69+
Connector("xadc", 0, {
70+
"vaux4_n": "G2",
71+
"vaux4_p": "G3",
72+
"vaux12_n": "J2",
73+
"vaux12_p": "H2"
74+
})
75+
]
76+
77+
def toolchain_program(self, products, name):
78+
with products.extract("{}.bit".format(name)) as bitstream_filename:
79+
subprocess.check_call(["openFPGALoader",
80+
"-b", "cmoda7_35t",
81+
"{}".format(bitstream_filename)
82+
])
83+
84+
85+
class CmodA7_15Platform(_CmodA7Platform):
86+
device = "xc7a15t"
87+
88+
class CmodA7_35Platform(_CmodA7Platform):
89+
device = "xc7a35t"
90+
91+
if __name__ == "__main__":
92+
from .test.blinky import *
93+
CmodA7_35Platform().build(Blinky(), do_program=True)

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