projects/ad4630_fmc: Updated README files

Signed-off-by: Cristian Mihai Popa <[email protected]>

Author: cristianmihaipopa

projects/ad4630_fmc/README.md

@@ -0,0 +1,19 @@
+# AD4630-FMC HDL Project
+
+- Evaluation board product page: [EVAL-AD4630-FMC](https://www.analog.com/eval-ad4630-24)
+- System documentation: TO BE ADDED
+- HDL project documentation: https://analogdevicesinc.github.io/hdl/projects/ad4630_fmc/index.html
+
+## Supported parts
+
+| Part name                                                    | Description                                                  |
+|--------------------------------------------------------------|--------------------------------------------------------------|
+| [AD4030](https://www.analog.com/en/products/ad4030-24)       | 24-Bit, 2 MSPS, Single Channel SAR ADC                       |
+| [AD4630](https://www.analog.com/ad4630-24)                   | 24-Bit, 2 MSPS, Dual Channel, Precision Differential SAR ADC |
+| [AD4632](https://www.analog.com/AD4632-24)                   | 24-Bit, 500 kSPS, Dual Channel SAR ADC                       |
+| [ADAQ4216](https://www.analog.com/en/products/adaq4216.html) | 16-Bit, 2MSPS, μModule Data-Acquisition Solution             |
+| [ADAQ4224](https://www.analog.com/en/products/adaq4224.html) | 24-Bit, 2 MSPS, μModule Data Acquisition Solution            |
+
+## Building the project
+
+Please enter the folder for the FPGA carrier you want to use and read the README.md.

projects/ad4630_fmc/Readme.md

@@ -1,36 +1,113 @@
+# AD4630-FMC/ZED HDL Project
 
-# EVAL-AD463X_FMCZ HDL reference design
+## Building the project
 
-## Building the design
+The parameters configurable through the `make` command, can be found below, as
+well as in the **system_project.tcl** file.
 
-The design supports almost all the digital interface modes of AD463x, AD403x 
-and adaq42xx a new bit stream should be generated each time when the targeted 
+```
+cd projects/ad4630_fmc/zed
+make
+```
+
+This design supports almost all the digital interface modes of AD463x, AD403x
+and ADAQ42xx. A new bitstream should be generated each time when the targeted
 configuration changes.
 
-Default configuration: generic SPI mode for clocking, 2 lanes per channel, SDR 
-data capture and capture zone 2. 
+If other configurations are desired, then the parameters from the HDL project
+need to be changed, as well as the Linux project configurations:
+
+The overwritable parameters from the environment are:
+
+- CLK_MODE: clocking mode of the device's digital interface
+  - 0 - SPI (default)
+  - 1 - Echo-clock or Master clock 
+- NUM_OF_SDI: the number of MOSI lines of the SPI interface
+  - 1 - Interleaved
+  - 2 - 1LPC
+  - 4 - 2LPC (default)
+  - 8 - 4LPC
+- CAPTURE_ZONE: the capture zone of the next sample
+  - 1 - negative edge of BUSY
+  - 2 - next positive edge of CNV (default)
+- DDR_EN: in echo and master clock mode, the SDI lines can have Single or Double data rates
+  - 0 - MISO runs on SDR (default)
+  - 1 - MISO runs on DDR
+
+### Example configurations
+
+#### Clock mode SPI, MOSI lines 4, Capture zone 2, SDR (default)
+
+This specific command is equivalent to running `make` only:
+
+```
+make CLK_MODE=0 NUM_OF_SDI=4 CAPTURE_ZONE=2 DDR_EN=0
+``` 
+
+Corresponding device trees:
+- [zynq-zed-adv7511-ad4630-24.dts](https://github.com/analogdevicesinc/linux/blob/main/arch/arm/boot/dts/xilinx/zynq-zed-adv7511-ad4630-24.dts)
+- [zynq-zed-adv7511-adaq4216.dts](https://github.com/analogdevicesinc/linux/blob/main/arch/arm/boot/dts/xilinx/zynq-zed-adv7511-adaq4216.dts)
+- [zynq-zed-adv7511-adaq4220.dts](https://github.com/analogdevicesinc/linux/blob/main/arch/arm/boot/dts/xilinx/zynq-zed-adv7511-adaq4220.dts)
+- [zynq-zed-adv7511-adaq4224-24.dts](https://github.com/analogdevicesinc/linux/blob/main/arch/arm/boot/dts/xilinx/zynq-zed-adv7511-adaq4224-24.dts)
+
+#### Clock mode SPI, MOSI lines 2, Capture zone 2, SDR
+
+```
+make CLK_MODE=0 NUM_OF_SDI=2 CAPTURE_ZONE=2 DDR_EN=0
+```
+
+Corresponding device trees: 
+
+- [zynq-zed-adv7511-ad4030-24.dts](https://github.com/analogdevicesinc/linux/blob/main/arch/arm/boot/dts/xilinx/zynq-zed-adv7511-ad4030-24.dts)
+- [zynq-zed-adv7511-ad4032-24.dts](https://github.com/analogdevicesinc/linux/blob/main/arch/arm/boot/dts/xilinx/zynq-zed-adv7511-ad4032-24.dts)
+- [zynq-zed-adv7511-ad4630-16.dts](https://github.com/analogdevicesinc/linux/blob/main/arch/arm/boot/dts/xilinx/zynq-zed-adv7511-ad4630-16.dts)
+
+#### Clock mode 0, MOSI lines 4, Capture zone 2, SDR
+
+```
+make CLK_MODE=0 NUM_OF_SDI=4 CAPTURE_ZONE=2 DDR_EN=0
+```
+
+Corresponding device tree: [zynq-zed-adv7511-adaq4224-24_cm0_sdi4_cz2.dts](https://github.com/analogdevicesinc/linux/blob/main/arch/arm/boot/dts/xilinx/zynq-zed-adv7511-adaq4224-24_cm0_sdi4_cz2.dts)
+
+#### Clock mode 0, MOSI lines 8, Capture zone 2, SDR
+
+```
+make CLK_MODE=0 NUM_OF_SDI=8 CAPTURE_ZONE=2 DDR_EN=0
+```
+
+#### Clock mode 1, MOSI lines 2, Capture zone 2, SDR
+
+```
+make CLK_MODE=1 NUM_OF_SDI=2 CAPTURE_ZONE=2 DDR_EN=0
+```
+
+#### Clock mode 1, MOSI lines 4, Capture zone 2, SDR
+
+```
+make CLK_MODE=1 NUM_OF_SDI=4 CAPTURE_ZONE=2 DDR_EN=0
+```
+
+#### Clock mode 1, MOSI lines 8, Capture zone 2, SDR
+
+```
+make CLK_MODE=1 NUM_OF_SDI=8 CAPTURE_ZONE=2 DDR_EN=0
+```
 
-### Building attributes
+#### Clock mode 1, MOSI lines 2, Capture zone 2, DDR
 
-|  Attribute name |                Valid values                       |
-| --------------- | ------------------------------------------------- |
-|  CLK_MODE       |  0 - SPI / 1 - Echo-clock or Master clock         |
-|  NUM_OF_SDI     |  1 - Interleaved / 2 - 1LPC / 4 - 2LPC / 8 - 4LPC |
-|  CAPTURE_ZONE   |  1 - negedge of BUSY / 2 - next posedge of CNV    |
-|  DDR_EN         |  0 - MISO runs on SDR / 1 - MISO runs on DDR      |
+```
+make CLK_MODE=1 NUM_OF_SDI=2 CAPTURE_ZONE=2 DDR_EN=1
+```
 
-**Example:** 
-  make CLK_MODE=0 NUM_OF_SDI=2 CAPTURE_ZONE=2 DDR_EN=0
-  make CLK_MODE=0 NUM_OF_SDI=4 CAPTURE_ZONE=2 DDR_EN=0
-  make CLK_MODE=0 NUM_OF_SDI=8 CAPTURE_ZONE=2 DDR_EN=0
-  make CLK_MODE=1 NUM_OF_SDI=2 CAPTURE_ZONE=2 DDR_EN=0
-  make CLK_MODE=1 NUM_OF_SDI=4 CAPTURE_ZONE=2 DDR_EN=0
-  make CLK_MODE=1 NUM_OF_SDI=8 CAPTURE_ZONE=2 DDR_EN=0
-  make CLK_MODE=1 NUM_OF_SDI=2 CAPTURE_ZONE=2 DDR_EN=1
-  make CLK_MODE=1 NUM_OF_SDI=4 CAPTURE_ZONE=2 DDR_EN=1
-  make CLK_MODE=1 NUM_OF_SDI=8 CAPTURE_ZONE=2 DDR_EN=1
+#### Clock mode 1, MOSI lines 4, Capture zone 2, DDR
 
-## Documentation
+```
+make CLK_MODE=1 NUM_OF_SDI=4 CAPTURE_ZONE=2 DDR_EN=1
+```
 
-https://wiki.analog.com/resources/eval/user-guides/ad463x/hdl
+#### Clock mode 1, MOSI lines 8, Capture zone 2, DDR
 
+```
+make CLK_MODE=1 NUM_OF_SDI=8 CAPTURE_ZONE=2 DDR_EN=1
+```