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unify spi engine script
add intel-compatible ad_* commands to the carrier common _qsys.tcl Signed-off-by: Laez Barbosa <[email protected]>
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‎library/spi_engine/scripts/spi_engine_gen.tcl‎

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###############################################################################
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## Copyright (C) 2020-2025 Analog Devices, Inc. All rights reserved.
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### SPDX short identifier: ADIBSD
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###############################################################################
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## Unified SPI Engine generation script
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## This script provides a single implementation that works for both Xilinx and Intel
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## by using the vendor-agnostic ad_* procedures from adi_board.tcl or <intel_carrier>_system_qsys.tcl
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## Detect the current vendor environment
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proc ad_detect_vendor {} {
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# Check for Vivado (Xilinx)
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if {[info commands get_bd_cells] != ""} {
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return "xilinx"
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}
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# Check for Platform Designer/Qsys (Intel)
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if {[info commands add_instance] != ""} {
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return "intel"
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}
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# Default to xilinx for backward compatibility
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return "xilinx"
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}
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proc spi_engine_create {args} {
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# Detect vendor using the abstraction layer
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set vendor [ad_detect_vendor]
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# Parse arguments based on vendor expectations
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if {$vendor == "xilinx"} {
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# Xilinx: name + optional parameters
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set name [lindex $args 0]
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set data_width [expr {[llength $args] > 1 ? [lindex $args 1] : 32}]
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set async_spi_clk [expr {[llength $args] > 2 ? [lindex $args 2] : 1}]
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set num_cs [expr {[llength $args] > 3 ? [lindex $args 3] : 1}]
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set num_sdi [expr {[llength $args] > 4 ? [lindex $args 4] : 1}]
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set num_sdo [expr {[llength $args] > 5 ? [lindex $args 5] : 1}]
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set sdi_delay [expr {[llength $args] > 6 ? [lindex $args 6] : 0}]
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set echo_sclk [expr {[llength $args] > 7 ? [lindex $args 7] : 0}]
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set sdo_streaming [expr {[llength $args] > 8 ? [lindex $args 8] : 0}]
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set cmd_mem_addr_width [expr {[llength $args] > 9 ? [lindex $args 9] : 4}]
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set data_mem_addr_width [expr {[llength $args] > 10 ? [lindex $args 10] : 4}]
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set sdi_fifo_addr_width [expr {[llength $args] > 11 ? [lindex $args 11] : 5}]
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set sdo_fifo_addr_width [expr {[llength $args] > 12 ? [lindex $args 12] : 5}]
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set sync_fifo_addr_width [expr {[llength $args] > 13 ? [lindex $args 13] : 4}]
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set cmd_fifo_addr_width [expr {[llength $args] > 14 ? [lindex $args 14] : 4}]
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} elseif {$vendor == "intel"} {
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# Intel: name + clocks + optional parameters
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if {[llength $args] < 4} {
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error "ERROR: Intel implementation requires at least: name, axi_clk, axi_reset, spi_clk"
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}
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set name [lindex $args 0]
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set axi_clk [lindex $args 1]
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set axi_reset [lindex $args 2]
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set spi_clk [lindex $args 3]
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set data_width [expr {[llength $args] > 4 ? [lindex $args 4] : 32}]
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set async_spi_clk [expr {[llength $args] > 5 ? [lindex $args 5] : 1}]
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set num_cs [expr {[llength $args] > 6 ? [lindex $args 6] : 1}]
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set num_sdi [expr {[llength $args] > 7 ? [lindex $args 7] : 1}]
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set num_sdo [expr {[llength $args] > 8 ? [lindex $args 8] : 1}]
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set sdi_delay [expr {[llength $args] > 9 ? [lindex $args 9] : 0}]
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set echo_sclk [expr {[llength $args] > 10 ? [lindex $args 10] : 0}]
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set sdo_streaming [expr {[llength $args] > 11 ? [lindex $args 11] : 0}]
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set cmd_mem_addr_width [expr {[llength $args] > 12 ? [lindex $args 12] : 4}]
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set data_mem_addr_width [expr {[llength $args] > 13 ? [lindex $args 13] : 4}]
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set sdi_fifo_addr_width [expr {[llength $args] > 14 ? [lindex $args 14] : 5}]
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set sdo_fifo_addr_width [expr {[llength $args] > 15 ? [lindex $args 15] : 5}]
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set sync_fifo_addr_width [expr {[llength $args] > 16 ? [lindex $args 16] : 4}]
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set cmd_fifo_addr_width [expr {[llength $args] > 17 ? [lindex $args 17] : 4}]
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}
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# Debug output for Xilinx
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if {$vendor == "xilinx" && $echo_sclk == 1} {
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puts "echo_sclk: $echo_sclk"
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}
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# Component instance names
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set execution "${name}_execution"
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set axi_regmap "${name}_axi_regmap"
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set offload "${name}_offload"
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set interconnect "${name}_interconnect"
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# Create hierarchy for Xilinx only
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if {$vendor == "xilinx"} {
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create_bd_cell -type hier $name
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current_bd_instance /$name
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# Create pins for the hierarchy
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if {$async_spi_clk == 1} {
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create_bd_pin -dir I -type clk spi_clk
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}
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if {$echo_sclk == 1} {
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create_bd_pin -dir I -type clk echo_sclk
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}
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create_bd_pin -dir I -type clk clk
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create_bd_pin -dir I -type rst resetn
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create_bd_pin -dir I trigger
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create_bd_pin -dir O irq
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create_bd_intf_pin -mode Master -vlnv analog.com:interface:spi_engine_rtl:1.0 m_spi
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create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 m_axis_sample
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if {$sdo_streaming == 1} {
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create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 s_axis_sample
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}
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}
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# Create IP instances using vendor-agnostic functions
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ad_ip_instance spi_engine_execution $execution
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ad_ip_parameter $execution CONFIG.DATA_WIDTH $data_width
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ad_ip_parameter $execution CONFIG.NUM_OF_CS $num_cs
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ad_ip_parameter $execution CONFIG.NUM_OF_SDI $num_sdi
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ad_ip_parameter $execution CONFIG.SDO_DEFAULT 1
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ad_ip_parameter $execution CONFIG.SDI_DELAY $sdi_delay
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ad_ip_parameter $execution CONFIG.ECHO_SCLK $echo_sclk
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ad_ip_instance axi_spi_engine $axi_regmap
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ad_ip_parameter $axi_regmap CONFIG.MM_IF_TYPE 0
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ad_ip_parameter $axi_regmap CONFIG.DATA_WIDTH $data_width
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ad_ip_parameter $axi_regmap CONFIG.NUM_OFFLOAD 1
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ad_ip_parameter $axi_regmap CONFIG.NUM_OF_SDI $num_sdi
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ad_ip_parameter $axi_regmap CONFIG.ASYNC_SPI_CLK $async_spi_clk
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ad_ip_parameter $axi_regmap CONFIG.OFFLOAD0_CMD_MEM_ADDRESS_WIDTH $cmd_mem_addr_width
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ad_ip_parameter $axi_regmap CONFIG.OFFLOAD0_SDO_MEM_ADDRESS_WIDTH $data_mem_addr_width
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ad_ip_parameter $axi_regmap CONFIG.SDI_FIFO_ADDRESS_WIDTH $sdi_fifo_addr_width
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ad_ip_parameter $axi_regmap CONFIG.SDO_FIFO_ADDRESS_WIDTH $sdo_fifo_addr_width
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ad_ip_parameter $axi_regmap CONFIG.SYNC_FIFO_ADDRESS_WIDTH $sync_fifo_addr_width
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ad_ip_parameter $axi_regmap CONFIG.CMD_FIFO_ADDRESS_WIDTH $cmd_fifo_addr_width
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ad_ip_instance spi_engine_offload $offload
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ad_ip_parameter $offload CONFIG.DATA_WIDTH $data_width
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ad_ip_parameter $offload CONFIG.ASYNC_SPI_CLK 0
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ad_ip_parameter $offload CONFIG.NUM_OF_SDI $num_sdi
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ad_ip_parameter $offload CONFIG.CMD_MEM_ADDRESS_WIDTH $cmd_mem_addr_width
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ad_ip_parameter $offload CONFIG.SDO_MEM_ADDRESS_WIDTH $data_mem_addr_width
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ad_ip_parameter $offload CONFIG.SDO_STREAMING $sdo_streaming
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# Intel-specific: Set ASYNC_TRIG parameter if needed
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if {$vendor == "intel"} {
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ad_ip_parameter $offload CONFIG.ASYNC_TRIG 0
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}
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ad_ip_instance spi_engine_interconnect $interconnect
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ad_ip_parameter $interconnect CONFIG.DATA_WIDTH $data_width
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ad_ip_parameter $interconnect CONFIG.NUM_OF_SDI $num_sdi
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# Create connections based on vendor
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if {$vendor == "xilinx"} {
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# Xilinx connection style (hierarchical with internal pins)
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ad_connect $axi_regmap/spi_engine_offload_ctrl0 $offload/spi_engine_offload_ctrl
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ad_connect $offload/m_interconnect_ctrl $interconnect/s_interconnect_ctrl
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ad_connect $offload/spi_engine_ctrl $interconnect/s0_ctrl
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ad_connect $axi_regmap/spi_engine_ctrl $interconnect/s1_ctrl
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ad_connect $interconnect/m_ctrl $execution/ctrl
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ad_connect $offload/offload_sdi m_axis_sample
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ad_connect $offload/trigger trigger
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ad_connect $execution/spi m_spi
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if {$sdo_streaming == 1} {
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ad_connect $offload/s_axis_sdo s_axis_sample
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}
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# Clock connections
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ad_connect clk $axi_regmap/s_axi_aclk
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if {$async_spi_clk == 1} {
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ad_connect spi_clk $offload/spi_clk
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ad_connect spi_clk $offload/ctrl_clk
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ad_connect spi_clk $execution/clk
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ad_connect spi_clk $axi_regmap/spi_clk
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ad_connect spi_clk $interconnect/clk
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} else {
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ad_connect clk $offload/spi_clk
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ad_connect clk $offload/ctrl_clk
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ad_connect clk $execution/clk
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ad_connect clk $axi_regmap/spi_clk
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ad_connect clk $interconnect/clk
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}
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if {$echo_sclk == 1} {
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ad_connect echo_sclk $execution/echo_sclk
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}
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# Reset connections
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ad_connect $axi_regmap/spi_resetn $offload/spi_resetn
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ad_connect $axi_regmap/spi_resetn $execution/resetn
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ad_connect $axi_regmap/spi_resetn $interconnect/resetn
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ad_connect resetn $axi_regmap/s_axi_aresetn
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ad_connect irq $axi_regmap/irq
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# Exit hierarchy
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current_bd_instance /
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} elseif {$vendor == "intel"} {
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# Intel connection style (flat with different interface naming)
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# Clock connections
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ad_connect $axi_clk $axi_regmap.s_axi_clock
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ad_connect $spi_clk $axi_regmap.if_spi_clk
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ad_connect $spi_clk $execution.if_clk
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ad_connect $spi_clk $interconnect.if_clk
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ad_connect $spi_clk $offload.if_ctrl_clk
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ad_connect $spi_clk $offload.if_spi_clk
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# Reset connections
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ad_connect $axi_reset $axi_regmap.s_axi_reset
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ad_connect $axi_regmap.if_spi_resetn $execution.if_resetn
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ad_connect $axi_regmap.if_spi_resetn $interconnect.if_resetn
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ad_connect $axi_regmap.if_spi_resetn $offload.if_spi_resetn
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# Data path connections
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ad_connect $interconnect.m_cmd $execution.cmd
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ad_connect $execution.sdi_data $interconnect.m_sdi
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ad_connect $interconnect.m_sdo $execution.sdo_data
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ad_connect $execution.sync $interconnect.m_sync
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ad_connect $axi_regmap.cmd $interconnect.s1_cmd
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ad_connect $interconnect.s1_sdi $axi_regmap.sdi_data
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ad_connect $axi_regmap.sdo_data $interconnect.s1_sdo
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ad_connect $interconnect.s1_sync $axi_regmap.sync
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ad_connect $offload.cmd $interconnect.s0_cmd
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ad_connect $interconnect.s0_sdi $offload.sdi_data
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ad_connect $offload.sdo_data $interconnect.s0_sdo
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ad_connect $interconnect.s0_sync $offload.sync
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ad_connect $offload.m_interconnect_ctrl $interconnect.s_interconnect_ctrl
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ad_connect $offload.ctrl_cmd_wr $axi_regmap.offload0_cmd
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ad_connect $offload.ctrl_sdo_wr $axi_regmap.offload0_sdo
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ad_connect $offload.if_ctrl_enable $axi_regmap.if_offload0_enable
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ad_connect $offload.if_ctrl_enabled $axi_regmap.if_offload0_enabled
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ad_connect $offload.if_ctrl_mem_reset $axi_regmap.if_offload0_mem_reset
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ad_connect $offload.status_sync $axi_regmap.offload_sync
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}
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}

‎projects/ad4052_ardz/common/ad4052_bd.tcl‎

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@@ -7,7 +7,7 @@ create_bd_port -dir O adc_cnv
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create_bd_port -dir I adc_gp1_n
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create_bd_intf_port -mode Master -vlnv analog.com:interface:spi_engine_rtl:1.0 adc_spi
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source $ad_hdl_dir/library/spi_engine/scripts/spi_engine_xilinx.tcl
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source $ad_hdl_dir/library/spi_engine/scripts/spi_engine_gen.tcl
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set data_width 32
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set async_spi_clk 1

‎projects/ad4052_ardz/common/ad4052_qsys.tcl‎

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@@ -58,7 +58,7 @@ set_connection_parameter_value spi_clk_pll.reconfig_to_pll/spi_clk_pll_reconfig.
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set_connection_parameter_value spi_clk_pll.reconfig_to_pll/spi_clk_pll_reconfig.reconfig_to_pll width {0}
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# spi engine
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source $ad_hdl_dir/library/spi_engine/scripts/spi_engine_intel.tcl
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source $ad_hdl_dir/library/spi_engine/scripts/spi_engine_gen.tcl
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set spi_engine_hier spi_ad4052
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‎projects/common/a10gx/a10gx_system_qsys.tcl‎

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### SPDX short identifier: ADIBSD
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###############################################################################
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# Intel specific helper proc/ compatibility with xilinx procs on adi_board.tcl
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source $ad_hdl_dir/projects/scripts/adi_board_intel.tcl
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# a10gx carrier qsys
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set system_type nios
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‎projects/common/a10soc/a10soc_system_qsys.tcl‎

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### SPDX short identifier: ADIBSD
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###############################################################################
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# Intel specific helper proc/ compatibility with xilinx procs on adi_board.tcl
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source $ad_hdl_dir/projects/scripts/adi_board_intel.tcl
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# a10soc carrier qsys
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set system_type a10soc
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‎projects/common/c5soc/c5soc_system_qsys.tcl‎

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### SPDX short identifier: ADIBSD
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###############################################################################
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# Intel specific helper proc/ compatibility with xilinx procs on adi_board.tcl
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source $ad_hdl_dir/projects/scripts/adi_board_intel.tcl
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# c5soc carrier qsys
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set system_type c5soc
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‎projects/common/de10nano/de10nano_system_qsys.tcl‎

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### SPDX short identifier: ADIBSD
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###############################################################################
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# Intel specific helper proc/ compatibility with xilinx procs on adi_board.tcl
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source $ad_hdl_dir/projects/scripts/adi_board_intel.tcl
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# de10nano carrier qsys
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# system clock
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‎projects/common/fm87/fm87_system_qsys.tcl‎

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### SPDX short identifier: ADIBSD
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###############################################################################
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# Intel specific helper proc/ compatibility with xilinx procs on adi_board.tcl
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source $ad_hdl_dir/projects/scripts/adi_board_intel.tcl
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# fm87 carrier qsys
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set system_type "Agilex 7"

‎projects/common/s10soc/s10soc_system_qsys.tcl‎

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### SPDX short identifier: ADIBSD
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###############################################################################
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# Intel specific helper proc/ compatibility with xilinx procs on adi_board.tcl
7+
source $ad_hdl_dir/projects/scripts/adi_board_intel.tcl
8+
69
# stratix10soc carrier qsys
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811
set system_type s10soc

‎projects/scripts/adi_board_intel.tcl‎

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###############################################################################
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## Copyright (C) 2025 Analog Devices, Inc. All rights reserved.
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### SPDX short identifier: ADIBSD
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###############################################################################
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proc ad_ip_instance {i_ip i_name {i_params {}}} {
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add_instance ${i_name} ${i_ip}
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# Set parameters if provided
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if {$i_params != {}} {
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foreach {k v} $i_params {
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set_instance_parameter_value ${i_name} $k $v
12+
}
13+
}
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}
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proc ad_ip_parameter {i_name i_param i_value} {
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# Remove CONFIG. prefix if present for Intel
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regsub {^CONFIG\.} $i_param {} param_name
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set_instance_parameter_value ${i_name} ${param_name} ${i_value}
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}
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proc ad_connect {name_a name_b} {
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add_connection $name_a $name_b
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}

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