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Update utility cores to inline hdl variants
With Vivado 2024.2, Xilinx introduced new utility IPs variants called "inline_hdl" that are now recommended and should lead to faster build times. The old variants are supposedly being removed in the 2026 Vivado release. Signed-off-by: Bogdan Luncan <[email protected]>
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‎library/axi_tdd/scripts/axi_tdd.tcl‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
###############################################################################
2-
## Copyright (C) 2022-2023 Analog Devices, Inc. All rights reserved.
2+
## Copyright (C) 2022-2023, 2025 Analog Devices, Inc. All rights reserved.
33
### SPDX short identifier: ADIBSD
44
###############################################################################
55

@@ -42,7 +42,7 @@ proc ad_tdd_gen_create {ip_name
4242
]
4343

4444
for {set i 0} {$i < $num_of_channels} {incr i} {
45-
ad_ip_instance xlslice "${ip_name}/tdd_ch_slice_${i}" [list \
45+
ad_ip_instance ilslice "${ip_name}/tdd_ch_slice_${i}" [list \
4646
DIN_WIDTH $num_of_channels \
4747
DIN_FROM $i \
4848
DIN_TO $i \

‎library/jesd204/scripts/jesd204.tcl‎

Lines changed: 8 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
###############################################################################
2-
## Copyright (C) 2017-2022 Analog Devices, Inc. All rights reserved.
2+
## Copyright (C) 2017-2022, 2025 Analog Devices, Inc. All rights reserved.
33
### SPDX short identifier: ADIJESD204
44
###############################################################################
55

@@ -226,24 +226,24 @@ proc adi_tpl_jesd204_tx_create {ip_name num_of_lanes num_of_converters samples_p
226226
# Concatenation and slicer cores
227227
# xconcat limited to 32 input ports
228228
for {set i 0} {$i < $num_of_converters} {incr i 32} {
229-
ad_ip_instance xlconcat "${ip_name}/data_concat[expr $i/32]" [list \
229+
ad_ip_instance ilconcat "${ip_name}/data_concat[expr $i/32]" [list \
230230
NUM_PORTS [expr min(32,$num_of_converters-$i)] \
231231
]
232232
}
233233
# main concat
234234
if {$num_of_converters > 32} {
235-
ad_ip_instance xlconcat "${ip_name}/data_concat" [list \
235+
ad_ip_instance ilconcat "${ip_name}/data_concat" [list \
236236
NUM_PORTS [expr int(ceil(double($num_of_converters)/32))] \
237237
]
238238
}
239239

240240
for {set i 0} {$i < $num_of_converters} {incr i} {
241-
ad_ip_instance xlslice "${ip_name}/enable_slice_${i}" [list \
241+
ad_ip_instance ilslice "${ip_name}/enable_slice_${i}" [list \
242242
DIN_WIDTH $num_of_converters \
243243
DIN_FROM $i \
244244
DIN_TO $i \
245245
]
246-
ad_ip_instance xlslice "${ip_name}/valid_slice_${i}" [list \
246+
ad_ip_instance ilslice "${ip_name}/valid_slice_${i}" [list \
247247
DIN_WIDTH $num_of_converters \
248248
DIN_FROM $i \
249249
DIN_TO $i \
@@ -357,18 +357,18 @@ proc adi_tpl_jesd204_rx_create {ip_name num_of_lanes num_of_converters samples_p
357357
if {$num_of_converters > 1} {
358358
# Slicer cores
359359
for {set i 0} {$i < $num_of_converters} {incr i} {
360-
ad_ip_instance xlslice ${ip_name}/data_slice_$i [list \
360+
ad_ip_instance ilslice ${ip_name}/data_slice_$i [list \
361361
DIN_WIDTH [expr $dma_sample_width*$samples_per_channel*$num_of_converters] \
362362
DIN_FROM [expr $dma_sample_width*$samples_per_channel*($i+1)-1] \
363363
DIN_TO [expr $dma_sample_width*$samples_per_channel*$i] \
364364
]
365365

366-
ad_ip_instance xlslice "${ip_name}/enable_slice_${i}" [list \
366+
ad_ip_instance ilslice "${ip_name}/enable_slice_${i}" [list \
367367
DIN_WIDTH $num_of_converters \
368368
DIN_FROM $i \
369369
DIN_TO $i \
370370
]
371-
ad_ip_instance xlslice "${ip_name}/valid_slice_${i}" [list \
371+
ad_ip_instance ilslice "${ip_name}/valid_slice_${i}" [list \
372372
DIN_WIDTH $num_of_converters \
373373
DIN_FROM $i \
374374
DIN_TO $i \
@@ -449,5 +449,3 @@ proc adi_jesd204_calc_tpl_width {link_datapath_width jesd_l jesd_m jesd_s jesd_n
449449
}
450450

451451
}
452-
453-

‎projects/ad469x_evb/common/ad469x_bd.tcl‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
###############################################################################
2-
## Copyright (C) 2020-2024 Analog Devices, Inc. All rights reserved.
2+
## Copyright (C) 2020-2025 Analog Devices, Inc. All rights reserved.
33
### SPDX short identifier: ADIBSD
44
###############################################################################
55

@@ -84,11 +84,11 @@ ad_connect spi_clk $hier_spi_engine/spi_clk
8484
ad_connect $hier_spi_engine/m_spi ad469x_spi
8585
ad_connect axi_ad469x_dma/s_axis $hier_spi_engine/M_AXIS_SAMPLE
8686

87-
ad_ip_instance util_vector_logic cnv_gate
87+
ad_ip_instance ilvector_logic cnv_gate
8888
ad_ip_parameter cnv_gate CONFIG.C_SIZE 1
8989
ad_ip_parameter cnv_gate CONFIG.C_OPERATION {and}
9090

91-
ad_ip_instance util_vector_logic cnv_gate_gpio
91+
ad_ip_instance ilvector_logic cnv_gate_gpio
9292
ad_ip_parameter cnv_gate_gpio CONFIG.C_SIZE 1
9393
ad_ip_parameter cnv_gate_gpio CONFIG.C_OPERATION {or}
9494

‎projects/ad738x_fmc/common/ad738x_bd.tcl‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
###############################################################################
2-
## Copyright (C) 2019-2024 Analog Devices, Inc. All rights reserved.
2+
## Copyright (C) 2019-2025 Analog Devices, Inc. All rights reserved.
33
### SPDX short identifier: ADIBSD
44
###############################################################################
55

@@ -51,7 +51,7 @@ ad_ip_parameter spi_clkgen CONFIG.VCO_MUL 8
5151
ad_connect $sys_cpu_clk spi_clkgen/clk
5252
ad_connect spi_clk spi_clkgen/clk_0
5353

54-
ad_ip_instance util_vector_logic cnv_gate
54+
ad_ip_instance ilvector_logic cnv_gate
5555
ad_ip_parameter cnv_gate CONFIG.C_SIZE 1
5656
ad_ip_parameter cnv_gate CONFIG.C_OPERATION {and}
5757

‎projects/ad9081_fmca_ebz/common/ad9081_fmca_ebz_bd.tcl‎

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -614,7 +614,7 @@ if {$INTF_CFG != "TX"} {
614614
ad_connect ext_sync_in rx_mxfe_tpl_core/adc_tpl_core/adc_sync_in
615615
if {$INTF_CFG == "RXTX"} {
616616
# Rx & Tx
617-
ad_ip_instance util_vector_logic manual_sync_or [list \
617+
ad_ip_instance ilvector_logic manual_sync_or [list \
618618
C_SIZE 1 \
619619
C_OPERATION {or} \
620620
]
@@ -625,17 +625,17 @@ if {$INTF_CFG != "TX"} {
625625
ad_connect rx_mxfe_tpl_core/adc_tpl_core/adc_sync_manual_req_out rx_mxfe_tpl_core/adc_tpl_core/adc_sync_manual_req_in
626626
}
627627
# Reset pack cores
628-
ad_ip_instance util_reduced_logic cpack_rst_logic
628+
ad_ip_instance ilreduced_logic cpack_rst_logic
629629
ad_ip_parameter cpack_rst_logic config.c_operation {or}
630630
ad_ip_parameter cpack_rst_logic config.c_size {3}
631631

632-
ad_ip_instance util_vector_logic rx_do_rstout_logic
632+
ad_ip_instance ilvector_logic rx_do_rstout_logic
633633
ad_ip_parameter rx_do_rstout_logic config.c_operation {not}
634634
ad_ip_parameter rx_do_rstout_logic config.c_size {1}
635635

636636
ad_connect $adc_data_offload_name/s_axis_tready rx_do_rstout_logic/Op1
637637

638-
ad_ip_instance xlconcat cpack_reset_sources
638+
ad_ip_instance ilconcat cpack_reset_sources
639639
ad_ip_parameter cpack_reset_sources config.num_ports {3}
640640
ad_connect rx_device_clk_rstgen/peripheral_reset cpack_reset_sources/in0
641641
ad_connect rx_mxfe_tpl_core/adc_tpl_core/adc_rst cpack_reset_sources/in1
@@ -657,11 +657,11 @@ if {$INTF_CFG != "RX"} {
657657
ad_connect tx_mxfe_tpl_core/dac_tpl_core/dac_sync_manual_req_out tx_mxfe_tpl_core/dac_tpl_core/dac_sync_manual_req_in
658658
}
659659
# Reset upack cores
660-
ad_ip_instance util_reduced_logic upack_rst_logic
660+
ad_ip_instance ilreduced_logic upack_rst_logic
661661
ad_ip_parameter upack_rst_logic config.c_operation {or}
662662
ad_ip_parameter upack_rst_logic config.c_size {2}
663663

664-
ad_ip_instance xlconcat upack_reset_sources
664+
ad_ip_instance ilconcat upack_reset_sources
665665
ad_ip_parameter upack_reset_sources config.num_ports {2}
666666
ad_connect tx_device_clk_rstgen/peripheral_reset upack_reset_sources/in0
667667
ad_connect tx_mxfe_tpl_core/dac_tpl_core/dac_rst upack_reset_sources/in1

‎projects/ad9081_fmca_ebz/common/versal_transceiver.tcl‎

Lines changed: 11 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
###############################################################################
2-
## Copyright (C) 2021-2024 Analog Devices, Inc. All rights reserved.
2+
## Copyright (C) 2021-2025 Analog Devices, Inc. All rights reserved.
33
### SPDX short identifier: ADIBSD
44
###############################################################################
55

@@ -57,11 +57,11 @@ proc create_reset_logic {
5757
set max_lanes [expr max($rx_num_lanes, $tx_num_lanes)]
5858
set num_quads [expr int(ceil(1.0 * $max_lanes / 4))]
5959

60-
ad_ip_instance xlconcat ${ip_name}/concat_powergood [list \
60+
ad_ip_instance ilconcat ${ip_name}/concat_powergood [list \
6161
NUM_PORTS $num_quads \
6262
]
6363

64-
ad_ip_instance util_reduced_logic ${ip_name}/and_powergood [list \
64+
ad_ip_instance ilreduced_logic ${ip_name}/and_powergood [list \
6565
C_SIZE $num_quads \
6666
]
6767

@@ -87,10 +87,10 @@ proc create_reset_logic {
8787
ad_connect ${ip_name}/${tx_bridge}/gt_ilo_reset ${ip_name}/gt_quad_base_${quad_index}/ch${ch_index}_iloreset
8888
}
8989
}
90-
ad_ip_instance xlconcat ${ip_name}/xlconcat_iloresetdone [list \
90+
ad_ip_instance ilconcat ${ip_name}/xlconcat_iloresetdone [list \
9191
NUM_PORTS ${rx_num_lanes} \
9292
]
93-
ad_ip_instance util_reduced_logic ${ip_name}/and_iloresetdone [list \
93+
ad_ip_instance ilreduced_logic ${ip_name}/and_iloresetdone [list \
9494
C_SIZE ${rx_num_lanes} \
9595
]
9696
for {set j 0} {$j < ${rx_num_lanes}} {incr j} {
@@ -101,10 +101,10 @@ proc create_reset_logic {
101101
ad_connect ${ip_name}/xlconcat_iloresetdone/dout ${ip_name}/and_iloresetdone/Op1
102102
ad_connect ${ip_name}/and_iloresetdone/Res ${ip_name}/${rx_bridge}/ilo_resetdone
103103
if {$asymmetric_mode} {
104-
ad_ip_instance xlconcat ${ip_name}/xlconcat_iloresetdone_tx [list \
104+
ad_ip_instance ilconcat ${ip_name}/xlconcat_iloresetdone_tx [list \
105105
NUM_PORTS ${tx_num_lanes} \
106106
]
107-
ad_ip_instance util_reduced_logic ${ip_name}/and_iloresetdone_tx [list \
107+
ad_ip_instance ilreduced_logic ${ip_name}/and_iloresetdone_tx [list \
108108
C_SIZE ${tx_num_lanes} \
109109
]
110110
for {set j 0} {$j < ${tx_num_lanes}} {incr j} {
@@ -122,10 +122,10 @@ proc create_reset_logic {
122122
}
123123

124124
set num_cplllocks [expr 2 * ${num_quads}]
125-
ad_ip_instance xlconcat ${ip_name}/concat_cplllock [list \
125+
ad_ip_instance ilconcat ${ip_name}/concat_cplllock [list \
126126
NUM_PORTS ${num_cplllocks} \
127127
]
128-
ad_ip_instance util_reduced_logic ${ip_name}/and_cplllock [list \
128+
ad_ip_instance ilreduced_logic ${ip_name}/and_cplllock [list \
129129
C_SIZE ${num_cplllocks} \
130130
]
131131

@@ -142,7 +142,7 @@ proc create_reset_logic {
142142
ad_connect ${ip_name}/and_cplllock/Res ${ip_name}/${tx_bridge}/gt_lcpll_lock
143143
}
144144

145-
ad_ip_instance xlconcat ${ip_name}/concat_phystatus [list \
145+
ad_ip_instance ilconcat ${ip_name}/concat_phystatus [list \
146146
NUM_PORTS ${rx_num_lanes} \
147147
]
148148
for {set j 0} {$j < ${rx_num_lanes}} {incr j} {
@@ -153,7 +153,7 @@ proc create_reset_logic {
153153
}
154154
ad_connect ${ip_name}/concat_phystatus/dout ${ip_name}/${rx_bridge}/ch_phystatus_in
155155
if {$asymmetric_mode} {
156-
ad_ip_instance xlconcat ${ip_name}/concat_phystatus_tx [list \
156+
ad_ip_instance ilconcat ${ip_name}/concat_phystatus_tx [list \
157157
NUM_PORTS ${rx_num_lanes} \
158158
]
159159
for {set j 0} {$j < ${rx_num_lanes}} {incr j} {

‎projects/ad9081_fmca_ebz/vcu118/system_bd.tcl‎

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -240,15 +240,15 @@ if {$ad_project_params(CORUNDUM) == "1"} {
240240
ad_connect corundum_hierarchy/input_axis_tdata util_corundum_cpack/packed_fifo_wr_data
241241
ad_connect corundum_hierarchy/input_axis_tready util_corundum_cpack/packed_fifo_wr_overflow
242242

243-
ad_ip_instance util_reduced_logic cpack_rst_logic_corundum
243+
ad_ip_instance ilreduced_logic cpack_rst_logic_corundum
244244
ad_ip_parameter cpack_rst_logic_corundum config.c_operation {or}
245245
ad_ip_parameter cpack_rst_logic_corundum config.c_size {4}
246246

247-
ad_ip_instance util_vector_logic rx_do_rstout_logic_corundum
247+
ad_ip_instance ilvector_logic rx_do_rstout_logic_corundum
248248
ad_ip_parameter rx_do_rstout_logic_corundum config.c_operation {not}
249249
ad_ip_parameter rx_do_rstout_logic_corundum config.c_size {1}
250250

251-
ad_ip_instance xlconcat cpack_reset_sources_corundum
251+
ad_ip_instance ilconcat cpack_reset_sources_corundum
252252
ad_ip_parameter cpack_reset_sources_corundum config.num_ports {4}
253253

254254
ad_connect corundum_hierarchy/input_axis_tready rx_do_rstout_logic_corundum/Op1
@@ -261,7 +261,7 @@ if {$ad_project_params(CORUNDUM) == "1"} {
261261
ad_connect cpack_reset_sources_corundum/dout cpack_rst_logic_corundum/op1
262262
ad_connect cpack_rst_logic_corundum/res util_corundum_cpack/reset
263263

264-
ad_ip_instance xlconcat input_enable_concat_corundum
264+
ad_ip_instance ilconcat input_enable_concat_corundum
265265
ad_ip_parameter input_enable_concat_corundum config.num_ports $INPUT_CHANNELS
266266

267267
for {set i 0} {$i<$INPUT_CHANNELS} {incr i} {
@@ -270,7 +270,7 @@ if {$ad_project_params(CORUNDUM) == "1"} {
270270

271271
ad_connect input_enable_concat_corundum/dout corundum_hierarchy/input_enable
272272

273-
ad_ip_instance xlconcat output_enable_concat_corundum
273+
ad_ip_instance ilconcat output_enable_concat_corundum
274274
ad_ip_parameter output_enable_concat_corundum config.num_ports $OUTPUT_CHANNELS
275275

276276
for {set i 0} {$i<$OUTPUT_CHANNELS} {incr i} {

‎projects/ad_gmsl2eth_sl/common/ad_gmsl2eth_sl_bd.tcl‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -534,7 +534,7 @@ assign_bd_address -offset 0xA000_0000 [get_bd_addr_segs \
534534
corundum_hierarchy/corundum_core/s_axil_ctrl/Reg
535535
] -target_address_space sys_ps8/Data
536536

537-
ad_ip_instance util_reduced_logic util_reduced_logic_0
537+
ad_ip_instance ilreduced_logic util_reduced_logic_0
538538
ad_ip_parameter util_reduced_logic_0 CONFIG.C_OPERATION {or}
539539
ad_ip_parameter util_reduced_logic_0 CONFIG.C_SIZE {8}
540540

‎projects/ad_quadmxfe1_ebz/common/ad_quadmxfe1_ebz_bd.tcl‎

Lines changed: 8 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -226,11 +226,11 @@ ad_data_offload_create $adc_offload_name \
226226
ad_ip_parameter $adc_offload_name/i_data_offload CONFIG.SYNC_EXT_ADD_INTERNAL_CDC 0
227227
ad_connect $adc_offload_name/sync_ext GND
228228

229-
ad_ip_instance util_vector_logic rx_do_rstout_logic
229+
ad_ip_instance ilvector_logic rx_do_rstout_logic
230230
ad_ip_parameter rx_do_rstout_logic config.c_operation {not}
231231
ad_ip_parameter rx_do_rstout_logic config.c_size {1}
232232

233-
ad_ip_instance util_vector_logic cpack_reset_logic
233+
ad_ip_instance ilvector_logic cpack_reset_logic
234234
ad_ip_parameter cpack_reset_logic config.c_operation {or}
235235
ad_ip_parameter cpack_reset_logic config.c_size {1}
236236

@@ -477,8 +477,8 @@ ad_connect axi_mxfe_rx_jesd/rx_axi/device_reset jesd204_phy_125_126/rx_reset_gt
477477
#
478478
if {$ADI_PHY_SEL == 0} {
479479
# Rx Physical lanes to PHY
480-
ad_ip_instance xlconcat rx_concat_7_0_p [list NUM_PORTS {8}]
481-
ad_ip_instance xlconcat rx_concat_7_0_n [list NUM_PORTS {8}]
480+
ad_ip_instance ilconcat rx_concat_7_0_p [list NUM_PORTS {8}]
481+
ad_ip_instance ilconcat rx_concat_7_0_n [list NUM_PORTS {8}]
482482

483483
ad_connect rx_data_0_p rx_concat_7_0_p/In0
484484
ad_connect rx_data_1_p rx_concat_7_0_p/In1
@@ -501,8 +501,8 @@ ad_connect rx_data_7_n rx_concat_7_0_n/In7
501501
ad_connect jesd204_phy_121_122/rxp_in rx_concat_7_0_p/dout
502502
ad_connect jesd204_phy_121_122/rxn_in rx_concat_7_0_n/dout
503503

504-
ad_ip_instance xlconcat rx_concat_15_8_p [list NUM_PORTS {8}]
505-
ad_ip_instance xlconcat rx_concat_15_8_n [list NUM_PORTS {8}]
504+
ad_ip_instance ilconcat rx_concat_15_8_p [list NUM_PORTS {8}]
505+
ad_ip_instance ilconcat rx_concat_15_8_n [list NUM_PORTS {8}]
506506

507507
ad_connect rx_data_8_p rx_concat_15_8_p/In0
508508
ad_connect rx_data_9_p rx_concat_15_8_p/In1
@@ -604,13 +604,13 @@ if {$ADI_PHY_SEL == 0} {
604604
# Tx Physical lanes to PHY
605605
#
606606
for {set i 0} {$i < $MAX_TX_LANES} {incr i} {
607-
ad_ip_instance xlslice txp_out_slice_$i [list \
607+
ad_ip_instance ilslice txp_out_slice_$i [list \
608608
DIN_TO [expr $i % 8] \
609609
DIN_FROM [expr $i % 8] \
610610
DIN_WIDTH {8} \
611611
DOUT_WIDTH {1} \
612612
]
613-
ad_ip_instance xlslice txn_out_slice_$i [list \
613+
ad_ip_instance ilslice txn_out_slice_$i [list \
614614
DIN_TO [expr $i % 8] \
615615
DIN_FROM [expr $i % 8] \
616616
DIN_WIDTH {8} \
@@ -740,4 +740,3 @@ ad_cpu_interrupt ps-12 mb-13 axi_mxfe_tx_dma/irq
740740
ad_cpu_interrupt ps-11 mb-14 axi_mxfe_rx_jesd/irq
741741
ad_cpu_interrupt ps-10 mb-15 axi_mxfe_tx_jesd/irq
742742
ad_cpu_interrupt ps-14 mb-8 axi_gpio_2/ip2intc_irpt
743-

‎projects/adrv9009/common/adrv9009_bd.tcl‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -338,7 +338,7 @@ ad_connect adrv9009_tx_device_clk_rstgen/peripheral_reset util_adrv9009_tx_upac
338338
if {$TX_NUM_OF_CONVERTERS <= 2} {
339339
ad_connect tx_fir_interpolator/valid_out_0 util_adrv9009_tx_upack/fifo_rd_en
340340
} else {
341-
ad_ip_instance util_vector_logic logic_or [list \
341+
ad_ip_instance ilvector_logic logic_or [list \
342342
C_OPERATION {or} \
343343
C_SIZE 1]
344344

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