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daq3: Replace adcfifo/dacfifo with data_offload
Signed-off-by: Ionut Podgoreanu <[email protected]>
1 parent ff84d37 commit 73420ca

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11 files changed

+139
-93
lines changed

11 files changed

+139
-93
lines changed

‎projects/daq3/common/daq3_bd.tcl

Lines changed: 65 additions & 32 deletions
Original file line numberDiff line numberDiff line change
@@ -11,6 +11,7 @@
1111
#
1212

1313
source $ad_hdl_dir/library/jesd204/scripts/jesd204.tcl
14+
source $ad_hdl_dir/projects/common/xilinx/data_offload_bd.tcl
1415

1516
# TX parameters
1617
set TX_NUM_OF_LANES $ad_project_params(TX_JESD_L) ; # L
@@ -21,7 +22,7 @@ set TX_SAMPLE_WIDTH 16 ; # N/NP
2122
set TX_SAMPLES_PER_CHANNEL [expr $TX_NUM_OF_LANES * 32 / \
2223
($TX_NUM_OF_CONVERTERS * $TX_SAMPLE_WIDTH)] ; # L * 32 / (M * N)
2324

24-
set dac_fifo_name axi_ad9152_fifo
25+
set dac_offload_name ad9152_data_offload
2526
set dac_data_width [expr $TX_SAMPLE_WIDTH * $TX_NUM_OF_CONVERTERS * $TX_SAMPLES_PER_CHANNEL]
2627

2728
# RX parameters
@@ -33,7 +34,7 @@ set RX_SAMPLE_WIDTH 16 ; # N/NP
3334
set RX_SAMPLES_PER_CHANNEL [expr $RX_NUM_OF_LANES * 32 / \
3435
($RX_NUM_OF_CONVERTERS * $RX_SAMPLE_WIDTH)] ; # L * 32 / (M * N)
3536

36-
set adc_fifo_name axi_ad9680_fifo
37+
set adc_offload_name ad9680_data_offload
3738
set adc_data_width [expr $RX_SAMPLE_WIDTH * $RX_NUM_OF_CONVERTERS * $RX_SAMPLES_PER_CHANNEL]
3839

3940
set MAX_TX_NUM_OF_LANES 4
@@ -72,7 +73,16 @@ ad_ip_parameter axi_ad9152_dma CONFIG.DMA_DATA_WIDTH_SRC 128
7273
ad_ip_parameter axi_ad9152_dma CONFIG.DMA_DATA_WIDTH_DEST $dac_data_width
7374
ad_ip_parameter axi_ad9152_dma CONFIG.CACHE_COHERENT $CACHE_COHERENCY
7475

75-
ad_dacfifo_create $dac_fifo_name $dac_data_width $dac_data_width $dac_fifo_address_width
76+
ad_data_offload_create $dac_offload_name \
77+
1 \
78+
$dac_offload_type \
79+
$dac_offload_size \
80+
$dac_data_width \
81+
$dac_data_width \
82+
$plddr_offload_axi_data_width
83+
84+
ad_ip_parameter $dac_offload_name/i_data_offload CONFIG.SYNC_EXT_ADD_INTERNAL_CDC 0
85+
ad_connect $dac_offload_name/sync_ext GND
7686

7787
# adc peripherals
7888

@@ -111,7 +121,16 @@ ad_ip_parameter axi_ad9680_dma CONFIG.DMA_DATA_WIDTH_DEST 64
111121
ad_ip_parameter axi_ad9680_dma CONFIG.CACHE_COHERENT $CACHE_COHERENCY
112122

113123
if {$sys_zynq == 0 || $sys_zynq == 1} {
114-
ad_adcfifo_create $adc_fifo_name $adc_data_width $adc_data_width $adc_fifo_address_width
124+
ad_data_offload_create $adc_offload_name \
125+
0 \
126+
$adc_offload_type \
127+
$adc_offload_size \
128+
$adc_data_width \
129+
$adc_data_width \
130+
$plddr_offload_axi_data_width
131+
132+
ad_ip_parameter $adc_offload_name/i_data_offload CONFIG.SYNC_EXT_ADD_INTERNAL_CDC 0
133+
ad_connect $adc_offload_name/sync_ext GND
115134
}
116135

117136
# shared transceiver core
@@ -155,26 +174,18 @@ for {set i 0} {$i < $TX_NUM_OF_CONVERTERS} {incr i} {
155174
}
156175

157176
if {$sys_zynq == 0 || $sys_zynq == 1} {
158-
ad_connect $sys_dma_clk axi_ad9152_fifo/dma_clk
159-
ad_connect $sys_dma_reset axi_ad9152_fifo/dma_rst
177+
ad_connect $sys_dma_clk $dac_offload_name/s_axis_aclk
178+
ad_connect $sys_dma_resetn $dac_offload_name/s_axis_aresetn
160179
ad_connect $sys_dma_clk axi_ad9152_dma/m_axis_aclk
161180
ad_connect $sys_dma_resetn axi_ad9152_dma/m_src_axi_aresetn
162-
ad_connect axi_ad9152_fifo/bypass GND
163181
}
164-
ad_connect util_daq3_xcvr/tx_out_clk_0 axi_ad9152_fifo/dac_clk
165-
ad_connect axi_ad9152_jesd_rstgen/peripheral_reset axi_ad9152_fifo/dac_rst
166-
167-
# TODO: Add streaming AXI interface for DAC FIFO
168-
ad_connect axi_ad9152_upack/s_axis_valid VCC
169-
ad_connect axi_ad9152_upack/s_axis_ready axi_ad9152_fifo/dac_valid
170-
ad_connect axi_ad9152_upack/s_axis_data axi_ad9152_fifo/dac_data
182+
ad_connect util_daq3_xcvr/tx_out_clk_0 $dac_offload_name/m_axis_aclk
183+
ad_connect axi_ad9152_jesd_rstgen/peripheral_aresetn $dac_offload_name/m_axis_aresetn
184+
ad_connect axi_ad9152_upack/s_axis $dac_offload_name/m_axis
171185

172-
ad_connect axi_ad9152_tpl_core/dac_dunf axi_ad9152_fifo/dac_dunf
173-
ad_connect axi_ad9152_fifo/dma_xfer_req axi_ad9152_dma/m_axis_xfer_req
174-
ad_connect axi_ad9152_fifo/dma_ready axi_ad9152_dma/m_axis_ready
175-
ad_connect axi_ad9152_fifo/dma_data axi_ad9152_dma/m_axis_data
176-
ad_connect axi_ad9152_fifo/dma_valid axi_ad9152_dma/m_axis_valid
177-
ad_connect axi_ad9152_fifo/dma_xfer_last axi_ad9152_dma/m_axis_last
186+
ad_connect $dac_offload_name/s_axis axi_ad9152_dma/m_axis
187+
ad_connect $dac_offload_name/init_req axi_ad9152_dma/m_axis_xfer_req
188+
ad_connect axi_ad9152_tpl_core/dac_dunf axi_ad9152_upack/fifo_rd_underflow
178189

179190
# connections (adc)
180191

@@ -185,23 +196,43 @@ ad_connect axi_ad9680_jesd/rx_data_tdata axi_ad9680_tpl_core/link_data
185196
ad_connect axi_ad9680_jesd/rx_data_tvalid axi_ad9680_tpl_core/link_valid
186197
ad_connect axi_ad9680_tpl_core/adc_valid_0 axi_ad9680_cpack/fifo_wr_en
187198

199+
ad_ip_instance xlconcat cpack_reset_sources
200+
ad_ip_parameter cpack_reset_sources config.num_ports {1}
201+
ad_connect axi_ad9680_jesd_rstgen/peripheral_reset cpack_reset_sources/in0
202+
203+
ad_ip_instance util_reduced_logic cpack_rst_logic
204+
ad_ip_parameter cpack_rst_logic config.c_operation {or}
205+
ad_ip_parameter cpack_rst_logic config.c_size {1}
206+
188207
if {$sys_zynq == 0 || $sys_zynq == 1} {
189-
ad_connect util_daq3_xcvr/rx_out_clk_0 axi_ad9680_fifo/adc_clk
190-
ad_connect axi_ad9680_jesd_rstgen/peripheral_reset axi_ad9680_fifo/adc_rst
191-
ad_connect axi_ad9680_cpack/packed_fifo_wr_en axi_ad9680_fifo/adc_wr
192-
ad_connect axi_ad9680_cpack/packed_fifo_wr_data axi_ad9680_fifo/adc_wdata
193-
ad_connect $sys_dma_clk axi_ad9680_fifo/dma_clk
208+
ad_connect util_daq3_xcvr/rx_out_clk_0 $adc_offload_name/s_axis_aclk
209+
ad_connect axi_ad9680_jesd_rstgen/peripheral_aresetn $adc_offload_name/s_axis_aresetn
210+
ad_connect axi_ad9680_cpack/packed_fifo_wr_en $adc_offload_name/s_axis_tvalid
211+
ad_connect axi_ad9680_cpack/packed_fifo_wr_data $adc_offload_name/s_axis_tdata
212+
ad_connect $adc_offload_name/s_axis_tlast GND
213+
ad_connect $adc_offload_name/s_axis_tkeep VCC
214+
ad_connect $sys_dma_clk $adc_offload_name/m_axis_aclk
215+
ad_connect $sys_dma_resetn $adc_offload_name/m_axis_aresetn
194216
ad_connect $sys_dma_clk axi_ad9680_dma/s_axis_aclk
195217
ad_connect $sys_dma_resetn axi_ad9680_dma/m_dest_axi_aresetn
196-
ad_connect axi_ad9680_fifo/dma_wr axi_ad9680_dma/s_axis_valid
197-
ad_connect axi_ad9680_fifo/dma_wdata axi_ad9680_dma/s_axis_data
198-
ad_connect axi_ad9680_fifo/dma_wready axi_ad9680_dma/s_axis_ready
199-
ad_connect axi_ad9680_fifo/dma_xfer_req axi_ad9680_dma/s_axis_xfer_req
200-
ad_connect axi_ad9680_tpl_core/adc_dovf axi_ad9680_fifo/adc_wovf
218+
ad_connect $adc_offload_name/m_axis axi_ad9680_dma/s_axis
219+
ad_connect $adc_offload_name/init_req axi_ad9680_dma/s_axis_xfer_req
220+
ad_connect axi_ad9680_cpack/fifo_wr_overflow axi_ad9680_tpl_core/adc_dovf
221+
222+
ad_ip_instance util_vector_logic rx_do_rstout_logic
223+
ad_ip_parameter rx_do_rstout_logic config.c_operation {not}
224+
ad_ip_parameter rx_do_rstout_logic config.c_size {1}
225+
226+
ad_connect $adc_offload_name/s_axis_tready rx_do_rstout_logic/op1
227+
228+
ad_ip_parameter cpack_reset_sources config.num_ports {2}
229+
ad_ip_parameter cpack_rst_logic config.c_size {2}
230+
ad_connect rx_do_rstout_logic/res cpack_reset_sources/in1
201231
}
202232

203233
ad_connect util_daq3_xcvr/rx_out_clk_0 axi_ad9680_cpack/clk
204-
ad_connect axi_ad9680_jesd_rstgen/peripheral_reset axi_ad9680_cpack/reset
234+
ad_connect cpack_reset_sources/dout cpack_rst_logic/op1
235+
ad_connect cpack_rst_logic/res axi_ad9680_cpack/reset
205236

206237
for {set i 0} {$i < $RX_NUM_OF_CONVERTERS} {incr i} {
207238
ad_connect axi_ad9680_tpl_core/adc_enable_$i axi_ad9680_cpack/enable_$i
@@ -214,13 +245,15 @@ ad_cpu_interconnect 0x44A60000 axi_ad9152_xcvr
214245
ad_cpu_interconnect 0x44A04000 axi_ad9152_tpl_core
215246
ad_cpu_interconnect 0x44A90000 axi_ad9152_jesd
216247
ad_cpu_interconnect 0x7c420000 axi_ad9152_dma
248+
ad_cpu_interconnect 0x7c430000 $dac_offload_name
217249
ad_cpu_interconnect 0x44A50000 axi_ad9680_xcvr
218250
ad_cpu_interconnect 0x44A10000 axi_ad9680_tpl_core
219251
ad_cpu_interconnect 0x44AA0000 axi_ad9680_jesd
220252
ad_cpu_interconnect 0x7c400000 axi_ad9680_dma
221253

222-
223254
if {$sys_zynq == 0 || $sys_zynq == 1} {
255+
ad_cpu_interconnect 0x7c410000 $adc_offload_name
256+
224257
ad_mem_hp1_interconnect $sys_dma_clk sys_ps7/S_AXI_HP1
225258
ad_mem_hp1_interconnect $sys_dma_clk axi_ad9152_dma/m_src_axi
226259
ad_mem_hp2_interconnect $sys_dma_clk sys_ps7/S_AXI_HP2

‎projects/daq3/kcu105/Makefile

Lines changed: 6 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
####################################################################################
2-
## Copyright (c) 2018 - 2023 Analog Devices, Inc.
2+
## Copyright (c) 2018 - 2025 Analog Devices, Inc.
33
### SPDX short identifier: BSD-1-Clause
44
## Auto-generated, do not modify!
55
####################################################################################
@@ -9,24 +9,25 @@ PROJECT_NAME := daq3_kcu105
99
M_DEPS += ../common/daq3_spi.v
1010
M_DEPS += ../common/daq3_bd.tcl
1111
M_DEPS += ../../scripts/adi_pd.tcl
12-
M_DEPS += ../../common/xilinx/dacfifo_bd.tcl
13-
M_DEPS += ../../common/xilinx/adcfifo_bd.tcl
1412
M_DEPS += ../../common/kcu105/kcu105_system_constr.xdc
1513
M_DEPS += ../../common/kcu105/kcu105_system_bd.tcl
14+
M_DEPS += ../../common/xilinx/data_offload_bd.tcl
15+
M_DEPS += ../../../library/util_hbm/scripts/adi_util_hbm.tcl
1616
M_DEPS += ../../../library/jesd204/scripts/jesd204.tcl
1717
M_DEPS += ../../../library/common/ad_iobuf.v
1818

1919
LIB_DEPS += axi_dmac
2020
LIB_DEPS += axi_sysid
21+
LIB_DEPS += data_offload
2122
LIB_DEPS += jesd204/ad_ip_jesd204_tpl_adc
2223
LIB_DEPS += jesd204/ad_ip_jesd204_tpl_dac
2324
LIB_DEPS += jesd204/axi_jesd204_rx
2425
LIB_DEPS += jesd204/axi_jesd204_tx
2526
LIB_DEPS += jesd204/jesd204_rx
2627
LIB_DEPS += jesd204/jesd204_tx
2728
LIB_DEPS += sysid_rom
28-
LIB_DEPS += util_adcfifo
29-
LIB_DEPS += util_dacfifo
29+
LIB_DEPS += util_do_ram
30+
LIB_DEPS += util_hbm
3031
LIB_DEPS += util_pack/util_cpack2
3132
LIB_DEPS += util_pack/util_upack2
3233
LIB_DEPS += xilinx/axi_adxcvr

‎projects/daq3/kcu105/system_bd.tcl

Lines changed: 11 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -1,19 +1,18 @@
11
###############################################################################
2-
## Copyright (C) 2015-2023 Analog Devices, Inc. All rights reserved.
2+
## Copyright (C) 2015-2025 Analog Devices, Inc. All rights reserved.
33
### SPDX short identifier: ADIBSD
44
###############################################################################
55

6-
## FIFO depth is 4Mb - 250k samples
7-
set adc_fifo_address_width 16
6+
## Offload attributes
7+
set adc_offload_type 0 ; ## BRAM
8+
set adc_offload_size [expr 1*1024*1024] ; ## 1 MB
89

9-
## FIFO depth is 4Mb - 250k samples
10-
set dac_fifo_address_width 15
10+
set dac_offload_type 0 ; ## BRAM
11+
set dac_offload_size [expr 512*1024] ; ## 512 kB
1112

12-
## NOTE: With this configuration the #36Kb BRAM utilization is at ~70%
13+
set plddr_offload_axi_data_width 0
1314

1415
source $ad_hdl_dir/projects/common/kcu105/kcu105_system_bd.tcl
15-
source $ad_hdl_dir/projects/common/xilinx/adcfifo_bd.tcl
16-
source $ad_hdl_dir/projects/common/xilinx/dacfifo_bd.tcl
1716
source ../common/daq3_bd.tcl
1817
source $ad_hdl_dir/projects/scripts/adi_pd.tcl
1918

@@ -28,8 +27,10 @@ S=$ad_project_params(RX_JESD_S)\
2827
TX:M=$ad_project_params(TX_JESD_M)\
2928
L=$ad_project_params(TX_JESD_L)\
3029
S=$ad_project_params(TX_JESD_S)\
31-
ADC_FIFO_ADDR_WIDTH=$adc_fifo_address_width\
32-
DAC_FIFO_ADDR_WIDTH=$dac_fifo_address_width"
30+
ADC_OFFLOAD:TYPE=$adc_offload_type\
31+
SIZE=$adc_offload_size\
32+
DAC_OFFLOAD:TYPE=$dac_offload_type\
33+
SIZE=$dac_offload_size"
3334

3435
sysid_gen_sys_init_file $sys_cstring
3536

‎projects/daq3/vcu118/Makefile

Lines changed: 6 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
####################################################################################
2-
## Copyright (c) 2018 - 2023 Analog Devices, Inc.
2+
## Copyright (c) 2018 - 2025 Analog Devices, Inc.
33
### SPDX short identifier: BSD-1-Clause
44
## Auto-generated, do not modify!
55
####################################################################################
@@ -9,24 +9,25 @@ PROJECT_NAME := daq3_vcu118
99
M_DEPS += ../common/daq3_spi.v
1010
M_DEPS += ../common/daq3_bd.tcl
1111
M_DEPS += ../../scripts/adi_pd.tcl
12-
M_DEPS += ../../common/xilinx/dacfifo_bd.tcl
13-
M_DEPS += ../../common/xilinx/adcfifo_bd.tcl
1412
M_DEPS += ../../common/vcu118/vcu118_system_constr.xdc
1513
M_DEPS += ../../common/vcu118/vcu118_system_bd.tcl
14+
M_DEPS += ../../common/xilinx/data_offload_bd.tcl
15+
M_DEPS += ../../../library/util_hbm/scripts/adi_util_hbm.tcl
1616
M_DEPS += ../../../library/jesd204/scripts/jesd204.tcl
1717
M_DEPS += ../../../library/common/ad_iobuf.v
1818

1919
LIB_DEPS += axi_dmac
2020
LIB_DEPS += axi_sysid
21+
LIB_DEPS += data_offload
2122
LIB_DEPS += jesd204/ad_ip_jesd204_tpl_adc
2223
LIB_DEPS += jesd204/ad_ip_jesd204_tpl_dac
2324
LIB_DEPS += jesd204/axi_jesd204_rx
2425
LIB_DEPS += jesd204/axi_jesd204_tx
2526
LIB_DEPS += jesd204/jesd204_rx
2627
LIB_DEPS += jesd204/jesd204_tx
2728
LIB_DEPS += sysid_rom
28-
LIB_DEPS += util_adcfifo
29-
LIB_DEPS += util_dacfifo
29+
LIB_DEPS += util_do_ram
30+
LIB_DEPS += util_hbm
3031
LIB_DEPS += util_pack/util_cpack2
3132
LIB_DEPS += util_pack/util_upack2
3233
LIB_DEPS += xilinx/axi_adxcvr

‎projects/daq3/vcu118/system_bd.tcl

Lines changed: 12 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -1,17 +1,18 @@
11
###############################################################################
2-
## Copyright (C) 2019-2023 Analog Devices, Inc. All rights reserved.
2+
## Copyright (C) 2019-2025 Analog Devices, Inc. All rights reserved.
33
### SPDX short identifier: ADIBSD
44
###############################################################################
55

6-
## FIFO depth is 4Mb - 250k samples
7-
set adc_fifo_address_width 16
6+
## Offload attributes
7+
set adc_offload_type 0 ; ## BRAM
8+
set adc_offload_size [expr 1*1024*1024] ; ## 1 MB
89

9-
## FIFO depth is 4Mb - 250k samples
10-
set dac_fifo_address_width 15
10+
set dac_offload_type 0 ; ## BRAM
11+
set dac_offload_size [expr 512*1024] ; ## 512 kB
12+
13+
set plddr_offload_axi_data_width 0
1114

1215
source $ad_hdl_dir/projects/common/vcu118/vcu118_system_bd.tcl
13-
source $ad_hdl_dir/projects/common/xilinx/adcfifo_bd.tcl
14-
source $ad_hdl_dir/projects/common/xilinx/dacfifo_bd.tcl
1516
source ../common/daq3_bd.tcl
1617
source $ad_hdl_dir/projects/scripts/adi_pd.tcl
1718

@@ -26,8 +27,10 @@ S=$ad_project_params(RX_JESD_S)\
2627
TX:M=$ad_project_params(TX_JESD_M)\
2728
L=$ad_project_params(TX_JESD_L)\
2829
S=$ad_project_params(TX_JESD_S)\
29-
ADC_FIFO_ADDR_WIDTH=$adc_fifo_address_width\
30-
DAC_FIFO_ADDR_WIDTH=$dac_fifo_address_width"
30+
ADC_OFFLOAD:TYPE=$adc_offload_type\
31+
SIZE=$adc_offload_size\
32+
DAC_OFFLOAD:TYPE=$dac_offload_type\
33+
SIZE=$dac_offload_size"
3134

3235
sysid_gen_sys_init_file $sys_cstring
3336

‎projects/daq3/zc706/Makefile

Lines changed: 7 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
####################################################################################
2-
## Copyright (c) 2018 - 2023 Analog Devices, Inc.
2+
## Copyright (c) 2018 - 2025 Analog Devices, Inc.
33
### SPDX short identifier: BSD-1-Clause
44
## Auto-generated, do not modify!
55
####################################################################################
@@ -11,9 +11,10 @@ M_DEPS += ../common/daq3_bd.tcl
1111
M_DEPS += ../../scripts/adi_pd.tcl
1212
M_DEPS += ../../common/zc706/zc706_system_constr.xdc
1313
M_DEPS += ../../common/zc706/zc706_system_bd.tcl
14+
M_DEPS += ../../common/zc706/zc706_plddr3_data_offload_bd.tcl
1415
M_DEPS += ../../common/zc706/zc706_plddr3_constr.xdc
15-
M_DEPS += ../../common/zc706/zc706_plddr3_adcfifo_bd.tcl
16-
M_DEPS += ../../common/xilinx/dacfifo_bd.tcl
16+
M_DEPS += ../../common/xilinx/data_offload_bd.tcl
17+
M_DEPS += ../../../library/util_hbm/scripts/adi_util_hbm.tcl
1718
M_DEPS += ../../../library/jesd204/scripts/jesd204.tcl
1819
M_DEPS += ../../../library/common/ad_iobuf.v
1920

@@ -22,17 +23,18 @@ LIB_DEPS += axi_dmac
2223
LIB_DEPS += axi_hdmi_tx
2324
LIB_DEPS += axi_spdif_tx
2425
LIB_DEPS += axi_sysid
26+
LIB_DEPS += data_offload
2527
LIB_DEPS += jesd204/ad_ip_jesd204_tpl_adc
2628
LIB_DEPS += jesd204/ad_ip_jesd204_tpl_dac
2729
LIB_DEPS += jesd204/axi_jesd204_rx
2830
LIB_DEPS += jesd204/axi_jesd204_tx
2931
LIB_DEPS += jesd204/jesd204_rx
3032
LIB_DEPS += jesd204/jesd204_tx
3133
LIB_DEPS += sysid_rom
32-
LIB_DEPS += util_dacfifo
34+
LIB_DEPS += util_do_ram
35+
LIB_DEPS += util_hbm
3336
LIB_DEPS += util_pack/util_cpack2
3437
LIB_DEPS += util_pack/util_upack2
35-
LIB_DEPS += xilinx/axi_adcfifo
3638
LIB_DEPS += xilinx/axi_adxcvr
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LIB_DEPS += xilinx/util_adxcvr
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