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library: corundum: Correct packaged IP-related warnings
Signed-off-by: alin724 <[email protected]> Signed-off-by: alin724 <[email protected]>
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+26
-62
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5 files changed

+26
-62
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‎library/corundum/corundum_core/corundum_core_ip.tcl‎

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -860,6 +860,8 @@ adi_add_bus_clock "ddr_clk" "m_axi_ddr:m_axi_ddr_app" "ddr_rst"
860860
adi_add_bus_clock "hbm_clk" "m_axi_hbm:m_axi_hbm_app" "hbm_rst"
861861
adi_add_bus_clock "tx_clk" "m_axis_tx:s_axis_direct_tx_app:m_axis_direct_tx_app" "tx_rst"
862862
adi_add_bus_clock "rx_clk" "s_axis_rx:s_axis_stat:s_axis_direct_rx_app:m_axis_direct_rx_app" "rx_rst"
863+
adi_add_bus_clock "tx_ptp_clk" "ethernet_ptp_tx" "tx_ptp_rst"
864+
adi_add_bus_clock "rx_ptp_clk" "ethernet_ptp_rx" "rx_ptp_rst"
863865

864866
## Parameter validation
865867

@@ -2527,6 +2529,9 @@ adi_set_ports_dependency "hbm_status" \
25272529
adi_set_bus_dependency "m_axil_csr" "m_axil_csr" \
25282530
"(spirit:decode(id('PARAM_VALUE.AXIL_CSR_ENABLE')) = 1)"
25292531

2532+
adi_set_bus_dependency "s_axis_stat" "s_axis_stat" \
2533+
"(spirit:decode(id('MODELPARAM_VALUE.STAT_ENABLE')) = 1)"
2534+
25302535
# Application dependencies
25312536

25322537
adi_set_bus_dependency "m_axi_ddr_app" "m_axi_ddr_app" \

‎library/corundum/ethernet/k26/ethernet_k26.v‎

Lines changed: 12 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -53,8 +53,8 @@ module ethernet_k26 #(
5353

5454
// Statistics counter subsystem
5555
parameter STAT_ENABLE = 0,
56-
parameter STAT_DMA_ENABLE = 1,
57-
parameter STAT_AXI_ENABLE = 1,
56+
parameter STAT_DMA_ENABLE = 0,
57+
parameter STAT_AXI_ENABLE = 0,
5858
parameter STAT_INC_WIDTH = 24,
5959
parameter STAT_ID_WIDTH = 12
6060
) (
@@ -139,11 +139,17 @@ module ethernet_k26 #(
139139

140140
output wire [PORT_COUNT-1:0] eth_tx_clk,
141141
output wire [PORT_COUNT-1:0] eth_tx_rst,
142+
143+
output wire [PORT_COUNT-1:0] eth_tx_ptp_clk,
144+
output wire [PORT_COUNT-1:0] eth_tx_ptp_rst,
142145
input wire [PORT_COUNT*PTP_TS_WIDTH-1:0] eth_tx_ptp_ts,
143146
input wire [PORT_COUNT-1:0] eth_tx_ptp_ts_step,
144147

145148
output wire [PORT_COUNT-1:0] eth_rx_clk,
146149
output wire [PORT_COUNT-1:0] eth_rx_rst,
150+
151+
output wire [PORT_COUNT-1:0] eth_rx_ptp_clk,
152+
output wire [PORT_COUNT-1:0] eth_rx_ptp_rst,
147153
input wire [PORT_COUNT*PTP_TS_WIDTH-1:0] eth_rx_ptp_ts,
148154
input wire [PORT_COUNT-1:0] eth_rx_ptp_ts_step,
149155

@@ -184,14 +190,6 @@ module ethernet_k26 #(
184190
input wire [PORT_COUNT*8-1:0] eth_rx_pfc_ack,
185191
output wire [PORT_COUNT-1:0] eth_rx_fc_quanta_clk_en,
186192

187-
/*
188-
* Statistics increment input
189-
*/
190-
output wire [STAT_INC_WIDTH-1:0] s_axis_stat_tdata,
191-
output wire [STAT_ID_WIDTH-1:0] s_axis_stat_tid,
192-
output wire s_axis_stat_tvalid,
193-
input wire s_axis_stat_tready,
194-
195193
input wire scl_i,
196194
output reg scl_o,
197195
output reg scl_t,
@@ -509,8 +507,12 @@ module ethernet_k26 #(
509507

510508
assign eth_tx_clk[n] = port_xgmii_tx_clk[n];
511509
assign eth_tx_rst[n] = port_xgmii_tx_rst[n];
510+
assign eth_tx_ptp_clk[n] = port_xgmii_tx_clk[n];
511+
assign eth_tx_ptp_rst[n] = port_xgmii_tx_rst[n];
512512
assign eth_rx_clk[n] = port_xgmii_rx_clk[n];
513513
assign eth_rx_rst[n] = port_xgmii_rx_rst[n];
514+
assign eth_rx_ptp_clk[n] = port_xgmii_rx_clk[n];
515+
assign eth_rx_ptp_rst[n] = port_xgmii_rx_rst[n];
514516

515517
eth_mac_10g #(
516518
.DATA_WIDTH(AXIS_DATA_WIDTH),

‎library/corundum/ethernet/k26/ethernet_k26_ip.tcl‎

Lines changed: 9 additions & 45 deletions
Original file line numberDiff line numberDiff line change
@@ -79,8 +79,6 @@ adi_add_bus "axis_eth_tx" "slave" \
7979
{"axis_eth_tx_tuser" "TUSER"} \
8080
]
8181

82-
adi_add_bus_clock "eth_tx_clk" "axis_eth_tx" "eth_tx_rst" "master" "master"
83-
8482
adi_add_bus "axis_eth_rx" "master" \
8583
"xilinx.com:interface:axis_rtl:1.0" \
8684
"xilinx.com:interface:axis:1.0" \
@@ -93,8 +91,6 @@ adi_add_bus "axis_eth_rx" "master" \
9391
{"axis_eth_rx_tuser" "TUSER"} \
9492
]
9593

96-
adi_add_bus_clock "eth_rx_clk" "axis_eth_rx" "eth_rx_rst" "master" "master"
97-
9894
adi_if_infer_bus analog.com:interface:if_ctrl_reg slave ctrl_reg [list \
9995
"ctrl_reg_wr_addr ctrl_reg_wr_addr" \
10096
"ctrl_reg_wr_data ctrl_reg_wr_data" \
@@ -136,47 +132,20 @@ adi_if_infer_bus analog.com:interface:if_axis_tx_ptp slave axis_tx_ptp [list \
136132
"ready axis_eth_tx_ptp_ts_ready" \
137133
]
138134

139-
adi_add_bus_clock "eth_tx_clk" "axis_tx_ptp" "eth_tx_rst" "master" "master"
140-
141-
ipx::infer_bus_interface clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
142-
set reset_intf_main [ipx::infer_bus_interface rst xilinx.com:signal:reset_rtl:1.0 [ipx::current_core]]
143-
set reset_polarity_main [ipx::add_bus_parameter "POLARITY" $reset_intf_main]
144-
set_property value "ACTIVE_HIGH" $reset_polarity_main
145-
146-
ipx::infer_bus_interface ptp_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
147-
ipx::infer_bus_interface ptp_sample_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
148-
149-
ipx::infer_bus_interface eth_tx_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
150-
ipx::infer_bus_interface eth_rx_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
151-
152-
set reset_intf_ptp [ipx::infer_bus_interface ptp_rst xilinx.com:signal:reset_rtl:1.0 [ipx::current_core]]
153-
set reset_polarity_ptp [ipx::add_bus_parameter "POLARITY" $reset_intf_ptp]
154-
set_property value "ACTIVE_HIGH" $reset_polarity_ptp
155-
156-
set eth_tx_rst_intf [ipx::infer_bus_interface eth_tx_rst xilinx.com:signal:reset_rtl:1.0 [ipx::current_core]]
157-
set eth_tx_rst_polarity [ipx::add_bus_parameter "POLARITY" $eth_tx_rst_intf]
158-
set_property value "ACTIVE_HIGH" $eth_tx_rst_polarity
159-
set eth_rx_rst_intf [ipx::infer_bus_interface eth_rx_rst xilinx.com:signal:reset_rtl:1.0 [ipx::current_core]]
160-
set eth_rx_rst_polarity [ipx::add_bus_parameter "POLARITY" $eth_rx_rst_intf]
161-
set_property value "ACTIVE_HIGH" $eth_rx_rst_polarity
162-
163135
adi_if_infer_bus analog.com:interface:if_ethernet_ptp slave ethernet_ptp_tx [list \
164-
"ptp_clk eth_tx_clk" \
165-
"ptp_rst eth_tx_rst" \
136+
"ptp_clk eth_tx_ptp_clk" \
137+
"ptp_rst eth_tx_ptp_rst" \
166138
"ptp_ts eth_tx_ptp_ts" \
167139
"ptp_ts_step eth_tx_ptp_ts_step" \
168140
]
169141

170142
adi_if_infer_bus analog.com:interface:if_ethernet_ptp slave ethernet_ptp_rx [list \
171-
"ptp_clk eth_rx_clk" \
172-
"ptp_rst eth_rx_rst" \
143+
"ptp_clk eth_rx_ptp_clk" \
144+
"ptp_rst eth_rx_ptp_rst" \
173145
"ptp_ts eth_rx_ptp_ts" \
174146
"ptp_ts_step eth_rx_ptp_ts_step" \
175147
]
176148

177-
adi_add_bus_clock "eth_tx_clk" "ethernet_ptp_tx" "eth_tx_rst" "master" "master"
178-
adi_add_bus_clock "eth_rx_clk" "ethernet_ptp_rx" "eth_rx_rst" "master" "master"
179-
180149
adi_if_infer_bus analog.com:interface:if_flow_control_tx slave flow_control_tx [list \
181150
"tx_enable eth_tx_enable" \
182151
"tx_status eth_tx_status" \
@@ -199,16 +168,6 @@ adi_if_infer_bus analog.com:interface:if_flow_control_rx slave flow_control_rx [
199168
"rx_fc_quanta_clk_en eth_rx_fc_quanta_clk_en" \
200169
]
201170

202-
adi_add_bus "m_axis_stat" "master" \
203-
"xilinx.com:interface:axis_rtl:1.0" \
204-
"xilinx.com:interface:axis:1.0" \
205-
[ list \
206-
{"s_axis_stat_tdata" "TDATA"} \
207-
{"s_axis_stat_tid" "TID"} \
208-
{"s_axis_stat_tvalid" "TVALID"} \
209-
{"s_axis_stat_tready" "TREADY"} \
210-
]
211-
212171
adi_if_infer_bus analog.com:interface:if_sfp master m_sfp [list \
213172
"rx_p sfp_rx_p" \
214173
"rx_n sfp_rx_n" \
@@ -271,6 +230,11 @@ adi_if_infer_bus analog.com:interface:if_ptp slave ptp_clock [list \
271230
"ptp_perout_pulse ptp_perout_pulse" \
272231
]
273232

233+
adi_add_bus_clock "eth_tx_clk" "axis_eth_tx:axis_tx_ptp" "eth_tx_rst" "master" "master"
234+
adi_add_bus_clock "eth_rx_clk" "axis_eth_rx" "eth_rx_rst" "master" "master"
235+
adi_add_bus_clock "eth_tx_ptp_clk" "ethernet_ptp_tx" "eth_tx_ptp_rst" "master" "master"
236+
adi_add_bus_clock "eth_rx_ptp_clk" "ethernet_ptp_rx" "eth_rx_ptp_rst" "master" "master"
237+
274238
## Customize GUI page
275239

276240
# Remove the automatically generated GUI page

‎library/corundum/scripts/corundum.tcl‎

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -402,7 +402,6 @@ if [string equal $board K26] {
402402
ad_connect corundum_core/ptp_clk ethernet_core/ptp_clk
403403
ad_connect corundum_core/ptp_rst ethernet_core/ptp_rst
404404
ad_connect corundum_core/ptp_sample_clk ethernet_core/ptp_sample_clk
405-
ad_connect corundum_core/s_axis_stat ethernet_core/m_axis_stat
406405
} else {
407406
ad_connect ethernet_core/clk_125mhz clk_125mhz
408407
ad_connect ethernet_core/rst_125mhz rst_125mhz

‎projects/ad_gmsl2eth_sl/common/ad_gmsl2eth_sl_bd.tcl‎

Lines changed: 0 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -500,12 +500,6 @@ ad_connect corundum_hierarchy/sfp_iic sfp_iic
500500

501501
ad_connect clk10_gen/clk_out1 ref_clk0
502502

503-
set axi_clk_freq [get_property CONFIG.FREQ_HZ [get_bd_pins sys_ps8/pl_clk1]]
504-
set_property CONFIG.FREQ_HZ $axi_clk_freq [get_bd_intf_pins corundum_hierarchy/m_axi]
505-
set_property CONFIG.FREQ_HZ $axi_clk_freq [get_bd_intf_pins /corundum_hierarchy/corundum_core/m_axi]
506-
set_property CONFIG.FREQ_HZ $axi_clk_freq [get_bd_intf_pins corundum_hierarchy/s_axil_corundum]
507-
set_property CONFIG.FREQ_HZ $axi_clk_freq [get_bd_intf_pins /corundum_hierarchy/corundum_core/s_axil_ctrl]
508-
509503
ad_ip_instance axi_interconnect smartconnect_corundum
510504
ad_ip_parameter smartconnect_corundum CONFIG.NUM_MI 2
511505
ad_ip_parameter smartconnect_corundum CONFIG.NUM_SI 1

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