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projects/ad4630_fmc: Updates READMEs
Signed-off-by: Cristian Mihai Popa <[email protected]>
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‎projects/ad4630_fmc/Readme.md

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# AD4630-24 Eval FMC HDL Project
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Here are some pointers to help you:
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* [Board Product Page]( https://www.analog.com/eval-ad4630-24)
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* Parts : [24-Bit, 2 MSPS, Dual Channel, Precision Differential SAR ADC](https://www.analog.com/ad4630-24)
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[24-Bit, 500 kSPS, Dual Channel SAR ADC](https://www.analog.com/AD4632-24)
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* Project Doc: https://wiki.analog.com/resources/eval/ad4630-24-eval-board
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* HDL Doc: https://wiki.analog.com/resources/eval/user-guides/ad463x/hdl
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* Linux Drivers: https://wiki.analog.com/resources/tools-software/uc-drivers/ad463x
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# AD4630-FMC HDL Project
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- Evaluation board product page: [EVAL-AD4630-FMC](https://www.analog.com/eval-ad4630-24)
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- System documentation: [TO BE ADDED]
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- HDL project documentation: https://analogdevicesinc.github.io/hdl/projects/ad4630_fmc/index.html
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## Supported parts
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| Part name | Description |
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|--------------------------------------------------------------|--------------------------------------------------------------|
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| [AD4030](https://www.analog.com/en/products/ad4030-24) | 24-Bit, 2 MSPS, Single Channel SAR ADC |
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| [AD4630](https://www.analog.com/ad4630-24) | 24-Bit, 2 MSPS, Dual Channel, Precision Differential SAR ADC |
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| [AD4632](https://www.analog.com/AD4632-24) | 24-Bit, 500 kSPS, Dual Channel SAR ADC |
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| [ADAQ4216](https://www.analog.com/en/products/adaq4216.html) | 16-Bit, 2MSPS, μModule Data-Acquisition Solution |
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| [ADAQ4224](https://www.analog.com/en/products/adaq4224.html) | 24-Bit, 2 MSPS, μModule Data Acquisition Solution |
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## Building the project
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Please enter the folder for the FPGA carrier you want to use and read the README.md.

‎projects/ad4630_fmc/zed/README.md

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# EVAL-AD463X-FMC/ZED HDL Project
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# EVAL-AD463X_FMCZ HDL reference design
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## Building the project
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## Building the design
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The parameters configurable through the `make` command, can be found below, as
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well as in the **system_project.tcl** file.
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The design supports almost all the digital interface modes of AD463x, AD403x
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and adaq42xx a new bit stream should be generated each time when the targeted
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configuration changes.
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```
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cd projects/ad4630_fmc/zed
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make
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```
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Default configuration: generic SPI mode for clocking, 2 lanes per channel, SDR
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data capture and capture zone 2.
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This design supports almost all the digital interface modes of AD463x, AD403x
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and ADAQ42xx. A new bit stream should be generated each time when the targeted
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configuration changes. More context on the supported modes can be found in the:
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### Building attributes
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- [AD403x-24 data sheet](https://www.analog.com/media/en/technical-documentation/data-sheets/ad4030-24-4032-24.pdf)
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- [AD463x-16 data sheet](https://www.analog.com/media/en/technical-documentation/data-sheets/ad4630-16-4632-16.pdf)
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- [AD463x-24 data sheet](https://www.analog.com/media/en/technical-documentation/data-sheets/ad4630-24_ad4632-24.pdf)
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- [ADAQ4216 data sheet](https://www.analog.com/media/en/technical-documentation/data-sheets/adaq4216.pdf)
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- [ADAQ4224 data sheet](https://www.analog.com/media/en/technical-documentation/data-sheets/adaq4224.pdf)
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| Attribute name | Valid values |
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| --------------- | ------------------------------------------------- |
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| CLK_MODE | 0 - SPI / 1 - Echo-clock or Master clock |
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| NUM_OF_SDI | 1 - Interleaved / 2 - 1LPC / 4 - 2LPC / 8 - 4LPC |
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| CAPTURE_ZONE | 1 - negedge of BUSY / 2 - next posedge of CNV |
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| DDR_EN | 0 - MISO runs on SDR / 1 - MISO runs on DDR |
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If other configurations are desired, then the parameters from the HDL project
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need to be changed, as well as the Linux project configurations:
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**Example:**
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make CLK_MODE=0 NUM_OF_SDI=2 CAPTURE_ZONE=2 DDR_EN=0
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make CLK_MODE=0 NUM_OF_SDI=4 CAPTURE_ZONE=2 DDR_EN=0
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make CLK_MODE=0 NUM_OF_SDI=8 CAPTURE_ZONE=2 DDR_EN=0
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make CLK_MODE=1 NUM_OF_SDI=2 CAPTURE_ZONE=2 DDR_EN=0
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make CLK_MODE=1 NUM_OF_SDI=4 CAPTURE_ZONE=2 DDR_EN=0
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make CLK_MODE=1 NUM_OF_SDI=8 CAPTURE_ZONE=2 DDR_EN=0
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make CLK_MODE=1 NUM_OF_SDI=2 CAPTURE_ZONE=2 DDR_EN=1
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make CLK_MODE=1 NUM_OF_SDI=4 CAPTURE_ZONE=2 DDR_EN=1
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make CLK_MODE=1 NUM_OF_SDI=8 CAPTURE_ZONE=2 DDR_EN=1
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The overwritable parameters from the environment are:
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## Documentation
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- CLK_MODE: clocking mode of the device's digital interface
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- 0 - SPI
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- 1 - Echo-clock or Master clock
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- NUM_OF_SDI: the number of MOSI lines of the SPI interface
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- 1 - Interleaved
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- 2 - 1LPC
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- 4 - 2LPC
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- 8 - 4LPC
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- CAPTURE_ZONE: the capture zone of the next sample
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- 1 - neg. edge of BUSY
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- 2 - next pos. edge of CNV
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- DDR_EN: in echo and master clock mode the SDI lines can have Single or Double data rates
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- 0 - MISO runs on SDR
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- 1 - MISO runs on DDR
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https://wiki.analog.com/resources/eval/user-guides/ad463x/hdl
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### Example configurations
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#### Clock mode 0, MOSI lines 2, Capture zone 2, DDR_EN 0
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This specific command is equivalent to running `make` only:
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```
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make CLK_MODE=0 NUM_OF_SDI=4 CAPTURE_ZONE=2 DDR_EN=0
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```
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#### Clock mode 0, MOSI lines 2, Capture zone 2, DDR_EN 0
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```
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make CLK_MODE=0 NUM_OF_SDI=2 CAPTURE_ZONE=2 DDR_EN=0
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```
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#### Clock mode 0, MOSI lines 4, Capture zone 2, DDR_EN 0
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```
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make CLK_MODE=0 NUM_OF_SDI=4 CAPTURE_ZONE=2 DDR_EN=0
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```
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#### Clock mode 0, MOSI lines 8, Capture zone 2, DDR_EN 0
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```
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make CLK_MODE=0 NUM_OF_SDI=8 CAPTURE_ZONE=2 DDR_EN=0
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```
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#### Clock mode 1, MOSI lines 2, Capture zone 2, DDR_EN 0
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```
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make CLK_MODE=1 NUM_OF_SDI=2 CAPTURE_ZONE=2 DDR_EN=0
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```
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#### Clock mode 1, MOSI lines 4, Capture zone 2, DDR_EN 0
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```
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make CLK_MODE=1 NUM_OF_SDI=4 CAPTURE_ZONE=2 DDR_EN=0
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```
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#### Clock mode 1, MOSI lines 8, Capture zone 2, DDR_EN 0
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```
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make CLK_MODE=1 NUM_OF_SDI=8 CAPTURE_ZONE=2 DDR_EN=0
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```
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#### Clock mode 1, MOSI lines 2, Capture zone 2, DDR_EN 1
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```
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make CLK_MODE=1 NUM_OF_SDI=2 CAPTURE_ZONE=2 DDR_EN=1
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```
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#### Clock mode 1, MOSI lines 4, Capture zone 2, DDR_EN 1
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```
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make CLK_MODE=1 NUM_OF_SDI=4 CAPTURE_ZONE=2 DDR_EN=1
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```
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#### Clock mode 1, MOSI lines 8, Capture zone 2, DDR_EN 1
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```
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make CLK_MODE=1 NUM_OF_SDI=8 CAPTURE_ZONE=2 DDR_EN=1
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```
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Corresponding device trees:
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- [zynq-zed-adv7511-ad4030-24.dts](https://github.com/analogdevicesinc/linux/blob/main/arch/arm/boot/dts/xilinx/zynq-zed-adv7511-ad4030-24.dts)
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- [zynq-zed-adv7511-ad4032-24.dts](https://github.com/analogdevicesinc/linux/blob/main/arch/arm/boot/dts/xilinx/zynq-zed-adv7511-ad4032-24.dts)
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- [zynq-zed-adv7511-ad4630-16.dts](https://github.com/analogdevicesinc/linux/blob/main/arch/arm/boot/dts/xilinx/zynq-zed-adv7511-ad4630-16.dts)
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- [zynq-zed-adv7511-ad4630-24.dts](https://github.com/analogdevicesinc/linux/blob/main/arch/arm/boot/dts/xilinx/zynq-zed-adv7511-ad4630-24.dts)
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- [zynq-zed-adv7511-adaq4216.dts](https://github.com/analogdevicesinc/linux/blob/main/arch/arm/boot/dts/xilinx/zynq-zed-adv7511-adaq4216.dts)
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- [zynq-zed-adv7511-adaq4220.dts](https://github.com/analogdevicesinc/linux/blob/main/arch/arm/boot/dts/xilinx/zynq-zed-adv7511-adaq4220.dts)
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- [zynq-zed-adv7511-adaq4224-24.dts](https://github.com/analogdevicesinc/linux/blob/main/arch/arm/boot/dts/xilinx/zynq-zed-adv7511-adaq4224-24.dts)
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- [zynq-zed-adv7511-adaq4224-24_cm0_sdi4_cz2.dts](https://github.com/analogdevicesinc/linux/blob/main/arch/arm/boot/dts/xilinx/zynq-zed-adv7511-adaq4224-24_cm0_sdi4_cz2.dts)

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