diff --git a/library/spi_engine/scripts/spi_engine.tcl b/library/spi_engine/scripts/spi_engine.tcl
index 0b22305e30a..63007966c2a 100644
--- a/library/spi_engine/scripts/spi_engine.tcl
+++ b/library/spi_engine/scripts/spi_engine.tcl
@@ -3,33 +3,106 @@
 ### SPDX short identifier: ADIBSD
 ###############################################################################
 
-proc spi_engine_create {{name "spi_engine"} {data_width 32} {async_spi_clk 1} {num_cs 1} {num_sdi 1} {num_sdo 1} {sdi_delay 0} {echo_sclk 0} {sdo_streaming 0} {cmd_mem_addr_width 4} {data_mem_addr_width 4} {sdi_fifo_addr_width 5} {sdo_fifo_addr_width 5} {sync_fifo_addr_width 4} {cmd_fifo_addr_width 4}} {
-  puts "echo_sclk: $echo_sclk"
+## Unified SPI Engine generation script
+## This script provides a single implementation that works for both Xilinx and Intel
+## by using the vendor-agnostic ad_* procedures from adi_board.tcl or <intel_carrier>_system_qsys.tcl
 
-  create_bd_cell -type hier $name
-  current_bd_instance /$name
-
-  if {$async_spi_clk == 1} {
-    create_bd_pin -dir I -type clk spi_clk
+proc ad_detect_vendor {} {
+  if {[info commands get_bd_cells] != ""} {
+    return "xilinx"
   }
-  if {$echo_sclk == 1} {
-    create_bd_pin -dir I -type clk echo_sclk
+  if {[info commands add_instance] != ""} {
+    return "intel"
   }
-  create_bd_pin -dir I -type clk clk
-  create_bd_pin -dir I -type rst resetn
-  create_bd_pin -dir I trigger
-  create_bd_pin -dir O irq
-  create_bd_intf_pin -mode Master -vlnv analog.com:interface:spi_engine_rtl:1.0 m_spi
-  create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 m_axis_sample
-  if {$sdo_streaming == 1} {
-    create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 s_axis_sample
+  # Default to xilinx for backward compatibility
+  return "xilinx"
+}
+
+proc optional_param {param_list index default_value} {
+  if {[llength $param_list] > $index} {
+    return [lindex $param_list $index]
+  } else {
+    return $default_value
   }
+}
 
+proc spi_engine_create {args} {
+
+  set vendor [ad_detect_vendor]
+
+  # Parse arguments based on vendor expectations
+  if {$vendor == "xilinx"} {
+    # Xilinx: name + optional parameters
+    set name                  [lindex $args 0]
+    set data_width            [optional_param $args 1 32]
+    set async_spi_clk         [optional_param $args 2 1]
+    set num_cs                [optional_param $args 3 1]
+    set num_sdi               [optional_param $args 4 1]
+    set num_sdo               [optional_param $args 5 1]
+    set sdi_delay             [optional_param $args 6 0]
+    set echo_sclk             [optional_param $args 7 0]
+    set sdo_streaming         [optional_param $args 8 0]
+    set cmd_mem_addr_width    [optional_param $args 9 4]
+    set data_mem_addr_width   [optional_param $args 10 4]
+    set sdi_fifo_addr_width   [optional_param $args 11 5]
+    set sdo_fifo_addr_width   [optional_param $args 12 5]
+    set sync_fifo_addr_width  [optional_param $args 13 4]
+    set cmd_fifo_addr_width   [optional_param $args 14 4]
+
+  } elseif {$vendor == "intel"} {
+    # Intel: name + clocks & resets + optional parameters
+    if {[llength $args] < 4} {
+      error "ERROR: Intel implementation requires at least: name, axi_clk, axi_reset, spi_clk"
+    }
+    set name                  [lindex $args 0]
+    set axi_clk               [lindex $args 1]
+    set axi_reset             [lindex $args 2]
+    set spi_clk               [lindex $args 3]
+    set data_width            [optional_param $args 4 32]
+    set async_spi_clk         [optional_param $args 5 1]
+    set num_cs                [optional_param $args 6 1]
+    set num_sdi               [optional_param $args 7 1]
+    set num_sdo               [optional_param $args 8 1]
+    set sdi_delay             [optional_param $args 9 0]
+    set echo_sclk             [optional_param $args 10 0]
+    set sdo_streaming         [optional_param $args 11 0]
+    set cmd_mem_addr_width    [optional_param $args 12 4]
+    set data_mem_addr_width   [optional_param $args 13 4]
+    set sdi_fifo_addr_width   [optional_param $args 14 5]
+    set sdo_fifo_addr_width   [optional_param $args 15 5]
+    set sync_fifo_addr_width  [optional_param $args 16 4]
+    set cmd_fifo_addr_width   [optional_param $args 17 4]
+  }
+
+  # Component instance names
   set execution "${name}_execution"
   set axi_regmap "${name}_axi_regmap"
   set offload "${name}_offload"
   set interconnect "${name}_interconnect"
 
+  if {$vendor == "xilinx"} {
+  # Create hierarchy for Xilinx only
+    create_bd_cell -type hier $name
+    current_bd_instance /$name
+    if {$async_spi_clk == 1} {
+      create_bd_pin -dir I -type clk spi_clk
+    }
+    if {$echo_sclk == 1} {
+      create_bd_pin -dir I -type clk echo_sclk
+    }
+    create_bd_pin -dir I -type clk clk
+    create_bd_pin -dir I -type rst resetn
+    create_bd_pin -dir I trigger
+    create_bd_pin -dir O irq
+    create_bd_intf_pin -mode Master -vlnv analog.com:interface:spi_engine_rtl:1.0 m_spi
+    create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 m_axis_sample
+    if {$sdo_streaming == 1} {
+      create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 s_axis_sample
+    }
+  }
+
+
+  # IP instances
   ad_ip_instance spi_engine_execution $execution
   ad_ip_parameter $execution CONFIG.DATA_WIDTH $data_width
   ad_ip_parameter $execution CONFIG.NUM_OF_CS $num_cs
@@ -39,6 +112,7 @@ proc spi_engine_create {{name "spi_engine"} {data_width 32} {async_spi_clk 1} {n
   ad_ip_parameter $execution CONFIG.ECHO_SCLK $echo_sclk
 
   ad_ip_instance axi_spi_engine $axi_regmap
+  ad_ip_parameter $axi_regmap CONFIG.MM_IF_TYPE 0
   ad_ip_parameter $axi_regmap CONFIG.DATA_WIDTH $data_width
   ad_ip_parameter $axi_regmap CONFIG.NUM_OFFLOAD 1
   ad_ip_parameter $axi_regmap CONFIG.NUM_OF_SDI $num_sdi
@@ -57,51 +131,97 @@ proc spi_engine_create {{name "spi_engine"} {data_width 32} {async_spi_clk 1} {n
   ad_ip_parameter $offload CONFIG.CMD_MEM_ADDRESS_WIDTH $cmd_mem_addr_width
   ad_ip_parameter $offload CONFIG.SDO_MEM_ADDRESS_WIDTH $data_mem_addr_width
   ad_ip_parameter $offload CONFIG.SDO_STREAMING $sdo_streaming
+  ad_ip_parameter $offload CONFIG.ASYNC_TRIG 0
 
   ad_ip_instance spi_engine_interconnect $interconnect
   ad_ip_parameter $interconnect CONFIG.DATA_WIDTH $data_width
   ad_ip_parameter $interconnect CONFIG.NUM_OF_SDI $num_sdi
 
-  ad_connect $axi_regmap/spi_engine_offload_ctrl0 $offload/spi_engine_offload_ctrl
-  ad_connect $offload/m_interconnect_ctrl $interconnect/s_interconnect_ctrl
-  ad_connect $offload/spi_engine_ctrl $interconnect/s0_ctrl
-  ad_connect $axi_regmap/spi_engine_ctrl $interconnect/s1_ctrl
-  ad_connect $interconnect/m_ctrl $execution/ctrl
-  ad_connect $offload/offload_sdi m_axis_sample
-  ad_connect $offload/trigger trigger
-
-  ad_connect $execution/spi m_spi
-
-   if {$sdo_streaming == 1} {
-    ad_connect $offload/s_axis_sdo s_axis_sample
-  }
-
-  ad_connect clk $axi_regmap/s_axi_aclk
-
-  if {$async_spi_clk == 1} {
-    ad_connect spi_clk $offload/spi_clk
-    ad_connect spi_clk $offload/ctrl_clk
-    ad_connect spi_clk $execution/clk
-    ad_connect spi_clk $axi_regmap/spi_clk
-    ad_connect spi_clk $interconnect/clk
-  } else {
-    ad_connect clk $offload/spi_clk
-    ad_connect clk $offload/ctrl_clk
-    ad_connect clk $execution/clk
-    ad_connect clk $axi_regmap/spi_clk
-    ad_connect clk $interconnect/clk
+  # Connections based on vendor
+  if {$vendor == "xilinx"} {
+
+    # Clock connections
+    ad_connect clk $axi_regmap/s_axi_aclk
+
+    if {$async_spi_clk == 1} {
+      ad_connect spi_clk $offload/spi_clk
+      ad_connect spi_clk $offload/ctrl_clk
+      ad_connect spi_clk $execution/clk
+      ad_connect spi_clk $axi_regmap/spi_clk
+      ad_connect spi_clk $interconnect/clk
+    } else {
+      ad_connect clk $offload/spi_clk
+      ad_connect clk $offload/ctrl_clk
+      ad_connect clk $execution/clk
+      ad_connect clk $axi_regmap/spi_clk
+      ad_connect clk $interconnect/clk
+    }
+
+    if {$echo_sclk == 1} {
+      ad_connect echo_sclk $execution/echo_sclk
+    }
+
+    # Reset connections
+    ad_connect $axi_regmap/spi_resetn $offload/spi_resetn
+    ad_connect $axi_regmap/spi_resetn $execution/resetn
+    ad_connect $axi_regmap/spi_resetn $interconnect/resetn
+    ad_connect resetn $axi_regmap/s_axi_aresetn
+    ad_connect irq $axi_regmap/irq
+
+    #Data path connections
+    ad_connect $axi_regmap/spi_engine_offload_ctrl0 $offload/spi_engine_offload_ctrl
+    ad_connect $offload/m_interconnect_ctrl $interconnect/s_interconnect_ctrl
+    ad_connect $offload/spi_engine_ctrl $interconnect/s0_ctrl
+    ad_connect $axi_regmap/spi_engine_ctrl $interconnect/s1_ctrl
+    ad_connect $interconnect/m_ctrl $execution/ctrl
+    ad_connect $offload/offload_sdi m_axis_sample
+    ad_connect $offload/trigger trigger
+    ad_connect $execution/spi m_spi
+
+    if {$sdo_streaming == 1} {
+      ad_connect $offload/s_axis_sdo s_axis_sample
+    }
+
+
+    # Exit hierarchy
+    current_bd_instance /
+
+  } elseif {$vendor == "intel"} {
+    # Intel connection style (flat with different interface naming)
+
+    # Clock connections
+    ad_connect $axi_clk $axi_regmap.s_axi_clock
+    ad_connect $spi_clk $axi_regmap.if_spi_clk
+    ad_connect $spi_clk $execution.if_clk
+    ad_connect $spi_clk $interconnect.if_clk
+    ad_connect $spi_clk $offload.if_ctrl_clk
+    ad_connect $spi_clk $offload.if_spi_clk
+
+    # Reset connections
+    ad_connect $axi_reset $axi_regmap.s_axi_reset
+    ad_connect $axi_regmap.if_spi_resetn $execution.if_resetn
+    ad_connect $axi_regmap.if_spi_resetn $interconnect.if_resetn
+    ad_connect $axi_regmap.if_spi_resetn $offload.if_spi_resetn
+
+    # Data path connections
+    ad_connect $interconnect.m_cmd $execution.cmd
+    ad_connect $execution.sdi_data $interconnect.m_sdi
+    ad_connect $interconnect.m_sdo $execution.sdo_data
+    ad_connect $execution.sync $interconnect.m_sync
+    ad_connect $axi_regmap.cmd $interconnect.s1_cmd
+    ad_connect $interconnect.s1_sdi $axi_regmap.sdi_data
+    ad_connect $axi_regmap.sdo_data $interconnect.s1_sdo
+    ad_connect $interconnect.s1_sync $axi_regmap.sync
+    ad_connect $offload.cmd $interconnect.s0_cmd
+    ad_connect $interconnect.s0_sdi $offload.sdi_data
+    ad_connect $offload.sdo_data $interconnect.s0_sdo
+    ad_connect $interconnect.s0_sync $offload.sync
+    ad_connect $offload.m_interconnect_ctrl $interconnect.s_interconnect_ctrl
+    ad_connect $offload.ctrl_cmd_wr $axi_regmap.offload0_cmd
+    ad_connect $offload.ctrl_sdo_wr $axi_regmap.offload0_sdo
+    ad_connect $offload.if_ctrl_enable $axi_regmap.if_offload0_enable
+    ad_connect $offload.if_ctrl_enabled $axi_regmap.if_offload0_enabled
+    ad_connect $offload.if_ctrl_mem_reset $axi_regmap.if_offload0_mem_reset
+    ad_connect $offload.status_sync $axi_regmap.offload_sync
   }
-
-  if {$echo_sclk == 1} {
-    ad_connect echo_sclk $execution/echo_sclk
-  }
-
-  ad_connect $axi_regmap/spi_resetn $offload/spi_resetn
-  ad_connect $axi_regmap/spi_resetn $execution/resetn
-  ad_connect $axi_regmap/spi_resetn $interconnect/resetn
-
-  ad_connect resetn $axi_regmap/s_axi_aresetn
-  ad_connect irq $axi_regmap/irq
-
-  current_bd_instance /
-}
+}
\ No newline at end of file
diff --git a/library/spi_engine/spi_engine_execution/spi_engine_execution_hw.tcl b/library/spi_engine/spi_engine_execution/spi_engine_execution_hw.tcl
index f2d95966097..6efb3180050 100644
--- a/library/spi_engine/spi_engine_execution/spi_engine_execution_hw.tcl
+++ b/library/spi_engine/spi_engine_execution/spi_engine_execution_hw.tcl
@@ -20,8 +20,9 @@ ad_ip_parameter DEFAULT_SPI_CFG INTEGER 0
 ad_ip_parameter DEFAULT_CLK_DIV INTEGER 0
 ad_ip_parameter DATA_WIDTH INTEGER 8
 ad_ip_parameter NUM_OF_SDI INTEGER 1
-ad_ip_parameter SDI_DELAY INTEGER 0
 ad_ip_parameter SDO_DEFAULT INTEGER 0
+ad_ip_parameter ECHO_SCLK INTEGER 0
+ad_ip_parameter SDI_DELAY INTEGER 0
 
 proc p_elaboration {} {
 
diff --git a/projects/ad4052_ardz/common/ad4052_qsys.tcl b/projects/ad4052_ardz/common/ad4052_qsys.tcl
index 89e0f8c2c3d..353a68732e9 100644
--- a/projects/ad4052_ardz/common/ad4052_qsys.tcl
+++ b/projects/ad4052_ardz/common/ad4052_qsys.tcl
@@ -11,36 +11,6 @@ set_instance_parameter_value axi_dmac_0 {CYCLIC} {0}
 set_instance_parameter_value axi_dmac_0 {DMA_DATA_WIDTH_SRC} {32}
 set_instance_parameter_value axi_dmac_0 {DMA_DATA_WIDTH_DEST} {128}
 
-# axi_spi_engine
-
-add_instance axi_spi_engine_0 axi_spi_engine
-set_instance_parameter_value axi_spi_engine_0 {ASYNC_SPI_CLK} {1}
-set_instance_parameter_value axi_spi_engine_0 {DATA_WIDTH} {32}
-set_instance_parameter_value axi_spi_engine_0 {MM_IF_TYPE} {0}
-set_instance_parameter_value axi_spi_engine_0 {NUM_OF_SDI} {1}
-set_instance_parameter_value axi_spi_engine_0 {NUM_OFFLOAD} {1}
-
-# spi_engine_execution
-
-add_instance spi_engine_execution_0 spi_engine_execution
-set_instance_parameter_value spi_engine_execution_0 {DATA_WIDTH} {32}
-set_instance_parameter_value spi_engine_execution_0 {NUM_OF_SDI} {1}
-set_instance_parameter_value spi_engine_execution_0 {SDI_DELAY} {0}
-
-# spi_engine_interconnect
-
-add_instance spi_engine_interconnect_0 spi_engine_interconnect
-set_instance_parameter_value spi_engine_interconnect_0 {DATA_WIDTH} {32}
-set_instance_parameter_value spi_engine_interconnect_0 {NUM_OF_SDI} {1}
-
-# spi_engine_offload
-
-add_instance spi_engine_offload_0 spi_engine_offload
-set_instance_parameter_value spi_engine_offload_0 {ASYNC_TRIG} {1}
-set_instance_parameter_value spi_engine_offload_0 {ASYNC_SPI_CLK} {0}
-set_instance_parameter_value spi_engine_offload_0 {DATA_WIDTH} {32}
-set_instance_parameter_value spi_engine_offload_0 {NUM_OF_SDI} {1}
-
 # axi_pwm_gen
 
 add_instance pwm_trigger axi_pwm_gen
@@ -87,6 +57,26 @@ set_connection_parameter_value spi_clk_pll.reconfig_to_pll/spi_clk_pll_reconfig.
 set_connection_parameter_value spi_clk_pll.reconfig_to_pll/spi_clk_pll_reconfig.reconfig_to_pll startPortLSB {0}
 set_connection_parameter_value spi_clk_pll.reconfig_to_pll/spi_clk_pll_reconfig.reconfig_to_pll width {0}
 
+# spi engine
+source $ad_hdl_dir/library/spi_engine/scripts/spi_engine.tcl
+
+set spi_engine_hier spi_ad4052
+
+set data_width 32
+set async_spi_clk 1
+set num_cs 1
+set num_sdi 1
+set num_sdo 1
+set sdi_delay 0
+set echo_sclk 0
+set sdo_streaming 0
+
+set axi_clk sys_clk.clk
+set axi_reset sys_clk.clk_reset
+set spi_clk spi_clk_pll.outclk0
+
+spi_engine_create $spi_engine_hier $axi_clk $axi_reset $spi_clk $data_width $async_spi_clk $num_cs $num_sdi $num_sdo $sdi_delay $echo_sclk $sdo_streaming
+set_instance_parameter_value ${spi_engine_hier}_offload {ASYNC_TRIG} {1}
 # exported interface
 
 add_interface adc_spi_sclk    clock source
@@ -95,27 +85,21 @@ add_interface adc_spi_sdo     conduit end
 add_interface adc_spi_cs      conduit end
 add_interface adc_drdy        conduit end
 
-set_interface_property adc_spi_sclk     EXPORT_OF spi_engine_execution_0.if_sclk
-set_interface_property adc_spi_sdi      EXPORT_OF spi_engine_execution_0.if_sdi
-set_interface_property adc_spi_sdo      EXPORT_OF spi_engine_execution_0.if_sdo
-set_interface_property adc_spi_cs       EXPORT_OF spi_engine_execution_0.if_cs
-set_interface_property adc_drdy_trigger EXPORT_OF spi_engine_offload_0.if_trigger
+set_interface_property adc_spi_sclk     EXPORT_OF ${spi_engine_hier}_execution.if_sclk
+set_interface_property adc_spi_sdi      EXPORT_OF ${spi_engine_hier}_execution.if_sdi
+set_interface_property adc_spi_sdo      EXPORT_OF ${spi_engine_hier}_execution.if_sdo
+set_interface_property adc_spi_cs       EXPORT_OF ${spi_engine_hier}_execution.if_cs
+set_interface_property adc_drdy_trigger EXPORT_OF ${spi_engine_hier}_offload.if_trigger
 set_interface_property adc_cnv          EXPORT_OF pwm_trigger.if_pwm_0
 
 # clocks
 
 add_connection sys_clk.clk spi_clk_pll.refclk
 add_connection sys_clk.clk spi_clk_pll_reconfig.mgmt_clk
-add_connection sys_clk.clk axi_spi_engine_0.s_axi_clock
 add_connection sys_clk.clk axi_dmac_0.s_axi_clock
 add_connection sys_clk.clk pwm_trigger.s_axi_clock
 
 add_connection spi_clk_pll.outclk0 pwm_trigger.if_ext_clk
-add_connection spi_clk_pll.outclk0 spi_engine_execution_0.if_clk
-add_connection spi_clk_pll.outclk0 spi_engine_interconnect_0.if_clk
-add_connection spi_clk_pll.outclk0 axi_spi_engine_0.if_spi_clk
-add_connection spi_clk_pll.outclk0 spi_engine_offload_0.if_ctrl_clk
-add_connection spi_clk_pll.outclk0 spi_engine_offload_0.if_spi_clk
 add_connection spi_clk_pll.outclk0 axi_dmac_0.if_s_axis_aclk
 
 add_connection sys_dma_clk.clk axi_dmac_0.m_dest_axi_clock
@@ -124,47 +108,19 @@ add_connection sys_dma_clk.clk axi_dmac_0.m_dest_axi_clock
 
 add_connection sys_clk.clk_reset spi_clk_pll.reset
 add_connection sys_clk.clk_reset spi_clk_pll_reconfig.mgmt_reset
-add_connection sys_clk.clk_reset axi_spi_engine_0.s_axi_reset
 add_connection sys_clk.clk_reset axi_dmac_0.s_axi_reset
 add_connection sys_clk.clk_reset pwm_trigger.s_axi_reset
 
-add_connection axi_spi_engine_0.if_spi_resetn spi_engine_execution_0.if_resetn
-add_connection axi_spi_engine_0.if_spi_resetn spi_engine_interconnect_0.if_resetn
-add_connection axi_spi_engine_0.if_spi_resetn spi_engine_offload_0.if_spi_resetn
-
 add_connection sys_dma_clk.clk_reset axi_dmac_0.m_dest_axi_reset
 
 # interfaces
 
-add_connection spi_engine_interconnect_0.m_cmd spi_engine_execution_0.cmd
-add_connection spi_engine_execution_0.sdi_data spi_engine_interconnect_0.m_sdi
-add_connection spi_engine_interconnect_0.m_sdo spi_engine_execution_0.sdo_data
-add_connection spi_engine_execution_0.sync spi_engine_interconnect_0.m_sync
-
-add_connection axi_spi_engine_0.cmd spi_engine_interconnect_0.s1_cmd
-add_connection spi_engine_interconnect_0.s1_sdi axi_spi_engine_0.sdi_data
-add_connection axi_spi_engine_0.sdo_data spi_engine_interconnect_0.s1_sdo
-add_connection spi_engine_interconnect_0.s1_sync axi_spi_engine_0.sync
-
-add_connection spi_engine_offload_0.cmd spi_engine_interconnect_0.s0_cmd
-add_connection spi_engine_interconnect_0.s0_sdi spi_engine_offload_0.sdi_data
-add_connection spi_engine_offload_0.sdo_data spi_engine_interconnect_0.s0_sdo
-add_connection spi_engine_interconnect_0.s0_sync spi_engine_offload_0.sync
-add_connection spi_engine_offload_0.m_interconnect_ctrl spi_engine_interconnect_0.s_interconnect_ctrl
-
-add_connection spi_engine_offload_0.ctrl_cmd_wr       axi_spi_engine_0.offload0_cmd
-add_connection spi_engine_offload_0.ctrl_sdo_wr       axi_spi_engine_0.offload0_sdo
-add_connection spi_engine_offload_0.if_ctrl_enable    axi_spi_engine_0.if_offload0_enable
-add_connection spi_engine_offload_0.if_ctrl_enabled   axi_spi_engine_0.if_offload0_enabled
-add_connection spi_engine_offload_0.if_ctrl_mem_reset axi_spi_engine_0.if_offload0_mem_reset
-add_connection spi_engine_offload_0.status_sync       axi_spi_engine_0.offload_sync
-
-add_connection spi_engine_offload_0.offload_sdi axi_dmac_0.s_axis
+add_connection ${spi_engine_hier}_offload.offload_sdi axi_dmac_0.s_axis
 
 # cpu interconnects
 
 ad_cpu_interconnect 0x00020000 axi_dmac_0.s_axi
-ad_cpu_interconnect 0x00030000 axi_spi_engine_0.s_axi
+ad_cpu_interconnect 0x00030000 ${spi_engine_hier}_axi_regmap.s_axi
 ad_cpu_interconnect 0x00040000 pwm_trigger.s_axi
 ad_cpu_interconnect 0x00050000 spi_clk_pll_reconfig.mgmt_avalon_slave
 
@@ -175,4 +131,4 @@ ad_dma_interconnect axi_dmac_0.m_dest_axi
 #interrupts
 
 ad_cpu_interrupt 4 axi_dmac_0.interrupt_sender
-ad_cpu_interrupt 5 axi_spi_engine_0.interrupt_sender
+ad_cpu_interrupt 5 ${spi_engine_hier}_axi_regmap.interrupt_sender
diff --git a/projects/ad411x_ad717x/common/ad411x_ad717x_asdz_qsys.tcl b/projects/ad411x_ad717x/common/ad411x_ad717x_asdz_qsys.tcl
index 2dea096fd42..dc60a0b0b23 100644
--- a/projects/ad411x_ad717x/common/ad411x_ad717x_asdz_qsys.tcl
+++ b/projects/ad411x_ad717x/common/ad411x_ad717x_asdz_qsys.tcl
@@ -12,40 +12,31 @@ set_instance_parameter_value axi_dmac_0 {CYCLIC} {0}
 set_instance_parameter_value axi_dmac_0 {DMA_DATA_WIDTH_SRC} {32}
 set_instance_parameter_value axi_dmac_0 {DMA_DATA_WIDTH_DEST} {128}
 
-# axi_spi_engine
-
-add_instance axi_spi_engine_0 axi_spi_engine
-set_instance_parameter_value axi_spi_engine_0 {ASYNC_SPI_CLK} {1}
-set_instance_parameter_value axi_spi_engine_0 {DATA_WIDTH}    {32}
-set_instance_parameter_value axi_spi_engine_0 {MM_IF_TYPE}    {0}
-set_instance_parameter_value axi_spi_engine_0 {NUM_OF_SDI}    {1}
-set_instance_parameter_value axi_spi_engine_0 {NUM_OFFLOAD}   {1}
-
-# spi_engine_execution
+# util_sigma_delta_spi
 
-add_instance spi_engine_execution_0 spi_engine_execution
-set_instance_parameter_value spi_engine_execution_0 {DATA_WIDTH} {32}
-set_instance_parameter_value spi_engine_execution_0 {NUM_OF_SDI} {1}
-set_instance_parameter_value spi_engine_execution_0 {SDI_DELAY} {0}
+add_instance util_sigma_delta_spi util_sigma_delta_spi
+set_instance_parameter_value util_sigma_delta_spi {NUM_OF_CS} {1}
 
-# spi_engine_interconnect
+# spi engine
+source $ad_hdl_dir/library/spi_engine/scripts/spi_engine.tcl
 
-add_instance spi_engine_interconnect_0 spi_engine_interconnect
-set_instance_parameter_value spi_engine_interconnect_0 {DATA_WIDTH} {32}
-set_instance_parameter_value spi_engine_interconnect_0 {NUM_OF_SDI} {1}
+set spi_engine_hier spi_ad411x_ad717x
 
-# spi_engine_offload
+set data_width 32
+set async_spi_clk 1
+set num_cs 1
+set num_sdi 1
+set num_sdo 1
+set sdi_delay 0
+set echo_sclk 0
+set sdo_streaming 0
 
-add_instance spi_engine_offload_0 spi_engine_offload
-set_instance_parameter_value spi_engine_offload_0 {ASYNC_TRIG}    {1}
-set_instance_parameter_value spi_engine_offload_0 {ASYNC_SPI_CLK} {0}
-set_instance_parameter_value spi_engine_offload_0 {DATA_WIDTH}    {32}
-set_instance_parameter_value spi_engine_offload_0 {NUM_OF_SDI}    {1}
+set axi_clk sys_clk.clk
+set axi_reset sys_clk.clk_reset
+set spi_clk sys_dma_clk.clk
 
-# util_sigma_delta_spi
-
-add_instance util_sigma_delta_spi util_sigma_delta_spi
-set_instance_parameter_value util_sigma_delta_spi {NUM_OF_CS} {1}
+spi_engine_create $spi_engine_hier $axi_clk $axi_reset $spi_clk $data_width $async_spi_clk $num_cs $num_sdi $num_sdo $sdi_delay $echo_sclk $sdo_streaming
+set_instance_parameter_value ${spi_engine_hier}_offload {ASYNC_TRIG}    {1}
 
 # exported interface
 
@@ -64,73 +55,37 @@ set_interface_property ad411x_spi_trigger EXPORT_OF util_sigma_delta_spi.if_data
 
 # clocks
 
-add_connection sys_clk.clk axi_spi_engine_0.s_axi_clock
 add_connection sys_clk.clk axi_dmac_0.s_axi_clock
 
+add_connection sys_dma_clk.clk axi_dmac_0.if_s_axis_aclk
+add_connection sys_dma_clk.clk axi_dmac_0.m_dest_axi_clock
+
 # util_sigma_delta_connection
 
 add_connection sys_dma_clk.clk util_sigma_delta_spi.if_clk
 add_connection sys_clk.clk_reset util_sigma_delta_spi.if_resetn
 
-add_connection spi_engine_execution_0.if_cs util_sigma_delta_spi.if_s_cs
-add_connection spi_engine_execution_0.if_sclk util_sigma_delta_spi.if_s_sclk
-add_connection spi_engine_execution_0.if_sdi util_sigma_delta_spi.if_s_sdi
-add_connection spi_engine_execution_0.if_sdo util_sigma_delta_spi.if_s_sdo
-add_connection spi_engine_execution_0.if_sdo_t util_sigma_delta_spi.if_s_sdo_t
-add_connection spi_engine_offload_0.if_trigger util_sigma_delta_spi.if_data_ready
-
-# add_connection axi_spi_engine_0.
-
-add_connection sys_dma_clk.clk spi_engine_execution_0.if_clk
-add_connection sys_dma_clk.clk spi_engine_interconnect_0.if_clk
-add_connection sys_dma_clk.clk axi_spi_engine_0.if_spi_clk
-add_connection sys_dma_clk.clk spi_engine_offload_0.if_ctrl_clk
-add_connection sys_dma_clk.clk spi_engine_offload_0.if_spi_clk
-add_connection sys_dma_clk.clk axi_dmac_0.if_s_axis_aclk
-add_connection sys_dma_clk.clk axi_dmac_0.m_dest_axi_clock
+add_connection ${spi_engine_hier}_execution.if_cs util_sigma_delta_spi.if_s_cs
+add_connection ${spi_engine_hier}_execution.if_sclk util_sigma_delta_spi.if_s_sclk
+add_connection ${spi_engine_hier}_execution.if_sdi util_sigma_delta_spi.if_s_sdi
+add_connection ${spi_engine_hier}_execution.if_sdo util_sigma_delta_spi.if_s_sdo
+add_connection ${spi_engine_hier}_execution.if_sdo_t util_sigma_delta_spi.if_s_sdo_t
+add_connection ${spi_engine_hier}_offload.if_trigger util_sigma_delta_spi.if_data_ready
 
 # resets
 
-add_connection sys_clk.clk_reset axi_spi_engine_0.s_axi_reset
 add_connection sys_clk.clk_reset axi_dmac_0.s_axi_reset
 
-add_connection axi_spi_engine_0.if_spi_resetn spi_engine_execution_0.if_resetn
-add_connection axi_spi_engine_0.if_spi_resetn spi_engine_interconnect_0.if_resetn
-add_connection axi_spi_engine_0.if_spi_resetn spi_engine_offload_0.if_spi_resetn
-
 add_connection sys_dma_clk.clk_reset axi_dmac_0.m_dest_axi_reset
 
 # interfaces
 
-add_connection spi_engine_interconnect_0.m_cmd spi_engine_execution_0.cmd
-add_connection spi_engine_execution_0.sdi_data spi_engine_interconnect_0.m_sdi
-add_connection spi_engine_interconnect_0.m_sdo spi_engine_execution_0.sdo_data
-add_connection spi_engine_execution_0.sync spi_engine_interconnect_0.m_sync
-
-add_connection axi_spi_engine_0.cmd spi_engine_interconnect_0.s1_cmd
-add_connection spi_engine_interconnect_0.s1_sdi axi_spi_engine_0.sdi_data
-add_connection axi_spi_engine_0.sdo_data spi_engine_interconnect_0.s1_sdo
-add_connection spi_engine_interconnect_0.s1_sync axi_spi_engine_0.sync
-add_connection spi_engine_offload_0.m_interconnect_ctrl spi_engine_interconnect_0.s_interconnect_ctrl
-
-add_connection spi_engine_offload_0.cmd spi_engine_interconnect_0.s0_cmd
-add_connection spi_engine_interconnect_0.s0_sdi  spi_engine_offload_0.sdi_data
-add_connection spi_engine_offload_0.sdo_data spi_engine_interconnect_0.s0_sdo
-add_connection spi_engine_interconnect_0.s0_sync spi_engine_offload_0.sync
-
-add_connection spi_engine_offload_0.ctrl_cmd_wr       axi_spi_engine_0.offload0_cmd
-add_connection spi_engine_offload_0.ctrl_sdo_wr       axi_spi_engine_0.offload0_sdo
-add_connection spi_engine_offload_0.if_ctrl_enable    axi_spi_engine_0.if_offload0_enable
-add_connection spi_engine_offload_0.if_ctrl_enabled   axi_spi_engine_0.if_offload0_enabled
-add_connection spi_engine_offload_0.if_ctrl_mem_reset axi_spi_engine_0.if_offload0_mem_reset
-add_connection spi_engine_offload_0.status_sync       axi_spi_engine_0.offload_sync
-
-add_connection spi_engine_offload_0.offload_sdi axi_dmac_0.s_axis
+add_connection ${spi_engine_hier}_offload.offload_sdi axi_dmac_0.s_axis
 
 # cpu interconnects
 
 ad_cpu_interconnect 0x00020000 axi_dmac_0.s_axi
-ad_cpu_interconnect 0x00030000 axi_spi_engine_0.s_axi
+ad_cpu_interconnect 0x00030000 ${spi_engine_hier}_axi_regmap.s_axi
 
 # dma interconnect
 ad_dma_interconnect axi_dmac_0.m_dest_axi
@@ -138,4 +93,4 @@ ad_dma_interconnect axi_dmac_0.m_dest_axi
 # interrupts
 
 ad_cpu_interrupt 4 axi_dmac_0.interrupt_sender
-ad_cpu_interrupt 5 axi_spi_engine_0.interrupt_sender
+ad_cpu_interrupt 5 ${spi_engine_hier}_axi_regmap.interrupt_sender
diff --git a/projects/ad4170_asdz/common/ad4170_asdz_qsys.tcl b/projects/ad4170_asdz/common/ad4170_asdz_qsys.tcl
index 666404987a2..a7a44e79d35 100644
--- a/projects/ad4170_asdz/common/ad4170_asdz_qsys.tcl
+++ b/projects/ad4170_asdz/common/ad4170_asdz_qsys.tcl
@@ -13,35 +13,26 @@ set_instance_parameter_value axi_dmac_0 {CYCLIC} {0}
 set_instance_parameter_value axi_dmac_0 {DMA_DATA_WIDTH_SRC} {32}
 set_instance_parameter_value axi_dmac_0 {DMA_DATA_WIDTH_DEST} {64}
 
-# axi_spi_engine
+# spi engine
+source $ad_hdl_dir/library/spi_engine/scripts/spi_engine.tcl
 
-add_instance axi_spi_engine_0 axi_spi_engine
-set_instance_parameter_value axi_spi_engine_0 {ASYNC_SPI_CLK} {1}
-set_instance_parameter_value axi_spi_engine_0 {DATA_WIDTH}    {32}
-set_instance_parameter_value axi_spi_engine_0 {MM_IF_TYPE}    {0}
-set_instance_parameter_value axi_spi_engine_0 {NUM_OF_SDI}    {1}
-set_instance_parameter_value axi_spi_engine_0 {NUM_OFFLOAD}   {1}
+set spi_engine_hier spi_ad4170
 
-# spi_engine_execution
+set data_width 32
+set async_spi_clk 1
+set num_cs 1
+set num_sdi 1
+set num_sdo 1
+set sdi_delay 0
+set echo_sclk 0
+set sdo_streaming 0
 
-add_instance spi_engine_execution_0 spi_engine_execution
-set_instance_parameter_value spi_engine_execution_0 {DATA_WIDTH} {32}
-set_instance_parameter_value spi_engine_execution_0 {NUM_OF_SDI} {1}
-set_instance_parameter_value spi_engine_execution_0 {SDI_DELAY} {0}
+set axi_clk sys_clk.clk
+set axi_reset sys_clk.clk_reset
+set spi_clk sys_dma_clk.clk
 
-# spi_engine_interconnect
-
-add_instance spi_engine_interconnect_0 spi_engine_interconnect
-set_instance_parameter_value spi_engine_interconnect_0 {DATA_WIDTH} {32}
-set_instance_parameter_value spi_engine_interconnect_0 {NUM_OF_SDI} {1}
-
-# spi_engine_offload
-
-add_instance spi_engine_offload_0 spi_engine_offload
-set_instance_parameter_value spi_engine_offload_0 {ASYNC_TRIG}    {1}
-set_instance_parameter_value spi_engine_offload_0 {ASYNC_SPI_CLK} {0}
-set_instance_parameter_value spi_engine_offload_0 {DATA_WIDTH}    {32}
-set_instance_parameter_value spi_engine_offload_0 {NUM_OF_SDI}    {1}
+spi_engine_create $spi_engine_hier $axi_clk $axi_reset $spi_clk $data_width $async_spi_clk $num_cs $num_sdi $num_sdo $sdi_delay $echo_sclk $sdo_streaming
+set_instance_parameter_value ${spi_engine_hier}_offload {ASYNC_TRIG} {1}
 
 # exported interface
 
@@ -51,67 +42,32 @@ add_interface ad4170_spi_sdi        conduit end
 add_interface ad4170_spi_sdo        conduit end
 add_interface ad4170_spi_trigger    conduit end
 
-set_interface_property ad4170_spi_cs      EXPORT_OF spi_engine_execution_0.if_cs
-set_interface_property ad4170_spi_sclk    EXPORT_OF spi_engine_execution_0.if_sclk
-set_interface_property ad4170_spi_sdi     EXPORT_OF spi_engine_execution_0.if_sdi
-set_interface_property ad4170_spi_sdo     EXPORT_OF spi_engine_execution_0.if_sdo
-set_interface_property ad4170_spi_trigger EXPORT_OF spi_engine_offload_0.if_trigger
+set_interface_property ad4170_spi_cs      EXPORT_OF ${spi_engine_hier}_execution.if_cs
+set_interface_property ad4170_spi_sclk    EXPORT_OF ${spi_engine_hier}_execution.if_sclk
+set_interface_property ad4170_spi_sdi     EXPORT_OF ${spi_engine_hier}_execution.if_sdi
+set_interface_property ad4170_spi_sdo     EXPORT_OF ${spi_engine_hier}_execution.if_sdo
+set_interface_property ad4170_spi_trigger EXPORT_OF ${spi_engine_hier}_offload.if_trigger
 
 # clocks
 
-add_connection sys_clk.clk axi_spi_engine_0.s_axi_clock
 add_connection sys_clk.clk axi_dmac_0.s_axi_clock
 
-add_connection sys_dma_clk.clk spi_engine_execution_0.if_clk
-add_connection sys_dma_clk.clk spi_engine_interconnect_0.if_clk
-add_connection sys_dma_clk.clk axi_spi_engine_0.if_spi_clk
-add_connection sys_dma_clk.clk spi_engine_offload_0.if_ctrl_clk
-add_connection sys_dma_clk.clk spi_engine_offload_0.if_spi_clk
 add_connection sys_dma_clk.clk axi_dmac_0.if_s_axis_aclk
 add_connection sys_dma_clk.clk axi_dmac_0.m_dest_axi_clock
 
 # resets
 
-add_connection sys_clk.clk_reset axi_spi_engine_0.s_axi_reset
 add_connection sys_clk.clk_reset axi_dmac_0.s_axi_reset
 
-add_connection axi_spi_engine_0.if_spi_resetn spi_engine_execution_0.if_resetn
-add_connection axi_spi_engine_0.if_spi_resetn spi_engine_interconnect_0.if_resetn
-add_connection axi_spi_engine_0.if_spi_resetn spi_engine_offload_0.if_spi_resetn
-
 add_connection sys_dma_clk.clk_reset axi_dmac_0.m_dest_axi_reset
 
 # interfaces
-
-add_connection spi_engine_interconnect_0.m_cmd spi_engine_execution_0.cmd
-add_connection spi_engine_execution_0.sdi_data spi_engine_interconnect_0.m_sdi
-add_connection spi_engine_interconnect_0.m_sdo spi_engine_execution_0.sdo_data
-add_connection spi_engine_execution_0.sync spi_engine_interconnect_0.m_sync
-
-add_connection axi_spi_engine_0.cmd spi_engine_interconnect_0.s1_cmd
-add_connection spi_engine_interconnect_0.s1_sdi axi_spi_engine_0.sdi_data
-add_connection axi_spi_engine_0.sdo_data spi_engine_interconnect_0.s1_sdo
-add_connection spi_engine_interconnect_0.s1_sync axi_spi_engine_0.sync
-
-add_connection spi_engine_offload_0.cmd spi_engine_interconnect_0.s0_cmd
-add_connection spi_engine_interconnect_0.s0_sdi  spi_engine_offload_0.sdi_data
-add_connection spi_engine_offload_0.sdo_data spi_engine_interconnect_0.s0_sdo
-add_connection spi_engine_interconnect_0.s0_sync spi_engine_offload_0.sync
-add_connection spi_engine_offload_0.m_interconnect_ctrl spi_engine_interconnect_0.s_interconnect_ctrl
-
-add_connection spi_engine_offload_0.ctrl_cmd_wr       axi_spi_engine_0.offload0_cmd
-add_connection spi_engine_offload_0.ctrl_sdo_wr       axi_spi_engine_0.offload0_sdo
-add_connection spi_engine_offload_0.if_ctrl_enable    axi_spi_engine_0.if_offload0_enable
-add_connection spi_engine_offload_0.if_ctrl_enabled   axi_spi_engine_0.if_offload0_enabled
-add_connection spi_engine_offload_0.if_ctrl_mem_reset axi_spi_engine_0.if_offload0_mem_reset
-add_connection spi_engine_offload_0.status_sync       axi_spi_engine_0.offload_sync
-
-add_connection spi_engine_offload_0.offload_sdi axi_dmac_0.s_axis
+add_connection ${spi_engine_hier}_offload.offload_sdi axi_dmac_0.s_axis
 
 # cpu interconnects
 
 ad_cpu_interconnect 0x00020000 axi_dmac_0.s_axi
-ad_cpu_interconnect 0x00030000 axi_spi_engine_0.s_axi
+ad_cpu_interconnect 0x00030000 ${spi_engine_hier}_axi_regmap.s_axi
 
 # dma interconnect
 ad_dma_interconnect axi_dmac_0.m_dest_axi
@@ -119,4 +75,4 @@ ad_dma_interconnect axi_dmac_0.m_dest_axi
 #interrupts
 
 ad_cpu_interrupt 4 axi_dmac_0.interrupt_sender
-ad_cpu_interrupt 5 axi_spi_engine_0.interrupt_sender
+ad_cpu_interrupt 5 ${spi_engine_hier}_axi_regmap.interrupt_sender
diff --git a/projects/ad469x_evb/common/ad469x_qsys.tcl b/projects/ad469x_evb/common/ad469x_qsys.tcl
index 1d70a7c328c..162c090f82b 100644
--- a/projects/ad469x_evb/common/ad469x_qsys.tcl
+++ b/projects/ad469x_evb/common/ad469x_qsys.tcl
@@ -13,36 +13,6 @@ set_instance_parameter_value axi_dmac_0 {CYCLIC} {0}
 set_instance_parameter_value axi_dmac_0 {DMA_DATA_WIDTH_SRC} {32}
 set_instance_parameter_value axi_dmac_0 {DMA_DATA_WIDTH_DEST} {64}
 
-# axi_spi_engine
-
-add_instance axi_spi_engine_0 axi_spi_engine
-set_instance_parameter_value axi_spi_engine_0 {ASYNC_SPI_CLK} {1}
-set_instance_parameter_value axi_spi_engine_0 {DATA_WIDTH}    {32}
-set_instance_parameter_value axi_spi_engine_0 {MM_IF_TYPE}    {0}
-set_instance_parameter_value axi_spi_engine_0 {NUM_OF_SDI}    {1}
-set_instance_parameter_value axi_spi_engine_0 {NUM_OFFLOAD}   {1}
-
-# spi_engine_execution
-
-add_instance spi_engine_execution_0 spi_engine_execution
-set_instance_parameter_value spi_engine_execution_0 {DATA_WIDTH} {32}
-set_instance_parameter_value spi_engine_execution_0 {NUM_OF_SDI} {1}
-set_instance_parameter_value spi_engine_execution_0 {SDI_DELAY} {0}
-
-# spi_engine_interconnect
-
-add_instance spi_engine_interconnect_0 spi_engine_interconnect
-set_instance_parameter_value spi_engine_interconnect_0 {DATA_WIDTH} {32}
-set_instance_parameter_value spi_engine_interconnect_0 {NUM_OF_SDI} {1}
-
-# spi_engine_offload
-
-add_instance spi_engine_offload_0 spi_engine_offload
-set_instance_parameter_value spi_engine_offload_0 {ASYNC_TRIG}    {1}
-set_instance_parameter_value spi_engine_offload_0 {ASYNC_SPI_CLK} {0}
-set_instance_parameter_value spi_engine_offload_0 {DATA_WIDTH}    {32}
-set_instance_parameter_value spi_engine_offload_0 {NUM_OF_SDI}    {1}
-
 # axi pwm gen
 
 add_instance ad469x_trigger_gen axi_pwm_gen
@@ -90,6 +60,26 @@ set_connection_parameter_value spi_clk_pll.reconfig_to_pll/spi_clk_pll_reconfig.
 set_connection_parameter_value spi_clk_pll.reconfig_to_pll/spi_clk_pll_reconfig.reconfig_to_pll startPortLSB {0}
 set_connection_parameter_value spi_clk_pll.reconfig_to_pll/spi_clk_pll_reconfig.reconfig_to_pll width {0}
 
+# spi engine
+source $ad_hdl_dir/library/spi_engine/scripts/spi_engine.tcl
+
+set spi_engine_hier ad469x_spi
+
+set data_width 32
+set async_spi_clk 1
+set num_cs 1
+set num_sdi 1
+set num_sdo 1
+set sdi_delay 0
+set echo_sclk 0
+set sdo_streaming 0
+
+set axi_clk sys_clk.clk
+set axi_reset sys_clk.clk_reset
+set spi_clk spi_clk_pll.outclk0
+
+spi_engine_create $spi_engine_hier $axi_clk $axi_reset $spi_clk $data_width $async_spi_clk $num_cs $num_sdi $num_sdo $sdi_delay $echo_sclk $sdo_streaming
+set_instance_parameter_value ${spi_engine_hier}_offload {ASYNC_TRIG} {1}
 
 # exported interface
 
@@ -100,11 +90,11 @@ add_interface ad469x_spi_sdo        conduit end
 add_interface ad469x_spi_trigger    conduit end
 add_interface ad469x_spi_cnv        conduit end
 
-set_interface_property ad469x_spi_cs      EXPORT_OF spi_engine_execution_0.if_cs
-set_interface_property ad469x_spi_sclk    EXPORT_OF spi_engine_execution_0.if_sclk
-set_interface_property ad469x_spi_sdi     EXPORT_OF spi_engine_execution_0.if_sdi
-set_interface_property ad469x_spi_sdo     EXPORT_OF spi_engine_execution_0.if_sdo
-set_interface_property ad469x_spi_trigger EXPORT_OF spi_engine_offload_0.if_trigger
+set_interface_property ad469x_spi_cs      EXPORT_OF ${spi_engine_hier}_execution.if_cs
+set_interface_property ad469x_spi_sclk    EXPORT_OF ${spi_engine_hier}_execution.if_sclk
+set_interface_property ad469x_spi_sdi     EXPORT_OF ${spi_engine_hier}_execution.if_sdi
+set_interface_property ad469x_spi_sdo     EXPORT_OF ${spi_engine_hier}_execution.if_sdo
+set_interface_property ad469x_spi_trigger EXPORT_OF ${spi_engine_hier}_offload.if_trigger
 set_interface_property ad469x_spi_cnv     EXPORT_OF ad469x_trigger_gen.if_pwm_0
 
 # clocks
@@ -112,15 +102,9 @@ set_interface_property ad469x_spi_cnv     EXPORT_OF ad469x_trigger_gen.if_pwm_0
 add_connection sys_clk.clk spi_clk_pll.refclk
 add_connection sys_clk.clk spi_clk_pll_reconfig.mgmt_clk
 add_connection sys_clk.clk ad469x_trigger_gen.s_axi_clock
-add_connection sys_clk.clk axi_spi_engine_0.s_axi_clock
 add_connection sys_clk.clk axi_dmac_0.s_axi_clock
 
 add_connection spi_clk_pll.outclk0 ad469x_trigger_gen.if_ext_clk
-add_connection spi_clk_pll.outclk0 spi_engine_execution_0.if_clk
-add_connection spi_clk_pll.outclk0 spi_engine_interconnect_0.if_clk
-add_connection spi_clk_pll.outclk0 axi_spi_engine_0.if_spi_clk
-add_connection spi_clk_pll.outclk0 spi_engine_offload_0.if_ctrl_clk
-add_connection spi_clk_pll.outclk0 spi_engine_offload_0.if_spi_clk
 add_connection spi_clk_pll.outclk0 axi_dmac_0.if_s_axis_aclk
 
 add_connection sys_dma_clk.clk axi_dmac_0.m_dest_axi_clock
@@ -129,42 +113,14 @@ add_connection sys_dma_clk.clk axi_dmac_0.m_dest_axi_clock
 
 add_connection sys_clk.clk_reset spi_clk_pll.reset
 add_connection sys_clk.clk_reset spi_clk_pll_reconfig.mgmt_reset
-add_connection sys_clk.clk_reset axi_spi_engine_0.s_axi_reset
 add_connection sys_clk.clk_reset axi_dmac_0.s_axi_reset
 add_connection sys_clk.clk_reset ad469x_trigger_gen.s_axi_reset
 
-add_connection axi_spi_engine_0.if_spi_resetn spi_engine_execution_0.if_resetn
-add_connection axi_spi_engine_0.if_spi_resetn spi_engine_interconnect_0.if_resetn
-add_connection axi_spi_engine_0.if_spi_resetn spi_engine_offload_0.if_spi_resetn
-
 add_connection sys_dma_clk.clk_reset axi_dmac_0.m_dest_axi_reset
 
 # interfaces
 
-add_connection spi_engine_interconnect_0.m_cmd spi_engine_execution_0.cmd
-add_connection spi_engine_execution_0.sdi_data spi_engine_interconnect_0.m_sdi
-add_connection spi_engine_interconnect_0.m_sdo spi_engine_execution_0.sdo_data
-add_connection spi_engine_execution_0.sync spi_engine_interconnect_0.m_sync
-
-add_connection axi_spi_engine_0.cmd spi_engine_interconnect_0.s1_cmd
-add_connection spi_engine_interconnect_0.s1_sdi axi_spi_engine_0.sdi_data
-add_connection axi_spi_engine_0.sdo_data spi_engine_interconnect_0.s1_sdo
-add_connection spi_engine_interconnect_0.s1_sync axi_spi_engine_0.sync
-
-add_connection spi_engine_offload_0.cmd spi_engine_interconnect_0.s0_cmd
-add_connection spi_engine_interconnect_0.s0_sdi  spi_engine_offload_0.sdi_data
-add_connection spi_engine_offload_0.sdo_data spi_engine_interconnect_0.s0_sdo
-add_connection spi_engine_interconnect_0.s0_sync spi_engine_offload_0.sync
-add_connection spi_engine_offload_0.m_interconnect_ctrl spi_engine_interconnect_0.s_interconnect_ctrl
-
-add_connection spi_engine_offload_0.ctrl_cmd_wr       axi_spi_engine_0.offload0_cmd
-add_connection spi_engine_offload_0.ctrl_sdo_wr       axi_spi_engine_0.offload0_sdo
-add_connection spi_engine_offload_0.if_ctrl_enable    axi_spi_engine_0.if_offload0_enable
-add_connection spi_engine_offload_0.if_ctrl_enabled   axi_spi_engine_0.if_offload0_enabled
-add_connection spi_engine_offload_0.if_ctrl_mem_reset axi_spi_engine_0.if_offload0_mem_reset
-add_connection spi_engine_offload_0.status_sync       axi_spi_engine_0.offload_sync
-
-add_connection spi_engine_offload_0.offload_sdi axi_dmac_0.s_axis
+add_connection ${spi_engine_hier}_offload.offload_sdi axi_dmac_0.s_axis
 
 add_interface dma_xfer_req conduit end
 
@@ -173,7 +129,7 @@ set_interface_property dma_xfer_req EXPORT_OF axi_dmac_0.if_s_axis_xfer_req
 # cpu interconnects
 
 ad_cpu_interconnect 0x00020000 axi_dmac_0.s_axi
-ad_cpu_interconnect 0x00030000 axi_spi_engine_0.s_axi
+ad_cpu_interconnect 0x00030000 ${spi_engine_hier}_axi_regmap.s_axi
 ad_cpu_interconnect 0x00040000 ad469x_trigger_gen.s_axi
 
 # dma interconnect
@@ -183,4 +139,4 @@ ad_dma_interconnect axi_dmac_0.m_dest_axi
 #interrupts
 
 ad_cpu_interrupt 4 axi_dmac_0.interrupt_sender
-ad_cpu_interrupt 5 axi_spi_engine_0.interrupt_sender
+ad_cpu_interrupt 5 ${spi_engine_hier}_axi_regmap.interrupt_sender
\ No newline at end of file
diff --git a/projects/ad57xx_ardz/common/ad57xx_ardz_qsys.tcl b/projects/ad57xx_ardz/common/ad57xx_ardz_qsys.tcl
index 170d5c9e0a1..d8bbdddcd3e 100644
--- a/projects/ad57xx_ardz/common/ad57xx_ardz_qsys.tcl
+++ b/projects/ad57xx_ardz/common/ad57xx_ardz_qsys.tcl
@@ -12,37 +12,6 @@ set_instance_parameter_value ad57xx_dma {CYCLIC} {0}
 set_instance_parameter_value ad57xx_dma {DMA_DATA_WIDTH_SRC} {128}
 set_instance_parameter_value ad57xx_dma {DMA_DATA_WIDTH_DEST} {32}
 
-# axi_spi_engine
-
-add_instance axi_spi_engine_0 axi_spi_engine
-set_instance_parameter_value axi_spi_engine_0 {ASYNC_SPI_CLK} {1}
-set_instance_parameter_value axi_spi_engine_0 {DATA_WIDTH}    {32}
-set_instance_parameter_value axi_spi_engine_0 {MM_IF_TYPE}    {0}
-set_instance_parameter_value axi_spi_engine_0 {NUM_OF_SDI}    {1}
-set_instance_parameter_value axi_spi_engine_0 {NUM_OFFLOAD}   {1}
-
-# spi_engine_execution
-
-add_instance spi_engine_execution_0 spi_engine_execution
-set_instance_parameter_value spi_engine_execution_0 {DATA_WIDTH} {32}
-set_instance_parameter_value spi_engine_execution_0 {NUM_OF_SDI} {1}
-set_instance_parameter_value spi_engine_execution_0 {SDI_DELAY} {0}
-
-# spi_engine_interconnect
-
-add_instance spi_engine_interconnect_0 spi_engine_interconnect
-set_instance_parameter_value spi_engine_interconnect_0 {DATA_WIDTH} {32}
-set_instance_parameter_value spi_engine_interconnect_0 {NUM_OF_SDI} {1}
-
-# spi_engine_offload
-
-add_instance spi_engine_offload_0 spi_engine_offload
-set_instance_parameter_value spi_engine_offload_0 {ASYNC_TRIG}    {1}
-set_instance_parameter_value spi_engine_offload_0 {ASYNC_SPI_CLK} {0}
-set_instance_parameter_value spi_engine_offload_0 {DATA_WIDTH}    {32}
-set_instance_parameter_value spi_engine_offload_0 {NUM_OF_SDI}    {1}
-set_instance_parameter_value spi_engine_offload_0 {SDO_STREAMING} {1}
-
 # axi pwm gen
 
 add_instance trig_gen axi_pwm_gen
@@ -90,6 +59,26 @@ set_connection_parameter_value spi_clk_pll.reconfig_to_pll/spi_clk_pll_reconfig.
 set_connection_parameter_value spi_clk_pll.reconfig_to_pll/spi_clk_pll_reconfig.reconfig_to_pll startPortLSB {0}
 set_connection_parameter_value spi_clk_pll.reconfig_to_pll/spi_clk_pll_reconfig.reconfig_to_pll width {0}
 
+# spi engine
+source $ad_hdl_dir/library/spi_engine/scripts/spi_engine.tcl
+
+set spi_engine_hier spi_ad57xx
+
+set data_width 32
+set async_spi_clk 1
+set num_cs 1
+set num_sdi 1
+set num_sdo 1
+set sdi_delay 0
+set echo_sclk 0
+set sdo_streaming 1
+
+set axi_clk sys_clk.clk
+set axi_reset sys_clk.clk_reset
+set spi_clk spi_clk_pll.outclk0
+
+spi_engine_create $spi_engine_hier $axi_clk $axi_reset $spi_clk $data_width $async_spi_clk $num_cs $num_sdi $num_sdo $sdi_delay $echo_sclk $sdo_streaming
+
 # exported interface
 
 add_interface ad57xx_spi_sclk    clock      source
@@ -98,27 +87,21 @@ add_interface ad57xx_spi_miso    conduit    end
 add_interface ad57xx_spi_mosi    conduit    end
 add_interface m_axis_offload_sdi axi4stream end
 
-set_interface_property ad57xx_spi_cs      EXPORT_OF spi_engine_execution_0.if_cs
-set_interface_property ad57xx_spi_sclk    EXPORT_OF spi_engine_execution_0.if_sclk
-set_interface_property ad57xx_spi_miso    EXPORT_OF spi_engine_execution_0.if_sdi
-set_interface_property ad57xx_spi_mosi    EXPORT_OF spi_engine_execution_0.if_sdo
-set_interface_property m_axis_offload_sdi EXPORT_OF spi_engine_offload_0.offload_sdi
+set_interface_property ad57xx_spi_cs      EXPORT_OF ${spi_engine_hier}_execution.if_cs
+set_interface_property ad57xx_spi_sclk    EXPORT_OF ${spi_engine_hier}_execution.if_sclk
+set_interface_property ad57xx_spi_miso    EXPORT_OF ${spi_engine_hier}_execution.if_sdi
+set_interface_property ad57xx_spi_mosi    EXPORT_OF ${spi_engine_hier}_execution.if_sdo
+set_interface_property m_axis_offload_sdi EXPORT_OF ${spi_engine_hier}_offload.offload_sdi
 
 # clocks
 
 add_connection sys_clk.clk spi_clk_pll.refclk
 add_connection sys_clk.clk spi_clk_pll_reconfig.mgmt_clk
 
-add_connection sys_clk.clk axi_spi_engine_0.s_axi_clock
 add_connection sys_clk.clk ad57xx_dma.s_axi_clock
 add_connection sys_clk.clk trig_gen.s_axi_clock
 
 add_connection spi_clk_pll.outclk0 trig_gen.if_ext_clk
-add_connection spi_clk_pll.outclk0 spi_engine_execution_0.if_clk
-add_connection spi_clk_pll.outclk0 spi_engine_interconnect_0.if_clk
-add_connection spi_clk_pll.outclk0 axi_spi_engine_0.if_spi_clk
-add_connection spi_clk_pll.outclk0 spi_engine_offload_0.if_ctrl_clk
-add_connection spi_clk_pll.outclk0 spi_engine_offload_0.if_spi_clk
 add_connection spi_clk_pll.outclk0 ad57xx_dma.if_m_axis_aclk
 add_connection sys_dma_clk.clk ad57xx_dma.m_src_axi_clock
 
@@ -126,48 +109,19 @@ add_connection sys_dma_clk.clk ad57xx_dma.m_src_axi_clock
 
 add_connection sys_clk.clk_reset spi_clk_pll.reset
 add_connection sys_clk.clk_reset spi_clk_pll_reconfig.mgmt_reset
-add_connection sys_clk.clk_reset axi_spi_engine_0.s_axi_reset
 add_connection sys_clk.clk_reset ad57xx_dma.s_axi_reset
 add_connection sys_clk.clk_reset trig_gen.s_axi_reset
 
-add_connection axi_spi_engine_0.if_spi_resetn spi_engine_execution_0.if_resetn
-add_connection axi_spi_engine_0.if_spi_resetn spi_engine_interconnect_0.if_resetn
-add_connection axi_spi_engine_0.if_spi_resetn spi_engine_offload_0.if_spi_resetn
-
 add_connection sys_dma_clk.clk_reset ad57xx_dma.m_src_axi_reset
 
 # interfaces
-
-add_connection spi_engine_interconnect_0.m_cmd spi_engine_execution_0.cmd
-add_connection spi_engine_execution_0.sdi_data spi_engine_interconnect_0.m_sdi
-add_connection  spi_engine_interconnect_0.m_sdo spi_engine_execution_0.sdo_data
-add_connection spi_engine_execution_0.sync spi_engine_interconnect_0.m_sync
-
-add_connection axi_spi_engine_0.cmd spi_engine_interconnect_0.s1_cmd
-add_connection spi_engine_interconnect_0.s1_sdi axi_spi_engine_0.sdi_data
-add_connection axi_spi_engine_0.sdo_data spi_engine_interconnect_0.s1_sdo
-add_connection spi_engine_interconnect_0.s1_sync axi_spi_engine_0.sync
-
-add_connection spi_engine_offload_0.cmd spi_engine_interconnect_0.s0_cmd
-add_connection spi_engine_interconnect_0.s0_sdi  spi_engine_offload_0.sdi_data
-add_connection spi_engine_offload_0.sdo_data spi_engine_interconnect_0.s0_sdo
-add_connection spi_engine_interconnect_0.s0_sync spi_engine_offload_0.sync
-add_connection spi_engine_offload_0.m_interconnect_ctrl spi_engine_interconnect_0.s_interconnect_ctrl
-
-add_connection spi_engine_offload_0.ctrl_cmd_wr       axi_spi_engine_0.offload0_cmd
-add_connection spi_engine_offload_0.ctrl_sdo_wr       axi_spi_engine_0.offload0_sdo
-add_connection spi_engine_offload_0.if_ctrl_enable    axi_spi_engine_0.if_offload0_enable
-add_connection spi_engine_offload_0.if_ctrl_enabled   axi_spi_engine_0.if_offload0_enabled
-add_connection spi_engine_offload_0.if_ctrl_mem_reset axi_spi_engine_0.if_offload0_mem_reset
-add_connection spi_engine_offload_0.status_sync       axi_spi_engine_0.offload_sync
-add_connection spi_engine_offload_0.if_trigger        trig_gen.if_pwm_0
-
-add_connection ad57xx_dma.m_axis spi_engine_offload_0.s_axis_sdo
+add_connection ${spi_engine_hier}_offload.if_trigger        trig_gen.if_pwm_0
+add_connection ad57xx_dma.m_axis ${spi_engine_hier}_offload.s_axis_sdo
 
 # cpu interconnects
 
 ad_cpu_interconnect 0x00030000 ad57xx_dma.s_axi
-ad_cpu_interconnect 0x00040000 axi_spi_engine_0.s_axi
+ad_cpu_interconnect 0x00040000 ${spi_engine_hier}_axi_regmap.s_axi
 ad_cpu_interconnect 0x00050000 trig_gen.s_axi
 ad_cpu_interconnect 0x00060000 spi_clk_pll_reconfig.mgmt_avalon_slave
 
@@ -178,4 +132,4 @@ ad_dma_interconnect ad57xx_dma.m_src_axi
 #interrupts
 
 ad_cpu_interrupt 4 ad57xx_dma.interrupt_sender
-ad_cpu_interrupt 5 axi_spi_engine_0.interrupt_sender
+ad_cpu_interrupt 5 ${spi_engine_hier}_axi_regmap.interrupt_sender
diff --git a/projects/cn0540/common/cn0540_qsys.tcl b/projects/cn0540/common/cn0540_qsys.tcl
index 1eec853d626..b5adf8a4d2f 100755
--- a/projects/cn0540/common/cn0540_qsys.tcl
+++ b/projects/cn0540/common/cn0540_qsys.tcl
@@ -12,35 +12,26 @@ set_instance_parameter_value axi_dmac_0 {CYCLIC} {0}
 set_instance_parameter_value axi_dmac_0 {DMA_DATA_WIDTH_SRC} {32}
 set_instance_parameter_value axi_dmac_0 {DMA_DATA_WIDTH_DEST} {128}
 
-# axi_spi_engine
+# spi engine
+source $ad_hdl_dir/library/spi_engine/scripts/spi_engine.tcl
 
-add_instance axi_spi_engine_0 axi_spi_engine
-set_instance_parameter_value axi_spi_engine_0 {ASYNC_SPI_CLK} {1}
-set_instance_parameter_value axi_spi_engine_0 {DATA_WIDTH}    {32}
-set_instance_parameter_value axi_spi_engine_0 {MM_IF_TYPE}    {0}
-set_instance_parameter_value axi_spi_engine_0 {NUM_OF_SDI}    {1}
-set_instance_parameter_value axi_spi_engine_0 {NUM_OFFLOAD}   {1}
+set spi_engine_hier cn0540_spi
 
-# spi_engine_execution
+set data_width 32
+set async_spi_clk 1
+set num_cs 1
+set num_sdi 1
+set num_sdo 1
+set sdi_delay 0
+set echo_sclk 0
+set sdo_streaming 0
 
-add_instance spi_engine_execution_0 spi_engine_execution
-set_instance_parameter_value spi_engine_execution_0 {DATA_WIDTH} {32}
-set_instance_parameter_value spi_engine_execution_0 {NUM_OF_SDI} {1}
-set_instance_parameter_value spi_engine_execution_0 {SDI_DELAY} {0}
+set axi_clk sys_clk.clk
+set axi_reset sys_clk.clk_reset
+set spi_clk sys_dma_clk.clk
 
-# spi_engine_interconnect
-
-add_instance spi_engine_interconnect_0 spi_engine_interconnect
-set_instance_parameter_value spi_engine_interconnect_0 {DATA_WIDTH} {32}
-set_instance_parameter_value spi_engine_interconnect_0 {NUM_OF_SDI} {1}
-
-# spi_engine_offload
-
-add_instance spi_engine_offload_0 spi_engine_offload
-set_instance_parameter_value spi_engine_offload_0 {ASYNC_TRIG}    {1}
-set_instance_parameter_value spi_engine_offload_0 {ASYNC_SPI_CLK} {0}
-set_instance_parameter_value spi_engine_offload_0 {DATA_WIDTH}    {32}
-set_instance_parameter_value spi_engine_offload_0 {NUM_OF_SDI}    {1}
+spi_engine_create $spi_engine_hier $axi_clk $axi_reset $spi_clk $data_width $async_spi_clk $num_cs $num_sdi $num_sdo $sdi_delay $echo_sclk $sdo_streaming
+set_instance_parameter_value ${spi_engine_hier}_offload {ASYNC_TRIG} {1}
 
 # exported interface
 
@@ -50,67 +41,33 @@ add_interface cn0540_spi_sdi        conduit end
 add_interface cn0540_spi_sdo        conduit end
 add_interface cn0540_spi_trigger    conduit end
 
-set_interface_property cn0540_spi_cs      EXPORT_OF spi_engine_execution_0.if_cs
-set_interface_property cn0540_spi_sclk    EXPORT_OF spi_engine_execution_0.if_sclk
-set_interface_property cn0540_spi_sdi     EXPORT_OF spi_engine_execution_0.if_sdi
-set_interface_property cn0540_spi_sdo     EXPORT_OF spi_engine_execution_0.if_sdo
-set_interface_property cn0540_spi_trigger EXPORT_OF spi_engine_offload_0.if_trigger
+set_interface_property cn0540_spi_cs      EXPORT_OF ${spi_engine_hier}_execution.if_cs
+set_interface_property cn0540_spi_sclk    EXPORT_OF ${spi_engine_hier}_execution.if_sclk
+set_interface_property cn0540_spi_sdi     EXPORT_OF ${spi_engine_hier}_execution.if_sdi
+set_interface_property cn0540_spi_sdo     EXPORT_OF ${spi_engine_hier}_execution.if_sdo
+set_interface_property cn0540_spi_trigger EXPORT_OF ${spi_engine_hier}_offload.if_trigger
 
 # clocks
 
-add_connection sys_clk.clk axi_spi_engine_0.s_axi_clock
 add_connection sys_clk.clk axi_dmac_0.s_axi_clock
 
-add_connection sys_dma_clk.clk spi_engine_execution_0.if_clk
-add_connection sys_dma_clk.clk spi_engine_interconnect_0.if_clk
-add_connection sys_dma_clk.clk axi_spi_engine_0.if_spi_clk
-add_connection sys_dma_clk.clk spi_engine_offload_0.if_ctrl_clk
-add_connection sys_dma_clk.clk spi_engine_offload_0.if_spi_clk
 add_connection sys_dma_clk.clk axi_dmac_0.if_s_axis_aclk
 add_connection sys_dma_clk.clk axi_dmac_0.m_dest_axi_clock
 
 # resets
 
-add_connection sys_clk.clk_reset axi_spi_engine_0.s_axi_reset
 add_connection sys_clk.clk_reset axi_dmac_0.s_axi_reset
 
-add_connection axi_spi_engine_0.if_spi_resetn spi_engine_execution_0.if_resetn
-add_connection axi_spi_engine_0.if_spi_resetn spi_engine_interconnect_0.if_resetn
-add_connection axi_spi_engine_0.if_spi_resetn spi_engine_offload_0.if_spi_resetn
-
 add_connection sys_dma_clk.clk_reset axi_dmac_0.m_dest_axi_reset
 
 # interfaces
 
-add_connection spi_engine_interconnect_0.m_cmd spi_engine_execution_0.cmd
-add_connection spi_engine_execution_0.sdi_data spi_engine_interconnect_0.m_sdi
-add_connection  spi_engine_interconnect_0.m_sdo spi_engine_execution_0.sdo_data
-add_connection spi_engine_execution_0.sync spi_engine_interconnect_0.m_sync
-
-add_connection axi_spi_engine_0.cmd spi_engine_interconnect_0.s1_cmd
-add_connection spi_engine_interconnect_0.s1_sdi axi_spi_engine_0.sdi_data
-add_connection axi_spi_engine_0.sdo_data spi_engine_interconnect_0.s1_sdo
-add_connection spi_engine_interconnect_0.s1_sync axi_spi_engine_0.sync
-
-add_connection spi_engine_offload_0.cmd spi_engine_interconnect_0.s0_cmd
-add_connection spi_engine_interconnect_0.s0_sdi  spi_engine_offload_0.sdi_data
-add_connection spi_engine_offload_0.sdo_data spi_engine_interconnect_0.s0_sdo
-add_connection spi_engine_interconnect_0.s0_sync spi_engine_offload_0.sync
-add_connection spi_engine_offload_0.m_interconnect_ctrl spi_engine_interconnect_0.s_interconnect_ctrl
-
-add_connection spi_engine_offload_0.ctrl_cmd_wr       axi_spi_engine_0.offload0_cmd
-add_connection spi_engine_offload_0.ctrl_sdo_wr       axi_spi_engine_0.offload0_sdo
-add_connection spi_engine_offload_0.if_ctrl_enable    axi_spi_engine_0.if_offload0_enable
-add_connection spi_engine_offload_0.if_ctrl_enabled   axi_spi_engine_0.if_offload0_enabled
-add_connection spi_engine_offload_0.if_ctrl_mem_reset axi_spi_engine_0.if_offload0_mem_reset
-add_connection spi_engine_offload_0.status_sync       axi_spi_engine_0.offload_sync
-
-add_connection spi_engine_offload_0.offload_sdi axi_dmac_0.s_axis
+add_connection ${spi_engine_hier}_offload.offload_sdi axi_dmac_0.s_axis
 
 # cpu interconnects
 
 ad_cpu_interconnect 0x00020000 axi_dmac_0.s_axi
-ad_cpu_interconnect 0x00030000 axi_spi_engine_0.s_axi
+ad_cpu_interconnect 0x00030000 ${spi_engine_hier}_axi_regmap.s_axi
 
 # dma interconnect
 ad_dma_interconnect axi_dmac_0.m_dest_axi
@@ -118,5 +75,4 @@ ad_dma_interconnect axi_dmac_0.m_dest_axi
 #interrupts
 
 ad_cpu_interrupt 4 axi_dmac_0.interrupt_sender
-ad_cpu_interrupt 5 axi_spi_engine_0.interrupt_sender
-
+ad_cpu_interrupt 5 ${spi_engine_hier}_axi_regmap.interrupt_sender
diff --git a/projects/cn0561/common/cn0561_qsys.tcl b/projects/cn0561/common/cn0561_qsys.tcl
index 7e245f9d810..e3dd25dca61 100644
--- a/projects/cn0561/common/cn0561_qsys.tcl
+++ b/projects/cn0561/common/cn0561_qsys.tcl
@@ -11,36 +11,6 @@ set_instance_parameter_value axi_dmac_0 {CYCLIC} {0}
 set_instance_parameter_value axi_dmac_0 {DMA_DATA_WIDTH_SRC} {128}
 set_instance_parameter_value axi_dmac_0 {DMA_DATA_WIDTH_DEST} {128}
 
-# axi_spi_engine
-
-add_instance axi_spi_engine_0 axi_spi_engine
-set_instance_parameter_value axi_spi_engine_0 {ASYNC_SPI_CLK} {1}
-set_instance_parameter_value axi_spi_engine_0 {DATA_WIDTH} {32}
-set_instance_parameter_value axi_spi_engine_0 {MM_IF_TYPE} {0}
-set_instance_parameter_value axi_spi_engine_0 {NUM_OF_SDI} {4}
-set_instance_parameter_value axi_spi_engine_0 {NUM_OFFLOAD} {1}
-
-# spi_engine_execution
-
-add_instance spi_engine_execution_0 spi_engine_execution
-set_instance_parameter_value spi_engine_execution_0 {DATA_WIDTH} {32}
-set_instance_parameter_value spi_engine_execution_0 {NUM_OF_SDI} {4}
-set_instance_parameter_value spi_engine_execution_0 {SDI_DELAY} {0}
-
-# spi_engine_interconnect
-
-add_instance spi_engine_interconnect_0 spi_engine_interconnect
-set_instance_parameter_value spi_engine_interconnect_0 {DATA_WIDTH} {32}
-set_instance_parameter_value spi_engine_interconnect_0 {NUM_OF_SDI} {4}
-
-# spi_engine_offload
-
-add_instance spi_engine_offload_0 spi_engine_offload
-set_instance_parameter_value spi_engine_offload_0 {ASYNC_TRIG} {1}
-set_instance_parameter_value spi_engine_offload_0 {ASYNC_SPI_CLK} {0}
-set_instance_parameter_value spi_engine_offload_0 {DATA_WIDTH} {32}
-set_instance_parameter_value spi_engine_offload_0 {NUM_OF_SDI} {4}
-
 # axi pwm gen
 
 add_instance odr_generator axi_pwm_gen
@@ -91,6 +61,27 @@ set_connection_parameter_value spi_clk_pll.reconfig_to_pll/spi_clk_pll_reconfig.
 set_connection_parameter_value spi_clk_pll.reconfig_to_pll/spi_clk_pll_reconfig.reconfig_to_pll startPortLSB {0}
 set_connection_parameter_value spi_clk_pll.reconfig_to_pll/spi_clk_pll_reconfig.reconfig_to_pll width {0}
 
+# spi engine
+source $ad_hdl_dir/library/spi_engine/scripts/spi_engine.tcl
+
+set spi_engine_hier cn0561_spi
+
+set data_width 32
+set async_spi_clk 1
+set num_cs 1
+set num_sdi 4
+set num_sdo 1
+set sdi_delay 0
+set echo_sclk 0
+set sdo_streaming 0
+
+set axi_clk sys_clk.clk
+set axi_reset sys_clk.clk_reset
+set spi_clk spi_clk_pll.outclk0
+
+spi_engine_create $spi_engine_hier $axi_clk $axi_reset $spi_clk $data_width $async_spi_clk $num_cs $num_sdi $num_sdo $sdi_delay $echo_sclk $sdo_streaming
+set_instance_parameter_value ${spi_engine_hier}_offload {ASYNC_TRIG} {1}
+
 # exported interface
 
 add_interface cn0561_spi_sclk    clock source
@@ -99,26 +90,20 @@ add_interface cn0561_spi_sdi     conduit end
 add_interface cn0561_spi_sdo     conduit end
 add_interface ad4134_odr         conduit end
 
-set_interface_property cn0561_spi_cs      EXPORT_OF spi_engine_execution_0.if_cs
-set_interface_property cn0561_spi_sclk    EXPORT_OF spi_engine_execution_0.if_sclk
-set_interface_property cn0561_spi_sdi     EXPORT_OF spi_engine_execution_0.if_sdi
-set_interface_property cn0561_spi_sdo     EXPORT_OF spi_engine_execution_0.if_sdo
+set_interface_property cn0561_spi_cs      EXPORT_OF ${spi_engine_hier}_execution.if_cs
+set_interface_property cn0561_spi_sclk    EXPORT_OF ${spi_engine_hier}_execution.if_sclk
+set_interface_property cn0561_spi_sdi     EXPORT_OF ${spi_engine_hier}_execution.if_sdi
+set_interface_property cn0561_spi_sdo     EXPORT_OF ${spi_engine_hier}_execution.if_sdo
 set_interface_property ad4134_odr         EXPORT_OF odr_generator.if_pwm_1
 
 # clocks
 
 add_connection sys_clk.clk spi_clk_pll.refclk
 add_connection sys_clk.clk spi_clk_pll_reconfig.mgmt_clk
-add_connection sys_clk.clk axi_spi_engine_0.s_axi_clock
 add_connection sys_clk.clk axi_dmac_0.s_axi_clock
 add_connection sys_clk.clk odr_generator.s_axi_clock
 
 add_connection spi_clk_pll.outclk0 odr_generator.if_ext_clk
-add_connection spi_clk_pll.outclk0 spi_engine_execution_0.if_clk
-add_connection spi_clk_pll.outclk0 spi_engine_interconnect_0.if_clk
-add_connection spi_clk_pll.outclk0 axi_spi_engine_0.if_spi_clk
-add_connection spi_clk_pll.outclk0 spi_engine_offload_0.if_ctrl_clk
-add_connection spi_clk_pll.outclk0 spi_engine_offload_0.if_spi_clk
 add_connection spi_clk_pll.outclk0 axi_dmac_0.if_s_axis_aclk
 
 add_connection sys_dma_clk.clk axi_dmac_0.m_dest_axi_clock
@@ -127,48 +112,20 @@ add_connection sys_dma_clk.clk axi_dmac_0.m_dest_axi_clock
 
 add_connection sys_clk.clk_reset spi_clk_pll.reset
 add_connection sys_clk.clk_reset spi_clk_pll_reconfig.mgmt_reset
-add_connection sys_clk.clk_reset axi_spi_engine_0.s_axi_reset
 add_connection sys_clk.clk_reset axi_dmac_0.s_axi_reset
 add_connection sys_clk.clk_reset odr_generator.s_axi_reset
 
-add_connection axi_spi_engine_0.if_spi_resetn spi_engine_execution_0.if_resetn
-add_connection axi_spi_engine_0.if_spi_resetn spi_engine_interconnect_0.if_resetn
-add_connection axi_spi_engine_0.if_spi_resetn spi_engine_offload_0.if_spi_resetn
-
 add_connection sys_dma_clk.clk_reset axi_dmac_0.m_dest_axi_reset
 
 # interfaces
 
-add_connection spi_engine_interconnect_0.m_cmd spi_engine_execution_0.cmd
-add_connection spi_engine_execution_0.sdi_data spi_engine_interconnect_0.m_sdi
-add_connection spi_engine_interconnect_0.m_sdo spi_engine_execution_0.sdo_data
-add_connection spi_engine_execution_0.sync spi_engine_interconnect_0.m_sync
-
-add_connection axi_spi_engine_0.cmd spi_engine_interconnect_0.s1_cmd
-add_connection spi_engine_interconnect_0.s1_sdi axi_spi_engine_0.sdi_data
-add_connection axi_spi_engine_0.sdo_data spi_engine_interconnect_0.s1_sdo
-add_connection spi_engine_interconnect_0.s1_sync axi_spi_engine_0.sync
-
-add_connection spi_engine_offload_0.cmd spi_engine_interconnect_0.s0_cmd
-add_connection spi_engine_interconnect_0.s0_sdi spi_engine_offload_0.sdi_data
-add_connection spi_engine_offload_0.sdo_data spi_engine_interconnect_0.s0_sdo
-add_connection spi_engine_interconnect_0.s0_sync spi_engine_offload_0.sync
-add_connection spi_engine_offload_0.m_interconnect_ctrl spi_engine_interconnect_0.s_interconnect_ctrl
-
-add_connection spi_engine_offload_0.ctrl_cmd_wr       axi_spi_engine_0.offload0_cmd
-add_connection spi_engine_offload_0.ctrl_sdo_wr       axi_spi_engine_0.offload0_sdo
-add_connection spi_engine_offload_0.if_ctrl_enable    axi_spi_engine_0.if_offload0_enable
-add_connection spi_engine_offload_0.if_ctrl_enabled   axi_spi_engine_0.if_offload0_enabled
-add_connection spi_engine_offload_0.if_ctrl_mem_reset axi_spi_engine_0.if_offload0_mem_reset
-add_connection spi_engine_offload_0.status_sync       axi_spi_engine_0.offload_sync
-
-add_connection spi_engine_offload_0.if_trigger odr_generator.if_pwm_0
-add_connection spi_engine_offload_0.offload_sdi axi_dmac_0.s_axis
+add_connection ${spi_engine_hier}_offload.if_trigger odr_generator.if_pwm_0
+add_connection ${spi_engine_hier}_offload.offload_sdi axi_dmac_0.s_axis
 
 # cpu interconnects
 
 ad_cpu_interconnect 0x00020000 axi_dmac_0.s_axi
-ad_cpu_interconnect 0x00030000 axi_spi_engine_0.s_axi
+ad_cpu_interconnect 0x00030000 ${spi_engine_hier}_axi_regmap.s_axi
 ad_cpu_interconnect 0x00040000 odr_generator.s_axi
 
 # dma interconnect
@@ -178,4 +135,4 @@ ad_dma_interconnect axi_dmac_0.m_dest_axi
 #interrupts
 
 ad_cpu_interrupt 4 axi_dmac_0.interrupt_sender
-ad_cpu_interrupt 5 axi_spi_engine_0.interrupt_sender
+ad_cpu_interrupt 5 ${spi_engine_hier}_axi_regmap.interrupt_sender
\ No newline at end of file
diff --git a/projects/common/a10gx/a10gx_system_qsys.tcl b/projects/common/a10gx/a10gx_system_qsys.tcl
index 9f67d9f1300..1bebd3491c6 100644
--- a/projects/common/a10gx/a10gx_system_qsys.tcl
+++ b/projects/common/a10gx/a10gx_system_qsys.tcl
@@ -3,6 +3,9 @@
 ### SPDX short identifier: ADIBSD
 ###############################################################################
 
+# Intel specific helper proc/ compatibility with xilinx procs on adi_board.tcl
+source $ad_hdl_dir/projects/scripts/adi_board_intel.tcl
+
 # a10gx carrier qsys
 set system_type nios
 
diff --git a/projects/common/a10soc/a10soc_system_qsys.tcl b/projects/common/a10soc/a10soc_system_qsys.tcl
index 6df72041e1a..999c579451f 100644
--- a/projects/common/a10soc/a10soc_system_qsys.tcl
+++ b/projects/common/a10soc/a10soc_system_qsys.tcl
@@ -3,6 +3,9 @@
 ### SPDX short identifier: ADIBSD
 ###############################################################################
 
+# Intel specific helper proc/ compatibility with xilinx procs on adi_board.tcl
+source $ad_hdl_dir/projects/scripts/adi_board_intel.tcl
+
 # a10soc carrier qsys
 set system_type a10soc
 
diff --git a/projects/common/c5soc/c5soc_system_qsys.tcl b/projects/common/c5soc/c5soc_system_qsys.tcl
index 1258a48f427..fa17d0b00e9 100644
--- a/projects/common/c5soc/c5soc_system_qsys.tcl
+++ b/projects/common/c5soc/c5soc_system_qsys.tcl
@@ -3,6 +3,9 @@
 ### SPDX short identifier: ADIBSD
 ###############################################################################
 
+# Intel specific helper proc/ compatibility with xilinx procs on adi_board.tcl
+source $ad_hdl_dir/projects/scripts/adi_board_intel.tcl
+
 # c5soc carrier qsys
 set system_type c5soc
 
diff --git a/projects/common/de10nano/de10nano_system_qsys.tcl b/projects/common/de10nano/de10nano_system_qsys.tcl
index 4f8174f353a..34f75e58590 100644
--- a/projects/common/de10nano/de10nano_system_qsys.tcl
+++ b/projects/common/de10nano/de10nano_system_qsys.tcl
@@ -3,6 +3,9 @@
 ### SPDX short identifier: ADIBSD
 ###############################################################################
 
+# Intel specific helper proc/ compatibility with xilinx procs on adi_board.tcl
+source $ad_hdl_dir/projects/scripts/adi_board_intel.tcl
+
 # de10nano carrier qsys
 # system clock
 
diff --git a/projects/common/fm87/fm87_system_qsys.tcl b/projects/common/fm87/fm87_system_qsys.tcl
index ea1ee432e0a..6cec89e234c 100644
--- a/projects/common/fm87/fm87_system_qsys.tcl
+++ b/projects/common/fm87/fm87_system_qsys.tcl
@@ -3,6 +3,9 @@
 ### SPDX short identifier: ADIBSD
 ###############################################################################
 
+# Intel specific helper proc/ compatibility with xilinx procs on adi_board.tcl
+source $ad_hdl_dir/projects/scripts/adi_board_intel.tcl
+
 # fm87 carrier qsys
 
 set system_type "Agilex 7"
diff --git a/projects/common/s10soc/s10soc_system_qsys.tcl b/projects/common/s10soc/s10soc_system_qsys.tcl
index 9da289fb63f..9b534d5e46d 100644
--- a/projects/common/s10soc/s10soc_system_qsys.tcl
+++ b/projects/common/s10soc/s10soc_system_qsys.tcl
@@ -3,6 +3,9 @@
 ### SPDX short identifier: ADIBSD
 ###############################################################################
 
+# Intel specific helper proc/ compatibility with xilinx procs on adi_board.tcl
+source $ad_hdl_dir/projects/scripts/adi_board_intel.tcl
+
 # stratix10soc carrier qsys
 
 set system_type s10soc
diff --git a/projects/scripts/adi_board.tcl b/projects/scripts/adi_board.tcl
index d49116668c0..614c821d7c4 100644
--- a/projects/scripts/adi_board.tcl
+++ b/projects/scripts/adi_board.tcl
@@ -3,8 +3,6 @@
 ### SPDX short identifier: ADIBSD
 ###############################################################################
 
-package require math
-
 ## Global variables for interconnect interface indexing
 #
 set sys_hpc0_interconnect_index -1
@@ -153,8 +151,8 @@ proc ad_connect_int_width {obj} {
   set left [get_property LEFT $obj]
   set right [get_property RIGHT $obj]
 
-  set high [::math::max $left $right]
-  set low [::math::min $left $right]
+  set high [expr max($left,$right)]
+  set low [expr min($left,$right)]
 
   return [expr {1 + $high - $low}]
 }
diff --git a/projects/scripts/adi_board_intel.tcl b/projects/scripts/adi_board_intel.tcl
new file mode 100644
index 00000000000..7ecc889a371
--- /dev/null
+++ b/projects/scripts/adi_board_intel.tcl
@@ -0,0 +1,26 @@
+###############################################################################
+## Copyright (C) 2025 Analog Devices, Inc. All rights reserved.
+### SPDX short identifier: ADIBSD
+###############################################################################
+
+proc ad_ip_instance {i_ip i_name {i_params {}}} {
+  add_instance ${i_name} ${i_ip}
+  # Set parameters if provided
+  if {$i_params != {}} {
+    foreach {k v} $i_params {
+      set_instance_parameter_value ${i_name} $k $v
+    }
+  }
+}
+
+proc ad_ip_parameter {i_name i_param i_value} {
+
+    # Remove CONFIG. prefix if present for Intel
+    regsub {^CONFIG\.} $i_param {} param_name
+    set_instance_parameter_value ${i_name} ${param_name} ${i_value}
+}
+
+proc ad_connect {name_a name_b} {
+
+    add_connection $name_a $name_b
+}