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5 changes: 5 additions & 0 deletions library/corundum/corundum_core/corundum_core_ip.tcl
Original file line number Diff line number Diff line change
Expand Up @@ -860,6 +860,8 @@ adi_add_bus_clock "ddr_clk" "m_axi_ddr:m_axi_ddr_app" "ddr_rst"
adi_add_bus_clock "hbm_clk" "m_axi_hbm:m_axi_hbm_app" "hbm_rst"
adi_add_bus_clock "tx_clk" "m_axis_tx:s_axis_direct_tx_app:m_axis_direct_tx_app" "tx_rst"
adi_add_bus_clock "rx_clk" "s_axis_rx:s_axis_stat:s_axis_direct_rx_app:m_axis_direct_rx_app" "rx_rst"
adi_add_bus_clock "tx_ptp_clk" "ethernet_ptp_tx" "tx_ptp_rst"
adi_add_bus_clock "rx_ptp_clk" "ethernet_ptp_rx" "rx_ptp_rst"

## Parameter validation

Expand Down Expand Up @@ -2527,6 +2529,9 @@ adi_set_ports_dependency "hbm_status" \
adi_set_bus_dependency "m_axil_csr" "m_axil_csr" \
"(spirit:decode(id('PARAM_VALUE.AXIL_CSR_ENABLE')) = 1)"

adi_set_bus_dependency "s_axis_stat" "s_axis_stat" \
"(spirit:decode(id('MODELPARAM_VALUE.STAT_ENABLE')) = 1)"

# Application dependencies

adi_set_bus_dependency "m_axi_ddr_app" "m_axi_ddr_app" \
Expand Down
22 changes: 12 additions & 10 deletions library/corundum/ethernet/k26/ethernet_k26.v
Original file line number Diff line number Diff line change
Expand Up @@ -53,8 +53,8 @@ module ethernet_k26 #(

// Statistics counter subsystem
parameter STAT_ENABLE = 0,
parameter STAT_DMA_ENABLE = 1,
parameter STAT_AXI_ENABLE = 1,
parameter STAT_DMA_ENABLE = 0,
parameter STAT_AXI_ENABLE = 0,
parameter STAT_INC_WIDTH = 24,
parameter STAT_ID_WIDTH = 12
) (
Expand Down Expand Up @@ -139,11 +139,17 @@ module ethernet_k26 #(

output wire [PORT_COUNT-1:0] eth_tx_clk,
output wire [PORT_COUNT-1:0] eth_tx_rst,

output wire [PORT_COUNT-1:0] eth_tx_ptp_clk,
output wire [PORT_COUNT-1:0] eth_tx_ptp_rst,
input wire [PORT_COUNT*PTP_TS_WIDTH-1:0] eth_tx_ptp_ts,
input wire [PORT_COUNT-1:0] eth_tx_ptp_ts_step,

output wire [PORT_COUNT-1:0] eth_rx_clk,
output wire [PORT_COUNT-1:0] eth_rx_rst,

output wire [PORT_COUNT-1:0] eth_rx_ptp_clk,
output wire [PORT_COUNT-1:0] eth_rx_ptp_rst,
input wire [PORT_COUNT*PTP_TS_WIDTH-1:0] eth_rx_ptp_ts,
input wire [PORT_COUNT-1:0] eth_rx_ptp_ts_step,

Expand Down Expand Up @@ -184,14 +190,6 @@ module ethernet_k26 #(
input wire [PORT_COUNT*8-1:0] eth_rx_pfc_ack,
output wire [PORT_COUNT-1:0] eth_rx_fc_quanta_clk_en,

/*
* Statistics increment input
*/
output wire [STAT_INC_WIDTH-1:0] s_axis_stat_tdata,
output wire [STAT_ID_WIDTH-1:0] s_axis_stat_tid,
output wire s_axis_stat_tvalid,
input wire s_axis_stat_tready,

input wire scl_i,
output reg scl_o,
output reg scl_t,
Expand Down Expand Up @@ -509,8 +507,12 @@ module ethernet_k26 #(

assign eth_tx_clk[n] = port_xgmii_tx_clk[n];
assign eth_tx_rst[n] = port_xgmii_tx_rst[n];
assign eth_tx_ptp_clk[n] = port_xgmii_tx_clk[n];
assign eth_tx_ptp_rst[n] = port_xgmii_tx_rst[n];
assign eth_rx_clk[n] = port_xgmii_rx_clk[n];
assign eth_rx_rst[n] = port_xgmii_rx_rst[n];
assign eth_rx_ptp_clk[n] = port_xgmii_rx_clk[n];
assign eth_rx_ptp_rst[n] = port_xgmii_rx_rst[n];

eth_mac_10g #(
.DATA_WIDTH(AXIS_DATA_WIDTH),
Expand Down
54 changes: 9 additions & 45 deletions library/corundum/ethernet/k26/ethernet_k26_ip.tcl
Original file line number Diff line number Diff line change
Expand Up @@ -79,8 +79,6 @@ adi_add_bus "axis_eth_tx" "slave" \
{"axis_eth_tx_tuser" "TUSER"} \
]

adi_add_bus_clock "eth_tx_clk" "axis_eth_tx" "eth_tx_rst" "master" "master"

adi_add_bus "axis_eth_rx" "master" \
"xilinx.com:interface:axis_rtl:1.0" \
"xilinx.com:interface:axis:1.0" \
Expand All @@ -93,8 +91,6 @@ adi_add_bus "axis_eth_rx" "master" \
{"axis_eth_rx_tuser" "TUSER"} \
]

adi_add_bus_clock "eth_rx_clk" "axis_eth_rx" "eth_rx_rst" "master" "master"

adi_if_infer_bus analog.com:interface:if_ctrl_reg slave ctrl_reg [list \
"ctrl_reg_wr_addr ctrl_reg_wr_addr" \
"ctrl_reg_wr_data ctrl_reg_wr_data" \
Expand Down Expand Up @@ -136,47 +132,20 @@ adi_if_infer_bus analog.com:interface:if_axis_tx_ptp slave axis_tx_ptp [list \
"ready axis_eth_tx_ptp_ts_ready" \
]

adi_add_bus_clock "eth_tx_clk" "axis_tx_ptp" "eth_tx_rst" "master" "master"

ipx::infer_bus_interface clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
set reset_intf_main [ipx::infer_bus_interface rst xilinx.com:signal:reset_rtl:1.0 [ipx::current_core]]
set reset_polarity_main [ipx::add_bus_parameter "POLARITY" $reset_intf_main]
set_property value "ACTIVE_HIGH" $reset_polarity_main

ipx::infer_bus_interface ptp_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
ipx::infer_bus_interface ptp_sample_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]

ipx::infer_bus_interface eth_tx_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
ipx::infer_bus_interface eth_rx_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]

set reset_intf_ptp [ipx::infer_bus_interface ptp_rst xilinx.com:signal:reset_rtl:1.0 [ipx::current_core]]
set reset_polarity_ptp [ipx::add_bus_parameter "POLARITY" $reset_intf_ptp]
set_property value "ACTIVE_HIGH" $reset_polarity_ptp

set eth_tx_rst_intf [ipx::infer_bus_interface eth_tx_rst xilinx.com:signal:reset_rtl:1.0 [ipx::current_core]]
set eth_tx_rst_polarity [ipx::add_bus_parameter "POLARITY" $eth_tx_rst_intf]
set_property value "ACTIVE_HIGH" $eth_tx_rst_polarity
set eth_rx_rst_intf [ipx::infer_bus_interface eth_rx_rst xilinx.com:signal:reset_rtl:1.0 [ipx::current_core]]
set eth_rx_rst_polarity [ipx::add_bus_parameter "POLARITY" $eth_rx_rst_intf]
set_property value "ACTIVE_HIGH" $eth_rx_rst_polarity

adi_if_infer_bus analog.com:interface:if_ethernet_ptp slave ethernet_ptp_tx [list \
"ptp_clk eth_tx_clk" \
"ptp_rst eth_tx_rst" \
"ptp_clk eth_tx_ptp_clk" \
"ptp_rst eth_tx_ptp_rst" \
"ptp_ts eth_tx_ptp_ts" \
"ptp_ts_step eth_tx_ptp_ts_step" \
]

adi_if_infer_bus analog.com:interface:if_ethernet_ptp slave ethernet_ptp_rx [list \
"ptp_clk eth_rx_clk" \
"ptp_rst eth_rx_rst" \
"ptp_clk eth_rx_ptp_clk" \
"ptp_rst eth_rx_ptp_rst" \
"ptp_ts eth_rx_ptp_ts" \
"ptp_ts_step eth_rx_ptp_ts_step" \
]

adi_add_bus_clock "eth_tx_clk" "ethernet_ptp_tx" "eth_tx_rst" "master" "master"
adi_add_bus_clock "eth_rx_clk" "ethernet_ptp_rx" "eth_rx_rst" "master" "master"

adi_if_infer_bus analog.com:interface:if_flow_control_tx slave flow_control_tx [list \
"tx_enable eth_tx_enable" \
"tx_status eth_tx_status" \
Expand All @@ -199,16 +168,6 @@ adi_if_infer_bus analog.com:interface:if_flow_control_rx slave flow_control_rx [
"rx_fc_quanta_clk_en eth_rx_fc_quanta_clk_en" \
]

adi_add_bus "m_axis_stat" "master" \
"xilinx.com:interface:axis_rtl:1.0" \
"xilinx.com:interface:axis:1.0" \
[ list \
{"s_axis_stat_tdata" "TDATA"} \
{"s_axis_stat_tid" "TID"} \
{"s_axis_stat_tvalid" "TVALID"} \
{"s_axis_stat_tready" "TREADY"} \
]

adi_if_infer_bus analog.com:interface:if_sfp master m_sfp [list \
"rx_p sfp_rx_p" \
"rx_n sfp_rx_n" \
Expand Down Expand Up @@ -271,6 +230,11 @@ adi_if_infer_bus analog.com:interface:if_ptp slave ptp_clock [list \
"ptp_perout_pulse ptp_perout_pulse" \
]

adi_add_bus_clock "eth_tx_clk" "axis_eth_tx:axis_tx_ptp" "eth_tx_rst" "master" "master"
adi_add_bus_clock "eth_rx_clk" "axis_eth_rx" "eth_rx_rst" "master" "master"
adi_add_bus_clock "eth_tx_ptp_clk" "ethernet_ptp_tx" "eth_tx_ptp_rst" "master" "master"
adi_add_bus_clock "eth_rx_ptp_clk" "ethernet_ptp_rx" "eth_rx_ptp_rst" "master" "master"

## Customize GUI page

# Remove the automatically generated GUI page
Expand Down
1 change: 0 additions & 1 deletion library/corundum/scripts/corundum.tcl
Original file line number Diff line number Diff line change
Expand Up @@ -402,7 +402,6 @@ if [string equal $board K26] {
ad_connect corundum_core/ptp_clk ethernet_core/ptp_clk
ad_connect corundum_core/ptp_rst ethernet_core/ptp_rst
ad_connect corundum_core/ptp_sample_clk ethernet_core/ptp_sample_clk
ad_connect corundum_core/s_axis_stat ethernet_core/m_axis_stat
} else {
ad_connect ethernet_core/clk_125mhz clk_125mhz
ad_connect ethernet_core/rst_125mhz rst_125mhz
Expand Down
6 changes: 0 additions & 6 deletions projects/ad_gmsl2eth_sl/common/ad_gmsl2eth_sl_bd.tcl
Original file line number Diff line number Diff line change
Expand Up @@ -500,12 +500,6 @@ ad_connect corundum_hierarchy/sfp_iic sfp_iic

ad_connect clk10_gen/clk_out1 ref_clk0

set axi_clk_freq [get_property CONFIG.FREQ_HZ [get_bd_pins sys_ps8/pl_clk1]]
set_property CONFIG.FREQ_HZ $axi_clk_freq [get_bd_intf_pins corundum_hierarchy/m_axi]
set_property CONFIG.FREQ_HZ $axi_clk_freq [get_bd_intf_pins /corundum_hierarchy/corundum_core/m_axi]
set_property CONFIG.FREQ_HZ $axi_clk_freq [get_bd_intf_pins corundum_hierarchy/s_axil_corundum]
set_property CONFIG.FREQ_HZ $axi_clk_freq [get_bd_intf_pins /corundum_hierarchy/corundum_core/s_axil_ctrl]

ad_ip_instance axi_interconnect smartconnect_corundum
ad_ip_parameter smartconnect_corundum CONFIG.NUM_MI 2
ad_ip_parameter smartconnect_corundum CONFIG.NUM_SI 1
Expand Down
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