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| 1 | +// *************************************************************************** |
| 2 | +// *************************************************************************** |
| 3 | +// Copyright (C) 2025 Analog Devices, Inc. All rights reserved. |
| 4 | +// |
| 5 | +// In this HDL repository, there are many different and unique modules, consisting |
| 6 | +// of various HDL (Verilog or VHDL) components. The individual modules are |
| 7 | +// developed independently, and may be accompanied by separate and unique license |
| 8 | +// terms. |
| 9 | +// |
| 10 | +// The user should read each of these license terms, and understand the |
| 11 | +// freedoms and responsibilities that he or she has by using this source/core. |
| 12 | +// |
| 13 | +// This core is distributed in the hope that it will be useful, but WITHOUT ANY |
| 14 | +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR |
| 15 | +// A PARTICULAR PURPOSE. |
| 16 | +// |
| 17 | +// Redistribution and use of source or resulting binaries, with or without modification |
| 18 | +// of this file, are permitted under one of the following two license terms: |
| 19 | +// |
| 20 | +// 1. The GNU General Public License version 2 as published by the |
| 21 | +// Free Software Foundation, which can be found in the top level directory |
| 22 | +// of this repository (LICENSE_GPL2), and also online at: |
| 23 | +// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html> |
| 24 | +// |
| 25 | +// OR |
| 26 | +// |
| 27 | +// 2. An ADI specific BSD license, which can be found in the top level directory |
| 28 | +// of this repository (LICENSE_ADIBSD), and also on-line at: |
| 29 | +// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD |
| 30 | +// This will allow to generate bit files and not release the source code, |
| 31 | +// as long as it attaches to an ADI device. |
| 32 | +// |
| 33 | +// *************************************************************************** |
| 34 | +// *************************************************************************** |
| 35 | + |
| 36 | +`timescale 1ns/1ps |
| 37 | + |
| 38 | +`include "utils.svh" |
| 39 | + |
| 40 | +module system_tb(); |
| 41 | + |
| 42 | + parameter ID = 0; |
| 43 | + parameter FPGA_TECHNOLOGY = 1; |
| 44 | + parameter IO_DELAY_GROUP = "adc_if_delay_group"; |
| 45 | + parameter DELAY_REFCLK_FREQUENCY = 200; |
| 46 | + |
| 47 | + // dco delay compared to the reference clk |
| 48 | + localparam DCO_DELAY = 12; |
| 49 | + |
| 50 | + // reg signals |
| 51 | + |
| 52 | + reg ref_clk = 1'b0; |
| 53 | + reg dco_init = 1'b0; |
| 54 | + reg cnv_out = 1'b0; |
| 55 | + reg clk_gate = 1'b0; |
| 56 | + reg dco_p; |
| 57 | + reg dco_n; |
| 58 | + reg da_p = 1'b0; |
| 59 | + reg da_n = 1'b0; |
| 60 | + reg db_p = 1'b0; |
| 61 | + reg db_n = 1'b0; |
| 62 | + |
| 63 | + // dma interface |
| 64 | + |
| 65 | + wire adc_valid; |
| 66 | + wire [`ADC_RES-1:0] adc_data; |
| 67 | + reg adc_dovf = 1'b0; |
| 68 | + |
| 69 | + // axi interface |
| 70 | + |
| 71 | + reg s_axi_aclk = 1'b0; |
| 72 | + reg s_axi_aresetn = 1'b0; |
| 73 | + reg s_axi_awvalid = 1'b0; |
| 74 | + reg [15:0] s_axi_awaddr = 16'b0; |
| 75 | + wire s_axi_awready; |
| 76 | + reg s_axi_wvalid = 1'b0; |
| 77 | + reg [31:0] s_axi_wdata = 32'b0; |
| 78 | + reg [ 3:0] s_axi_wstrb = 4'b0; |
| 79 | + wire s_axi_wready; |
| 80 | + wire s_axi_bvalid; |
| 81 | + wire [ 1:0] s_axi_bresp; |
| 82 | + reg s_axi_bready = 1'b0; |
| 83 | + reg s_axi_arvalid = 1'b0; |
| 84 | + reg [15:0] s_axi_araddr = 1'b0; |
| 85 | + wire s_axi_arready; |
| 86 | + wire s_axi_rvalid; |
| 87 | + wire [ 1:0] s_axi_rresp; |
| 88 | + wire [31:0] s_axi_rdata; |
| 89 | + reg s_axi_rready = 1'b0; |
| 90 | + reg [ 2:0] s_axi_awprot = 3'b0; |
| 91 | + reg [ 2:0] s_axi_arprot = 3'b0; |
| 92 | + |
| 93 | + // local wires and registers |
| 94 | + |
| 95 | + wire cnv; |
| 96 | + reg dco = 1'b0; |
| 97 | + |
| 98 | + integer cnv_count = 0; |
| 99 | + |
| 100 | + // test bench variables |
| 101 | + |
| 102 | + always #25 ref_clk = ~ref_clk; |
| 103 | + //always #2.564 ref_clk = ~ref_clk; |
| 104 | + |
| 105 | + // --------------------------------------------------------------------------- |
| 106 | + // Creating a "gate" through which the data clock can run (and only then) |
| 107 | + // --------------------------------------------------------------------------- |
| 108 | + always @ (*) begin |
| 109 | + if (clk_gate == 1'b1) begin |
| 110 | + dco_init = ref_clk; |
| 111 | + end else begin |
| 112 | + dco_init = 1'b0; |
| 113 | + end |
| 114 | + end |
| 115 | + |
| 116 | + initial begin |
| 117 | + s_axi_aresetn <= 1'b0; |
| 118 | + repeat(10) @(posedge s_axi_aclk); |
| 119 | + s_axi_aresetn <= 1'b1; |
| 120 | + end |
| 121 | + // Data clocks generation |
| 122 | + // --------------------------------------------------------------------------- |
| 123 | + |
| 124 | + always @ (dco_init) begin |
| 125 | + dco_p <= #DCO_DELAY dco_init; |
| 126 | + dco_n <= #DCO_DELAY ~dco_init; |
| 127 | + end |
| 128 | + |
| 129 | + `TEST_PROGRAM test( |
| 130 | + .ref_clk (ref_clk), |
| 131 | + .clk_gate (clk_gate), |
| 132 | + .dco_in (dco_init), |
| 133 | + .da_p (da_p), |
| 134 | + .da_n (da_n), |
| 135 | + .db_p (db_p), |
| 136 | + .db_n (db_n), |
| 137 | + .cnv (cnv)); |
| 138 | + |
| 139 | + test_harness `TH ( |
| 140 | + .ref_clk (ref_clk), |
| 141 | + .sampling_clk (sampling_clk), |
| 142 | + .dco_p (dco_p), |
| 143 | + .dco_n (dco_n), |
| 144 | + .cnv (cnv), |
| 145 | + .da_n (da_n), |
| 146 | + .da_p (da_p), |
| 147 | + .db_n (db_n), |
| 148 | + .db_p (db_p), |
| 149 | + .clk_gate (clk_gate)); |
| 150 | + |
| 151 | +endmodule |
| 152 | + |
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