Release v1.4.16 (#502)

* FPGA developer kit now supports Xilinx Vivado/Vitis 2020.1
* Updated Vitis examples to include usage of Vitis Libraries.
* Added documentation and examples to show Xilinx Alveo design migration to F1.
* Removed support for Xilinx toolsets 2017.4, 2018.2 and 2018.3.

Author: deeppat

.gitmodules

@@ -1,19 +1,10 @@
-[submodule "SDAccel/examples/xilinx_2017.4"]
-	path = SDAccel/examples/xilinx_2017.4
-	url = https://github.com/Xilinx/SDAccel_Examples.git
-	branch = aws_2017.4
-[submodule "SDAccel/examples/xilinx_2018.2"]
-	path = SDAccel/examples/xilinx_2018.2
-	url = https://github.com/Xilinx/SDAccel_Examples.git
-	branch = 2018.2_xdf
-[submodule "SDAccel/examples/xilinx_2018.3"]
-	path = SDAccel/examples/xilinx_2018.3
-	url = https://github.com/Xilinx/SDAccel_Examples.git
-	branch = master	
 [submodule "SDAccel/examples/xilinx_2019.1"]
 	path = SDAccel/examples/xilinx_2019.1
 	url = https://github.com/Xilinx/SDAccel_Examples.git
 [submodule "Vitis/examples/xilinx_2019.2"]
 	path = Vitis/examples/xilinx_2019.2
 	branch = master
 	url = https://github.com/Xilinx/Vitis_Accel_Examples
+[submodule "Vitis/examples/xilinx_2020.1"]
+	path = Vitis/examples/xilinx_2020.1
+	url = https://github.com/Xilinx/Vitis_Accel_Examples

ERRATA.md

@@ -20,6 +20,8 @@ If the check fails, the design is susceptible to the issue and will need to be r
 For designs under development, we recommend applying the patch to your on-premises tools or update to developer kit v1.4.15. 
 For additional details, please refer to the [Xilinx Answer Record #73068](https://www.xilinx.com/support/answers/73068.html)
 
+We recommend using [Developer Kit Release v1.4.15a](https://github.com/aws/aws-fpga/releases/tag/v1.4.15a) or newer to allow for patching and fixing the DDR4 IP timing exception by re-generating the IP.
+
 ### 2019.1 
 * Vivado `compile_simlib` command fails to generate the following verilog IP libraries for the following simulators.
 * Please refer to the Xilinx Answer record for details.

FAQs.md

@@ -29,7 +29,7 @@ AWS designed its FPGA instances to provide a developer experience with ease of u
 
 - AWS provides cloud based debug tools: [Virtual JTAG](./hdk/docs/Virtual_JTAG_XVC.md) which is equivalent to debug using JTAG with on-premises development, and Virtual LED together with Virtual DIP Switch emulation the LED and DIP switches in typical development board.
 
-- For developers who want to develop on-premises, Xilinx provides an [on-premises license](./hdk/docs/on_premise_licensing_help.md ) that matches all the needed components needed to be licensed for F1 development on premises.
+- For developers who want to develop on-premises, Xilinx provides an [on-premises license](docs/on_premise_licensing_help.md ) that matches all the needed components needed to be licensed for F1 development on premises.
 
 - The developers' output is a Design Checkpoint (DCP) and not an FPGA bitstream: The FPGA bitstream is actually generated by AWS after the developer submits the DCP.
 
@@ -185,7 +185,7 @@ AWS prefers not to limit developers to a specific template in terms of how we ad
 
 If you decide to use the [FPGA Developer AMI on AWS Marketplace](https://aws.amazon.com/marketplace/pp/B06VVYBLZZ), Xilinx licenses for simulation, encryption, SDAccel and Design Checkpoint generation are included at no additional cost.
 
-If you want to run using other methods or on a local machine, you will need to obtain any necessary licenses, specifically you will need to have setup the appropriate Xilinx Vivado license. For more details, please refer to [On-premises licensing help](./hdk/docs/on_premise_licensing_help.md)
+If you want to run using other methods or on a local machine, you will need to obtain any necessary licenses, specifically you will need to have setup the appropriate Xilinx Vivado license. For more details, please refer to [On-premises licensing help](docs/on_premise_licensing_help.md)
 
 
 **Q: Does AWS provide physical FPGA boards for on-premises development?**
@@ -492,7 +492,7 @@ Parent process (pid 8160) has died. This helper process will now exit
 
 *For On Premise runs:*
 
-You would need a valid [on premise license](./hdk/docs/on_premise_licensing_help.md) provided by Xilinx.
+You would need a valid [on premise license](docs/on_premise_licensing_help.md) provided by Xilinx.
 
 *For runs using the FPGA Developer AMI:* Please contact us through [AWS FPGA Developers forum](https://forums.aws.amazon.com/forum.jspa?forumID=243)
 
@@ -504,4 +504,25 @@ Please modify RDP options to choose any color depth less than 32 bit and try re-
 
 **Q: Why did my AFI creation fail with `***ERROR***: DCP has DNA_PORT instantiation, ingestion failed, exiting`?**
 
-AWS does not support creating AFI's with the Device DNA instantiated within your design. Please create your design without instantiating the DNA_PORT primitive to be able to create your AFI.
+AWS does not support creating AFI's with the Device DNA instantiated within your design. Please create your design without instantiating the DNA_PORT primitive to be able to create your AFI.
+ 
+**Q: How do I know which HDK version I have on my instance/machine? **
+
+Look for the ./hdk/hdk_version.txt file.
+
+**Q: How do I know what my Shell version is? **
+
+The Shell version of an FPGA slot is available through the FPGA Image Management tools after an AFI has been loaded.  
+See the description of `fpga-describe-local-image` for more details on retrieving the shell version from a slot. 
+Prior to loading an AFI, the state of the FPGA (including shell version) is undefined and non-deterministic.  
+
+**Q: How do I know what version of FPGA Image management tools are running on my instance? **
+
+The FPGA Image management tools version is reported with any command executed from these tools.  
+See the description of `fpga-describe-local-image` for more details.
+
+**Q: How do I update my existing design with a new release?**
+
+1. Start by pulling changes from a new [aws-fpga github release](https://github.com/aws/aws-fpga)
+1. If the [AWS Shell Interface Specification](./hdk/docs/AWS_Shell_Interface_Specification.md) has changed, update your CL design to conform to the new specification.
+3. Follow the process for AFI generation

Jenkinsfile

@@ -126,45 +126,23 @@ task_label = [
 ]
 
 // Put the latest version last
-def xilinx_versions = [ '2019.1', '2019.2' ]
+def xilinx_versions = [ '2019.1', '2019.2', '2020.1' ]
 
-def vitis_versions = ['2019.2']
+def vitis_versions = ['2019.2', '2020.1']
 
 // We want the default to be the latest.
 def default_xilinx_version = xilinx_versions.last()
 
 def dsa_map = [
-    '2017.4' : [ 'DYNAMIC_5_0' : 'dyn'],
-    '2018.2' : [ 'DYNAMIC_5_0' : 'dyn'],
-    '2018.3' : [ 'DYNAMIC_5_0' : 'dyn'],
     '2019.1' : [ 'DYNAMIC_5_0' : 'dyn'],
 ]
 
 def xsa_map = [
-    '2019.2' : [ 'DYNAMIC':'dyn']
+    '2019.2' : [ 'DYNAMIC':'dyn'],
+    '2020.1' : [ 'DYNAMIC':'dyn']
 ]
 
 def sdaccel_example_default_map = [
-    '2017.4' : [
-        'Hello_World_1ddr': 'SDAccel/examples/xilinx/getting_started/host/helloworld_ocl',
-        'Gmem_2Banks_2ddr': 'SDAccel/examples/xilinx/getting_started/kernel_to_gmem/gmem_2banks_ocl',
-        'kernel_3ddr_bandwidth_4ddr': 'SDAccel/examples/aws/kernel_3ddr_bandwidth',
-        'Kernel_Global_Bw_4ddr': 'SDAccel/examples/xilinx/getting_started/kernel_to_gmem/kernel_global_bandwidth',
-        'RTL_Vadd_Debug': 'SDAccel/examples/xilinx/getting_started/rtl_kernel/rtl_vadd_hw_debug'
-    ],
-    '2018.2' : [
-        'Hello_World_1ddr': 'SDAccel/examples/xilinx/getting_started/host/helloworld_ocl',
-        'Gmem_2Banks_2ddr': 'SDAccel/examples/xilinx/getting_started/kernel_to_gmem/gmem_2banks_ocl',
-        'kernel_3ddr_bandwidth_4ddr': 'SDAccel/examples/aws/kernel_3ddr_bandwidth',
-        'Kernel_Global_Bw_4ddr': 'SDAccel/examples/xilinx/getting_started/kernel_to_gmem/kernel_global_bandwidth',
-        'RTL_Vadd_Debug': 'SDAccel/examples/xilinx/getting_started/rtl_kernel/rtl_vadd_hw_debug'
-    ],
-    '2018.3' : [
-        'Hello_World_1ddr': 'SDAccel/examples/xilinx/getting_started/host/helloworld_ocl',
-        'Gmem_2Banks_2ddr': 'SDAccel/examples/xilinx/getting_started/kernel_to_gmem/gmem_2banks_ocl',
-        'Kernel_Global_Bw_4ddr': 'SDAccel/examples/xilinx/getting_started/kernel_to_gmem/kernel_global_bandwidth',
-        'RTL_Vadd_Debug': 'SDAccel/examples/xilinx/getting_started/rtl_kernel/rtl_vadd_hw_debug'
-    ],
     '2019.1' : [
         'Hello_World_1ddr': 'SDAccel/examples/xilinx/getting_started/hello_world/helloworld_ocl',
         'Gmem_2Banks_2ddr': 'SDAccel/examples/xilinx/getting_started/kernel_to_gmem/gmem_2banks_ocl_5.0_shell',
@@ -179,28 +157,18 @@ def vitis_example_default_map = [
         'Gmem_2Banks_2ddr': 'Vitis/examples/xilinx/ocl_kernels/cl_gmem_2banks',
         'Kernel_Global_Bw_4ddr': 'Vitis/examples/xilinx/cpp_kernels/kernel_global_bandwidth',
         'RTL_Vadd_Debug': 'Vitis/examples/xilinx/rtl_kernels/rtl_vadd_hw_debug'
+    ],
+    '2020.1' : [
+        'Hello_World_1ddr': 'Vitis/examples/xilinx/ocl_kernels/cl_helloworld',
+        'Gmem_2Banks_2ddr': 'Vitis/examples/xilinx/ocl_kernels/cl_gmem_2banks',
+        'Kernel_Global_Bw_4ddr': 'Vitis/examples/xilinx/cpp_kernels/kernel_global_bandwidth',
+        'RTL_Vadd_Debug': 'Vitis/examples/xilinx/rtl_kernels/rtl_vadd_hw_debug',
+        'gemm_blas': 'Vitis/examples/xilinx/library_examples/gemm',
+        'gzip_app': 'Vitis/examples/xilinx/library_examples/gzip_app'
     ]
 ]
 
 def simulator_tool_default_map = [
-    '2017.4' : [
-        'vivado': 'xilinx/SDx/2017.4_04112018',
-        'vcs': 'synopsys/vcs-mx/M-2017.03-SP2-11',
-        'questa': 'questa/10.6b',
-        'ies': 'incisive/15.20.063'
-     ],
-     '2018.2' : [
-         'vivado': 'xilinx/SDx/2018.2_06142018',
-         'vcs': 'synopsys/vcs-mx/N-2017.12-SP2',
-         'questa': 'questa/10.6c_1',
-         'ies': 'incisive/15.20.063'
-     ],
-     '2018.3' : [
-         'vivado': 'xilinx/SDx/2018.3_1207',
-         'vcs': 'synopsys/vcs-mx/N-2017.12-SP2',
-         'questa': 'questa/10.6c_1',
-         'ies': 'incisive/15.20.063'
-     ],
      '2019.1' : [
          'vivado': 'xilinx/SDx/2019.1.op2552052',
          'vcs': 'synopsys/vcs-mx/N-2017.12-SP2',
@@ -212,6 +180,12 @@ def simulator_tool_default_map = [
          'vcs': 'synopsys/vcs-mx/O-2018.09-SP2-1',
          'questa': 'questa/2019.2',
          'ies': 'incisive/15.20.063'
+     ],
+     '2020.1' : [
+         'vivado': 'xilinx/Vivado/2020.1',
+         'vcs': 'synopsys/vcs-mx/P-2019.06-SP1-1',
+         'questa': 'questa/2019.4',
+         'ies': 'incisive/15.20.079'
      ]
 ]
 

Jenkinsfile_int_sims

@@ -47,6 +47,12 @@ def simulator_tool_default_map = [
          'vcs': 'synopsys/vcs-mx/O-2018.09-SP2-1',
          'questa': 'questa/2019.2',
          'ies': 'incisive/15.20.063'
+     ],
+     '2020.1' : [
+         'vivado': 'xilinx/Vivado/2020.1',
+         'vcs': 'synopsys/vcs-mx/P-2019.06-SP1-1',
+         'questa': 'questa/2019.4',
+         'ies': 'incisive/15.20.079'
      ]
 ]