File tree
5,378 files changed
+1592
-11676615
lines changed- docs-rtd
- source
- hdk
- cl/examples
- CL-TEMPLATE
- cl-dram-hbm-dma
- verif
- cl-mem-perf
- verif
- docs
- sdk/apps/virtual-ethernet/doc
- vitis
- hdk
- cl/examples
- CL_TEMPLATE
- build/scripts
- design
- cl_dram_hbm_dma/design
- cl_sde/software/runtime
- common/ip
- cl_ip
- bd
- sc_1x1
- sim
- axi_infrastructure_v1_1_0
- axi_register_slice_v2_1_30
- axi_vip_v1_1_16
- smartconnect_v1_0
- src
- lib_cdc_v1_0_2
- proc_sys_reset_v5_0_14
- smartconnect_v1_0
- xlconstant_v1_1_8
- xgui
- sc_2x2
- sim
- axi_infrastructure_v1_1_0
- axi_register_slice_v2_1_30
- axi_vip_v1_1_16
- src
- cl_axi_sc_2x2_fifo_generator_0_0
- cl_axi_sc_2x2_fifo_generator_xdma_0
- lib_cdc_v1_0_2
- proc_sys_reset_v5_0_14
- smartconnect_v1_0
- xlconstant_v1_1_8
- xgui
- scripts
- cl_ip.cache/wt
- cl_ip.gen/sources_1
- bd
- cl_axi_sc_1x1
- hdl
- hw_handoff
- ip/cl_axi_sc_1x1_smartconnect_0_0
- bd_0
- hdl
- hw_handoff
- ip
- ip_0
- sim
- synth
- ip_10
- sim
- synth
- ip_11
- sim
- synth
- ip_12
- sim
- synth
- ip_13
- sim
- synth
- ip_14
- sim
- synth
- ip_1
- sim
- synth
- ip_2
- sim
- synth
- ip_3
- sim
- synth
- ip_4
- sim
- synth
- ip_5
- sim
- synth
- ip_6
- sim
- synth
- ip_7
- sim
- synth
- ip_8
- sim
- synth
- ip_9
- sim
- synth
- sim
- synth
- sim
- synth
- xtlm
- sim
- synth
- cl_axi_sc_2x2
- hdl
- hw_handoff
- ip/cl_axi_sc_2x2_smartconnect_0_0
- bd_0
- hdl
- hw_handoff
- ip
- ip_0
- sim
- synth
- ip_10
- sim
- synth
- ip_11
- sim
- synth
- ip_12
- sim
- synth
- ip_13
- sim
- synth
- ip_14
- sim
- synth
- ip_15
- sim
- synth
- ip_16
- sim
- synth
- ip_17
- sim
- synth
- ip_18
- sim
- synth
- ip_19
- sim
- synth
- ip_1
- sim
- synth
- ip_20
- sim
- synth
- ip_21
- sim
- synth
- ip_22
- sim
- synth
- ip_23
- sim
- synth
- ip_24
- sim
- synth
- ip_25
- sim
- synth
- ip_26
- sim
- synth
- ip_27
- sim
- synth
- ip_28
- sim
- synth
- ip_29
- sim
- synth
- ip_2
- sim
- synth
- ip_30
- sim
- synth
- ip_31
- sim
- synth
- ip_32
- sim
- synth
- ip_33
- sim
- synth
- ip_34
- sim
- synth
- ip_35
- sim
- synth
- ip_36
- sim
- synth
- ip_37
- sim
- synth
- ip_38
- sim
- synth
- ip_3
- sim
- synth
- ip_4
- sim
- synth
- ip_5
- sim
- synth
- ip_6
- sim
- synth
- ip_7
- sim
- synth
- ip_8
- sim
- synth
- ip_9
- sim
- synth
- sim
- synth
- sim
- synth
- xtlm
- sim
- synth
- ip
- axi_clock_converter_0
- doc
- hdl
- simulation
- sim
- synth
- sysc
- axi_register_slice_light
- doc
- hdl
- sim
- synth
- sysc
- axi_register_slice
- doc
- hdl
- sim
- synth
- sysc
- cl_axi3_256b_reg_slice
- doc
- hdl
- sim
- synth
- sysc
- cl_axi4_to_axi3_conv
- doc
- hdl
- simulation
- sim
- src
- synth
- cl_axi_clock_converter_256b
- doc
- hdl
- simulation
- sim
- synth
- sysc
- cl_axi_clock_converter_light
- doc
- hdl
- simulation
- sim
- synth
- sysc
- cl_axi_clock_converter
- doc
- hdl
- simulation
- sim
- synth
- sysc
- cl_axi_interconnect_64G_ddr
- doc
- hdl
- simulation
- sim
- src
- synth
- cl_axi_interconnect
- doc
- hdl
- simulation
- sim
- src
- synth
- cl_axi_register_slice_256
- doc
- hdl
- sim
- synth
- sysc
- cl_axi_register_slice_light
- doc
- hdl
- sim
- synth
- sysc
- cl_axi_register_slice
- doc
- hdl
- sim
- synth
- sysc
- cl_axi_width_cnv_512_to_256
- doc
- hdl
- simulation
- sim
- src
- synth
- cl_c2c_xbar_128G
- doc
- hdl
- simulation
- sim
- src
- synth
- cl_clk_axil_xbar
- doc
- hdl
- simulation
- sim
- src
- synth
- cl_ddr4_32g_ap
- bd_0
- hdl
- hw_handoff
- ip
- ip_0
- data
- hdl
- sim
- synth
- ip_10
- hdl
- sim
- synth
- ip_1
- hdl
- sim
- synth
- ip_2
- hdl
- sim
- synth
- ip_3
- hdl
- sim
- synth
- ip_4
- hdl
- sim
- synth
- ip_5
- hdl
- sim
- synth
- ip_6
- hdl
- simulation
- sim
- synth
- ip_7
- hdl
- sim
- synth
- ip_8
- hdl
- sim
- synth
- ip_9
- hdl
- simulation
- sim
- synth
- sim
- synth
- doc
- ip_0
- sim
- synth
- ip_1
- par
- rtl
- clocking
- iob
- ip_top
- map
- phy
- xiphy_files
- par
- rtl
- axi_ctrl
- axi
- cal
- clocking
- controller
- ip_top
- ui
- sim_tlm/top
- sim
- sw/calibration_0/Debug
- tb
- cl_ddr4_32g
- bd_0
- hdl
- hw_handoff
- ip
- ip_0
- data
- hdl
- sim
- synth
- ip_10
- hdl
- sim
- synth
- ip_1
- hdl
- sim
- synth
- ip_2
- hdl
- sim
- synth
- ip_3
- hdl
- sim
- synth
- ip_4
- hdl
- sim
- synth
- ip_5
- hdl
- sim
- synth
- ip_6
- hdl
- simulation
- sim
- synth
- ip_7
- hdl
- sim
- synth
- ip_8
- hdl
- sim
- synth
- ip_9
- hdl
- simulation
- sim
- synth
- sim
- synth
- doc
- ip_0
- sim
- synth
- ip_1
- par
- rtl
- clocking
- iob
- ip_top
- map
- phy
- xiphy_files
- par
- rtl
- axi_ctrl
- axi
- cal
- clocking
- controller
- ip_top
- ui
- sim_tlm/top
- sim
- sw/calibration_0/Debug
- tb
- cl_ddr4_64g_ap
- bd_0
- hdl
- hw_handoff
- ip
- ip_0
- data
- hdl
- sim
- synth
- ip_10
- hdl
- sim
- synth
- ip_1
- hdl
- sim
- synth
- ip_2
- hdl
- sim
- synth
- ip_3
- hdl
- sim
- synth
- ip_4
- hdl
- sim
- synth
- ip_5
- hdl
- sim
- synth
- ip_6
- hdl
- simulation
- sim
- synth
- ip_7
- hdl
- sim
- synth
- ip_8
- hdl
- sim
- synth
- ip_9
- hdl
- simulation
- sim
- synth
- sim
- synth
- doc
- ip_0
- sim
- synth
- ip_1
- par
- rtl
- clocking
- iob
- ip_top
- map
- phy
- xiphy_files
- par
- rtl
- axi_ctrl
- axi
- cal
- clocking
- controller
- ip_top
- ui
- sim_tlm/top
- sim
- sw/calibration_0/Debug
- tb
- cl_ddr4
- bd_0
- hdl
- hw_handoff
- ip
- ip_0
- data
- hdl
- sim
- synth
- ip_10
- hdl
- sim
- synth
- ip_1
- hdl
- sim
- synth
- ip_2
- hdl
- sim
- synth
- ip_3
- hdl
- sim
- synth
- ip_4
- hdl
- sim
- synth
- ip_5
- hdl
- sim
- synth
- ip_6
- hdl
- simulation
- sim
- synth
- ip_7
- hdl
- sim
- synth
- ip_8
- hdl
- sim
- synth
- ip_9
- hdl
- simulation
- sim
- synth
- sim
- synth
- doc
- ip_0
- sim
- synth
- ip_1
- par
- rtl
- clocking
- iob
- ip_top
- map
- phy
- xiphy_files
- par
- rtl
- axi_ctrl
- axi
- cal
- clocking
- controller
- ip_top
- ui
- sim_tlm/top
- sim
- sw/calibration_0/Debug
- tb
- cl_debug_bridge
- bd_0
- hdl
- hw_handoff
- ip
- ip_0
- constraints
- hdl
- verilog
- sim
- synth
- ip_1
- hdl
- sim
- synth
- sim
- synth
- doc
- sim
- synth
- cl_hbm_mmcm
- doc
- cl_hbm
- doc
- hdl
- par
- rtl
- sim
- synth
- sysc
- include
- src
- verif/model
- cl_sda_axil_xbar
- doc
- hdl
- simulation
- sim
- src
- synth
- clk_mmcm_a
- axi_lite_ipif_v1_01_a/hdl/src/vhdl
- doc
- proc_common_v3_00_a/hdl/src/vhdl
- clk_mmcm_b
- axi_lite_ipif_v1_01_a/hdl/src/vhdl
- doc
- proc_common_v3_00_a/hdl/src/vhdl
- clk_mmcm_c
- axi_lite_ipif_v1_01_a/hdl/src/vhdl
- doc
- proc_common_v3_00_a/hdl/src/vhdl
- clk_mmcm_hbm
- axi_lite_ipif_v1_01_a/hdl/src/vhdl
- doc
- proc_common_v3_00_a/hdl/src/vhdl
- dest_register_slice
- doc
- hdl
- sim
- synth
- sysc
- ila_1
- doc
- hdl
- verilog
- ila_v6_2/constraints
- sim
- synth
- ila_c2c
- doc
- hdl
- verilog
- ila_v6_2/constraints
- sim
- synth
- ila_vio_counter
- doc
- hdl
- verilog
- ila_v6_2/constraints
- sim
- synth
- pcie_bridge_ep
- doc
- hdl
- verilog
- ip_0
- ip_0
- hdl
- sim
- synth
- sim
- source
- synth
- ip_1
- hdl
- simulation
- sim
- synth
- ip_2
- hdl
- simulation
- sim
- synth
- sim
- source
- synth
- xdma_v4_1/hdl/verilog
- pcie_bridge_rc
- doc
- hdl
- verilog
- ip_0
- ip_0
- hdl
- sim
- synth
- sim
- source
- synth
- ip_1
- hdl
- simulation
- sim
- synth
- ip_2
- hdl
- simulation
- sim
- synth
- sim
- source
- synth
- xdma_v4_1/hdl/verilog
- src_register_slice
- doc
- hdl
- sim
- synth
- sysc
- vio_0
- doc
- hdl
- verilog
- sim
- synth
- cl_ip.hw
- cl_ip.ip_user_files
- bd
- cl_axi_sc_1x1
- ip/cl_axi_sc_1x1_smartconnect_0_0
- bd_0
- ip
- ip_0/sim
- ip_10/sim
- ip_11/sim
- ip_12/sim
- ip_13/sim
- ip_14/sim
- ip_1/sim
- ip_2/sim
- ip_3/sim
- ip_4/sim
- ip_5/sim
- ip_6/sim
- ip_7/sim
- ip_8/sim
- ip_9/sim
- sim
- sim
- sim
- cl_axi_sc_2x2
- ip/cl_axi_sc_2x2_smartconnect_0_0
- bd_0
- ip
- ip_0/sim
- ip_10/sim
- ip_11/sim
- ip_12/sim
- ip_13/sim
- ip_14/sim
- ip_15/sim
- ip_16/sim
- ip_17/sim
- ip_18/sim
- ip_19/sim
- ip_1/sim
- ip_20/sim
- ip_21/sim
- ip_22/sim
- ip_23/sim
- ip_24/sim
- ip_25/sim
- ip_26/sim
- ip_27/sim
- ip_28/sim
- ip_29/sim
- ip_2/sim
- ip_30/sim
- ip_31/sim
- ip_32/sim
- ip_33/sim
- ip_34/sim
- ip_35/sim
- ip_36/sim
- ip_37/sim
- ip_38/sim
- ip_3/sim
- ip_4/sim
- ip_5/sim
- ip_6/sim
- ip_7/sim
- ip_8/sim
- ip_9/sim
- sim
- sim
- sim
- ipstatic
- axi_infrastructure_v1_1_0/sim/axi_infrastructure_v1_1_0
- axi_register_slice_v2_1_30/sim/axi_register_slice_v2_1_30
- axi_vip_v1_1_16/sim/axi_vip_v1_1_16
- hdl
- verilog
- ip_1/simulation
- lib_cdc_v1_0_2/src/lib_cdc_v1_0_2
- pcie_bridge_ep/ip_1/simulation
- pcie_bridge_rc/ip_1/simulation
- proc_sys_reset_v5_0_14/src/proc_sys_reset_v5_0_14
- simulation
- smartconnect_v1_0
- sim/smartconnect_v1_0
- src/smartconnect_v1_0
- verif/model
- xlconstant_v1_1_8/src/xlconstant_v1_1_8
- ip
- axi_clock_converter_0
- axi_register_slice_light
- axi_register_slice
- cl_axi3_256b_reg_slice
- cl_axi4_to_axi3_conv
- cl_axi_clock_converter_256b
- cl_axi_clock_converter_light
- cl_axi_clock_converter
- cl_axi_interconnect_64G_ddr
- cl_axi_interconnect
- cl_axi_register_slice_256
- cl_axi_register_slice_light
- cl_axi_register_slice
- cl_axi_width_cnv_512_to_256
- cl_c2c_xbar_128G
- cl_clk_axil_xbar
- cl_ddr4_32g_ap
- cl_ddr4_32g
- cl_ddr4_64g_ap
- cl_ddr4
- cl_debug_bridge
- cl_hbm_mmcm
- cl_hbm
- cl_sda_axil_xbar
- clk_mmcm_a
- clk_mmcm_b
- clk_mmcm_c
- clk_mmcm_hbm
- dest_register_slice
- ila_1
- ila_c2c
- ila_vio_counter
- pcie_bridge_ep
- pcie_bridge_rc
- src_register_slice
- vio_0
- mem_init_files
- sim_scripts/axi_clock_converter_0
- activehdl
- modelsim
Some content is hidden
Large Commits have some content hidden by default. Use the searchbox below for content that may be hidden.
5,378 files changed
+1592
-11676615
lines changed| Original file line number | Diff line number | Diff line change | |
|---|---|---|---|
| |||
2 | 2 | | |
3 | 3 | | |
4 | 4 | | |
| 5 | + | |
| 6 | + | |
| 7 | + | |
| 8 | + | |
| Original file line number | Diff line number | Diff line change | |
|---|---|---|---|
| |||
42 | 42 | | |
43 | 43 | | |
44 | 44 | | |
| 45 | + | |
| 46 | + | |
| 47 | + | |
| 48 | + | |
| 49 | + | |
| 50 | + | |
| 51 | + | |
| 52 | + | |
| 53 | + | |
| 54 | + | |
| 55 | + | |
| 56 | + | |
| 57 | + | |
| 58 | + | |
| 59 | + | |
| 60 | + | |
| 61 | + | |
| 62 | + | |
| 63 | + | |
| 64 | + | |
| 65 | + | |
| 66 | + | |
| 67 | + | |
| 68 | + | |
45 | 69 | | |
46 | 70 | | |
47 | | - | |
| 71 | + | |
48 | 72 | | |
49 | | - | |
| 73 | + | |
50 | 74 | | |
51 | 75 | | |
| Original file line number | Diff line number | Diff line change | |
|---|---|---|---|
| |||
1 | 1 | | |
2 | 2 | | |
| 3 | + | |
| 4 | + | |
| 5 | + | |
| 6 | + | |
| 7 | + | |
| 8 | + | |
3 | 9 | | |
4 | 10 | | |
5 | 11 | | |
| |||
| Original file line number | Diff line number | Diff line change | |
|---|---|---|---|
| |||
14 | 14 | | |
15 | 15 | | |
16 | 16 | | |
17 | | - | |
18 | 17 | | |
19 | 18 | | |
20 | 19 | | |
| |||
47 | 46 | | |
48 | 47 | | |
49 | 48 | | |
50 | | - | |
| 49 | + | |
51 | 50 | | |
52 | 51 | | |
53 | 52 | | |
| |||
154 | 153 | | |
155 | 154 | | |
156 | 155 | | |
157 | | - | |
158 | | - | |
159 | | - | |
160 | | - | |
161 | | - | |
| 156 | + | |
| 157 | + | |
| 158 | + | |
| 159 | + | |
162 | 160 | | |
163 | 161 | | |
164 | 162 | | |
| |||
181 | 179 | | |
182 | 180 | | |
183 | 181 | | |
| 182 | + | |
184 | 183 | | |
185 | 184 | | |
186 | 185 | | |
187 | 186 | | |
188 | 187 | | |
189 | 188 | | |
190 | | - | |
191 | | - | |
192 | 189 | | |
193 | 190 | | |
194 | 191 | | |
| |||
| Original file line number | Diff line number | Diff line change | |
|---|---|---|---|
| |||
2 | 2 | | |
3 | 3 | | |
4 | 4 | | |
5 | | - | |
| 5 | + | |
6 | 6 | | |
7 | 7 | | |
8 | 8 | | |
| |||
| Original file line number | Diff line number | Diff line change | |
|---|---|---|---|
| |||
71 | 71 | | |
72 | 72 | | |
73 | 73 | | |
74 | | - | |
| 74 | + | |
| 75 | + | |
| 76 | + | |
| 77 | + | |
| 78 | + | |
| 79 | + | |
| 80 | + | |
| 81 | + | |
| 82 | + | |
| 83 | + | |
| 84 | + | |
| 85 | + | |
| 86 | + | |
| 87 | + | |
| 88 | + | |
| 89 | + | |
| 90 | + | |
| 91 | + | |
| 92 | + | |
| 93 | + | |
| 94 | + | |
| 95 | + | |
| 96 | + | |
| 97 | + | |
| 98 | + | |
| 99 | + | |
| 100 | + | |
| 101 | + | |
| 102 | + | |
75 | 103 | | |
76 | 104 | | |
77 | 105 | | |
78 | 106 | | |
79 | | - | |
| 107 | + | |
80 | 108 | | |
81 | | - | |
| 109 | + | |
82 | 110 | | |
83 | 111 | | |
84 | 112 | | |
| |||
| Original file line number | Diff line number | Diff line change | |
|---|---|---|---|
| |||
1 | 1 | | |
2 | 2 | | |
3 | 3 | | |
| 4 | + | |
| 5 | + | |
| 6 | + | |
| 7 | + | |
| 8 | + | |
| 9 | + | |
| 10 | + | |
| 11 | + | |
4 | 12 | | |
5 | 13 | | |
6 | 14 | | |
| |||
Lines changed: 30 additions & 34 deletions
| Original file line number | Diff line number | Diff line change | |
|---|---|---|---|
| |||
4 | 4 | | |
5 | 5 | | |
6 | 6 | | |
7 | | - | |
| 7 | + | |
8 | 8 | | |
9 | | - | |
| 9 | + | |
| 10 | + | |
| 11 | + | |
| 12 | + | |
10 | 13 | | |
11 | | - | |
12 | | - | |
13 | | - | |
14 | | - | |
| 14 | + | |
| 15 | + | |
15 | 16 | | |
16 | | - | |
17 | | - | |
| 17 | + | |
| 18 | + | |
| 19 | + | |
| 20 | + | |
| 21 | + | |
| 22 | + | |
18 | 23 | | |
19 | | - | |
20 | | - | |
21 | | - | |
22 | | - | |
23 | | - | |
24 | | - | |
| 24 | + | |
25 | 25 | | |
26 | | - | |
| 26 | + | |
27 | 27 | | |
28 | | - | |
29 | | - | |
30 | | - | |
31 | | - | |
32 | | - | |
| 28 | + | |
33 | 29 | | |
34 | 30 | | |
35 | 31 | | |
| |||
65 | 61 | | |
66 | 62 | | |
67 | 63 | | |
68 | | - | |
69 | | - | |
| 64 | + | |
| 65 | + | |
70 | 66 | | |
71 | 67 | | |
72 | 68 | | |
| |||
130 | 126 | | |
131 | 127 | | |
132 | 128 | | |
133 | | - | |
| 129 | + | |
134 | 130 | | |
135 | 131 | | |
136 | 132 | | |
| |||
294 | 290 | | |
295 | 291 | | |
296 | 292 | | |
297 | | - | |
| 293 | + | |
298 | 294 | | |
299 | | - | |
300 | | - | |
301 | 295 | | |
302 | | - | |
303 | | - | |
| 296 | + | |
| 297 | + | |
| 298 | + | |
| 299 | + | |
| 300 | + | |
| 301 | + | |
304 | 302 | | |
305 | | - | |
306 | 303 | | |
307 | 304 | | |
308 | 305 | | |
| |||
357 | 354 | | |
358 | 355 | | |
359 | 356 | | |
| 357 | + | |
| 358 | + | |
| 359 | + | |
| 360 | + | |
360 | 361 | | |
361 | 362 | | |
362 | 363 | | |
| |||
373 | 374 | | |
374 | 375 | | |
375 | 376 | | |
376 | | - | |
377 | | - | |
378 | | - | |
379 | | - | |
380 | | - | |
381 | 377 | | |
382 | 378 | | |
383 | 379 | | |
| |||
| Original file line number | Diff line number | Diff line change | |
|---|---|---|---|
| |||
9 | 9 | | |
10 | 10 | | |
11 | 11 | | |
12 | | - | |
| 12 | + | |
13 | 13 | | |
14 | 14 | | |
15 | 15 | | |
| |||
| Original file line number | Diff line number | Diff line change | |
|---|---|---|---|
| |||
10 | 10 | | |
11 | 11 | | |
12 | 12 | | |
13 | | - | |
| 13 | + | |
14 | 14 | | |
15 | | - | |
| 15 | + | |
16 | 16 | | |
17 | 17 | | |
18 | 18 | | |
| |||
135 | 135 | | |
136 | 136 | | |
137 | 137 | | |
| 138 | + | |
| 139 | + | |
138 | 140 | | |
139 | 141 | | |
140 | 142 | | |
| |||
199 | 201 | | |
200 | 202 | | |
201 | 203 | | |
| 204 | + | |
| 205 | + | |
202 | 206 | | |
203 | 207 | | |
204 | 208 | | |
| |||
0 commit comments