Release v1.4.20 (#524)

kyyalama2 · web-flow · commit b56533a890e6 · 2021-06-23T08:08:28.000-05:00
* Bug Fix release to fix XDMA to fix Issue #516 * Miscallaneous documentation updates
diff --git a/ERRATA.md b/ERRATA.md
@@ -7,7 +7,8 @@ Shell errata is [documented here](./hdk/docs/AWS_Shell_ERRATA.md)
 ## HDK
 * Multiple SDE instances per CL is not supported in this release. Support is planned for a future release.
 * DRAM Data retention is not supported for CL designs with less than 4 DDRs enabled
-* Combinatorial loops in CL designs are not supported.  
+* Combinatorial loops in CL designs are not supported.
+  * We will display a `UNKNOWN_BITSTREAM_GENERATE_ERROR` on detection of a combinatorial loop in the CL design and an AFI will not be generated.
 * Connecting one of the clocks provided from the shell (clk_main_a0, clk_extra_a1, etc...) directly to a BUFG in the CL is not supported by the Xilinx tools and may result in a non-functional clock. To workaround this limitation, it is recommended to use an MMCM to feed the BUFG (clk_from_shell -> MMCM -> BUFG). Please refer to [Xilinx AR# 73360](https://www.xilinx.com/support/answers/73360.html) for further details.
 
 ### flop_ccf.sv bug
diff --git a/Vitis/README.md b/Vitis/README.md
@@ -200,7 +200,7 @@ For help with AFI creation issues, see [create-fpga-image error codes](../hdk/do
     $ cd $AWS_FPGA_REPO_DIR
     $ source vitis_runtime_setup.sh   # Other runtime env settings needed by the host app should be setup after this step
     # Wait till the MPD service has initialized. Check systemctl status mpd
-    $ ./host ./vadd.awsxclbin 
+    $ ./hello_world ./vadd.awsxclbin 
     ```
 * The runtime setup script also starts the Xilinx XRT Message Proxy Daemon(MPD) service. To learn more about the XRT implementation, check the [XRT Instructions](./docs/XRT_installation_instructions.md#mpd)
 
diff --git a/Vitis/docs/Alveo_to_AWS_F1_Migration/example/README.md b/Vitis/docs/Alveo_to_AWS_F1_Migration/example/README.md
@@ -46,7 +46,7 @@ The [`u200`](./u200) and  The [`u200`](./u200) and [`f1`](./f1) directories cont
     sp=vadd_1.out:DDR[1]
     ```
 
-    * The `platform` option specifies which acceleration platform is targeted for the build. Here we are using the U200 shell.
+    * The `platform` option specifies which acceleration platform is targeted for the build. Here we are using the U200 shell. 
     * The `sp` options are used to specify the assignment of kernel arguments to DDR banks. In this case, we are mapping all three kernel arguments to DDR[1], which is the DDR interface located in the shell on Alveo U200.
     
     > Putting all the platform-specific options in one file is not mandatory but it is very convenient and facilitates the porting process. With this approach, the main command line can be reused as is for all platforms. Refer to the [Vitis Documentation](https://www.xilinx.com/html_docs/xilinx2020_1/vitis_doc/kme1569523964461.html) for more information on v++ related commands and options. 
@@ -70,7 +70,8 @@ In order to port the vector-add example from Alveo U200 to AWS F1, the only chan
     sp=vadd_1.out:DDR[0]
     ```
     
-    * The `platform` option is set to target the AWS F1 shell. The string used corresponds to the name of the latest shell which can be found [here](https://github.com/aws/aws-fpga/tree/master/Vitis/aws_platform) on the aws-fpga repo.
+    * The `platform` option is set to target the AWS F1 shell. The string used corresponds to the name of the latest shell which can be found [here](https://github.com/aws/aws-fpga/tree/master/Vitis/aws_platform) on the aws-fpga repo. Point the platform to the xpfm file. For example, 
+    ```platform=$AWS_PLATFORM```
     * The `sp` options are set to connect the kernel arguments to DDR[0], which is the DDR interface located in the AWS F1 shell. Keeping the same settings as the U200 would produce a working design on AWS F1. But in order to produce exactly the same configuration and target the DDR interface located in the AWS F1 shell, the sp options are modified to use DDR[0].
 
     These changes are the only ones needed to port this project from U200 to F1. 
@@ -84,7 +85,7 @@ In order to port the vector-add example from Alveo U200 to AWS F1, the only chan
 
     v++ -c -g -t hw -R 1 -k vadd --config ./options.cfg --profile_kernel data:all:all:all --profile_kernel stall:all:all:all --save-temps --temp_dir ./temp_dir --report_dir ./report_dir --log_dir ./log_dir -I../src ../src/vadd.cpp -o ./vadd.hw.xo
     
-    v++ -l -g -t hw -R 1 --config ./options.cfg --profile_kernel data:all:all:all --profile_kernel stall:all:all:all --temp_dir ./temp_dir --report_dir ./report_dir --log_dir ./log_dir -I../src vadd.hw.xo -o add.hw.xclbin    
+    v++ -l -g -t hw -R 1 --config ./options.cfg --profile_kernel data:all:all:all --profile_kernel stall:all:all:all --temp_dir ./temp_dir --report_dir ./report_dir --log_dir ./log_dir -I../src vadd.hw.xo -o vadd.xclbin    
     ```
     
     *NOTE: The PLATFORM_REPO_PATHS environment variable is used to specify the directory where the AWS platform (xilinx_aws-vu9p-f1_shell-v04261818_201920_2) is installed.*
diff --git a/hdk/cl/examples/cl_dram_dma/verif/scripts/Makefile.ies b/hdk/cl/examples/cl_dram_dma/verif/scripts/Makefile.ies
@@ -38,6 +38,6 @@ else
 endif
 
 $(COMPLIB_DIR):
-	cd $(SIM_ROOT) && echo "compile_simlib -language all -dir $(COMPLIB_DIR) -simulator $(SIMULATOR) -library all -family  all" > create_libs.tcl
+	cd $(SIM_ROOT) && echo "compile_simlib -language all -dir $(COMPLIB_DIR) -simulator $(SIMULATOR) -no_systemc_compile -library all -family  all" > create_libs.tcl
 	-cd $(SIM_ROOT) && vivado -mode batch -source create_libs.tcl
 	cd $(SIM_ROOT) && rm -rf create_libs.tcl
diff --git a/hdk/cl/examples/cl_dram_dma/verif/scripts/Makefile.questa b/hdk/cl/examples/cl_dram_dma/verif/scripts/Makefile.questa
@@ -40,7 +40,7 @@ else
 endif
 
 $(COMPLIB_DIR):
-	cd $(SIM_ROOT) && echo "compile_simlib -language all -dir $(COMPLIB_DIR) -simulator $(SIMULATOR) -library all -family  all" > create_libs.tcl
+	cd $(SIM_ROOT) && echo "compile_simlib -language all -dir $(COMPLIB_DIR) -simulator $(SIMULATOR) -no_systemc_compile -library all -family  all" > create_libs.tcl
 	cd $(SIM_ROOT) && vivado -mode batch -source create_libs.tcl
 	cd $(SIM_ROOT) && rm -rf create_libs.tcl 
 
diff --git a/hdk/cl/examples/cl_dram_dma/verif/scripts/Makefile.vcs b/hdk/cl/examples/cl_dram_dma/verif/scripts/Makefile.vcs
@@ -38,6 +38,6 @@ else
 endif
 
 $(COMPLIB_DIR):
-	cd $(SIM_ROOT) && echo "compile_simlib -language all -dir $(COMPLIB_DIR) -simulator $(SIMULATOR) -library all -family  all" > create_libs.tcl
+	cd $(SIM_ROOT) && echo "compile_simlib -language all -dir $(COMPLIB_DIR) -simulator $(SIMULATOR) -no_systemc_compile -library all -family  all" > create_libs.tcl
 	-cd $(SIM_ROOT) && vivado -mode batch -source create_libs.tcl
 	cd $(SIM_ROOT) && rm -rf create_libs.tcl
diff --git a/hdk/cl/examples/cl_hello_world/verif/scripts/Makefile.ies b/hdk/cl/examples/cl_hello_world/verif/scripts/Makefile.ies
@@ -38,6 +38,6 @@ else
 endif
 
 $(COMPLIB_DIR):
-	cd $(SIM_ROOT) && echo "compile_simlib -language all -dir $(COMPLIB_DIR) -simulator $(SIMULATOR) -library all -family  all" > create_libs.tcl
+	cd $(SIM_ROOT) && echo "compile_simlib -language all -dir $(COMPLIB_DIR) -simulator $(SIMULATOR) -no_systemc_compile -library all -family  all" > create_libs.tcl
 	-cd $(SIM_ROOT) && vivado -mode batch -source create_libs.tcl
 	cd $(SIM_ROOT) && rm -rf create_libs.tcl
diff --git a/hdk/cl/examples/cl_hello_world/verif/scripts/Makefile.questa b/hdk/cl/examples/cl_hello_world/verif/scripts/Makefile.questa
@@ -39,7 +39,7 @@ else
 endif
 
 $(COMPLIB_DIR):
-	cd $(SIM_ROOT) && echo "compile_simlib -language all -dir $(COMPLIB_DIR) -simulator $(SIMULATOR) -library all -family  all" > create_libs.tcl
+	cd $(SIM_ROOT) && echo "compile_simlib -language all -dir $(COMPLIB_DIR) -simulator $(SIMULATOR) -no_systemc_compile -library all -family  all" > create_libs.tcl
 	cd $(SIM_ROOT) && vivado -mode batch -source create_libs.tcl
 	cd $(SIM_ROOT) && rm -rf create_libs.tcl
 
diff --git a/hdk/cl/examples/cl_hello_world/verif/scripts/Makefile.vcs b/hdk/cl/examples/cl_hello_world/verif/scripts/Makefile.vcs
@@ -37,6 +37,6 @@ else
 endif
 
 $(COMPLIB_DIR):
-	cd $(SIM_ROOT) && echo "compile_simlib -language all -dir $(COMPLIB_DIR) -simulator $(SIMULATOR) -library all -family  all" > create_libs.tcl
+	cd $(SIM_ROOT) && echo "compile_simlib -language all -dir $(COMPLIB_DIR) -simulator $(SIMULATOR) -no_systemc_compile -library all -family  all" > create_libs.tcl
 	-cd $(SIM_ROOT) && vivado -mode batch -source create_libs.tcl
-	cd $(SIM_ROOT) && rm -rf create_libs.tcl
+	cd $(SIM_ROOT) && rm -rf create_libs.tcl
diff --git a/hdk/cl/examples/cl_hello_world_vhdl/verif/scripts/Makefile.questa b/hdk/cl/examples/cl_hello_world_vhdl/verif/scripts/Makefile.questa
@@ -36,7 +36,7 @@ run:
 	cd $(SIM_DIR) &&  vsim -c -voptargs="+acc" -64 -t ps -sv_seed random $(LIBLISTS_ARGS) -do "run -all; quit -f" tb glbl $(TEST)
 
 $(COMPLIB_DIR):
-	cd $(SIM_ROOT) && echo "compile_simlib -language all -dir $(COMPLIB_DIR) -simulator $(SIMULATOR) -library all -family  all" > create_libs.tcl
+	cd $(SIM_ROOT) && echo "compile_simlib -language all -dir $(COMPLIB_DIR) -simulator $(SIMULATOR) -no_systemc_compile -library all -family  all" > create_libs.tcl
 	cd $(SIM_ROOT) && vivado -mode batch -source create_libs.tcl
 	cd $(SIM_ROOT) && rm -rf create_libs.tcl 
 
diff --git a/hdk/cl/examples/cl_hello_world_vhdl/verif/scripts/Makefile.vcs b/hdk/cl/examples/cl_hello_world_vhdl/verif/scripts/Makefile.vcs
@@ -33,6 +33,6 @@ run:
 	cd $(SIM_DIR) && ./simv -l $(TEST).log $(PLUSARGS) +ntb_random_seed_automatic +vpdfile+$(TEST).vpd
 
 $(COMPLIB_DIR):
-	cd $(SIM_ROOT) && echo "compile_simlib -language all -dir $(COMPLIB_DIR) -simulator $(SIMULATOR) -library all -family  all" > create_libs.tcl
+	cd $(SIM_ROOT) && echo "compile_simlib -language all -dir $(COMPLIB_DIR) -simulator $(SIMULATOR) -no_systemc_compile -library all -family  all" > create_libs.tcl
 	-cd $(SIM_ROOT) && vivado -mode batch -source create_libs.tcl
 	cd $(SIM_ROOT) && rm -rf create_libs.tcl
diff --git a/hdk/cl/examples/cl_sde/README.md b/hdk/cl/examples/cl_sde/README.md
@@ -8,6 +8,8 @@
 3. [Software](#Software)
 3. [Metadata](#Metadata)
 
+⚠️**Note**: Please note that Virtual Ethernet/SDE is not supported by Vitis (XRT)
+
 <a name="Overview"></a>
 ## Overview
 The CL_SDE example implements the FPGA custom logic used to generate the AFI to demonstrate the [Virtual Ethernet Application](../../../../sdk/apps/virtual-ethernet/doc/Virtual_Ethernet_Application_Guide.md). The CL_SDE demonstrates the following - 
diff --git a/hdk/cl/examples/cl_sde/verif/scripts/Makefile.ies b/hdk/cl/examples/cl_sde/verif/scripts/Makefile.ies
@@ -38,6 +38,6 @@ else
 endif
 
 $(COMPLIB_DIR):
-	cd $(SIM_ROOT) && echo "compile_simlib -language all -dir $(COMPLIB_DIR) -simulator $(SIMULATOR) -library all -family  all" > create_libs.tcl
+	cd $(SIM_ROOT) && echo "compile_simlib -language all -dir $(COMPLIB_DIR) -simulator $(SIMULATOR) -no_systemc_compile -library all -family  all" > create_libs.tcl
 	-cd $(SIM_ROOT) && vivado -mode batch -source create_libs.tcl
 	cd $(SIM_ROOT) && rm -rf create_libs.tcl
diff --git a/hdk/cl/examples/cl_sde/verif/scripts/Makefile.questa b/hdk/cl/examples/cl_sde/verif/scripts/Makefile.questa
@@ -39,7 +39,7 @@ else
 endif
 
 $(COMPLIB_DIR):
-	cd $(SIM_ROOT)/.. && echo "compile_simlib -language all -dir $(COMPLIB_DIR) -simulator $(SIMULATOR) -library all -family  all" > create_libs.tcl
+	cd $(SIM_ROOT)/.. && echo "compile_simlib -language all -dir $(COMPLIB_DIR) -simulator $(SIMULATOR) -no_systemc_compile -library all -family  all" > create_libs.tcl
 	cd $(SIM_ROOT)/.. && vivado -mode batch -source create_libs.tcl
 	cd $(SIM_ROOT)/.. && rm -rf create_libs.tcl 
 
diff --git a/hdk/cl/examples/cl_sde/verif/scripts/Makefile.vcs b/hdk/cl/examples/cl_sde/verif/scripts/Makefile.vcs
@@ -32,6 +32,6 @@ run:
 	cd $(SIM_DIR) && ./simv -l $(TEST).log $(PLUSARGS) +ntb_random_seed_automatic +vpdfile+$(TEST).vpd
 
 $(COMPLIB_DIR):
-	cd $(SIM_ROOT) && echo "compile_simlib -language all -dir $(COMPLIB_DIR) -simulator $(SIMULATOR) -library all -family  all" > create_libs.tcl
+	cd $(SIM_ROOT) && echo "compile_simlib -language all -dir $(COMPLIB_DIR) -simulator $(SIMULATOR) -no_systemc_compile -library all -family  all" > create_libs.tcl
 	-cd $(SIM_ROOT) && vivado -mode batch -source create_libs.tcl
 	cd $(SIM_ROOT) && rm -rf create_libs.tcl
diff --git a/hdk/cl/examples/cl_uram_example/verif/scripts/Makefile.ies b/hdk/cl/examples/cl_uram_example/verif/scripts/Makefile.ies
@@ -39,6 +39,6 @@ else
 endif
 
 $(COMPLIB_DIR):
-	cd $(SIM_ROOT) && echo "compile_simlib -language all -dir $(COMPLIB_DIR) -simulator $(SIMULATOR) -library all -family  all" > create_libs.tcl
+	cd $(SIM_ROOT) && echo "compile_simlib -language all -dir $(COMPLIB_DIR) -simulator $(SIMULATOR) -no_systemc_compile -library all -family  all" > create_libs.tcl
 	-cd $(SIM_ROOT) && vivado -mode batch -source create_libs.tcl
 	cd $(SIM_ROOT) && rm -rf create_libs.tcl
diff --git a/hdk/cl/examples/cl_uram_example/verif/scripts/Makefile.questa b/hdk/cl/examples/cl_uram_example/verif/scripts/Makefile.questa
@@ -40,7 +40,7 @@ else
 endif
 
 $(COMPLIB_DIR):
-	cd $(SIM_ROOT) && echo "compile_simlib -language all -dir $(COMPLIB_DIR) -simulator $(SIMULATOR) -library all -family  all" > create_libs.tcl
+	cd $(SIM_ROOT) && echo "compile_simlib -language all -dir $(COMPLIB_DIR) -simulator $(SIMULATOR) -no_systemc_compile -library all -family  all" > create_libs.tcl
 	cd $(SIM_ROOT) && vivado -mode batch -source create_libs.tcl
 	cd $(SIM_ROOT) && rm -rf create_libs.tcl 
 
diff --git a/hdk/cl/examples/cl_uram_example/verif/scripts/Makefile.vcs b/hdk/cl/examples/cl_uram_example/verif/scripts/Makefile.vcs
@@ -38,6 +38,6 @@ else
 endif
 
 $(COMPLIB_DIR):
-	cd $(SIM_ROOT) && echo "compile_simlib -language all -dir $(COMPLIB_DIR) -simulator $(SIMULATOR) -library all -family  all" > create_libs.tcl
+	cd $(SIM_ROOT) && echo "compile_simlib -language all -dir $(COMPLIB_DIR) -simulator $(SIMULATOR) -no_systemc_compile -library all -family  all" > create_libs.tcl
 	-cd $(SIM_ROOT) && vivado -mode batch -source create_libs.tcl
-	cd $(SIM_ROOT) && rm -rf create_libs.tcl
+	cd $(SIM_ROOT) && rm -rf create_libs.tcl
diff --git a/hdk/docs/create_fpga_image_error_codes.md b/hdk/docs/create_fpga_image_error_codes.md
@@ -58,5 +58,9 @@ Errors can occurs when calling this API and this document provides the specifica
  
 * `DCP_NOT_ENCRYPTED`
       *The DCP was not encrypted*
-
-
+  
+* `UNKNOWN_BITSTREAM_GENERATE_ERROR`
+      *An error occurred generating the FPGA image bitstream. If an S3 LogsStorageLocation was provided in the CreateFpgaImage request, review the captured bitstream generation logs saved to S3 under the FpgaImageId for this AFI.*
+  * **Note:** This is a catch-all error and could be caused due to a variety of issues, for eg:
+      * We found a combinatorial loop in the CL design. Bitstream generation logs might show errors like `ERROR: [DRC LUTLP-1] Combinatorial Loop Alert: 2 LUT cells form a combinatorial loop.
+      Combinatorial loops are not allowed in CL designs and AFI's are not generated in such a case. 
diff --git a/sdk/apps/virtual-ethernet/README.md b/sdk/apps/virtual-ethernet/README.md
@@ -2,6 +2,8 @@
 
 The Virtual Ethernet framework facilitates streaming Ethernet frames from a network interface (or any source) into the FPGA for processing and back out to some destination. Possible use cases for this include deep packet inspection, software defined networking, stream encryption or compression, and more.
 
+⚠️**Note**: Please note that Virtual Ethernet/SDE is not supported by Vitis (XRT)
+
 ## Prerequisites
 
 In order to get the most from this document, readers may want to familiarize themselves with the following:
diff --git a/sdk/apps/virtual-ethernet/doc/Virtual_Ethernet_Application_Guide.md b/sdk/apps/virtual-ethernet/doc/Virtual_Ethernet_Application_Guide.md
@@ -99,7 +99,7 @@ Testpmd application setup and start phase
 
 ```
 cd <install_dir>/dpdk
-./x86_64-native-linuxapp-gcc/app/testpmd -l 0-1  -- --port-topology=chained --auto-start --stats-period=3 --forward-mode=spp-eni-addr-swap
+sudo ./x86_64-native-linuxapp-gcc/app/testpmd -l 0-1  -- --port-topology=chained --auto-start --stats-period=3 --forward-mode=spp-eni-addr-swap
 ```
 
 The `spp-eni-addr-swap` testpmd forwarding mode swaps the Ethernet MAC and IP addresses so the Packet Generator instance can receive the loopback Ethernet frames.
@@ -141,7 +141,7 @@ start 0
 
 ```
 cd <install_dir>/pktgen-dpdk
-./app/x86_64-native-linuxapp-gcc/pktgen -l 0,1 -n 4 --proc-type auto --log-level 7 --socket-mem 2048 --file-prefix pg -b 00:03.0 -- -T -P -m [1].0 -f $(SDK_DIR)/apps/virtual-ethernet/scripts/pktgen-ena.pkt
+sudo ./app/x86_64-native-linuxapp-gcc/pktgen -l 0,1 -n 4 --proc-type auto --log-level 7 --socket-mem 2048 --file-prefix pg -b 00:03.0 -- -T -P -m [1].0 -f $(SDK_DIR)/apps/virtual-ethernet/scripts/pktgen-ena.pkt
 ```
 
 Also provided is a sample Packet Generator `pktgen-ena-range.pkt` script.  This script will need to be modified to work with your F1 instances.  `pktgen-ena-range.pkt` varies the source and destination UDP ports but leaves the size at 64B to show PPS performance using multiple UDP flows.
diff --git a/sdk/linux_kernel_drivers/xdma/libxdma.c b/sdk/linux_kernel_drivers/xdma/libxdma.c
@@ -53,6 +53,21 @@ unsigned int desc_blen_max = XDMA_DESC_BLEN_MAX;
 module_param(desc_blen_max, uint, 0644);
 MODULE_PARM_DESC(desc_blen_max, "per descriptor max. buffer length, default is (1 << 28) - 1");
 
+/*
+ * make sure to wait till the timeout even if
+ * wait_event_interruptible_timeout was interrupted
+ */
+#define xdma_wait_event_timeout(wq, condition, timeout) \
+({ \
+	int __ret = 0;  \
+	unsigned long expire = timeout + jiffies; \
+	do { \
+		__ret = wait_event_interruptible_timeout(wq, condition, \
+						timeout); \
+	} while ((__ret < 0) && (jiffies < expire)); \
+	__ret; \
+})
+
 /*
  * xdma device management
  * maintains a list of the xdma devices
@@ -3177,7 +3192,7 @@ ssize_t xdma_xfer_submit(void *dev_hndl, int channel, bool write, u64 ep_addr,
 			rv = engine_service_poll(engine, desc_count);
 
 		} else {
-			rv = wait_event_interruptible_timeout(xfer->wq,
+			rv = xdma_wait_event_timeout(xfer->wq,
                 	        (xfer->state != TRANSFER_STATE_SUBMITTED),
 				msecs_to_jiffies(timeout_ms));
 		}
@@ -4012,15 +4027,15 @@ static int transfer_monitor_cyclic(struct xdma_engine *engine,
 		if (enable_credit_mp){
 			dbg_tfr("%s: rx_head=%d,rx_tail=%d, wait ...\n",
 				engine->name, engine->rx_head, engine->rx_tail);
-			rc = wait_event_interruptible_timeout( transfer->wq,
+			rc = xdma_wait_event_timeout(transfer->wq,
 					(engine->rx_head!=engine->rx_tail ||
 					 engine->rx_overrun),
 					msecs_to_jiffies(timeout_ms));
 			dbg_tfr("%s: wait returns %d, rx %d/%d, overrun %d.\n",
 				 engine->name, rc, engine->rx_head,
 				engine->rx_tail, engine->rx_overrun);
 		} else {
-			rc = wait_event_interruptible_timeout( transfer->wq,
+			rc = xdma_wait_event_timeout(transfer->wq,
 					engine->eop_found,
 					msecs_to_jiffies(timeout_ms));
 			dbg_tfr("%s: wait returns %d, eop_found %d.\n",
@@ -4452,7 +4467,7 @@ static int cyclic_shutdown_interrupt(struct xdma_engine *engine)
 		return -EINVAL;
 	}
 
-	rc = wait_event_interruptible_timeout(engine->shutdown_wq,
+	rc = xdma_wait_event_timeout(engine->shutdown_wq,
 				!engine->running, msecs_to_jiffies(10000));
 	if (engine->running) {
 		pr_info("%s still running?!, %d\n", engine->name, rc);
