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History / Digital System Routing

Revisions

  • Fix up headings

    @d235j d235j committed Aug 15, 2017
    03f8391

  • Added diagram with hseg wire to HS register mapping

    @lowfatcomputing lowfatcomputing committed Jan 17, 2017
    9a04aa0

  • Rawgit links should use the CDN so we don't get rate-limited

    @cyrozap cyrozap committed Dec 15, 2016
    ce4d2fe

  • fixed anchor link "pld-port-interface-pi-tiles" under DSI Input section

    @lowfatcomputing lowfatcomputing committed Oct 5, 2016
    3008906

  • Under PLD PI tile section, explain that U1 is not always the upper UDB and U0 is not always the lower UDB.

    @lowfatcomputing lowfatcomputing committed Oct 5, 2016
    349e559

  • CDN urls never update. Using non-CDN url for non-primary source image.

    @lowfatcomputing lowfatcomputing committed Oct 5, 2016
    6faff8b

  • Made an image of the two UDB banks with DSI, PRT tiles labeled. Also, notice the pattern with U1 and U0.

    @lowfatcomputing lowfatcomputing committed Oct 4, 2016
    337cd95

  • PI Tiles connect with HC Tiles. Ordered those sections accordingly.

    @lowfatcomputing lowfatcomputing committed Sep 27, 2016
    48a511b

  • should have been called "Digital System Routing"

    @lowfatcomputing lowfatcomputing committed Sep 27, 2016
    45984f8