diff --git a/include/tcp_pkg.sv b/include/tcp_pkg.sv index 9bc304c..c7a972b 100644 --- a/include/tcp_pkg.sv +++ b/include/tcp_pkg.sv @@ -13,6 +13,11 @@ package tcp_pkg; localparam RX_PAYLOAD_PTR_W = PAYLOAD_PTR_W; localparam TX_PAYLOAD_PTR_W = PAYLOAD_PTR_W; + // TODO: idx width? + + localparam MALLOC_LEN_MAX = 9216; + localparam MALLOC_LEN_W = $clog2(MALLOC_LEN_MAX); + localparam RT_ACK_THRESHOLD = 3; localparam RT_ACK_THRESHOLD_W = $clog2(RT_ACK_THRESHOLD) + 1; diff --git a/rx_buf_ptrs.sv b/rx_buf_ptrs.sv index 70a896c..4041b8b 100644 --- a/rx_buf_ptrs.sv +++ b/rx_buf_ptrs.sv @@ -1,204 +1,204 @@ -module rx_buf_ptrs +module rx_buf_idxs import tcp_pkg::*; ( input clk ,input rst - ,input head_ptr_wr_req_val - ,input [FLOWID_W-1:0] head_ptr_wr_req_addr - ,input [RX_PAYLOAD_PTR_W:0] head_ptr_wr_req_data - ,output head_ptr_wr_req_rdy - - ,input head_ptr_rd0_req_val - ,input [FLOWID_W-1:0] head_ptr_rd0_req_addr - ,output logic head_ptr_rd0_req_rdy - - ,output logic head_ptr_rd0_resp_val - ,output logic [RX_PAYLOAD_PTR_W:0] head_ptr_rd0_resp_data - ,input head_ptr_rd0_resp_rdy + ,input head_idx_wr_req_val + ,input [FLOWID_W-1:0] head_idx_wr_req_addr + ,input tcp_buf_idx head_idx_wr_req_data + ,output head_idx_wr_req_rdy + + ,input head_idx_rd0_req_val + ,input [FLOWID_W-1:0] head_idx_rd0_req_addr + ,output logic head_idx_rd0_req_rdy + + ,output logic head_idx_rd0_resp_val + ,output tcp_buf_idx head_idx_rd0_resp_data + ,input head_idx_rd0_resp_rdy - ,input head_ptr_rd1_req_val - ,input [FLOWID_W-1:0] head_ptr_rd1_req_addr - ,output logic head_ptr_rd1_req_rdy + ,input head_idx_rd1_req_val + ,input [FLOWID_W-1:0] head_idx_rd1_req_addr + ,output logic head_idx_rd1_req_rdy - ,output logic head_ptr_rd1_resp_val - ,output logic [RX_PAYLOAD_PTR_W:0] head_ptr_rd1_resp_data - ,input head_ptr_rd1_resp_rdy + ,output logic head_idx_rd1_resp_val + ,output tcp_buf_idx head_idx_rd1_resp_data + ,input head_idx_rd1_resp_rdy - ,input commit_ptr_wr_req_val - ,input [FLOWID_W-1:0] commit_ptr_wr_req_addr - ,input [RX_PAYLOAD_PTR_W:0] commit_ptr_wr_req_data - ,output commit_ptr_wr_req_rdy - - ,input commit_ptr_rd0_req_val - ,input [FLOWID_W-1:0] commit_ptr_rd0_req_addr - ,output logic commit_ptr_rd0_req_rdy - - ,output logic commit_ptr_rd0_resp_val - ,output logic [RX_PAYLOAD_PTR_W:0] commit_ptr_rd0_resp_data - ,input commit_ptr_rd0_resp_rdy + ,input commit_idx_wr_req_val + ,input [FLOWID_W-1:0] commit_idx_wr_req_addr + ,input tcp_buf_idx commit_idx_wr_req_data + ,output commit_idx_wr_req_rdy + + ,input commit_idx_rd0_req_val + ,input [FLOWID_W-1:0] commit_idx_rd0_req_addr + ,output logic commit_idx_rd0_req_rdy + + ,output logic commit_idx_rd0_resp_val + ,output tcp_buf_idx commit_idx_rd0_resp_data + ,input commit_idx_rd0_resp_rdy - ,input commit_ptr_rd1_req_val - ,input [FLOWID_W-1:0] commit_ptr_rd1_req_addr - ,output logic commit_ptr_rd1_req_rdy + ,input commit_idx_rd1_req_val + ,input [FLOWID_W-1:0] commit_idx_rd1_req_addr + ,output logic commit_idx_rd1_req_rdy - ,output logic commit_ptr_rd1_resp_val - ,output logic [RX_PAYLOAD_PTR_W:0] commit_ptr_rd1_resp_data - ,input commit_ptr_rd1_resp_rdy + ,output logic commit_idx_rd1_resp_val + ,output tcp_buf_idx commit_idx_rd1_resp_data + ,input commit_idx_rd1_resp_rdy - ,input tail_ptr_wr_req_val - ,input [FLOWID_W-1:0] tail_ptr_wr_req_addr - ,input [RX_PAYLOAD_PTR_W:0] tail_ptr_wr_req_data - ,output tail_ptr_wr_req_rdy + ,input tail_idx_wr_req_val + ,input [FLOWID_W-1:0] tail_idx_wr_req_addr + ,input tcp_buf_idx tail_idx_wr_req_data + ,output tail_idx_wr_req_rdy - ,input tail_ptr_rd_req_val - ,input [FLOWID_W-1:0] tail_ptr_rd_req_addr - ,output logic tail_ptr_rd_req_rdy + ,input tail_idx_rd_req_val + ,input [FLOWID_W-1:0] tail_idx_rd_req_addr + ,output logic tail_idx_rd_req_rdy - ,output logic tail_ptr_rd_resp_val - ,output logic [RX_PAYLOAD_PTR_W:0] tail_ptr_rd_resp_data - ,input tail_ptr_rd_resp_rdy + ,output logic tail_idx_rd_resp_val + ,output tcp_buf_idx tail_idx_rd_resp_data + ,input tail_idx_rd_resp_rdy ,input new_flow_val ,input [FLOWID_W-1:0] new_flow_flowid - ,input [RX_PAYLOAD_PTR_W:0] new_rx_head_ptr - ,input [RX_PAYLOAD_PTR_W:0] new_rx_tail_ptr - ,output new_flow_rx_payload_ptrs_rdy + ,input tcp_buf_idx new_rx_head_idx + ,input tcp_buf_idx new_rx_tail_idx + ,output new_flow_rx_payload_idxs_rdy // TODO: make sure this is good... never had to deal with yet. ); - logic head_ptr_mem_wr_req_rdy; - logic tail_ptr_mem_wr_req_rdy; - logic commit_ptr_mem_wr_req_rdy; + logic head_idx_mem_wr_req_rdy; + logic tail_idx_mem_wr_req_rdy; + logic commit_idx_mem_wr_req_rdy; - logic head_ptr_mem_wr_req_val; - logic tail_ptr_mem_wr_req_val; - logic commit_ptr_mem_wr_req_val; + logic head_idx_mem_wr_req_val; + logic tail_idx_mem_wr_req_val; + logic commit_idx_mem_wr_req_val; - logic [RX_PAYLOAD_PTR_W:0] head_ptr_mem_wr_req_data; - logic [RX_PAYLOAD_PTR_W:0] tail_ptr_mem_wr_req_data; - logic [RX_PAYLOAD_PTR_W:0] commit_ptr_mem_wr_req_data; + tcp_buf_idx head_idx_mem_wr_req_data; + tcp_buf_idx tail_idx_mem_wr_req_data; + tcp_buf_idx commit_idx_mem_wr_req_data; - logic [FLOWID_W-1:0] head_ptr_mem_wr_req_addr; - logic [FLOWID_W-1:0] tail_ptr_mem_wr_req_addr; - logic [FLOWID_W-1:0] commit_ptr_mem_wr_req_addr; + logic [FLOWID_W-1:0] head_idx_mem_wr_req_addr; + logic [FLOWID_W-1:0] tail_idx_mem_wr_req_addr; + logic [FLOWID_W-1:0] commit_idx_mem_wr_req_addr; - assign new_flow_rx_payload_ptrs_rdy = head_ptr_mem_wr_req_rdy - & tail_ptr_mem_wr_req_rdy - & commit_ptr_mem_wr_req_rdy; + assign new_flow_rx_payload_idxs_rdy = head_idx_mem_wr_req_rdy + & tail_idx_mem_wr_req_rdy + & commit_idx_mem_wr_req_rdy; - assign head_ptr_wr_req_rdy = ~new_flow_val & head_ptr_mem_wr_req_rdy; - assign tail_ptr_wr_req_rdy = ~new_flow_val & tail_ptr_mem_wr_req_rdy; - assign commit_ptr_wr_req_rdy = ~new_flow_val & commit_ptr_mem_wr_req_rdy; + assign head_idx_wr_req_rdy = ~new_flow_val & head_idx_mem_wr_req_rdy; + assign tail_idx_wr_req_rdy = ~new_flow_val & tail_idx_mem_wr_req_rdy; + assign commit_idx_wr_req_rdy = ~new_flow_val & commit_idx_mem_wr_req_rdy; - assign head_ptr_mem_wr_req_val = new_flow_val | head_ptr_wr_req_val; - assign tail_ptr_mem_wr_req_val = new_flow_val | tail_ptr_wr_req_val; - assign commit_ptr_mem_wr_req_val = new_flow_val | commit_ptr_wr_req_val; + assign head_idx_mem_wr_req_val = new_flow_val | head_idx_wr_req_val; + assign tail_idx_mem_wr_req_val = new_flow_val | tail_idx_wr_req_val; + assign commit_idx_mem_wr_req_val = new_flow_val | commit_idx_wr_req_val; - assign head_ptr_mem_wr_req_addr = new_flow_val + assign head_idx_mem_wr_req_addr = new_flow_val ? new_flow_flowid - : head_ptr_wr_req_addr; + : head_idx_wr_req_addr; - assign tail_ptr_mem_wr_req_addr = new_flow_val + assign tail_idx_mem_wr_req_addr = new_flow_val ? new_flow_flowid - : tail_ptr_wr_req_addr; + : tail_idx_wr_req_addr; - assign commit_ptr_mem_wr_req_addr = new_flow_val + assign commit_idx_mem_wr_req_addr = new_flow_val ? new_flow_flowid - : commit_ptr_wr_req_addr; + : commit_idx_wr_req_addr; - assign head_ptr_mem_wr_req_data = new_flow_val - ? new_rx_head_ptr - : head_ptr_wr_req_data; + assign head_idx_mem_wr_req_data = new_flow_val + ? new_rx_head_idx + : head_idx_wr_req_data; - assign tail_ptr_mem_wr_req_data = new_flow_val - ? new_rx_tail_ptr - : tail_ptr_wr_req_data; + assign tail_idx_mem_wr_req_data = new_flow_val + ? new_rx_tail_idx + : tail_idx_wr_req_data; - assign commit_ptr_mem_wr_req_data = new_flow_val - ? new_rx_tail_ptr - : commit_ptr_wr_req_data; + assign commit_idx_mem_wr_req_data = new_flow_val + ? new_rx_tail_idx + : commit_idx_wr_req_data; ram_2r1w_sync_backpressure #( - .width_p (RX_PAYLOAD_PTR_W + 1 ) + .width_p (RX_PAYLOAD_IDX_W + 1 ) ,.els_p (MAX_FLOW_CNT ) - ) head_ptrs ( + ) head_idxs ( .clk (clk) ,.rst (rst) - ,.wr_req_val (head_ptr_mem_wr_req_val ) - ,.wr_req_addr (head_ptr_mem_wr_req_addr ) - ,.wr_req_data (head_ptr_mem_wr_req_data ) - ,.wr_req_rdy (head_ptr_mem_wr_req_rdy ) + ,.wr_req_val (head_idx_mem_wr_req_val ) + ,.wr_req_addr (head_idx_mem_wr_req_addr ) + ,.wr_req_data (head_idx_mem_wr_req_data.idx) + ,.wr_req_rdy (head_idx_mem_wr_req_rdy ) - ,.rd0_req_val (head_ptr_rd0_req_val ) - ,.rd0_req_addr (head_ptr_rd0_req_addr ) - ,.rd0_req_rdy (head_ptr_rd0_req_rdy ) + ,.rd0_req_val (head_idx_rd0_req_val ) + ,.rd0_req_addr (head_idx_rd0_req_addr ) + ,.rd0_req_rdy (head_idx_rd0_req_rdy ) - ,.rd0_resp_val (head_ptr_rd0_resp_val ) + ,.rd0_resp_val (head_idx_rd0_resp_val ) ,.rd0_resp_addr () - ,.rd0_resp_data (head_ptr_rd0_resp_data ) - ,.rd0_resp_rdy (head_ptr_rd0_resp_rdy ) + ,.rd0_resp_data (head_idx_rd0_resp_data.idx ) + ,.rd0_resp_rdy (head_idx_rd0_resp_rdy ) - ,.rd1_req_val (head_ptr_rd1_req_val ) - ,.rd1_req_addr (head_ptr_rd1_req_addr ) - ,.rd1_req_rdy (head_ptr_rd1_req_rdy ) + ,.rd1_req_val (head_idx_rd1_req_val ) + ,.rd1_req_addr (head_idx_rd1_req_addr ) + ,.rd1_req_rdy (head_idx_rd1_req_rdy ) - ,.rd1_resp_val (head_ptr_rd1_resp_val ) + ,.rd1_resp_val (head_idx_rd1_resp_val ) ,.rd1_resp_addr () - ,.rd1_resp_data (head_ptr_rd1_resp_data ) - ,.rd1_resp_rdy (head_ptr_rd1_resp_rdy ) + ,.rd1_resp_data (head_idx_rd1_resp_data.idx ) + ,.rd1_resp_rdy (head_idx_rd1_resp_rdy ) ); ram_2r1w_sync_backpressure #( - .width_p (RX_PAYLOAD_PTR_W + 1 ) + .width_p (RX_PAYLOAD_IDX_W + 1 ) ,.els_p (MAX_FLOW_CNT ) - ) commit_ptrs ( + ) commit_idxs ( .clk (clk) ,.rst (rst) - ,.wr_req_val (commit_ptr_mem_wr_req_val ) - ,.wr_req_addr (commit_ptr_mem_wr_req_addr ) - ,.wr_req_data (commit_ptr_mem_wr_req_data ) - ,.wr_req_rdy (commit_ptr_mem_wr_req_rdy ) + ,.wr_req_val (commit_idx_mem_wr_req_val ) + ,.wr_req_addr (commit_idx_mem_wr_req_addr ) + ,.wr_req_data (commit_idx_mem_wr_req_data.idx) + ,.wr_req_rdy (commit_idx_mem_wr_req_rdy ) - ,.rd0_req_val (commit_ptr_rd0_req_val ) - ,.rd0_req_addr (commit_ptr_rd0_req_addr ) - ,.rd0_req_rdy (commit_ptr_rd0_req_rdy ) + ,.rd0_req_val (commit_idx_rd0_req_val ) + ,.rd0_req_addr (commit_idx_rd0_req_addr ) + ,.rd0_req_rdy (commit_idx_rd0_req_rdy ) - ,.rd0_resp_val (commit_ptr_rd0_resp_val ) + ,.rd0_resp_val (commit_idx_rd0_resp_val ) ,.rd0_resp_addr () - ,.rd0_resp_data (commit_ptr_rd0_resp_data ) - ,.rd0_resp_rdy (commit_ptr_rd0_resp_rdy ) + ,.rd0_resp_data (commit_idx_rd0_resp_data.idx ) + ,.rd0_resp_rdy (commit_idx_rd0_resp_rdy ) - ,.rd1_req_val (commit_ptr_rd1_req_val ) - ,.rd1_req_addr (commit_ptr_rd1_req_addr ) - ,.rd1_req_rdy (commit_ptr_rd1_req_rdy ) + ,.rd1_req_val (commit_idx_rd1_req_val ) + ,.rd1_req_addr (commit_idx_rd1_req_addr ) + ,.rd1_req_rdy (commit_idx_rd1_req_rdy ) - ,.rd1_resp_val (commit_ptr_rd1_resp_val ) + ,.rd1_resp_val (commit_idx_rd1_resp_val ) ,.rd1_resp_addr () - ,.rd1_resp_data (commit_ptr_rd1_resp_data ) - ,.rd1_resp_rdy (commit_ptr_rd1_resp_rdy ) + ,.rd1_resp_data (commit_idx_rd1_resp_data.idx ) + ,.rd1_resp_rdy (commit_idx_rd1_resp_rdy ) ); ram_1r1w_sync_backpressure #( - .width_p (RX_PAYLOAD_PTR_W + 1 ) + .width_p (RX_PAYLOAD_IDX_W + 1 ) ,.els_p (MAX_FLOW_CNT ) - ) tail_ptrs ( + ) tail_idxs ( .clk (clk ) ,.rst (rst ) - ,.wr_req_val (tail_ptr_mem_wr_req_val ) - ,.wr_req_addr (tail_ptr_mem_wr_req_addr ) - ,.wr_req_data (tail_ptr_mem_wr_req_data ) - ,.wr_req_rdy (tail_ptr_mem_wr_req_rdy ) + ,.wr_req_val (tail_idx_mem_wr_req_val ) + ,.wr_req_addr (tail_idx_mem_wr_req_addr ) + ,.wr_req_data (tail_idx_mem_wr_req_data.idx) + ,.wr_req_rdy (tail_idx_mem_wr_req_rdy ) - ,.rd_req_val (tail_ptr_rd_req_val ) - ,.rd_req_addr (tail_ptr_rd_req_addr ) - ,.rd_req_rdy (tail_ptr_rd_req_rdy ) + ,.rd_req_val (tail_idx_rd_req_val ) + ,.rd_req_addr (tail_idx_rd_req_addr ) + ,.rd_req_rdy (tail_idx_rd_req_rdy ) - ,.rd_resp_val (tail_ptr_rd_resp_val ) - ,.rd_resp_data (tail_ptr_rd_resp_data ) - ,.rd_resp_rdy (tail_ptr_rd_resp_rdy ) + ,.rd_resp_val (tail_idx_rd_resp_val ) + ,.rd_resp_data (tail_idx_rd_resp_data.idx ) + ,.rd_resp_rdy (tail_idx_rd_resp_rdy ) ); endmodule diff --git a/rx_buf_store.sv b/rx_buf_store.sv new file mode 100644 index 0000000..7853221 --- /dev/null +++ b/rx_buf_store.sv @@ -0,0 +1,68 @@ +module rx_buf_store +import tcp_pkg::*; +( + input clk + ,input rst + + ,input wr_req_val + ,input [FLOWID_W-1:0] wr_req_flowid // this and idx are concatenated to make the real waddr + ,input [RX_PAYLOAD_IDX_W-1:0] wr_req_idx + ,input tcp_buf wr_req_data + ,output wr_req_rdy + + ,input rd0_req_val + ,input [FLOWID_W-1:0] rd0_req_flowid + ,input [RX_PAYLOAD_IDX_W-1:0] rd0_req_idx + ,output logic rd0_req_rdy + + ,output logic rd0_resp_val + ,output tcp_buf rd0_resp_data // we can't return it with the idx because the idx is incomplete (missing top bit) + ,input rd0_resp_rdy + + ,input rd1_req_val + ,input [FLOWID_W-1:0] rd1_req_flowid + ,input [RX_PAYLOAD_IDX_W-1:0] rd1_req_idx + ,output logic rd1_req_rdy + + ,output logic rd1_resp_val + ,output tcp_buf rd1_resp_data + ,input rd1_resp_rdy +); + +// convert from flowid + index to addr +wire [FLOWID_W + MAX_PAYLOAD_IDX_W - 1:0] wr_req_addr = '{wr_req_flowid , wr_req_idx }; +wire [FLOWID_W + MAX_PAYLOAD_IDX_W - 1:0] rd0_req_addr = '{rd0_req_flowid, rd0_req_idx}; +wire [FLOWID_W + MAX_PAYLOAD_IDX_W - 1:0] rd1_req_addr = '{rd1_req_flowid, rd1_req_idx}; + +ram_2r1w_sync_backpressure #( + .width_p (TCP_BUF_W ) + ,.els_p (MAX_FLOW_CNT * MAX_NUM_BUFS ) +) rx_state_store ( + .clk (clk ) + ,.rst (rst ) + + ,.wr_req_val (wr_req_val ) + ,.wr_req_addr (wr_req_addr ) + ,.wr_req_data (wr_req_data ) + ,.wr_req_rdy (wr_req_rdy ) + + ,.rd0_req_val (rd0_req_val ) + ,.rd0_req_addr (rd0_req_addr ) + ,.rd0_req_rdy (rd0_req_rdy ) + + ,.rd0_resp_val (rd0_resp_val ) + ,.rd0_resp_addr () + ,.rd0_resp_data (rd0_resp_data ) + ,.rd0_resp_rdy (rd0_resp_rdy ) + + ,.rd1_req_val (rd1_req_val ) + ,.rd1_req_addr (rd1_req_addr ) + ,.rd1_req_rdy (rd1_req_rdy ) + + ,.rd1_resp_val (rd1_resp_val ) + ,.rd1_resp_addr () + ,.rd1_resp_data (rd1_resp_data ) + ,.rd1_resp_rdy (rd1_resp_rdy ) +); + +endmodule \ No newline at end of file diff --git a/tcp.core b/tcp.core index a21ab9f..eb0bd7a 100644 --- a/tcp.core +++ b/tcp.core @@ -18,6 +18,7 @@ filesets: - send_pkt_mux.sv - tcp.sv - tcp_hdr_assembler.sv + - tcp_malloc.sv - tcp_rx.sv - tcp_rx_ctrl.sv - tcp_rx_datap.sv diff --git a/tcp.sv b/tcp.sv index 4be51a9..ea2296a 100644 --- a/tcp.sv +++ b/tcp.sv @@ -7,7 +7,7 @@ import packet_struct_pkg::*; input clk ,input rst - ,input src_tcp_rx_hdr_val + ,input src_tcp_rx_hdr_val // tmp queue not empty (i think) ,output logic tcp_src_rx_hdr_rdy ,input [`IP_ADDR_W-1:0] src_tcp_rx_src_ip ,input [`IP_ADDR_W-1:0] src_tcp_rx_dst_ip @@ -31,18 +31,18 @@ import packet_struct_pkg::*; ,output payload_buf_struct tcp_rx_dst_payload_entry ,input logic dst_tcp_rx_hdr_rdy - ,input logic store_buf_commit_ptr_wr_req_val - ,input logic [FLOWID_W-1:0] store_buf_commit_ptr_wr_req_addr - ,input logic [RX_PAYLOAD_PTR_W:0] store_buf_commit_ptr_wr_req_data - ,output logic commit_ptr_store_buf_wr_req_rdy + ,input logic store_buf_commit_idx_wr_req_val + ,input logic [FLOWID_W-1:0] store_buf_commit_idx_wr_req_addr + ,input tcp_buf_idx store_buf_commit_idx_wr_req_data + ,output logic commit_idx_store_buf_wr_req_rdy - ,input logic store_buf_commit_ptr_rd_req_val - ,input logic [FLOWID_W-1:0] store_buf_commit_ptr_rd_req_addr - ,output logic commit_ptr_store_buf_rd_req_rdy + ,input logic store_buf_commit_idx_rd_req_val + ,input logic [FLOWID_W-1:0] store_buf_commit_idx_rd_req_addr + ,output logic commit_idx_store_buf_rd_req_rdy - ,output logic commit_ptr_store_buf_rd_resp_val - ,output logic [RX_PAYLOAD_PTR_W:0] commit_ptr_store_buf_rd_resp_data - ,input logic store_buf_commit_ptr_rd_resp_rdy + ,output logic commit_idx_store_buf_rd_resp_val + ,output tcp_buf_idx commit_idx_store_buf_rd_resp_data + ,input logic store_buf_commit_idx_rd_resp_rdy /******************************** * App interface @@ -52,26 +52,31 @@ import packet_struct_pkg::*; ,output four_tuple_struct app_new_flow_entry ,input logic app_new_flow_notif_rdy - ,input logic app_rx_head_ptr_wr_req_val - ,input logic [FLOWID_W-1:0] app_rx_head_ptr_wr_req_addr - ,input logic [RX_PAYLOAD_PTR_W:0] app_rx_head_ptr_wr_req_data - ,output logic rx_head_ptr_app_wr_req_rdy + ,input logic app_rx_head_idx_wr_req_val + ,input logic [FLOWID_W-1:0] app_rx_head_idx_wr_req_addr + ,input tcp_buf_idx app_rx_head_idx_wr_req_data + ,output logic rx_head_idx_app_wr_req_rdy - ,input logic app_rx_head_ptr_rd_req_val - ,input logic [FLOWID_W-1:0] app_rx_head_ptr_rd_req_addr - ,output logic rx_head_ptr_app_rd_req_rdy + ,input logic app_rx_head_idx_rd_req_val + ,input logic [FLOWID_W-1:0] app_rx_head_idx_rd_req_addr + ,output logic rx_head_idx_app_rd_req_rdy - ,output logic rx_head_ptr_app_rd_resp_val - ,output logic [RX_PAYLOAD_PTR_W:0] rx_head_ptr_app_rd_resp_data - ,input logic app_rx_head_ptr_rd_resp_rdy + ,output logic rx_head_idx_app_rd_resp_val + ,output tcp_buf_idx rx_head_idx_app_rd_resp_data + ,input logic app_rx_head_idx_rd_resp_rdy - ,input logic app_rx_commit_ptr_rd_req_val - ,input logic [FLOWID_W-1:0] app_rx_commit_ptr_rd_req_addr - ,output logic rx_commit_ptr_app_rd_req_rdy + ,input logic app_rx_commit_idx_rd_req_val + ,input logic [FLOWID_W-1:0] app_rx_commit_idx_rd_req_addr + ,output logic rx_commit_idx_app_rd_req_rdy - ,output logic rx_commit_ptr_app_rd_resp_val - ,output logic [RX_PAYLOAD_PTR_W:0] rx_commit_ptr_app_rd_resp_data - ,input logic app_rx_commit_ptr_rd_resp_rdy + ,output logic rx_commit_idx_app_rd_resp_val + ,output tcp_buf_idx rx_commit_idx_app_rd_resp_data + ,input logic app_rx_commit_idx_rd_resp_rdy + + ,input logic app_rx_free_req_val + ,input logic [RX_PAYLOAD_PTR_W-1:0] app_rx_free_req_addr + ,input logic [MALLOC_LEN_W-1:0] app_rx_free_req_len + ,output logic rx_free_app_req_rdy ,input app_tx_head_ptr_rd_req_val ,input [FLOWID_W-1:0] app_tx_head_ptr_rd_req_addr @@ -99,6 +104,27 @@ import packet_struct_pkg::*; ,input logic app_sched_update_val ,input sched_cmd_struct app_sched_update_cmd ,output logic sched_app_update_rdy + + /* + Buf Store + */ + ,input logic app_rx_head_buf_rd_req_val + ,input logic [FLOWID_W-1:0] app_rx_head_buf_rd_req_flowid + ,input logic [RX_PAYLOAD_IDX_W-1:0] app_rx_head_buf_rd_req_idx + ,output logic rx_head_buf_app_rd_req_rdy + + ,output logic rx_head_buf_app_rd_resp_val + ,output tcp_buf rx_head_buf_app_rd_resp_data + ,input logic app_rx_head_buf_rd_resp_rdy + + ,input rx_store_buf_rx_buf_store_rd_req_val + ,input [FLOWID_W-1:0] rx_store_buf_rx_buf_store_rd_req_flowid + ,input [RX_PAYLOAD_IDX_W-1:0] rx_store_buf_rx_buf_store_rd_req_idx + ,output logic rx_buf_store_rx_store_buf_rd_req_rdy + + ,output logic rx_buf_store_rx_store_buf_rd_resp_val + ,output tcp_buf rx_buf_store_rx_store_buf_rd_resp_data + ,input rx_store_buf_rx_buf_store_rd_resp_rdy ); @@ -132,26 +158,26 @@ import packet_struct_pkg::*; logic [TX_PAYLOAD_PTR_W:0] new_tx_tail_ptr; logic new_flow_rdy; - logic rx_pipe_rx_head_ptr_rd_req_val; - logic [FLOWID_W-1:0] rx_pipe_rx_head_ptr_rd_req_addr; - logic rx_head_ptr_rx_pipe_rd_req_rdy; + logic rx_pipe_rx_head_idx_rd_req_val; + logic [FLOWID_W-1:0] rx_pipe_rx_head_idx_rd_req_addr; + logic rx_head_idx_rx_pipe_rd_req_rdy; - logic rx_head_ptr_rx_pipe_rd_resp_val; - logic [RX_PAYLOAD_PTR_W:0] rx_head_ptr_rx_pipe_rd_resp_data; - logic rx_pipe_rx_head_ptr_rd_resp_rdy; + logic rx_head_idx_rx_pipe_rd_resp_val; + tcp_buf_idx rx_head_idx_rx_pipe_rd_resp_data; + logic rx_pipe_rx_head_idx_rd_resp_rdy; - logic rx_pipe_rx_tail_ptr_wr_req_val; - logic [FLOWID_W-1:0] rx_pipe_rx_tail_ptr_wr_req_addr; - logic [RX_PAYLOAD_PTR_W:0] rx_pipe_rx_tail_ptr_wr_req_data; - logic rx_tail_ptr_rx_pipe_wr_req_rdy; + logic rx_pipe_rx_tail_idx_wr_req_val; + logic [FLOWID_W-1:0] rx_pipe_rx_tail_idx_wr_req_addr; + tcp_buf_idx rx_pipe_rx_tail_idx_wr_req_data; + logic rx_tail_idx_rx_pipe_wr_req_rdy; - logic rx_pipe_rx_tail_ptr_rd_req_val; - logic [FLOWID_W-1:0] rx_pipe_rx_tail_ptr_rd_req_addr; - logic rx_tail_ptr_rx_pipe_rd_req_rdy; + logic rx_pipe_rx_tail_idx_rd_req_val; + logic [FLOWID_W-1:0] rx_pipe_rx_tail_idx_rd_req_addr; + logic rx_tail_idx_rx_pipe_rd_req_rdy; - logic rx_tail_ptr_rx_pipe_rd_resp_val; - logic [RX_PAYLOAD_PTR_W:0] rx_tail_ptr_rx_pipe_rd_resp_data; - logic rx_pipe_rx_tail_ptr_rd_resp_rdy; + logic rx_tail_idx_rx_pipe_rd_resp_val; + tcp_buf_idx rx_tail_idx_rx_pipe_rd_resp_data; + logic rx_pipe_rx_tail_idx_rd_resp_rdy; logic rx_pipe_tx_head_ptr_wr_req_val; logic [FLOWID_W-1:0] rx_pipe_tx_head_ptr_wr_req_addr; @@ -237,6 +263,23 @@ import packet_struct_pkg::*; smol_tx_state_struct tx_state_tx_pipe_rd_resp_data; logic tx_pipe_tx_state_rd_resp_rdy; + logic rx_pipe_rx_malloc_req_val; + logic [MALLOC_LEN_W-1:0] rx_pipe_rx_malloc_req_len; + logic rx_malloc_rx_pipe_req_rdy; + + logic rx_malloc_rx_pipe_resp_val; + logic rx_malloc_rx_pipe_resp_success; + logic [RX_PAYLOAD_PTR_W-1:0] rx_malloc_rx_pipe_resp_addr; + logic rx_pipe_rx_malloc_resp_rdy; + + logic [RX_PAYLOAD_PTR_W:0] rx_malloc_rx_pipe_approx_empty_space; + + logic rx_pipe_rx_buf_store_wr_req_val; + logic [FLOWID_W-1:0] rx_pipe_rx_buf_store_wr_req_flowid; + logic [RX_PAYLOAD_IDX_W-1:0] rx_pipe_rx_buf_store_wr_req_idx; + tcp_buf rx_pipe_rx_buf_store_wr_req_data; + logic rx_buf_store_rx_pipe_wr_req_rdy; + assign new_flow_rdy = new_flow_rx_state_rdy & & new_flow_rx_payload_ptrs_rdy & new_flow_tx_state_rdy & new_flow_tx_payload_ptrs_rdy & tx_new_flow_rdy; @@ -333,26 +376,26 @@ import packet_struct_pkg::*; ,.curr_tx_state_rd_resp_data (curr_tx_state_rd_resp_data ) ,.curr_tx_state_rd_resp_rdy (curr_tx_state_rd_resp_rdy ) - ,.rx_pipe_rx_head_ptr_rd_req_val (rx_pipe_rx_head_ptr_rd_req_val ) - ,.rx_pipe_rx_head_ptr_rd_req_addr (rx_pipe_rx_head_ptr_rd_req_addr ) - ,.rx_head_ptr_rx_pipe_rd_req_rdy (rx_head_ptr_rx_pipe_rd_req_rdy ) + ,.rx_pipe_rx_head_idx_rd_req_val (rx_pipe_rx_head_idx_rd_req_val ) + ,.rx_pipe_rx_head_idx_rd_req_addr (rx_pipe_rx_head_idx_rd_req_addr ) + ,.rx_head_idx_rx_pipe_rd_req_rdy (rx_head_idx_rx_pipe_rd_req_rdy ) - ,.rx_head_ptr_rx_pipe_rd_resp_val (rx_head_ptr_rx_pipe_rd_resp_val ) - ,.rx_head_ptr_rx_pipe_rd_resp_data (rx_head_ptr_rx_pipe_rd_resp_data ) - ,.rx_pipe_rx_head_ptr_rd_resp_rdy (rx_pipe_rx_head_ptr_rd_resp_rdy ) + ,.rx_head_idx_rx_pipe_rd_resp_val (rx_head_idx_rx_pipe_rd_resp_val ) + ,.rx_head_idx_rx_pipe_rd_resp_data (rx_head_idx_rx_pipe_rd_resp_data.idx) // TODO: probably just change tcp_rx to accept the struct lol + ,.rx_pipe_rx_head_idx_rd_resp_rdy (rx_pipe_rx_head_idx_rd_resp_rdy ) - ,.rx_pipe_rx_tail_ptr_wr_req_val (rx_pipe_rx_tail_ptr_wr_req_val ) - ,.rx_pipe_rx_tail_ptr_wr_req_addr (rx_pipe_rx_tail_ptr_wr_req_addr ) - ,.rx_pipe_rx_tail_ptr_wr_req_data (rx_pipe_rx_tail_ptr_wr_req_data ) - ,.rx_tail_ptr_rx_pipe_wr_req_rdy (rx_tail_ptr_rx_pipe_wr_req_rdy ) + ,.rx_pipe_rx_tail_idx_wr_req_val (rx_pipe_rx_tail_idx_wr_req_val ) + ,.rx_pipe_rx_tail_idx_wr_req_addr (rx_pipe_rx_tail_idx_wr_req_addr ) + ,.rx_pipe_rx_tail_idx_wr_req_data (rx_pipe_rx_tail_idx_wr_req_data.idx) + ,.rx_tail_ptr_rx_pipe_wr_req_rdy (rx_tail_idx_rx_pipe_wr_req_rdy ) - ,.rx_pipe_rx_tail_ptr_rd_req_val (rx_pipe_rx_tail_ptr_rd_req_val ) - ,.rx_pipe_rx_tail_ptr_rd_req_addr (rx_pipe_rx_tail_ptr_rd_req_addr ) - ,.rx_tail_ptr_rx_pipe_rd_req_rdy (rx_tail_ptr_rx_pipe_rd_req_rdy ) + ,.rx_pipe_rx_tail_idx_rd_req_val (rx_pipe_rx_tail_idx_rd_req_val ) + ,.rx_pipe_rx_tail_idx_rd_req_addr (rx_pipe_rx_tail_idx_rd_req_addr ) + ,.rx_tail_idx_rx_pipe_rd_req_rdy (rx_tail_idx_rx_pipe_rd_req_rdy ) - ,.rx_tail_ptr_rx_pipe_rd_resp_val (rx_tail_ptr_rx_pipe_rd_resp_val ) - ,.rx_tail_ptr_rx_pipe_rd_resp_data (rx_tail_ptr_rx_pipe_rd_resp_data ) - ,.rx_pipe_rx_tail_ptr_rd_resp_rdy (rx_pipe_rx_tail_ptr_rd_resp_rdy ) + ,.rx_tail_idx_rx_pipe_rd_resp_val (rx_tail_idx_rx_pipe_rd_resp_val ) + ,.rx_tail_idx_rx_pipe_rd_resp_data (rx_tail_idx_rx_pipe_rd_resp_data.idx) + ,.rx_pipe_rx_tail_idx_rd_resp_rdy (rx_pipe_rx_tail_idx_rd_resp_rdy ) ,.rx_pipe_tx_head_ptr_wr_req_val (rx_pipe_tx_head_ptr_wr_req_val ) ,.rx_pipe_tx_head_ptr_wr_req_addr (rx_pipe_tx_head_ptr_wr_req_addr ) @@ -369,6 +412,23 @@ import packet_struct_pkg::*; ,.rx_sched_update_val (rx_sched_update_val ) ,.rx_sched_update_cmd (rx_sched_update_cmd ) ,.sched_rx_update_rdy (sched_rx_update_rdy ) + + ,.rx_pipe_rx_malloc_req_val (rx_pipe_rx_malloc_req_val ) + ,.rx_pipe_rx_malloc_req_len (rx_pipe_rx_malloc_req_len ) + ,.rx_malloc_rx_pipe_req_rdy (rx_malloc_rx_pipe_req_rdy ) + + ,.rx_malloc_rx_pipe_resp_val (rx_malloc_rx_pipe_resp_val ) + ,.rx_malloc_rx_pipe_resp_success (rx_malloc_rx_pipe_resp_success ) + ,.rx_malloc_rx_pipe_resp_addr (rx_malloc_rx_pipe_resp_addr ) + ,.rx_pipe_rx_malloc_resp_rdy (rx_pipe_rx_malloc_resp_rdy ) + + ,.rx_malloc_rx_pipe_approx_empty_space(rx_malloc_rx_pipe_approx_empty_space) + + ,.rx_pipe_rx_buf_store_wr_req_val (rx_pipe_rx_buf_store_wr_req_val ) + ,.rx_pipe_rx_buf_store_wr_req_flowid(rx_pipe_rx_buf_store_wr_req_flowid ) + ,.rx_pipe_rx_buf_store_wr_req_idx (rx_pipe_rx_buf_store_wr_req_idx ) + ,.rx_pipe_rx_buf_store_wr_req_data (rx_pipe_rx_buf_store_wr_req_data ) + ,.rx_buf_store_rx_pipe_wr_req_rdy (rx_buf_store_rx_pipe_wr_req_rdy ) ); tcp_tx tx_engine ( @@ -555,70 +615,99 @@ import packet_struct_pkg::*; ,.rd1_resp_rdy (curr_tx_state_rd_resp_rdy ) ); - rx_buf_ptrs rx_ptrs ( + rx_buf_idxs rx_idxs ( .clk (clk ) ,.rst (rst ) - ,.head_ptr_wr_req_val (app_rx_head_ptr_wr_req_val ) - ,.head_ptr_wr_req_addr (app_rx_head_ptr_wr_req_addr ) - ,.head_ptr_wr_req_data (app_rx_head_ptr_wr_req_data ) - ,.head_ptr_wr_req_rdy (rx_head_ptr_app_wr_req_rdy ) - - ,.head_ptr_rd0_req_val (app_rx_head_ptr_rd_req_val ) - ,.head_ptr_rd0_req_addr (app_rx_head_ptr_rd_req_addr ) - ,.head_ptr_rd0_req_rdy (rx_head_ptr_app_rd_req_rdy ) - - ,.head_ptr_rd0_resp_val (rx_head_ptr_app_rd_resp_val ) - ,.head_ptr_rd0_resp_data (rx_head_ptr_app_rd_resp_data ) - ,.head_ptr_rd0_resp_rdy (app_rx_head_ptr_rd_resp_rdy ) + ,.head_idx_wr_req_val (app_rx_head_idx_wr_req_val ) + ,.head_idx_wr_req_addr (app_rx_head_idx_wr_req_addr ) + ,.head_idx_wr_req_data (app_rx_head_idx_wr_req_data ) + ,.head_idx_wr_req_rdy (rx_head_idx_app_wr_req_rdy ) + + ,.head_idx_rd0_req_val (app_rx_head_idx_rd_req_val ) + ,.head_idx_rd0_req_addr (app_rx_head_idx_rd_req_addr ) + ,.head_idx_rd0_req_rdy (rx_head_idx_app_rd_req_rdy ) + + ,.head_idx_rd0_resp_val (rx_head_idx_app_rd_resp_val ) + ,.head_idx_rd0_resp_data (rx_head_idx_app_rd_resp_data ) + ,.head_idx_rd0_resp_rdy (app_rx_head_idx_rd_resp_rdy ) - ,.head_ptr_rd1_req_val (rx_pipe_rx_head_ptr_rd_req_val ) - ,.head_ptr_rd1_req_addr (rx_pipe_rx_head_ptr_rd_req_addr ) - ,.head_ptr_rd1_req_rdy (rx_head_ptr_rx_pipe_rd_req_rdy ) + ,.head_idx_rd1_req_val (rx_pipe_rx_head_idx_rd_req_val ) + ,.head_idx_rd1_req_addr (rx_pipe_rx_head_idx_rd_req_addr ) + ,.head_idx_rd1_req_rdy (rx_head_idx_rx_pipe_rd_req_rdy ) - ,.head_ptr_rd1_resp_val (rx_head_ptr_rx_pipe_rd_resp_val ) - ,.head_ptr_rd1_resp_data (rx_head_ptr_rx_pipe_rd_resp_data ) - ,.head_ptr_rd1_resp_rdy (rx_pipe_rx_head_ptr_rd_resp_rdy ) + ,.head_idx_rd1_resp_val (rx_head_idx_rx_pipe_rd_resp_val ) + ,.head_idx_rd1_resp_data (rx_head_idx_rx_pipe_rd_resp_data ) + ,.head_idx_rd1_resp_rdy (rx_pipe_rx_head_idx_rd_resp_rdy ) - ,.commit_ptr_wr_req_val (store_buf_commit_ptr_wr_req_val ) - ,.commit_ptr_wr_req_addr (store_buf_commit_ptr_wr_req_addr ) - ,.commit_ptr_wr_req_data (store_buf_commit_ptr_wr_req_data ) - ,.commit_ptr_wr_req_rdy (commit_ptr_store_buf_wr_req_rdy ) - - ,.commit_ptr_rd0_req_val (store_buf_commit_ptr_rd_req_val ) - ,.commit_ptr_rd0_req_addr (store_buf_commit_ptr_rd_req_addr ) - ,.commit_ptr_rd0_req_rdy (commit_ptr_store_buf_rd_req_rdy ) - - ,.commit_ptr_rd0_resp_val (commit_ptr_store_buf_rd_resp_val ) - ,.commit_ptr_rd0_resp_data (commit_ptr_store_buf_rd_resp_data ) - ,.commit_ptr_rd0_resp_rdy (store_buf_commit_ptr_rd_resp_rdy ) + ,.commit_idx_wr_req_val (store_buf_commit_idx_wr_req_val ) + ,.commit_idx_wr_req_addr (store_buf_commit_idx_wr_req_addr ) + ,.commit_idx_wr_req_data (store_buf_commit_idx_wr_req_data ) + ,.commit_idx_wr_req_rdy (commit_idx_store_buf_wr_req_rdy ) + + ,.commit_idx_rd0_req_val (store_buf_commit_idx_rd_req_val ) + ,.commit_idx_rd0_req_addr (store_buf_commit_idx_rd_req_addr ) + ,.commit_idx_rd0_req_rdy (commit_idx_store_buf_rd_req_rdy ) + + ,.commit_idx_rd0_resp_val (commit_idx_store_buf_rd_resp_val ) + ,.commit_idx_rd0_resp_data (commit_idx_store_buf_rd_resp_data ) + ,.commit_idx_rd0_resp_rdy (store_buf_commit_idx_rd_resp_rdy ) - ,.commit_ptr_rd1_req_val (app_rx_commit_ptr_rd_req_val ) - ,.commit_ptr_rd1_req_addr (app_rx_commit_ptr_rd_req_addr ) - ,.commit_ptr_rd1_req_rdy (rx_commit_ptr_app_rd_req_rdy ) + ,.commit_idx_rd1_req_val (app_rx_commit_idx_rd_req_val ) + ,.commit_idx_rd1_req_addr (app_rx_commit_idx_rd_req_addr ) + ,.commit_idx_rd1_req_rdy (rx_commit_idx_app_rd_req_rdy ) - ,.commit_ptr_rd1_resp_val (rx_commit_ptr_app_rd_resp_val ) - ,.commit_ptr_rd1_resp_data (rx_commit_ptr_app_rd_resp_data ) - ,.commit_ptr_rd1_resp_rdy (app_rx_commit_ptr_rd_resp_rdy ) + ,.commit_idx_rd1_resp_val (rx_commit_idx_app_rd_resp_val ) + ,.commit_idx_rd1_resp_data (rx_commit_idx_app_rd_resp_data ) + ,.commit_idx_rd1_resp_rdy (app_rx_commit_idx_rd_resp_rdy ) - ,.tail_ptr_wr_req_val (rx_pipe_rx_tail_ptr_wr_req_val ) - ,.tail_ptr_wr_req_addr (rx_pipe_rx_tail_ptr_wr_req_addr ) - ,.tail_ptr_wr_req_data (rx_pipe_rx_tail_ptr_wr_req_data ) - ,.tail_ptr_wr_req_rdy (rx_tail_ptr_rx_pipe_wr_req_rdy ) + ,.tail_idx_wr_req_val (rx_pipe_rx_tail_idx_wr_req_val ) + ,.tail_idx_wr_req_addr (rx_pipe_rx_tail_idx_wr_req_addr ) + ,.tail_idx_wr_req_data (rx_pipe_rx_tail_idx_wr_req_data ) + ,.tail_idx_wr_req_rdy (rx_tail_idx_rx_pipe_wr_req_rdy ) - ,.tail_ptr_rd_req_val (rx_pipe_rx_tail_ptr_rd_req_val ) - ,.tail_ptr_rd_req_addr (rx_pipe_rx_tail_ptr_rd_req_addr ) - ,.tail_ptr_rd_req_rdy (rx_tail_ptr_rx_pipe_rd_req_rdy ) + ,.tail_idx_rd_req_val (rx_pipe_rx_tail_idx_rd_req_val ) + ,.tail_idx_rd_req_addr (rx_pipe_rx_tail_idx_rd_req_addr ) + ,.tail_idx_rd_req_rdy (rx_tail_idx_rx_pipe_rd_req_rdy ) - ,.tail_ptr_rd_resp_val (rx_tail_ptr_rx_pipe_rd_resp_val ) - ,.tail_ptr_rd_resp_data (rx_tail_ptr_rx_pipe_rd_resp_data ) - ,.tail_ptr_rd_resp_rdy (rx_pipe_rx_tail_ptr_rd_resp_rdy ) + ,.tail_idx_rd_resp_val (rx_tail_idx_rx_pipe_rd_resp_val ) + ,.tail_idx_rd_resp_data (rx_tail_idx_rx_pipe_rd_resp_data ) + ,.tail_idx_rd_resp_rdy (rx_pipe_rx_tail_idx_rd_resp_rdy ) ,.new_flow_val (new_flow_val ) ,.new_flow_flowid (new_flow_flow_id ) - ,.new_rx_head_ptr ('0) - ,.new_rx_tail_ptr ('0) - ,.new_flow_rx_payload_ptrs_rdy (new_flow_rx_payload_ptrs_rdy ) + ,.new_rx_head_idx ('{idx:'0}) + ,.new_rx_tail_idx ('{idx:'0}) + ,.new_flow_rx_payload_idxs_rdy (new_flow_rx_payload_idxs_rdy ) + ); + + rx_buf_store rx_bufs ( + .clk (clk ) + ,.rst (rst ) + + ,.wr_req_val (rx_pipe_rx_buf_store_wr_req_val ) + ,.wr_req_flowid (rx_pipe_rx_buf_store_wr_req_flowid ) + ,.wr_req_idx (rx_pipe_rx_buf_store_wr_req_idx ) + ,.wr_req_data (rx_pipe_rx_buf_store_wr_req_data ) + ,.wr_req_rdy (rx_buf_store_rx_pipe_wr_req_rdy ) + + ,.rd0_req_val (app_rx_head_buf_rd_req_val ) + ,.rd0_req_flowid (app_rx_head_buf_rd_req_flowid ) + ,.rd0_req_idx (app_rx_head_buf_rd_req_idx ) + ,.rd0_req_rdy (rx_head_buf_app_rd_req_rdy ) + + ,.rd0_resp_val (rx_head_buf_app_rd_resp_val ) + ,.rd0_resp_data (rx_head_buf_app_rd_resp_data ) + ,.rd0_resp_rdy (app_rx_head_buf_rd_resp_rdy ) + + ,.rd1_req_val (rx_store_buf_rx_buf_store_rd_req_val ) + ,.rd1_req_flowid (rx_store_buf_rx_buf_store_rd_req_flowid ) + ,.rd1_req_idx (rx_store_buf_rx_buf_store_rd_req_idx ) + ,.rd1_req_rdy (rx_buf_store_rx_store_buf_rd_req_rdy ) + + ,.rd1_resp_val (rx_buf_store_rx_store_buf_rd_resp_val ) + ,.rd1_resp_data (rx_buf_store_rx_store_buf_rd_resp_data ) + ,.rd1_resp_rdy (rx_store_buf_rx_buf_store_rd_resp_rdy ) ); tx_buf_ptrs tx_payload_qs ( @@ -678,4 +767,29 @@ import packet_struct_pkg::*; ,.new_flow_rdy (new_flow_tx_payload_ptrs_rdy ) ); + tcp_malloc #( + .PTR_W(RX_PAYLOAD_PTR_W) // TODO: is that right? is that a crazy amount of memory? also TODO is hook that up to the actual backing memory + ,.LEN_MAX(MALLOC_LEN_MAX) + ,.STALL(0) + ) malloc ( + .clk(clk) + ,.rst(rst) + + ,.malloc_req_val(rx_pipe_rx_malloc_req_val) + ,.malloc_req_len(rx_pipe_rx_malloc_req_len) + ,.malloc_req_rdy(rx_malloc_rx_pipe_req_rdy) + + ,.malloc_resp_val(rx_malloc_rx_pipe_resp_val) + ,.malloc_resp_success(rx_malloc_rx_pipe_resp_success) + ,.malloc_resp_addr(rx_malloc_rx_pipe_resp_addr) + ,.malloc_resp_rdy(rx_pipe_rx_malloc_resp_rdy) + + ,.malloc_approx_empty_space(rx_malloc_rx_pipe_approx_empty_space) + + ,.free_req_val(app_rx_free_req_val) + ,.free_req_addr(app_rx_free_req_addr) + ,.free_req_len(app_rx_free_req_len) + ,.free_req_rdy(rx_free_app_req_rdy) + ); + endmodule diff --git a/tcp_malloc.sv b/tcp_malloc.sv new file mode 100644 index 0000000..51bc22f --- /dev/null +++ b/tcp_malloc.sv @@ -0,0 +1,252 @@ +module tcp_malloc #( + parameter PTR_W = 0 // determines how big the backing memory should be + ,parameter LEN_MAX = 0 // the largest buffer that a user will request. in the naive impl, the memory is split into fixed sized chunks where this is the chunk size. + ,parameter STALL = 0 // whether or not to stall when we get a malloc that we can't yet fulfill. stall=0 -> return !resp_success, stall=1 -> don't return until we fulfill the request. + + // generated param + ,parameter LEN_W = $clog2(LEN_MAX) +)( + input clk + ,input rst + + ,input malloc_req_val + ,input [LEN_W-1:0] malloc_req_len // in the native impl, this must equal LEN_MAX + ,output malloc_req_rdy + + ,output malloc_resp_val + ,output malloc_resp_success // 1 = addr is valid. 0 = addr is junk, retry your request or otherwise handle OOM. + ,output [PTR_W-1:0] malloc_resp_addr + ,input malloc_resp_rdy + + ,output [PTR_W:0] malloc_approx_empty_space + + ,input free_req_val + ,input [PTR_W-1:0] free_req_addr + ,input [LEN_W-1:0] free_req_len // in the native impl, this must equal LEN_MAX + ,output free_req_rdy +); + +localparam BACKING_SIZE_UPPER = 2**PTR_W; + +localparam NUM_TOTAL_SLICES = BACKING_SIZE_UPPER/LEN_MAX; // round down, half-avail slices aren't useful +localparam SLICES_W = $clog2(NUM_TOTAL_SLICES); +localparam BACKING_SIZE_EXACT = NUM_TOTAL_SLICES * LEN_MAX; + +// hookup the inputs and outputs +logic malloc_req_fifo_wr_req; +logic [LEN_W-1:0] malloc_req_fifo_wr_data; +logic malloc_req_fifo_full; +assign malloc_req_fifo_wr_req = malloc_req_val; +assign malloc_req_fifo_wr_data = malloc_req_len; +assign malloc_req_rdy = ~malloc_req_fifo_full; + +logic malloc_resp_fifo_empty; +logic [PTR_W:0] malloc_resp_fifo_rd_data; +logic malloc_resp_fifo_rd_req; +assign malloc_resp_val = ~malloc_resp_fifo_empty; +assign malloc_resp_success = malloc_resp_fifo_rd_data[PTR_W]; +assign malloc_resp_addr = malloc_resp_fifo_rd_data[PTR_W-1:0]; +assign malloc_resp_fifo_rd_req = malloc_resp_rdy; + +logic free_req_fifo_wr_req; +logic [PTR_W+LEN_W-1:0] free_req_fifo_wr_data; +logic free_req_fifo_full; +assign free_req_fifo_wr_req = free_req_val; +assign free_req_fifo_wr_data = '{free_req_addr, free_req_len}; +assign free_req_rdy = ~free_req_fifo_full; + +always_ff @(posedge clk) begin + if (malloc_req_val && malloc_req_rdy) begin + if (malloc_req_len != LEN_MAX) begin + $fatal("Error: naive malloc requires malloc_req_len == LEN_MAX == %d instead of %d", LEN_MAX, malloc_req_len); + end + end + if (free_req_val && free_req_rdy) begin + if (free_req_len != LEN_MAX) begin + $fatal("Error: naive malloc requires free_req_len == LEN_MAX == %d instead of %d", LEN_MAX, free_req_len); + end + end +end + +// internal logic. req feeds resp, free and reset feed slices, slices also feeds resp. +// free || reset -> slices, slices && req -> resp + +logic slices_fifo_rd_req; +logic slices_fifo_empty; +logic [PTR_W+LEN_W-1:0] slices_fifo_rd_data; + +logic slices_fifo_wr_req; +logic [PTR_W+LEN_W-1:0] slices_fifo_wr_data; +logic slices_fifo_full; + +logic malloc_req_fifo_rd_req; +logic malloc_req_fifo_empty; +logic [LEN_W-1:0] malloc_req_fifo_rd_data; // unused. + +logic malloc_resp_fifo_wr_req; +logic [LEN_W:0] malloc_resp_fifo_wr_data; +logic malloc_resp_fifo_full; + +logic free_req_fifo_rd_req; +logic free_req_fifo_empty; +logic [PTR_W+LEN_W-1:0] free_req_fifo_rd_data; + +// not actually a fifo, but framed like one for convenience +logic reset_fifo_rd_req; +logic reset_fifo_empty; +logic [PTR_W+LEN_W-1:0] reset_fifo_rd_data; + +always_ff @(posedge clk) begin + if (rst) begin + if (LEN_MAX > BACKING_SIZE_EXACT) begin + $fatal("len max > backing size of tcp malloc unit... bad configuration"); + end + end else begin + if (slices_fifo_full) begin + $fatal("slices fifo should never fill up, an error was made calculating its size"); + end + end +end + +// free || reset -> slices +assign free_req_fifo_rd_req = ~slices_fifo_full; +assign reset_fifo_rd_req = free_req_fifo_empty && ~slices_fifo_full; +assign slices_fifo_wr_req = ~free_req_fifo_empty || (free_req_fifo_empty && ~reset_fifo_empty); +assign slices_fifo_wr_data = ~free_req_fifo_empty ? free_req_fifo_rd_data : reset_fifo_rd_data; + +// slices && req -> resp +assign slices_fifo_rd_req = ~malloc_resp_fifo_full && ~malloc_req_fifo_empty; +generate + if (STALL) begin + assign malloc_req_fifo_rd_req = ~malloc_resp_fifo_full && ~slices_fifo_empty; + assign malloc_resp_fifo_wr_req = ~slices_fifo_empty && ~malloc_req_fifo_empty; + assign malloc_resp_fifo_wr_data = '{1'b1, slices_fifo_rd_data[PTR_W+LEN_W-1:LEN_W]}; + end else begin + assign malloc_req_fifo_rd_req = ~malloc_resp_fifo_full; + assign malloc_resp_fifo_wr_req = ~malloc_req_fifo_empty; + assign malloc_resp_fifo_wr_data = '{~slices_fifo_empty, slices_fifo_rd_data[PTR_W+LEN_W-1:LEN_W]}; + end +endgenerate + + +// reset logic +logic [PTR_W:0] reset_current_addr_reg = 0; +logic [PTR_W:0] reset_current_addr_next; +logic reset_done = 0; +assign reset_current_addr_next = reset_current_addr_reg + LEN_MAX; + +assign reset_fifo_empty = reset_done; +assign reset_fifo_rd_data = '{reset_current_addr_reg[PTR_W-1:0], LEN_MAX}; + +always_ff @(posedge clk) begin + if (rst) begin + reset_current_addr_reg <= '0; + reset_done <= '0; + end else begin + if (reset_fifo_rd_req && ~reset_fifo_empty) begin + // transaction occurred. + reset_current_addr_reg <= reset_current_addr_next; + if (reset_current_addr_next >= BACKING_SIZE_EXACT) begin + reset_done <= 1; + end + end + end +end + +// free bytes/empty space logic +logic [PTR_W:0] free_bytes_cnt_reg = BACKING_SIZE_EXACT; +logic [PTR_W:0] free_bytes_cnt_next; +assign malloc_approx_empty_space = free_bytes_cnt_reg; + +always_comb begin + free_bytes_cnt_next = free_bytes_cnt_reg; + + // malloc request means one fewer slice + if (slices_fifo_rd_req && ~slices_fifo_empty) begin + free_bytes_cnt_next = free_bytes_cnt_next - LEN_MAX; + end + + // slice write from the free fifo means one more slice + // notably, reset doesn't increment. it starts out totally empty. + if (slices_fifo_wr_req && ~slices_fifo_full && ~free_req_fifo_empty && free_req_fifo_rd_req) begin + free_bytes_cnt_next = free_bytes_cnt_next + LEN_MAX; + end +end + +always @(posedge clk) begin + if (rst) begin + free_bytes_cnt_reg <= BACKING_SIZE_EXACT; + end else begin + free_bytes_cnt_reg <= free_bytes_cnt_next; + if (free_bytes_cnt_next > BACKING_SIZE_EXACT) begin + $fatal("bug in free bytes calculation"); + end + end + +end + +fifo_1r1w #( + .width_p (PTR_W+LEN_W) + ,.log2_els_p (SLICES_W) +) slices_fifo ( + .clk (clk) + ,.rst (rst) + + ,.rd_req (slices_fifo_rd_req ) + ,.empty (slices_fifo_empty ) + ,.rd_data (slices_fifo_rd_data ) + + ,.wr_req (slices_fifo_wr_req ) + ,.wr_data (slices_fifo_wr_data ) + ,.full (slices_fifo_full ) +); + +fifo_1r1w #( + .width_p (LEN_W) + ,.log2_els_p (1) +) malloc_req_fifo ( + .clk (clk) + ,.rst (rst) + + ,.rd_req (malloc_req_fifo_rd_req ) + ,.empty (malloc_req_fifo_empty ) + ,.rd_data (malloc_req_fifo_rd_data ) + + ,.wr_req (malloc_req_fifo_wr_req ) + ,.wr_data (malloc_req_fifo_wr_data ) + ,.full (malloc_req_fifo_full ) +); + +fifo_1r1w #( + .width_p (1+LEN_W) + ,.log2_els_p (1) +) malloc_resp_fifo ( + .clk (clk) + ,.rst (rst) + + ,.rd_req (malloc_resp_fifo_rd_req ) + ,.empty (malloc_resp_fifo_empty ) + ,.rd_data (malloc_resp_fifo_rd_data ) + + ,.wr_req (malloc_resp_fifo_wr_req ) + ,.wr_data (malloc_resp_fifo_wr_data ) + ,.full (malloc_resp_fifo_full ) +); + +fifo_1r1w #( + .width_p (PTR_W+LEN_W) + ,.log2_els_p (1) +) free_req_fifo ( + .clk (clk) + ,.rst (rst) + + ,.rd_req (free_req_fifo_rd_req ) + ,.empty (free_req_fifo_empty ) + ,.rd_data (free_req_fifo_rd_data ) + + ,.wr_req (free_req_fifo_wr_req ) + ,.wr_data (free_req_fifo_wr_data ) + ,.full (free_req_fifo_full ) +); + +endmodule \ No newline at end of file diff --git a/tcp_rx.sv b/tcp_rx.sv index c044a0c..96ac0c9 100644 --- a/tcp_rx.sv +++ b/tcp_rx.sv @@ -55,26 +55,26 @@ import packet_struct_pkg::*; ,input smol_tx_state_struct curr_tx_state_rd_resp_data ,output logic curr_tx_state_rd_resp_rdy - ,output logic rx_pipe_rx_head_ptr_rd_req_val - ,output logic [FLOWID_W-1:0] rx_pipe_rx_head_ptr_rd_req_addr - ,input logic rx_head_ptr_rx_pipe_rd_req_rdy + ,output logic rx_pipe_rx_head_idx_rd_req_val + ,output logic [FLOWID_W-1:0] rx_pipe_rx_head_idx_rd_req_addr + ,input logic rx_head_idx_rx_pipe_rd_req_rdy - ,input logic rx_head_ptr_rx_pipe_rd_resp_val - ,input logic [RX_PAYLOAD_PTR_W:0] rx_head_ptr_rx_pipe_rd_resp_data - ,output logic rx_pipe_rx_head_ptr_rd_resp_rdy - - ,output logic rx_pipe_rx_tail_ptr_wr_req_val - ,output logic [FLOWID_W-1:0] rx_pipe_rx_tail_ptr_wr_req_addr - ,output logic [RX_PAYLOAD_PTR_W:0] rx_pipe_rx_tail_ptr_wr_req_data - ,input logic rx_tail_ptr_rx_pipe_wr_req_rdy + ,input logic rx_head_idx_rx_pipe_rd_resp_val + ,input logic [RX_PAYLOAD_IDX_W:0] rx_head_idx_rx_pipe_rd_resp_data + ,output logic rx_pipe_rx_head_idx_rd_resp_rdy + + ,output logic rx_pipe_rx_tail_idx_wr_req_val + ,output logic [FLOWID_W-1:0] rx_pipe_rx_tail_idx_wr_req_addr + ,output logic [RX_PAYLOAD_IDX_W:0] rx_pipe_rx_tail_idx_wr_req_data + ,input logic rx_tail_idx_rx_pipe_wr_req_rdy - ,output logic rx_pipe_rx_tail_ptr_rd_req_val - ,output logic [FLOWID_W-1:0] rx_pipe_rx_tail_ptr_rd_req_addr - ,input logic rx_tail_ptr_rx_pipe_rd_req_rdy + ,output logic rx_pipe_rx_tail_idx_rd_req_val + ,output logic [FLOWID_W-1:0] rx_pipe_rx_tail_idx_rd_req_addr + ,input logic rx_tail_idx_rx_pipe_rd_req_rdy - ,input logic rx_tail_ptr_rx_pipe_rd_resp_val - ,input logic [RX_PAYLOAD_PTR_W:0] rx_tail_ptr_rx_pipe_rd_resp_data - ,output logic rx_pipe_rx_tail_ptr_rd_resp_rdy + ,input logic rx_tail_idx_rx_pipe_rd_resp_val + ,input logic [RX_PAYLOAD_IDX_W:0] rx_tail_idx_rx_pipe_rd_resp_data + ,output logic rx_pipe_rx_tail_idx_rd_resp_rdy ,output rx_pipe_tx_head_ptr_wr_req_val ,output [FLOWID_W-1:0] rx_pipe_tx_head_ptr_wr_req_addr @@ -91,6 +91,23 @@ import packet_struct_pkg::*; ,output logic rx_sched_update_val ,output sched_cmd_struct rx_sched_update_cmd ,input logic sched_rx_update_rdy + + ,output rx_pipe_rx_malloc_req_val + ,output [MALLOC_LEN_W-1:0] rx_pipe_rx_malloc_req_len // in the native impl, this must equal LEN_MAX + ,input rx_malloc_rx_pipe_req_rdy + + ,input rx_malloc_rx_pipe_resp_val + ,input rx_malloc_rx_pipe_resp_success // 1 = addr is valid. 0 = addr is junk, retry your request or otherwise handle OOM. + ,input [RX_PAYLOAD_PTR_W-1:0] rx_malloc_rx_pipe_resp_addr + ,output rx_pipe_rx_malloc_resp_rdy + + ,input [RX_PAYLOAD_PTR_W:0] rx_malloc_rx_pipe_approx_empty_space + + ,output rx_pipe_rx_buf_store_wr_req_val + ,output [FLOWID_W-1:0] rx_pipe_rx_buf_store_wr_req_flowid + ,output [RX_PAYLOAD_IDX_W-1:0] rx_pipe_rx_buf_store_wr_req_idx + ,output tcp_buf rx_pipe_rx_buf_store_wr_req_data + ,input rx_buf_store_rx_pipe_wr_req_rdy ); logic read_flow_cam_val; @@ -101,6 +118,7 @@ import packet_struct_pkg::*; logic ctrl_datap_save_input; logic ctrl_datap_save_flow_state; logic ctrl_datap_save_calcs; + logic ctrl_datap_save_malloc_resp; logic slow_path_val; tcp_pkt_hdr slow_path_pkt; @@ -175,20 +193,20 @@ import packet_struct_pkg::*; ,.curr_tx_state_rd_resp_val (curr_tx_state_rd_resp_val ) ,.curr_tx_state_rd_resp_rdy (curr_tx_state_rd_resp_rdy ) - ,.rx_pipe_rx_head_ptr_rd_req_val (rx_pipe_rx_head_ptr_rd_req_val ) - ,.rx_head_ptr_rx_pipe_rd_req_rdy (rx_head_ptr_rx_pipe_rd_req_rdy ) + ,.rx_pipe_rx_head_idx_rd_req_val (rx_pipe_rx_head_idx_rd_req_val ) + ,.rx_head_idx_rx_pipe_rd_req_rdy (rx_head_idx_rx_pipe_rd_req_rdy ) - ,.rx_head_ptr_rx_pipe_rd_resp_val (rx_head_ptr_rx_pipe_rd_resp_val ) - ,.rx_pipe_rx_head_ptr_rd_resp_rdy (rx_pipe_rx_head_ptr_rd_resp_rdy ) + ,.rx_head_idx_rx_pipe_rd_resp_val (rx_head_idx_rx_pipe_rd_resp_val ) + ,.rx_pipe_rx_head_idx_rd_resp_rdy (rx_pipe_rx_head_idx_rd_resp_rdy ) - ,.rx_pipe_rx_tail_ptr_wr_req_val (rx_pipe_rx_tail_ptr_wr_req_val ) - ,.rx_tail_ptr_rx_pipe_wr_req_rdy (rx_tail_ptr_rx_pipe_wr_req_rdy ) + ,.rx_pipe_rx_tail_idx_wr_req_val (rx_pipe_rx_tail_idx_wr_req_val ) + ,.rx_tail_idx_rx_pipe_wr_req_rdy (rx_tail_idx_rx_pipe_wr_req_rdy ) - ,.rx_pipe_rx_tail_ptr_rd_req_val (rx_pipe_rx_tail_ptr_rd_req_val ) - ,.rx_tail_ptr_rx_pipe_rd_req_rdy (rx_tail_ptr_rx_pipe_rd_req_rdy ) + ,.rx_pipe_rx_tail_idx_rd_req_val (rx_pipe_rx_tail_idx_rd_req_val ) + ,.rx_tail_idx_rx_pipe_rd_req_rdy (rx_tail_idx_rx_pipe_rd_req_rdy ) - ,.rx_tail_ptr_rx_pipe_rd_resp_val (rx_tail_ptr_rx_pipe_rd_resp_val ) - ,.rx_pipe_rx_tail_ptr_rd_resp_rdy (rx_pipe_rx_tail_ptr_rd_resp_rdy ) + ,.rx_tail_idx_rx_pipe_rd_resp_val (rx_tail_idx_rx_pipe_rd_resp_val ) + ,.rx_pipe_rx_tail_idx_rd_resp_rdy (rx_pipe_rx_tail_idx_rd_resp_rdy ) ,.rx_pipe_tx_head_ptr_wr_req_val (rx_pipe_tx_head_ptr_wr_req_val ) ,.tx_head_ptr_rx_pipe_wr_req_rdy (tx_head_ptr_rx_pipe_wr_req_rdy ) @@ -196,6 +214,7 @@ import packet_struct_pkg::*; ,.ctrl_datap_save_input (ctrl_datap_save_input ) ,.ctrl_datap_save_flow_state (ctrl_datap_save_flow_state ) ,.ctrl_datap_save_calcs (ctrl_datap_save_calcs ) + ,.ctrl_datap_save_malloc_resp (ctrl_datap_save_malloc_resp ) ,.rx_sched_update_val (rx_sched_update_val ) ,.sched_rx_update_rdy (sched_rx_update_rdy ) @@ -207,6 +226,15 @@ import packet_struct_pkg::*; ,.slow_path_done_val (slow_path_done_val ) ,.slow_path_done_rdy (slow_path_done_rdy ) + + ,.rx_pipe_rx_malloc_req_val (rx_pipe_rx_malloc_req_val ) + ,.rx_malloc_rx_pipe_req_rdy (rx_malloc_rx_pipe_req_rdy ) + + ,.rx_malloc_rx_pipe_resp_val (rx_malloc_rx_pipe_resp_val ) + ,.rx_pipe_rx_malloc_resp_rdy (rx_pipe_rx_malloc_resp_rdy ) + + ,.rx_pipe_rx_buf_store_wr_req_val (rx_pipe_rx_buf_store_wr_req_val ) + ,.rx_buf_store_rx_pipe_wr_req_rdy (rx_buf_store_rx_pipe_wr_req_rdy ) ); flowid_manager flowid_manager ( @@ -251,16 +279,16 @@ import packet_struct_pkg::*; ,.curr_tx_state_rd_resp_data (curr_tx_state_rd_resp_data ) - ,.rx_pipe_rx_head_ptr_rd_req_addr (rx_pipe_rx_head_ptr_rd_req_addr ) + ,.rx_pipe_rx_head_idx_rd_req_addr (rx_pipe_rx_head_idx_rd_req_addr ) - ,.rx_head_ptr_rx_pipe_rd_resp_data (rx_head_ptr_rx_pipe_rd_resp_data ) + ,.rx_head_idx_rx_pipe_rd_resp_data (rx_head_idx_rx_pipe_rd_resp_data ) - ,.rx_pipe_rx_tail_ptr_wr_req_addr (rx_pipe_rx_tail_ptr_wr_req_addr ) - ,.rx_pipe_rx_tail_ptr_wr_req_data (rx_pipe_rx_tail_ptr_wr_req_data ) + ,.rx_pipe_rx_tail_idx_wr_req_addr (rx_pipe_rx_tail_idx_wr_req_addr ) + ,.rx_pipe_rx_tail_idx_wr_req_data (rx_pipe_rx_tail_idx_wr_req_data ) - ,.rx_pipe_rx_tail_ptr_rd_req_addr (rx_pipe_rx_tail_ptr_rd_req_addr ) + ,.rx_pipe_rx_tail_idx_rd_req_addr (rx_pipe_rx_tail_idx_rd_req_addr ) - ,.rx_tail_ptr_rx_pipe_rd_resp_data (rx_tail_ptr_rx_pipe_rd_resp_data ) + ,.rx_tail_idx_rx_pipe_rd_resp_data (rx_tail_idx_rx_pipe_rd_resp_data ) ,.rx_pipe_tx_head_ptr_wr_req_addr (rx_pipe_tx_head_ptr_wr_req_addr ) ,.rx_pipe_tx_head_ptr_wr_req_data (rx_pipe_tx_head_ptr_wr_req_data ) @@ -278,6 +306,7 @@ import packet_struct_pkg::*; ,.ctrl_datap_save_input (ctrl_datap_save_input ) ,.ctrl_datap_save_flow_state (ctrl_datap_save_flow_state ) ,.ctrl_datap_save_calcs (ctrl_datap_save_calcs ) + ,.ctrl_datap_save_malloc_resp (ctrl_datap_save_malloc_resp ) ,.rx_sched_update_cmd (rx_sched_update_cmd ) @@ -290,6 +319,17 @@ import packet_struct_pkg::*; ,.slow_path_send_pkt_enqueue_flowid (rx_send_pkt_enq_flowid ) ,.slow_path_send_pkt_enqueue_src_ip (rx_send_pkt_enq_src_ip ) ,.slow_path_send_pkt_enqueue_dst_ip (rx_send_pkt_enq_dst_ip ) + + ,.rx_pipe_rx_malloc_req_len (rx_pipe_rx_malloc_req_len ) + + ,.rx_malloc_rx_pipe_resp_success (rx_malloc_rx_pipe_resp_success ) + ,.rx_malloc_rx_pipe_resp_addr (rx_malloc_rx_pipe_resp_addr ) + + ,.rx_malloc_rx_pipe_approx_empty_space(rx_malloc_rx_pipe_approx_empty_space) + + ,.rx_pipe_rx_buf_store_wr_req_flowid(rx_pipe_rx_buf_store_wr_req_flowid ) + ,.rx_pipe_rx_buf_store_wr_req_idx (rx_pipe_rx_buf_store_wr_req_idx ) + ,.rx_pipe_rx_buf_store_wr_req_data (rx_pipe_rx_buf_store_wr_req_data ) ); logic [MAX_FLOW_CNT-1:0] cam_wr_val; diff --git a/tcp_rx_ctrl.sv b/tcp_rx_ctrl.sv index f341279..37be5fa 100644 --- a/tcp_rx_ctrl.sv +++ b/tcp_rx_ctrl.sv @@ -26,20 +26,20 @@ module tcp_rx_ctrl ( ,input logic curr_tx_state_rd_resp_val ,output logic curr_tx_state_rd_resp_rdy - ,output logic rx_pipe_rx_head_ptr_rd_req_val - ,input logic rx_head_ptr_rx_pipe_rd_req_rdy + ,output logic rx_pipe_rx_head_idx_rd_req_val + ,input logic rx_head_idx_rx_pipe_rd_req_rdy - ,input logic rx_head_ptr_rx_pipe_rd_resp_val - ,output logic rx_pipe_rx_head_ptr_rd_resp_rdy + ,input logic rx_head_idx_rx_pipe_rd_resp_val + ,output logic rx_pipe_rx_head_idx_rd_resp_rdy - ,output logic rx_pipe_rx_tail_ptr_wr_req_val - ,input logic rx_tail_ptr_rx_pipe_wr_req_rdy + ,output logic rx_pipe_rx_tail_idx_wr_req_val + ,input logic rx_tail_idx_rx_pipe_wr_req_rdy - ,output logic rx_pipe_rx_tail_ptr_rd_req_val - ,input logic rx_tail_ptr_rx_pipe_rd_req_rdy + ,output logic rx_pipe_rx_tail_idx_rd_req_val + ,input logic rx_tail_idx_rx_pipe_rd_req_rdy - ,input logic rx_tail_ptr_rx_pipe_rd_resp_val - ,output logic rx_pipe_rx_tail_ptr_rd_resp_rdy + ,input logic rx_tail_idx_rx_pipe_rd_resp_val + ,output logic rx_pipe_rx_tail_idx_rd_resp_rdy ,output logic rx_pipe_tx_head_ptr_wr_req_val ,input tx_head_ptr_rx_pipe_wr_req_rdy @@ -47,6 +47,8 @@ module tcp_rx_ctrl ( ,output logic ctrl_datap_save_input ,output logic ctrl_datap_save_flow_state ,output logic ctrl_datap_save_calcs + ,output logic ctrl_datap_save_malloc_resp + ,input logic datap_ctrl_payload_accepted ,output logic rx_sched_update_val ,input logic sched_rx_update_rdy @@ -58,6 +60,15 @@ module tcp_rx_ctrl ( ,input logic slow_path_done_val ,output logic slow_path_done_rdy + + ,output rx_pipe_rx_malloc_req_val + ,input rx_malloc_rx_pipe_req_rdy + + ,input rx_malloc_rx_pipe_resp_val + ,output rx_pipe_rx_malloc_resp_rdy + + ,output rx_pipe_rx_buf_store_wr_req_val + ,input rx_buf_store_rx_pipe_wr_req_rdy ); typedef enum logic[3:0] { @@ -67,9 +78,12 @@ module tcp_rx_ctrl ( WAIT_NEW_FLOW_SETUP = 4'd3, WAIT_STATE_RESP = 4'd4, CALCULATE = 4'd5, - WRITEBACK = 4'd6, + WRITEBACK1 = 4'd6, SCHEDULE = 4'd7, PKT_OUT = 4'd8, + WAIT_MALLOC_REQ = 4'd9, + WAIT_MALLOC_RESP = 4'd10, + WRITEBACK2 = 4'd11, UND = 'X } state_e; @@ -91,21 +105,22 @@ module tcp_rx_ctrl ( ctrl_datap_save_input = 1'b0; ctrl_datap_save_flow_state = 1'b0; ctrl_datap_save_calcs = 1'b0; + ctrl_datap_save_malloc_resp = 1'b0; tcp_rx_dst_hdr_val = 1'b0; curr_rx_state_rd_req_val = 1'b0; curr_tx_state_rd_req_val = 1'b0; - rx_pipe_rx_head_ptr_rd_req_val = 1'b0; - rx_pipe_rx_tail_ptr_rd_req_val = 1'b0; + rx_pipe_rx_head_idx_rd_req_val = 1'b0; + rx_pipe_rx_tail_idx_rd_req_val = 1'b0; - rx_pipe_rx_tail_ptr_wr_req_val = 1'b0; + rx_pipe_rx_tail_idx_wr_req_val = 1'b0; rx_pipe_tx_head_ptr_wr_req_val = 1'b0; curr_tx_state_rd_resp_rdy = 1'b0; curr_rx_state_rd_resp_rdy = 1'b0; - rx_pipe_rx_head_ptr_rd_resp_rdy = 1'b0; - rx_pipe_rx_tail_ptr_rd_resp_rdy = 1'b0; + rx_pipe_rx_head_idx_rd_resp_rdy = 1'b0; + rx_pipe_rx_tail_idx_rd_resp_rdy = 1'b0; next_rx_state_wr_req_val = 1'b0; @@ -138,16 +153,16 @@ module tcp_rx_ctrl ( READ_STATE: begin curr_rx_state_rd_req_val = 1'b1; curr_tx_state_rd_req_val = 1'b1; - rx_pipe_rx_head_ptr_rd_req_val = 1'b1; - rx_pipe_rx_tail_ptr_rd_req_val = 1'b1; + rx_pipe_rx_head_idx_rd_req_val = 1'b1; + rx_pipe_rx_tail_idx_rd_req_val = 1'b1; curr_tx_state_rd_resp_rdy = 1'b1; curr_rx_state_rd_resp_rdy = 1'b1; - rx_pipe_rx_head_ptr_rd_resp_rdy = 1'b1; - rx_pipe_rx_tail_ptr_rd_resp_rdy = 1'b1; + rx_pipe_rx_head_idx_rd_resp_rdy = 1'b1; + rx_pipe_rx_tail_idx_rd_resp_rdy = 1'b1; if (curr_rx_state_rd_req_rdy & curr_tx_state_rd_req_rdy & - rx_head_ptr_rx_pipe_rd_req_rdy & rx_tail_ptr_rx_pipe_rd_req_rdy) begin + rx_head_idx_rx_pipe_rd_req_rdy & rx_tail_idx_rx_pipe_rd_req_rdy) begin state_next = WAIT_STATE_RESP; end end @@ -166,25 +181,47 @@ module tcp_rx_ctrl ( WAIT_STATE_RESP: begin ctrl_datap_save_flow_state = 1'b1; if (curr_rx_state_rd_resp_val & curr_tx_state_rd_resp_val & - rx_head_ptr_rx_pipe_rd_resp_val & rx_tail_ptr_rx_pipe_rd_resp_val) begin + rx_head_idx_rx_pipe_rd_resp_val & rx_tail_idx_rx_pipe_rd_resp_val) begin curr_rx_state_rd_resp_rdy = 1'b1; curr_tx_state_rd_resp_rdy = 1'b1; - rx_pipe_rx_head_ptr_rd_resp_rdy = 1'b1; - rx_pipe_rx_tail_ptr_rd_resp_rdy = 1'b1; + rx_pipe_rx_head_idx_rd_resp_rdy = 1'b1; + rx_pipe_rx_tail_idx_rd_resp_rdy = 1'b1; + state_next = WAIT_MALLOC_REQ; + end + end + // TODO: future optimization to move malloc to READ_STATE, but then need to free if packet not accepted. + WAIT_MALLOC_REQ: begin + rx_pipe_rx_malloc_req_val = 1'b1; + if (rx_pipe_rx_malloc_req_val && rx_malloc_rx_pipe_req_rdy) begin + state_next = WAIT_MALLOC_RESP; + end + end + WAIT_MALLOC_RESP: begin + rx_pipe_rx_malloc_resp_rdy = 1'b1; + ctrl_datap_save_malloc_resp = 1'b1; + if (rx_malloc_rx_pipe_resp_val && rx_pipe_rx_malloc_resp_rdy) begin state_next = CALCULATE; end end CALCULATE: begin ctrl_datap_save_calcs = 1'b1; - state_next = WRITEBACK; + state_next = WRITEBACK1; end - WRITEBACK: begin + WRITEBACK1: begin next_rx_state_wr_req_val = 1'b1; - rx_pipe_rx_tail_ptr_wr_req_val = 1'b1; + rx_pipe_rx_tail_idx_wr_req_val = 1'b1; rx_pipe_tx_head_ptr_wr_req_val = 1'b1; - if (next_rx_state_wr_req_rdy & rx_tail_ptr_rx_pipe_wr_req_rdy & + if (next_rx_state_wr_req_rdy & rx_tail_idx_rx_pipe_wr_req_rdy & tx_head_ptr_rx_pipe_wr_req_rdy) begin + state_next = WRITEBACK2; + end + end + WRITEBACK2: begin + rx_pipe_rx_buf_store_wr_req_val = datap_ctrl_payload_accepted; + if (~datap_ctrl_payload_accepted) begin + state_next = SCHEDULE; + end else if (rx_pipe_rx_buf_store_wr_req_val && rx_buf_store_rx_pipe_wr_req_rdy) begin state_next = SCHEDULE; end end diff --git a/tcp_rx_datap.sv b/tcp_rx_datap.sv index 593d651..fd248ec 100644 --- a/tcp_rx_datap.sv +++ b/tcp_rx_datap.sv @@ -31,16 +31,16 @@ import packet_struct_pkg::*; ,input smol_tx_state_struct curr_tx_state_rd_resp_data - ,output logic [FLOWID_W-1:0] rx_pipe_rx_head_ptr_rd_req_addr + ,output logic [FLOWID_W-1:0] rx_pipe_rx_head_idx_rd_req_addr - ,input logic [RX_PAYLOAD_PTR_W:0] rx_head_ptr_rx_pipe_rd_resp_data + ,input logic [RX_PAYLOAD_IDX_W:0] rx_head_idx_rx_pipe_rd_resp_data - ,output logic [FLOWID_W-1:0] rx_pipe_rx_tail_ptr_wr_req_addr - ,output logic [RX_PAYLOAD_PTR_W:0] rx_pipe_rx_tail_ptr_wr_req_data + ,output logic [FLOWID_W-1:0] rx_pipe_rx_tail_idx_wr_req_addr + ,output logic [RX_PAYLOAD_IDX_W:0] rx_pipe_rx_tail_idx_wr_req_data - ,output logic [FLOWID_W-1:0] rx_pipe_rx_tail_ptr_rd_req_addr + ,output logic [FLOWID_W-1:0] rx_pipe_rx_tail_idx_rd_req_addr - ,input logic [RX_PAYLOAD_PTR_W:0] rx_tail_ptr_rx_pipe_rd_resp_data + ,input logic [RX_PAYLOAD_IDX_W:0] rx_tail_idx_rx_pipe_rd_resp_data ,output [FLOWID_W-1:0] rx_pipe_tx_head_ptr_wr_req_addr ,output [TX_PAYLOAD_PTR_W:0] rx_pipe_tx_head_ptr_wr_req_data @@ -58,6 +58,8 @@ import packet_struct_pkg::*; ,input ctrl_datap_save_input ,input ctrl_datap_save_flow_state ,input ctrl_datap_save_calcs + ,input ctrl_datap_save_malloc_resp + ,output datap_ctrl_payload_accepted ,output sched_cmd_struct rx_sched_update_cmd @@ -70,6 +72,17 @@ import packet_struct_pkg::*; ,output [FLOWID_W-1:0] slow_path_send_pkt_enqueue_flowid ,output [`IP_ADDR_W-1:0] slow_path_send_pkt_enqueue_src_ip ,output [`IP_ADDR_W-1:0] slow_path_send_pkt_enqueue_dst_ip + + ,output [MALLOC_LEN_W-1:0] rx_pipe_rx_malloc_req_len // in the native impl, this must equal LEN_MAX + + ,input rx_malloc_rx_pipe_resp_success // 1 = addr is valid. 0 = addr is junk, retry your request or otherwise handle OOM. + ,input [RX_PAYLOAD_PTR_W-1:0] rx_malloc_rx_pipe_resp_addr + + ,input [RX_PAYLOAD_PTR_W:0] rx_malloc_rx_pipe_approx_empty_space + + ,output [FLOWID_W-1:0] rx_pipe_rx_buf_store_wr_req_flowid + ,output [RX_PAYLOAD_IDX_W-1:0] rx_pipe_rx_buf_store_wr_req_idx + ,output tcp_buf rx_pipe_rx_buf_store_wr_req_data ); localparam OUR_SEQ_NUM = 32'hff; @@ -99,18 +112,23 @@ import packet_struct_pkg::*; logic [`ACK_NUM_W-1:0] their_ack_num; ack_state_struct our_ack_state; - logic [RX_PAYLOAD_PTR_W:0] next_rx_tail_ptr_next; - logic [RX_PAYLOAD_PTR_W:0] next_rx_tail_ptr_reg; - logic [RX_PAYLOAD_PTR_W:0] next_rx_tail_ptr; + logic [RX_PAYLOAD_IDX_W:0] next_rx_tail_idx_next; + logic [RX_PAYLOAD_IDX_W:0] next_rx_tail_idx_reg; + logic [RX_PAYLOAD_IDX_W:0] next_rx_tail_idx; logic [TX_PAYLOAD_PTR_W:0] next_tx_head_ptr_next; logic [TX_PAYLOAD_PTR_W:0] next_tx_head_ptr_reg; logic [TX_PAYLOAD_PTR_W:0] next_tx_head_ptr; - logic [RX_PAYLOAD_PTR_W:0] curr_rx_head_reg; - logic [RX_PAYLOAD_PTR_W:0] curr_rx_tail_reg; - logic [RX_PAYLOAD_PTR_W:0] curr_rx_head_next; - logic [RX_PAYLOAD_PTR_W:0] curr_rx_tail_next; + logic [RX_PAYLOAD_IDX_W:0] curr_rx_head_reg; + logic [RX_PAYLOAD_IDX_W:0] curr_rx_tail_reg; + logic [RX_PAYLOAD_IDX_W:0] curr_rx_head_next; + logic [RX_PAYLOAD_IDX_W:0] curr_rx_tail_next; + + logic malloc_success_reg; + logic malloc_success_next; + logic [RX_PAYLOAD_PTR_W-1:0] malloc_addr_reg; + logic [RX_PAYLOAD_PTR_W-1:0] malloc_addr_next; logic [RX_PAYLOAD_PTR_W:0] our_win; @@ -132,8 +150,10 @@ import packet_struct_pkg::*; curr_tx_data_reg <= curr_tx_data_next; curr_rx_head_reg <= curr_rx_head_next; curr_rx_tail_reg <= curr_rx_tail_next; + malloc_success_reg <= malloc_success_next; + malloc_addr_reg <= malloc_addr_next; next_rx_state_reg <= next_rx_state_next; - next_rx_tail_ptr_reg <= next_rx_tail_ptr_next; + next_rx_tail_idx_reg <= next_rx_tail_idx_next; next_tx_head_ptr_reg <= next_tx_head_ptr_next; accept_payload_reg <= accept_payload_next; set_rt_reg <= set_rt_next; @@ -141,7 +161,7 @@ import packet_struct_pkg::*; assign datap_slow_path_pkt = tcp_hdr_reg; assign next_rx_state_wr_req_data = next_rx_state_reg; - assign rx_pipe_rx_tail_ptr_wr_req_data = next_rx_tail_ptr_reg; + assign rx_pipe_rx_tail_idx_wr_req_data = next_rx_tail_idx_reg; assign rx_pipe_tx_head_ptr_wr_req_data = next_tx_head_ptr_reg; assign datap_ctrl_set_rt = set_rt_reg; @@ -156,9 +176,9 @@ import packet_struct_pkg::*; ? flowid_manager_flowid : curr_flowid_reg; - assign rx_pipe_rx_head_ptr_rd_req_addr = curr_flowid_reg; - assign rx_pipe_rx_tail_ptr_rd_req_addr = curr_flowid_reg; - assign rx_pipe_rx_tail_ptr_wr_req_addr = curr_flowid_reg; + assign rx_pipe_rx_head_idx_rd_req_addr = curr_flowid_reg; + assign rx_pipe_rx_tail_idx_rd_req_addr = curr_flowid_reg; + assign rx_pipe_rx_tail_idx_wr_req_addr = curr_flowid_reg; assign rx_pipe_tx_head_ptr_wr_req_addr = curr_flowid_reg; assign curr_rx_state_rd_req_addr = curr_flowid_reg; @@ -169,9 +189,19 @@ import packet_struct_pkg::*; assign tcp_rx_dst_pkt_accept = accept_payload_reg; assign tcp_rx_dst_payload_entry = payload_entry_reg; + assign rx_pipe_rx_malloc_req_len = MALLOC_LEN_MAX; + + assign rx_pipe_rx_buf_store_wr_req_flowid = curr_flowid_reg; + assign rx_pipe_rx_buf_store_wr_req_idx = next_rx_tail_idx_reg[RX_PAYLOAD_IDX_W-1:0]; + assign rx_pipe_rx_buf_store_wr_req_data.ptr = malloc_addr_reg; + assign rx_pipe_rx_buf_store_wr_req_data.len = MALLOC_LEN_MAX; + assign rx_pipe_rx_buf_store_wr_req_data.cap = MALLOC_LEN_MAX; + + assign datap_ctrl_payload_accepted = accept_payload_reg; + always_comb begin next_rx_state_next = '0; - next_rx_tail_ptr_next = next_rx_tail_ptr_reg; + next_rx_tail_idx_next = next_rx_tail_idx_reg; next_tx_head_ptr_next = next_tx_head_ptr_reg; accept_payload_next = accept_payload_reg; set_rt_next = set_rt_reg; @@ -181,14 +211,14 @@ import packet_struct_pkg::*; next_rx_state_next.their_win_size = tcp_hdr_reg.win_size; next_rx_state_next.their_ack_num = their_ack_num; next_rx_state_next.our_win_size = our_win; - next_rx_tail_ptr_next = next_rx_tail_ptr; + next_rx_tail_idx_next = next_rx_tail_idx; next_tx_head_ptr_next = next_tx_head_ptr; accept_payload_next = accept_payload; set_rt_next = set_rt; end else begin next_rx_state_next = next_rx_state_reg; - next_rx_tail_ptr_next = next_rx_tail_ptr_reg; + next_rx_tail_idx_next = next_rx_tail_idx_reg; next_tx_head_ptr_next = next_tx_head_ptr_reg; accept_payload_next = accept_payload_reg; set_rt_next = set_rt_reg; @@ -199,8 +229,8 @@ import packet_struct_pkg::*; if (ctrl_datap_save_flow_state) begin curr_rx_data_next = curr_rx_state_rd_resp_data; curr_tx_data_next = curr_tx_state_rd_resp_data; - curr_rx_head_next = rx_head_ptr_rx_pipe_rd_resp_data; - curr_rx_tail_next = rx_tail_ptr_rx_pipe_rd_resp_data; + curr_rx_head_next = rx_head_idx_rx_pipe_rd_resp_data; + curr_rx_tail_next = rx_tail_idx_rx_pipe_rd_resp_data; end else begin curr_rx_data_next = curr_rx_data_reg; @@ -225,21 +255,34 @@ import packet_struct_pkg::*; end end + always_comb begin + if (ctrl_datap_save_malloc_resp) begin + malloc_success_next = rx_malloc_rx_pipe_resp_success; + malloc_addr_next = rx_malloc_rx_pipe_resp_addr; + end + else begin + malloc_success_next = malloc_success_reg; + malloc_addr_next = malloc_addr_reg; + end + end + /*************************************************************** * Fastpath logic **************************************************************/ // process the receiving stream to generate the ACKs for their data send their_ack_process their_ack_process ( - .their_curr_ack_num (curr_rx_data_reg.their_ack_num ) - ,.packet_seq_num (tcp_hdr_reg.seq_num ) - ,.packet_payload_len (payload_entry_reg.payload_len ) - ,.rx_tail_ptr (curr_rx_tail_reg ) - ,.rx_head_ptr (curr_rx_head_reg ) + .their_curr_ack_num (curr_rx_data_reg.their_ack_num ) + ,.packet_seq_num (tcp_hdr_reg.seq_num ) + ,.packet_payload_len (payload_entry_reg.payload_len ) + ,.rx_tail_idx (curr_rx_tail_reg ) + ,.rx_head_idx (curr_rx_head_reg ) + ,.malloc_success (malloc_success_reg ) + ,.malloc_approx_space (rx_malloc_rx_pipe_approx_empty_space ) - ,.their_next_ack_num (their_ack_num ) - ,.accept_payload (accept_payload ) - ,.next_rx_tail_ptr (next_rx_tail_ptr ) - ,.our_win (our_win ) + ,.their_next_ack_num (their_ack_num ) + ,.accept_payload (accept_payload ) + ,.next_rx_tail_idx (next_rx_tail_idx ) + ,.our_win (our_win ) ); our_ack_process our_ack_process ( @@ -291,7 +334,7 @@ import packet_struct_pkg::*; new_flow_rx_state.their_ack_num = tcp_hdr_reg.seq_num + 1'b1; new_flow_rx_state.their_win_size = tcp_hdr_reg.win_size; - new_flow_rx_state.our_win_size = (1 << RX_PAYLOAD_PTR_W); + new_flow_rx_state.our_win_size = (1 << RX_PAYLOAD_PTR_W); // TODO: adjust to malloc empty space probs? end always_comb begin @@ -313,7 +356,7 @@ import packet_struct_pkg::*; ,.seq_num (OUR_SEQ_NUM ) ,.ack_num (tcp_hdr_reg.seq_num + 1 ) ,.flags (`TCP_SYN | `TCP_ACK ) - ,.window ({(PAYLOAD_PTR_W){1'b1}} ) + ,.window ({(PAYLOAD_PTR_W){1'b1}} ) // TODO: what is this? window is hardcoded? ,.tcp_hdr_req_rdy () ,.outbound_tcp_hdr_val () diff --git a/their_ack_process.sv b/their_ack_process.sv index d967383..6429863 100644 --- a/their_ack_process.sv +++ b/their_ack_process.sv @@ -7,46 +7,48 @@ import tcp_pkg::*; input logic [`ACK_NUM_W-1:0] their_curr_ack_num ,input logic [`SEQ_NUM_W-1:0] packet_seq_num ,input logic [PAYLOAD_ENTRY_LEN_W-1:0] packet_payload_len - ,input logic [RX_PAYLOAD_PTR_W:0] rx_tail_ptr - ,input logic [RX_PAYLOAD_PTR_W:0] rx_head_ptr + ,input logic [RX_PAYLOAD_IDX_W:0] rx_tail_idx + ,input logic [RX_PAYLOAD_IDX_W:0] rx_head_idx + ,input logic malloc_success + ,input logic [RX_PAYLOAD_PTR_W:0] malloc_approx_space ,output logic [`ACK_NUM_W-1:0] their_next_ack_num ,output logic accept_payload - ,output logic [RX_PAYLOAD_PTR_W:0] next_rx_tail_ptr + ,output logic [RX_PAYLOAD_IDX_W:0] next_rx_tail_idx ,output logic [RX_PAYLOAD_PTR_W:0] our_win ); - logic [RX_PAYLOAD_PTR_W:0] rx_buf_space_used; - logic [RX_PAYLOAD_PTR_W:0] rx_buf_space_left; - logic rx_buf_has_space; + logic [RX_PAYLOAD_IDX_W:0] rx_buf_idx_used; + logic [RX_PAYLOAD_IDX_W:0] rx_buf_idx_left; + logic rx_buf_has_idx; - assign rx_buf_space_used = rx_tail_ptr - rx_head_ptr; - assign rx_buf_space_left = {1'b1, {(RX_PAYLOAD_PTR_W){1'b0}}} - rx_buf_space_used; - assign rx_buf_has_space = rx_buf_space_left >= packet_payload_len; + assign rx_buf_idx_used = rx_tail_idx - rx_head_idx; + assign rx_buf_idx_left = {1'b1, {(RX_PAYLOAD_IDX_W){1'b0}}} - rx_buf_idx_used; + assign rx_buf_has_idx = rx_buf_idx_left >= 1; // we're calculating ack numbers here by bytes rather than straight packet numbers // this can be modified later always_comb begin their_next_ack_num = their_curr_ack_num; - next_rx_tail_ptr = rx_tail_ptr; - our_win = rx_buf_space_left; + next_rx_tail_idx = rx_tail_idx; + our_win = malloc_approx_space; accept_payload = 1'b0; // if we've received the packet we expect, then ack for the next byte - if (rx_buf_has_space & (packet_seq_num == their_curr_ack_num)) begin + if (malloc_success & rx_buf_has_idx & (packet_seq_num == their_curr_ack_num)) begin accept_payload = 1'b1; their_next_ack_num = packet_seq_num + packet_payload_len; - next_rx_tail_ptr = rx_tail_ptr + packet_payload_len; - our_win = rx_buf_space_left - packet_payload_len; + next_rx_tail_idx = rx_tail_idx + 1; + our_win = malloc_approx_space - packet_payload_len; end // we're somehow out of order...just dup ack else begin accept_payload = 1'b0; their_next_ack_num = their_curr_ack_num; - next_rx_tail_ptr = rx_tail_ptr; - our_win = rx_buf_space_left; + next_rx_tail_idx = rx_tail_idx; + our_win = malloc_approx_space; end end endmodule